Pixel driving circuit, display panel driving circuit, and display panel

Abstract

The present application discloses a pixel drive circuit, a display panel drive circuit, and a display panel. Each pixel sub-area includes eight pixels arranged in a 2×4 pattern, wherein at least 2m sub-pixels in the first and second pixels are connected to the nth scan line, and the remaining sub-pixels in the first and second pixels are connected to the n+1th scan line; at least 2p sub-pixels in the third and fourth pixels are connected to the n+2th scan line, and the remaining sub-pixels in the third and fourth pixels are connected to the n+3th scan line; at least 2q sub-pixels in the fifth and sixth pixels are connected to the nth scan line, and the remaining sub-pixels in the fifth and sixth pixels are connected to the n+1th scan line; and at least 2r sub-pixels in the seventh and eighth pixels are connected to the n+2th scan line, and the remaining sub-pixels in the seventh and eighth pixels are connected to the n+3th scan line. Through the above approach, a DLG function can be implemented in an equivalent Flip Pixel architecture.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular to a pixel driving circuit, a display panel driving circuit, and a display panel. Background Art

[0002] In the field of display panel technology, there is not only EVA (Extended Viewing Angle) technology, but also a technology that uses low refresh to drive high refresh, called DLG (Dual Line Gate), and the pixel driving circuit has FlipPixel architecture and Strip architecture.

[0003] In terms of power consumption, the Strip architecture has poor display uniformity. There is a slight asymmetry between the positive and negative polarities of the same column and the same grayscale. When the field of view shakes horizontally, there will be a certain sense of vertical lines, which is more noticeable in pure colors and low gray. It is also easy to have vertical crosstalk and other problems.

[0004] In EVA technology, sub-pixels alternate between bright and dark in horizontal and vertical directions, but the Strip architecture is prone to head shakes. Two consecutive horizontal rows of the same polarity exacerbate head shakes. In the EVA technology pixel driver circuit, sub-pixels alternate between bright and dark in horizontal and vertical directions. In the Flip Pixel architecture, sub-pixels alternate between positive and negative in both horizontal and vertical directions. This directly creates a Flip Pixel architecture with a flickering effect, which can cause severe screen flicker. The vertical use of positive-negative-positive-positive-negative-positive breaks the same polarity pattern of bright and dark. Vertical polarity switching consumes excessive data line power and causes severe driver heat generation. The horizontal use of positive-negative-positive-positive-negative-positive breaks the same polarity pattern of bright and dark. Two consecutive horizontal rows of the same polarity also cause head shakes. Summary of the Invention

[0005] The present application provides a pixel driving circuit, a display panel driving circuit and a display panel, which can realize the DLG function with an equivalent FlipPixel architecture, and further realize the EVA function, and the brightness and polarity are evenly arranged, and the display quality effect is good.

[0006] In a first aspect, the present application provides a pixel driving circuit, comprising a plurality of scan lines and a plurality of data lines, and a plurality of pixels driven respectively by the plurality of scan lines and the plurality of data lines, wherein along the data line direction, the plurality of pixels are divided into a plurality of pixel regions, and along the scan line direction, each pixel region is divided into a plurality of pixel sub-regions, each pixel sub-region comprises eight pixels arranged in a 2×4 pattern, each pixel comprises three sub-pixels of different colors, and the eight pixels are respectively a first pixel, a second pixel, a third pixel, a fourth pixel, a fifth pixel, a sixth pixel, a seventh pixel, and an eighth pixel; wherein at least 2m sub-pixels of the first pixel and the second pixel are connected to the nth row of scan lines, and the remaining sub-pixels of the first pixel and the second pixel are connected to the nth row of scan lines. +1 row scan line; at least 2p sub-pixels in the third pixel and the fourth pixel are connected to the n+2 row scan line, and the remaining sub-pixels in the third pixel and the fourth pixel are connected to the n+3 row scan line; at least 2q sub-pixels in the fifth pixel and the sixth pixel are connected to the nth row scan line, and the remaining sub-pixels in the fifth pixel and the sixth pixel are connected to the n+1 row scan line; at least 2r sub-pixels in the seventh pixel and the eighth pixel are connected to the n+2 row scan line, and the remaining sub-pixels in the seventh pixel and the eighth pixel are connected to the n+3 row scan line; wherein n is a natural number greater than or equal to 1, m, p, q, and r are natural numbers greater than or equal to 2, and the 2m sub-pixels, 2p sub-pixels, 2q sub-pixels, and 2r sub-pixels come from different pixels.

[0007] Among them, 4 sub-pixels in the first pixel and the second pixel are connected to the nth row scan line, and the other 2 sub-pixels in the first pixel and the second pixel are connected to the n+1th row scan line; 4 sub-pixels in the third pixel and the fourth pixel are connected to the n+2th row scan line, and the other 2 sub-pixels in the third pixel and the fourth pixel are connected to the n+3th row scan line; 2 sub-pixels in the fifth pixel and the sixth pixel are connected to the nth row scan line, and the other 4 sub-pixels in the fifth pixel and the sixth pixel are connected to the n+1th row scan line; 2 sub-pixels in the seventh pixel and the eighth pixel are connected to the n+2th row scan line, and the other 4 sub-pixels in the seventh pixel and the eighth pixel are connected to the n+3th row scan line.

[0008] Among them, two sub-pixels in the first pixel and the second pixel are connected to the nth row scan line, and the other four sub-pixels in the first pixel and the second pixel are connected to the n+1th row scan line; four sub-pixels in the third pixel and the fourth pixel are connected to the n+2th row scan line, and the other two sub-pixels in the third pixel and the fourth pixel are connected to the n+3th row scan line; four sub-pixels in the fifth pixel and the sixth pixel are connected to the nth row scan line, and the other two sub-pixels in the fifth pixel and the sixth pixel are connected to the n+1th row scan line; two sub-pixels in the seventh pixel and the eighth pixel are connected to the n+2th row scan line, and the other four sub-pixels in the seventh pixel and the eighth pixel are connected to the n+3th row scan line.

[0009] Among them, two sub-pixels in the first pixel and the second pixel are connected to the nth row scan line, and the other four sub-pixels in the first pixel and the second pixel are connected to the n+1th row scan line; two sub-pixels in the third pixel and the fourth pixel are connected to the n+2th row scan line, and the other four sub-pixels in the third pixel and the fourth pixel are connected to the n+3th row scan line; four sub-pixels in the fifth pixel and the sixth pixel are connected to the nth row scan line, and the other two sub-pixels in the fifth pixel and the sixth pixel are connected to the n+1th row scan line; four sub-pixels in the seventh pixel and the eighth pixel are connected to the n+2th row scan line, and the other two sub-pixels in the seventh pixel and the eighth pixel are connected to the n+3th row scan line.

[0010] Among them, 4 sub-pixels in the first pixel and the second pixel are connected to the nth row scan line, and the other 2 sub-pixels in the first pixel and the second pixel are connected to the n+1th row scan line; 2 sub-pixels in the third pixel and the fourth pixel are connected to the n+2th row scan line, and the other 4 sub-pixels in the third pixel and the fourth pixel are connected to the n+3th row scan line; 2 sub-pixels in the fifth pixel and the sixth pixel are connected to the nth row scan line, and the other 4 sub-pixels in the fifth pixel and the sixth pixel are connected to the n+1th row scan line; 4 sub-pixels in the seventh pixel and the eighth pixel are connected to the n+2th row scan line, and the other 2 sub-pixels in the seventh pixel and the eighth pixel are connected to the n+3th row scan line.

[0011] When the DLG mode is turned on, the n+1th scan line and the n+3th scan line are turned on simultaneously, and then the n+2th scan line and the n+4th scan line are turned on simultaneously.

[0012] Among them, when the EVA mode is turned on, along the data line direction, the polarities of multiple sub-pixels are distributed according to positive, positive, negative, negative, positive, positive, negative, and negative; along the scan line direction, the polarities of multiple sub-pixels are distributed according to positive, negative, negative, positive, positive, negative, negative, and positive.

[0013] When performing pixel display, each data line outputs data of the same polarity within a frame, and performs polarity inversion in a column inversion manner.

[0014] In a second aspect, the present application provides a driving circuit for a display panel, comprising a gate driving circuit and a pixel driving circuit as provided in the first aspect, wherein the gate driving circuit comprises a plurality of gate driving units, and the plurality of gate driving units are respectively connected one-to-one with the scanning lines in the pixel driving circuit.

[0015] In a third aspect, the present application provides a display panel, comprising the pixel driving circuit provided in the first aspect or the display panel driving circuit provided in the second aspect.

[0016] The beneficial effects of the present application are as follows: different from the prior art, the pixel driving circuit, the display panel driving circuit and the display panel provided by the present application include eight pixels arranged in a 2×4 pattern in each pixel sub-region, each pixel includes three sub-pixels of different colors, and the eight pixels are respectively a first pixel, a second pixel, a third pixel, a fourth pixel, a fifth pixel, a sixth pixel, a seventh pixel and an eighth pixel; wherein, at least 2m sub-pixels in the first pixel and the second pixel are connected to the nth row of scan lines, and the remaining sub-pixels in the first pixel and the second pixel are connected to the n+1th row of scan lines; at least 2p sub-pixels in the third pixel and the fourth pixel are connected to the n+2th row of scan lines. The remaining sub-pixels in the third pixel and the fourth pixel are connected to the n+3th row scan line; at least 2q sub-pixels in the fifth pixel and the sixth pixel are connected to the nth row scan line, and the remaining sub-pixels in the fifth pixel and the sixth pixel are connected to the n+1th row scan line; at least 2r sub-pixels in the seventh pixel and the eighth pixel are connected to the n+2th row scan line, and the remaining sub-pixels in the seventh pixel and the eighth pixel are connected to the n+3th row scan line; wherein, n is a natural number greater than or equal to 1, m, p, q, and r are natural numbers greater than or equal to 2, 2m sub-pixels, 2p sub-pixels, 2q sub-pixels, and 2r sub-pixels come from different pixels, which can be equivalent to the Flip Pixel architecture to realize the DLG function, and further realize the EVA function, and the brightness and polarity are evenly arranged, the display taste effect is good, and it is particularly suitable for high refresh and high resolution products with DLG function. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0018] Figure 1 This is a schematic structural diagram of an embodiment of a pixel driving circuit provided by the present application;

[0019] Figure 2 is a structural diagram of another embodiment of the pixel driving circuit provided by the present application;

[0020] Figure 3 is a structural diagram of another embodiment of the pixel driving circuit provided by the present application;

[0021] Figure 4 is a structural diagram of another embodiment of the pixel driving circuit provided by the present application;

[0022] Figure 5 is a structural diagram of another embodiment of the pixel driving circuit provided by the present application;

[0023] Figure 6 1 is a schematic structural diagram of an embodiment of a driving circuit for a display panel provided in the present application;

[0024] Figure 7 is a structural diagram of an embodiment of a display panel provided by the present application;

[0025] Figure 8 It is a structural schematic diagram of another embodiment of the display panel provided by the present application. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some, rather than all, structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0027] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0028] In the field of display panel technology, EVA (Extended Viewing Angle) technology works by presenting different grayscale brightness on adjacent sub-pixels. For example, compared to the original display image, EVA technology controls odd sub-pixels to be brighter and even sub-pixels to be darker, and so on. When splitting, the macro brightness of the odd and even sub-pixels must be kept unchanged. Adjacent sub-pixels have different grayscale voltages, and the liquid crystal has different rotation angles. The light emission angle is wider to widen the viewing angle.

[0029] The display industry is pursuing increasingly higher refresh rates. A recent technology, called DLG (Dual Line Gate), has emerged, which uses low refresh rates to drive high refresh rates. For example, a 4K×2K UHD 60Hz display can be displayed as a 4K×1K UHD 120Hz display by adjusting the timing. Similarly, a 4K×2K UHD 120Hz display can be displayed as a 4K×1K UHD 240Hz display by adjusting the timing. Because the total amount of data displayed is the same, the specifications of the driver components remain the same, with no additional cost. The refresh rate is doubled simply by adjusting the timing, though the resolution is halved. End users can freely switch between these two display states using a remote control.

[0030] In DLG mode, 4K2K becomes 4K1K, 2 rows of pixels are merged into one row, and the horizontal scanning signal of the pixel driving circuit turns on two rows at the same time. When charging 1K rows normally in the same time, 2K rows are charged in DLG mode, so the refresh rate changes from 120Hz to 240Hz, and the cycle changes from 10H to 5H.

[0031] In the Flip Pixel, or Z-architecture, pixel driver circuitry allows two adjacent rows of sub-pixels on the same data line to represent different colors, preventing merging of these two rows of sub-pixels. This means it doesn't support DLG. However, it uses column inversion for low power consumption, and dot inversion for display, resulting in better display uniformity and quality.

[0032] The strip architecture's column inversion also offers significant advantages in terms of power consumption. Within a frame, the data lines are charged and discharged without polarity reversal. However, this architecture exhibits poor display uniformity. Within the same column, within the same grayscale, there is a slight asymmetry between the positive and negative polarities. Horizontal movement can produce a sense of vertical streaks, which are more noticeable in solid colors with low grayscale. Furthermore, vertical crosstalk is a common artifact.

[0033] Furthermore, in EVA technology, the horizontal and vertical sub-pixels are bright and dark, combined with Figure 1 , the level is positive-negative-positive-negative (the next frame is negative-positive-negative-positive), so the bright and dark are of the same polarity, which is easy to produce horizontal crosstalk. The level uses positive-negative-negative-positive-positive-negative-positive to break the same polarity bright and dark rule, but Figure 1 The Strip architecture itself is prone to head shakes, and two consecutive horizontal rows of the same polarity exacerbate these shakes. EVA technology utilizes pixel drive circuits, with horizontal and vertical subpixels displaying a constant pattern of bright and dark. The Z architecture uses both positive and negative subpixels, resulting in a flickering effect. The vertical use of positive-negative-positive-positive-negative-positive disrupts the same polarity pattern of bright and dark. Vertical polarity switching consumes excessive data line power and causes severe driver heat generation. The horizontal use of positive-negative-positive-positive-negative-positive disrupts the same polarity pattern of bright and dark. Two consecutive horizontal rows of the same polarity also cause head shakes.

[0034] Based on this, this application proposes any of the following technical solutions to solve at least one of the above technical problems.

[0035] Specifically, the pixel driving circuit provided in the present application includes multiple scan lines and multiple data lines, as well as multiple pixels driven by the multiple scan lines and the multiple data lines respectively. Along the data line direction, the multiple pixels are divided into multiple pixel areas, and along the scan line direction, each pixel area is divided into multiple pixel sub-areas, each pixel sub-area includes eight pixels arranged in a 2×4 pattern, each pixel includes three sub-pixels of different colors, and the eight pixels are respectively a first pixel, a second pixel, a third pixel, a fourth pixel, a fifth pixel, a sixth pixel, a seventh pixel and an eighth pixel.

[0036] Among them, at least 2m sub-pixels in the first pixel and the second pixel are connected to the nth row scan line, and the remaining sub-pixels in the first pixel and the second pixel are connected to the n+1th row scan line; at least 2p sub-pixels in the third pixel and the fourth pixel are connected to the n+2th row scan line, and the remaining sub-pixels in the third pixel and the fourth pixel are connected to the n+3th row scan line; at least 2q sub-pixels in the fifth pixel and the sixth pixel are connected to the nth row scan line, and the remaining sub-pixels in the fifth pixel and the sixth pixel are connected to the n+1th row scan line; at least 2r sub-pixels in the seventh pixel and the eighth pixel are connected to the n+2th row scan line, and the remaining sub-pixels in the seventh pixel and the eighth pixel are connected to the n+3th row scan line; wherein n is a natural number greater than or equal to 1, m, p, q, and r are natural numbers greater than or equal to 2, and the 2m sub-pixels, 2p sub-pixels, 2q sub-pixels, and 2r sub-pixels come from different pixels.

[0037] In some embodiments, as Figure 2 As shown, the pixel driving circuit includes multiple scan lines (such as Gn, Gn+1, Gn+2, Gn+3) and multiple data lines (such as Dn, Dn+1, Dn+2, Dn+3, Dn+4, Dn+5, Dn+6), and multiple pixels driven by the multiple scan lines and the multiple data lines respectively. Along the data line direction, the multiple pixels are divided into multiple pixel areas, and along the scan line direction, each pixel area is divided into multiple pixel sub-areas, each pixel sub-area includes eight pixels arranged in 2×4, each pixel includes three sub-pixels of different colors, and the eight pixels are respectively a first pixel 1, a second pixel 2, a third pixel 3, a fourth pixel 4, a fifth pixel 5, a sixth pixel 6, a seventh pixel 7 and an eighth pixel 8.

[0038] Among them, four sub-pixels in the first pixel 1 and the second pixel 2 are connected to the nth row of scan line (Gn), and the other two sub-pixels in the first pixel 1 and the second pixel 2 are connected to the n+1th row of scan line (Gn+1).

[0039] Four sub-pixels in the third pixel 3 and the fourth pixel 4 are connected to the n+2th scan line (Gn+2), and the other two sub-pixels in the third pixel 3 and the fourth pixel 4 are connected to the n+3th scan line (Gn+3).

[0040] Two sub-pixels in the fifth pixel 5 and the sixth pixel 6 are connected to the n-th scan line (Gn), and the other four sub-pixels in the fifth pixel 5 and the sixth pixel 6 are connected to the n+1-th scan line (Gn+1).

[0041] Two sub-pixels in the seventh pixel 7 and the eighth pixel 8 are connected to the n+2th scan line (Gn+2), and the other four sub-pixels in the seventh pixel 7 and the eighth pixel 8 are connected to the n+3th scan line (Gn+3).

[0042] Specifically, each pixel includes three sub-pixels: red, green, and blue. Therefore, the red and green sub-pixels in the first pixel 1 and the green and blue sub-pixels in the second pixel 2 are connected to the nth scan line (Gn), and the blue sub-pixel in the first pixel 1 and the red sub-pixel in the second pixel 2 are connected to the n+1th scan line (Gn+1).

[0043] The red sub-pixel and green sub-pixel in the third pixel 3, the green sub-pixel and blue sub-pixel in the fourth pixel 4 are connected to the n+2th scan line (Gn+2), and the blue sub-pixel in the third pixel 3 and the red sub-pixel in the fourth pixel 4 are connected to the n+3th scan line (Gn+3).

[0044] The blue sub-pixel in the fifth pixel 5 and the red sub-pixel in the sixth pixel 6 are connected to the nth scan line (Gn), and the red sub-pixel, green sub-pixel in the fifth pixel 5 and the green sub-pixel and blue sub-pixel in the sixth pixel 6 are connected to the n+1th scan line (Gn+1).

[0045] The blue sub-pixel in the seventh pixel 7 and the red sub-pixel in the eighth pixel 8 are connected to the n+2th scan line (Gn+2), and the red sub-pixel and green sub-pixel in the seventh pixel 7 and the green sub-pixel and blue sub-pixel in the eighth pixel 8 are connected to the n+3th scan line (Gn+3).

[0046] like Figure 2In the pixel driving circuit shown, 4 rows and 6 columns form a minimum unit. When Gn is turned on, the signals output by the data side are R11 / G11 / G12 / B12 / B31 / R32 respectively (the letters R / G / B represent the three colors of red, green and blue. The first number represents the row number, and the second number represents the pixel number, such as R32 represents the red sub-pixel of the second pixel in the third row); when Gn+1 is turned on, the signals output by the data side are B11 / R12 / R31 / G31 / G32 / B32 respectively; when Gn+2 is turned on, the signals output by the data side are R21 / G21 / G22 / B22 / B41 / R42 respectively; when Gn+3 is turned on, the signals output by the data side are B21 / R22 / R41 / G41 / G42 / B42 respectively.

[0047] As can be seen from the above, each scanning line Gn controls two rows to be turned on at the same time. The number of sub-pixels turned on in the first row and the second row is 2+4 or 4+2 (taking Gn as an example, Figure 2 When G1 is turned on, the 4 sub-pixels in the first row and the 2 sub-pixels in the third row are turned on, which is the so-called 4+2 combination. Gn+1 turns on the 2 sub-pixels in the first row and the 4 sub-pixels in the third row, which is the so-called 2+4 combination). The number of the first turned-on sub-pixels in Gn / Gn+1 / Gn+2 / Gn+3 is the connection structure code, such as Figure 2 As shown, it can be defined as a 1G1D-4242 architecture (the first line of G1 turns on 4 sub-pixels, the first line of G2 turns on 2 sub-pixels, the first line of G3 turns on 4 sub-pixels, and the first line of G4 turns on 2 sub-pixels).

[0048] In some embodiments, Figure 2 When the DLG mode is enabled, the pixel driver circuit shown simultaneously turns on the n+1th scan line (Gn+1) and the n+3th scan line (Gn+3), and then simultaneously turns on the n+2th scan line (Gn+2) and the n+4th scan line (Gn+4). This pixel driver circuit structure is equivalent to a flip pixel architecture to implement the DLG function.

[0049] In some embodiments, Figure 2 When the pixel driving circuit shown is in EVA mode, the polarities of the plurality of sub-pixels are distributed in the direction of the data line according to "positive, positive, negative, negative, positive, positive, negative, negative"; and the polarities of the plurality of sub-pixels are distributed in the direction of the scan line according to "positive, negative, negative, positive, positive, negative, negative, positive". Figure 2, the polarity of the red sub-pixel of the first pixel 1 is positive, the polarity of the green sub-pixel is negative, and the polarity of the blue sub-pixel is negative; the polarity of the red sub-pixel of the second pixel 2 is positive, the polarity of the green sub-pixel is positive, and the polarity of the blue sub-pixel is negative; the polarity of the red sub-pixel of the third pixel 3 is positive, the polarity of the green sub-pixel is negative, and the polarity of the blue sub-pixel is negative; the polarity of the red sub-pixel of the fourth pixel 4 is positive, the polarity of the green sub-pixel is positive, and the polarity of the blue sub-pixel is negative. , the polarity of the red sub-pixel of the fifth pixel 5 is negative, the polarity of the green sub-pixel is positive, and the polarity of the blue sub-pixel is positive, the polarity of the red sub-pixel of the sixth pixel 6 is negative, the polarity of the green sub-pixel is negative, and the polarity of the blue sub-pixel is positive, the polarity of the red sub-pixel of the seventh pixel 7 is negative, the polarity of the green sub-pixel is positive, and the polarity of the blue sub-pixel is positive, and the polarity of the red sub-pixel of the eighth pixel 8 is negative, the polarity of the green sub-pixel is negative, and the polarity of the blue sub-pixel is positive.

[0050] That is, after turning on EVA, the horizontal direction also uses positive-negative-positive-positive-negative-positive to break the same polarity light and dark rule, so as to expand the viewing angle effect. The picture will not have the problem of displaying the same polarity in the same column, and there is no shaking head wrinkle. The vertical direction is positive-positive-negative-positive-positive-negative-positive, and the polarity switches, which is not easy to produce crosstalk. Overall, it presents a large dot inversion with four sub-pixels as one dot (the polarity of each four sub-pixels is opposite up and down, left and right), and the macro polarity is uniform.

[0051] In some embodiments, Figure 2 When the pixel driving circuit is performing pixel display, each data line outputs data of the same polarity within a frame and performs polarity reversal in a column reversal manner, thereby reducing power consumption.

[0052] In actual application, corresponding functions can be selected for display according to actual needs.

[0053] Through the above-mentioned pixel driving circuit, the equivalent Flip Pixel architecture can be used to realize the DLG function, and further the EVA function can be realized. The brightness and polarity are evenly arranged, the display effect is good, and it is particularly suitable for high-refresh, high-resolution products with DLG function.

[0054] In another embodiment, Figure 3As shown, the pixel driving circuit includes multiple scan lines (such as Gn, Gn+1, Gn+2, Gn+3) and multiple data lines (such as Dn, Dn+1, Dn+2, Dn+3, Dn+4, Dn+5, Dn+6), and multiple pixels driven by the multiple scan lines and the multiple data lines respectively. Along the data line direction, the multiple pixels are divided into multiple pixel areas, and along the scan line direction, each pixel area is divided into multiple pixel sub-areas, each pixel sub-area includes eight pixels arranged in 2×4, each pixel includes three sub-pixels of different colors, and the eight pixels are respectively a first pixel 1, a second pixel 2, a third pixel 3, a fourth pixel 4, a fifth pixel 5, a sixth pixel 6, a seventh pixel 7 and an eighth pixel 8.

[0055] Among them, two sub-pixels in the first pixel 1 and the second pixel 2 are connected to the nth row scan line (Gn), and the other four sub-pixels in the first pixel 1 and the second pixel 2 are connected to the n+1th row scan line (Gn+1); four sub-pixels in the third pixel 3 and the fourth pixel 4 are connected to the n+2th row scan line (Gn+2), and the other two sub-pixels in the third pixel 3 and the fourth pixel 4 are connected to the n+3th row scan line (Gn+3); four sub-pixels in the fifth pixel 5 and the sixth pixel 6 are connected to the nth row scan line (Gn), and the other two sub-pixels in the fifth pixel 5 and the sixth pixel 6 are connected to the n+1th row scan line (Gn+1); two sub-pixels in the seventh pixel 7 and the eighth pixel 8 are connected to the n+2th row scan line (Gn+2), and the other four sub-pixels in the seventh pixel 7 and the eighth pixel 8 are connected to the n+3th row scan line (Gn+3).

[0056] Specifically, each pixel includes three sub-pixels: red, green, and blue. Therefore, the red and green sub-pixels in the first pixel 1 and the green and blue sub-pixels in the second pixel 2 are connected to the n+1th scan line (Gn+1), and the blue sub-pixel in the first pixel 1 and the red sub-pixel in the second pixel 2 are connected to the nth scan line (Gn).

[0057] The red sub-pixel and green sub-pixel in the third pixel 3, the green sub-pixel and blue sub-pixel in the fourth pixel 4 are connected to the n+2th scan line (Gn+2), and the blue sub-pixel in the third pixel 3 and the red sub-pixel in the fourth pixel 4 are connected to the n+3th scan line (Gn+3).

[0058] The blue sub-pixel in the fifth pixel 5 and the red sub-pixel in the sixth pixel 6 are connected to the n+1th scan line (Gn+1), and the red sub-pixel and green sub-pixel in the fifth pixel 5 and the green sub-pixel and blue sub-pixel in the sixth pixel 6 are connected to the nth scan line (Gn).

[0059] The blue sub-pixel in the seventh pixel 7 and the red sub-pixel in the eighth pixel 8 are connected to the n+2th scan line (Gn+2), and the red sub-pixel and green sub-pixel in the seventh pixel 7 and the green sub-pixel and blue sub-pixel in the eighth pixel 8 are connected to the n+3th scan line (Gn+3).

[0060] like Figure 3 In the pixel driving circuit shown, 4 rows and 6 columns form a minimum unit. When Gn is turned on, the signals output by the data side are B11 / R12 / R31 / G31 / G32 / B32 (the letters R / G / B represent the three colors red, green and blue. The first number represents the row number, and the second number represents the pixel number, such as B32 represents the blue sub-pixel of the second pixel in the third row); when Gn+1 is turned on, the signals output by the data side are R11 / G11 / G12 / B12 / B31 / R32; when Gn+2 is turned on, the signals output by the data side are R21 / G21 / G22 / B22 / B41 / R42; when Gn+3 is turned on, the signals output by the data side are B21 / R22 / R41 / G41 / G42 / B42.

[0061] As can be seen from the above, each scanning line Gn controls two rows to be turned on at the same time. The number of sub-pixels turned on in the first row and the second row is 2+4 or 4+2 (taking Gn as an example, Figure 3 When G1 is turned on, it will turn on the 2 sub-pixels in the first row and the 4 sub-pixels in the third row, which is the so-called 2+4 combination. Gn+1 will turn on the 4 sub-pixels in the first row and the 2 sub-pixels in the third row, which is the so-called 4+2 combination). The number of the first turned-on sub-pixels in Gn / Gn+1 / Gn+2 / Gn+3 is the connection structure code, such as Figure 3 As shown, it can be defined as a 1G1D-2442 architecture (the first line of G1 turns on 2 sub-pixels, the first line of G2 turns on 4 sub-pixels, the first line of G3 turns on 4 sub-pixels, and the first line of G4 turns on 2 sub-pixels).

[0062] In some embodiments, Figure 3 When the DLG mode is enabled, the pixel driver circuit shown simultaneously turns on the n+1th scan line (Gn+1) and the n+3th scan line (Gn+3), and then simultaneously turns on the n+2th scan line (Gn+2) and the n+4th scan line (Gn+4). This pixel driver circuit structure is equivalent to a flip pixel architecture to implement the DLG function.

[0063] In some embodiments, Figure 3When the pixel driving circuit shown is in EVA mode, the polarities of multiple sub-pixels are distributed according to "positive, positive, negative, negative, positive, positive, negative, negative" along the data line direction, and the polarities of multiple sub-pixels are distributed according to "positive, negative, negative, positive, positive, negative, negative, positive" along the scan line direction.

[0064] Combine Figure 3 , the polarity of the red sub-pixel of the first pixel 1 is positive, the polarity of the green sub-pixel is negative, and the polarity of the blue sub-pixel is negative; the polarity of the red sub-pixel of the second pixel 2 is positive, the polarity of the green sub-pixel is positive, and the polarity of the blue sub-pixel is negative; the polarity of the red sub-pixel of the third pixel 3 is positive, the polarity of the green sub-pixel is negative, and the polarity of the blue sub-pixel is negative; the polarity of the red sub-pixel of the fourth pixel 4 is positive, the polarity of the green sub-pixel is positive, and the polarity of the blue sub-pixel is negative. , the polarity of the red sub-pixel of the fifth pixel 5 is negative, the polarity of the green sub-pixel is positive, and the polarity of the blue sub-pixel is positive, the polarity of the red sub-pixel of the sixth pixel 6 is negative, the polarity of the green sub-pixel is negative, and the polarity of the blue sub-pixel is positive, the polarity of the red sub-pixel of the seventh pixel 7 is negative, the polarity of the green sub-pixel is positive, and the polarity of the blue sub-pixel is positive, and the polarity of the red sub-pixel of the eighth pixel 8 is negative, the polarity of the green sub-pixel is negative, and the polarity of the blue sub-pixel is positive.

[0065] That is, after turning on EVA, the horizontal direction also uses positive-negative-positive-positive-negative-positive to break the same polarity light and dark rule, so as to expand the viewing angle effect. The picture will not have the problem of displaying the same polarity in the same column, and there is no shaking head wrinkle. The vertical direction is positive-positive-negative-positive-positive-negative-positive, and the polarity switches, which is not easy to produce crosstalk. Overall, it presents a large dot inversion with four sub-pixels as one dot (the polarity of each four sub-pixels is opposite up and down, left and right), and the macro polarity is uniform.

[0066] In some embodiments, Figure 3 When the pixel driving circuit is performing pixel display, each data line outputs data of the same polarity within a frame and performs polarity reversal in a column reversal manner, thereby reducing power consumption.

[0067] In actual application, corresponding functions can be selected for display according to actual needs.

[0068] In another embodiment, Figure 4As shown, the pixel driving circuit includes multiple scan lines (such as Gn, Gn+1, Gn+2, Gn+3) and multiple data lines (such as Dn, Dn+1, Dn+2, Dn+3, Dn+4, Dn+5, Dn+6), and multiple pixels driven by the multiple scan lines and the multiple data lines respectively. Along the data line direction, the multiple pixels are divided into multiple pixel areas, and along the scan line direction, each pixel area is divided into multiple pixel sub-areas, each pixel sub-area includes eight pixels arranged in 2×4, each pixel includes three sub-pixels of different colors, and the eight pixels are respectively a first pixel 1, a second pixel 2, a third pixel 3, a fourth pixel 4, a fifth pixel 5, a sixth pixel 6, a seventh pixel 7 and an eighth pixel 8.

[0069] Among them, two sub-pixels in the first pixel 1 and the second pixel 2 are connected to the nth row scan line (Gn), and the other four sub-pixels in the first pixel 1 and the second pixel 2 are connected to the n+1th row scan line (Gn+1); two sub-pixels in the third pixel 3 and the fourth pixel 4 are connected to the n+2th row scan line (Gn+2), and the other four sub-pixels in the third pixel 3 and the fourth pixel 4 are connected to the n+3th row scan line (Gn+3); four sub-pixels in the fifth pixel 5 and the sixth pixel 6 are connected to the nth row scan line (Gn), and the other two sub-pixels in the fifth pixel 5 and the sixth pixel 6 are connected to the n+1th row scan line (Gn+1); four sub-pixels in the seventh pixel 7 and the eighth pixel 8 are connected to the n+2th row scan line (Gn+2), and the other two sub-pixels in the seventh pixel 7 and the eighth pixel 8 are connected to the n+3th row scan line (Gn+3).

[0070] Specifically, each pixel includes three sub-pixels: red, green, and blue. Therefore, the red and green sub-pixels in the first pixel 1 and the green and blue sub-pixels in the second pixel 2 are connected to the n+1th scan line (Gn+1), and the blue sub-pixel in the first pixel 1 and the red sub-pixel in the second pixel 2 are connected to the nth scan line (Gn+2).

[0071] The red sub-pixel and green sub-pixel in the third pixel 3, the green sub-pixel and blue sub-pixel in the fourth pixel 4 are connected to the n+3th scan line (Gn+3), and the blue sub-pixel in the third pixel 3 and the red sub-pixel in the fourth pixel 4 are connected to the n+2th scan line (Gn+2).

[0072] The blue sub-pixel in the fifth pixel 5 and the red sub-pixel in the sixth pixel 6 are connected to the n+1th scan line (Gn+1), and the red sub-pixel and green sub-pixel in the fifth pixel 5 and the green sub-pixel and blue sub-pixel in the sixth pixel 6 are connected to the nth scan line (Gn).

[0073] The blue sub-pixel in the seventh pixel 7 and the red sub-pixel in the eighth pixel 8 are connected to the n+3th scan line (Gn+3), and the red sub-pixel and green sub-pixel in the seventh pixel 7 and the green sub-pixel and blue sub-pixel in the eighth pixel 8 are connected to the n+2th scan line (Gn+2).

[0074] like Figure 4 In the pixel driving circuit shown, 4 rows and 6 columns form a minimum unit. When Gn is turned on, the signals output by the data side are B11 / R12 / R31 / G31 / G32 / B32 (the letters R / G / B represent the three colors red, green and blue. The first number represents the row number, and the second number represents the pixel number, such as B32 represents the blue sub-pixel of the second pixel in the third row); when Gn+1 is turned on, the signals output by the data side are R11 / G11 / G12 / B12 / B31 / R32; when Gn+2 is turned on, the signals output by the data side are B21 / R22 / R41 / G41 / G42 / B42; when Gn+3 is turned on, the signals output by the data side are R21 / G21 / G22 / B22 / B41 / R42.

[0075] As can be seen from the above, each scanning line Gn controls two rows to be turned on at the same time. The number of sub-pixels turned on in the first row and the second row is 2+4 or 4+2 (taking Gn as an example, Figure 4 When G1 is turned on, it will turn on the 2 sub-pixels in the first row and the 4 sub-pixels in the third row, which is the so-called 2+4 combination. Gn+1 will turn on the 4 sub-pixels in the first row and the 2 sub-pixels in the third row, which is the so-called 4+2 combination). The number of the first turned-on sub-pixels in Gn / Gn+1 / Gn+2 / Gn+3 is the connection structure code, such as Figure 2 As shown, it can be defined as a 1G1D-2424 architecture (the first line of G1 turns on 2 sub-pixels, the first line of G2 turns on 4 sub-pixels, the first line of G3 turns on 2 sub-pixels, and the first line of G4 turns on 4 sub-pixels).

[0076] In some embodiments, Figure 4 When the DLG mode is enabled, the pixel driver circuit shown simultaneously turns on the n+1th scan line (Gn+1) and the n+3th scan line (Gn+3), and then simultaneously turns on the n+2th scan line (Gn+2) and the n+4th scan line (Gn+4). This pixel driver circuit structure is equivalent to a flip pixel architecture to implement the DLG function.

[0077] In some embodiments, Figure 4When the pixel driving circuit shown is in EVA mode, the polarities of multiple sub-pixels are distributed according to "positive, positive, negative, negative, positive, positive, negative, negative" along the data line direction, and the polarities of multiple sub-pixels are distributed according to "positive, negative, negative, positive, positive, negative, negative, positive" along the scan line direction.

[0078] Combine Figure 4 , the polarity of the red sub-pixel of the first pixel 1 is positive, the polarity of the green sub-pixel is negative, and the polarity of the blue sub-pixel is negative; the polarity of the red sub-pixel of the second pixel 2 is positive, the polarity of the green sub-pixel is positive, and the polarity of the blue sub-pixel is negative; the polarity of the red sub-pixel of the third pixel 3 is positive, the polarity of the green sub-pixel is negative, and the polarity of the blue sub-pixel is negative; the polarity of the red sub-pixel of the fourth pixel 4 is positive, the polarity of the green sub-pixel is positive, and the polarity of the blue sub-pixel is negative. , the polarity of the red sub-pixel of the fifth pixel 5 is negative, the polarity of the green sub-pixel is positive, and the polarity of the blue sub-pixel is positive, the polarity of the red sub-pixel of the sixth pixel 6 is negative, the polarity of the green sub-pixel is negative, and the polarity of the blue sub-pixel is positive, the polarity of the red sub-pixel of the seventh pixel 7 is negative, the polarity of the green sub-pixel is positive, and the polarity of the blue sub-pixel is positive, and the polarity of the red sub-pixel of the eighth pixel 8 is negative, the polarity of the green sub-pixel is negative, and the polarity of the blue sub-pixel is positive.

[0079] That is, after turning on EVA, the horizontal direction also uses positive-negative-positive-positive-negative-positive to break the same polarity light and dark rule, so as to expand the viewing angle effect. The picture will not have the problem of displaying the same polarity in the same column, and there is no shaking head wrinkle. The vertical direction is positive-positive-negative-positive-positive-negative-positive, and the polarity switches, which is not easy to produce crosstalk. Overall, it presents a large dot inversion with four sub-pixels as one dot (the polarity of each four sub-pixels is opposite up and down, left and right), and the macro polarity is uniform.

[0080] In some embodiments, Figure 4 When the pixel driving circuit is performing pixel display, each data line outputs data of the same polarity within a frame and performs polarity reversal in a column reversal manner, thereby reducing power consumption.

[0081] In actual application, corresponding functions can be selected for display according to actual needs.

[0082] In another embodiment, Figure 5As shown, the pixel driving circuit includes multiple scan lines (such as Gn, Gn+1, Gn+2, Gn+3) and multiple data lines (such as Dn, Dn+1, Dn+2, Dn+3, Dn+4, Dn+5, Dn+6), and multiple pixels driven by the multiple scan lines and the multiple data lines respectively. Along the data line direction, the multiple pixels are divided into multiple pixel areas, and along the scan line direction, each pixel area is divided into multiple pixel sub-areas, each pixel sub-area includes eight pixels arranged in 2×4, each pixel includes three sub-pixels of different colors, and the eight pixels are respectively a first pixel 1, a second pixel 2, a third pixel 3, a fourth pixel 4, a fifth pixel 5, a sixth pixel 6, a seventh pixel 7 and an eighth pixel 8.

[0083] Among them, four sub-pixels in the first pixel 1 and the second pixel 2 are connected to the n-th row scan line (Gn), and the other two sub-pixels in the first pixel 1 and the second pixel 2 are connected to the n+1-th row scan line (Gn+1). Two sub-pixels in the third pixel 3 and the fourth pixel 4 are connected to the n+2-th row scan line (Gn+2), and the other four sub-pixels in the third pixel 3 and the fourth pixel 4 are connected to the n+3-th row scan line (Gn+3).

[0084] Two sub-pixels in the fifth pixel 5 and the sixth pixel 6 are connected to the n-th scan line (Gn), and the other four sub-pixels in the fifth pixel 5 and the sixth pixel 6 are connected to the n+1-th scan line (Gn+1).

[0085] Four sub-pixels in the seventh pixel 7 and the eighth pixel 8 are connected to the n+2th scan line (Gn+2), and the other two sub-pixels in the seventh pixel 7 and the eighth pixel 8 are connected to the n+3th scan line (Gn+3).

[0086] Specifically, each pixel includes three sub-pixels: red, green, and blue. Therefore, the red and green sub-pixels in the first pixel 1 and the green and blue sub-pixels in the second pixel 2 are connected to the nth scan line (Gn), and the blue sub-pixel in the first pixel 1 and the red sub-pixel in the second pixel 2 are connected to the n+1th scan line (Gn+1).

[0087] The red sub-pixel and green sub-pixel in the third pixel 3, the green sub-pixel and blue sub-pixel in the fourth pixel 4 are connected to the n+3th scan line (Gn+3), and the blue sub-pixel in the third pixel 3 and the red sub-pixel in the fourth pixel 4 are connected to the n+2th scan line (Gn+2).

[0088] The blue sub-pixel in the fifth pixel 5 and the red sub-pixel in the sixth pixel 6 are connected to the nth scan line (Gn), and the red sub-pixel, green sub-pixel in the fifth pixel 5 and the green sub-pixel and blue sub-pixel in the sixth pixel 6 are connected to the n+1th scan line (Gn+1).

[0089] The blue sub-pixel in the seventh pixel 7 and the red sub-pixel in the eighth pixel 8 are connected to the n+3th scan line (Gn+3), and the red sub-pixel and green sub-pixel in the seventh pixel 7 and the green sub-pixel and blue sub-pixel in the eighth pixel 8 are connected to the n+2th scan line (Gn+2).

[0090] like Figure 5 In the pixel driving circuit shown, 4 rows and 6 columns form a minimum unit. When Gn is turned on, the signals output by the data side are R11 / G11 / G12 / B12 / B31 / R32 (the letters R / G / B represent the three colors of red, green and blue. The first number represents the row number, and the second number represents the pixel number, such as R32 represents the red sub-pixel of the second pixel in the third row); when Gn+1 is turned on, the signals output by the data side are B11 / R12 / R31 / G31 / G32 / B32; when Gn+2 is turned on, the signals output by the data side are B21 / R22 / R41 / G41 / G42 / B42; when Gn+3 is turned on, the signals output by the data side are R21 / G21 / G22 / B22 / B41 / R42.

[0091] As can be seen from the above, each scanning line Gn controls two rows to be turned on at the same time. The number of sub-pixels turned on in the first row and the second row is 2+4 or 4+2 (taking Gn as an example, Figure 5 When G1 is turned on, the 4 sub-pixels in the first row and the 2 sub-pixels in the third row are turned on, which is the so-called 4+2 combination. Gn+1 turns on the 2 sub-pixels in the first row and the 4 sub-pixels in the third row, which is the so-called 2+4 combination). The number of the first turned-on sub-pixels in Gn / Gn+1 / Gn+2 / Gn+3 is the connection structure code, such as Figure 5 As shown, it can be defined as a 1G1D-4224 architecture (the first line of G1 turns on 4 sub-pixels, the first line of G2 turns on 2 sub-pixels, the first line of G3 turns on 2 sub-pixels, and the first line of G4 turns on 4 sub-pixels).

[0092] In some embodiments, Figure 5 When the DLG mode is enabled, the pixel driver circuit shown simultaneously turns on the n+1th scan line (Gn+1) and the n+3th scan line (Gn+3), and then simultaneously turns on the n+2th scan line (Gn+2) and the n+4th scan line (Gn+4). This pixel driver circuit structure is equivalent to a flip pixel architecture to implement the DLG function.

[0093] In some embodiments, Figure 5In the pixel driving circuit shown, when the EVA mode is turned on, the polarities of multiple sub-pixels are distributed according to "positive, positive, negative, negative, positive, positive, negative, negative" along the data line direction, and the polarities of multiple sub-pixels are distributed according to "positive, negative, negative, positive, positive, negative, negative, positive" along the scan line direction.

[0094] Combine Figure 5 , the polarity of the red sub-pixel of the first pixel 1 is positive, the polarity of the green sub-pixel is negative, and the polarity of the blue sub-pixel is negative; the polarity of the red sub-pixel of the second pixel 2 is positive, the polarity of the green sub-pixel is positive, and the polarity of the blue sub-pixel is negative; the polarity of the red sub-pixel of the third pixel 3 is positive, the polarity of the green sub-pixel is negative, and the polarity of the blue sub-pixel is negative; the polarity of the red sub-pixel of the fourth pixel 4 is positive, the polarity of the green sub-pixel is positive, and the polarity of the blue sub-pixel is negative. , the polarity of the red sub-pixel of the fifth pixel 5 is negative, the polarity of the green sub-pixel is positive, and the polarity of the blue sub-pixel is positive, the polarity of the red sub-pixel of the sixth pixel 6 is negative, the polarity of the green sub-pixel is negative, and the polarity of the blue sub-pixel is positive, the polarity of the red sub-pixel of the seventh pixel 7 is negative, the polarity of the green sub-pixel is positive, and the polarity of the blue sub-pixel is positive, and the polarity of the red sub-pixel of the eighth pixel 8 is negative, the polarity of the green sub-pixel is negative, and the polarity of the blue sub-pixel is positive.

[0095] That is, after turning on EVA, the horizontal direction also uses positive-negative-positive-positive-negative-positive to break the same polarity light and dark rule, so as to expand the viewing angle effect. The picture will not have the problem of displaying the same polarity in the same column, and there is no shaking head wrinkle. The vertical direction is positive-positive-negative-positive-positive-negative-positive, and the polarity switches, which is not easy to produce crosstalk. Overall, it presents a large dot inversion with four sub-pixels as one dot (the polarity of each four sub-pixels is opposite up and down, left and right), and the macro polarity is uniform.

[0096] In some embodiments, Figure 5 When the pixel driving circuit is performing pixel display, each data line outputs data of the same polarity within a frame and performs polarity reversal in a column reversal manner, thereby reducing power consumption.

[0097] In actual application, corresponding functions can be selected for display according to actual needs.

[0098] In one application scenario, the display panel is composed of multiple display units with 4 rows and 6 columns as the minimum. The routing method of each unit can adopt different routing architecture combinations, such as Figure 2 、 Figure 3 、 Figure 4 and Figure 5Taking a 4K2K UD display as an example, with 2160 rows vertically and 3840*3 columns horizontally, the total number of possible combinations theoretically can reach (2160 / 4)*(3840*3 / 6)*4=540*1920*4=4147200.

[0099] See Figure 6 , Figure 6 1 is a schematic diagram of the structure of an embodiment of a display panel driving circuit provided in the present application. The display panel driving circuit 100 includes a gate driving circuit 10 and a pixel driving circuit 20. The gate driving circuit 10 includes a plurality of gate driving units (not shown), and the plurality of gate driving units are connected one-to-one to the scan lines in the pixel driving circuit 20. The pixel driving circuit 20 can be any of the pixel driving circuits described in the present application.

[0100] See Figure 7 , Figure 7 FIG1 is a schematic diagram of the structure of an embodiment of a display panel provided in the present application. The display panel 1000 includes a driving circuit 100 of the display panel.

[0101] See Figure 8 , Figure 8 FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present invention. The display panel 1000 includes a pixel driving circuit 20 .

[0102] In summary, the pixel driving circuit, the driving circuit of the display panel, and the display panel provided by the present application include eight pixels arranged in a 2×4 pattern in each pixel sub-region, each pixel including three sub-pixels of different colors, and the eight pixels are respectively a first pixel, a second pixel, a third pixel, a fourth pixel, a fifth pixel, a sixth pixel, a seventh pixel, and an eighth pixel; wherein, at least 2m sub-pixels in the first pixel and the second pixel are connected to the nth row of scan lines, and the remaining sub-pixels in the first pixel and the second pixel are connected to the n+1th row of scan lines; at least 2p sub-pixels in the third pixel and the fourth pixel are connected to the n+2th row of scan lines, and the third pixel and the fourth pixel are connected to the n+2th row of scan lines. The remaining sub-pixels in the fifth pixel and the sixth pixel are connected to the nth row scan line; at least 2q sub-pixels in the fifth pixel and the sixth pixel are connected to the nth row scan line, and the remaining sub-pixels in the fifth pixel and the sixth pixel are connected to the n+1th row scan line; at least 2r sub-pixels in the seventh pixel and the eighth pixel are connected to the n+2th row scan line, and the remaining sub-pixels in the seventh pixel and the eighth pixel are connected to the n+3th row scan line; wherein, n is a natural number greater than or equal to 1, m, p, q, r are natural numbers greater than or equal to 2, 2m sub-pixels, 2p sub-pixels, 2q sub-pixels, and 2r sub-pixels come from different pixels. Through the above-mentioned pixel driving circuit, the Flip Pixel architecture can be equivalent to realize the DLG function, and further realize the EVA function, and the brightness and polarity are evenly arranged, the display quality effect is good, and it is particularly suitable for high refresh rate and high resolution products with DLG function.

[0103] Furthermore, although the DRD architecture mode in the related art can also achieve the same effect as DLG and EVA, it does not have the low power advantage. DRD has a cost advantage, but it has a fatal disadvantage. DRD (2G1D) will halve the charging time. The time for a UHD 60Hz display at 1G1D is 1 / 60 / 2250 = 7.41uS, while the time for a UHD 60Hz display at DRD is 1 / 60 / (2250*2) = 3.705uS. The UHD 60Hz display at DRD can barely be fully charged, so a higher refresh rate cannot be fully charged. Now, with 1G1D, the DRD architecture cannot be used. The time for a line is 1 / 120 / (2250*2) = 1.85uS, which cannot fully charge the display and cannot meet the display requirements. Therefore, high-refresh and high-resolution products still require the 1G1D architecture. At the same time, taking into account the drive polarity uniformity, EVA wide viewing angle and DLG function, the technical solution of this application is particularly suitable.

[0104] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical functional division. In actual implementation, other division methods may be used, such as combining or integrating multiple units or components into another system, or ignoring or not implementing certain features.

[0105] If the integrated units in the above other embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0106] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A pixel driving circuit comprising a plurality of scan lines and a plurality of data lines, and a plurality of pixels driven by the plurality of scan lines and the plurality of data lines, wherein: Along the data line direction, the plurality of pixels are divided into a plurality of pixel areas, and along the scan line direction, each pixel area is divided into a plurality of pixel sub-areas, each pixel sub-area includes eight pixels arranged in a 2×4 pattern, each pixel includes three sub-pixels of different colors, and the eight pixels are respectively a first pixel, a second pixel, a third pixel, a fourth pixel, a fifth pixel, a sixth pixel, a seventh pixel, and an eighth pixel; At least 2m sub-pixels in the first pixel and the second pixel are connected to the nth scan line, and the remaining sub-pixels in the first pixel and the second pixel are connected to the n+1th scan line; at least 2p sub-pixels in the third pixel and the fourth pixel are connected to the n+2th scan line, and the remaining sub-pixels in the third pixel and the fourth pixel are connected to the n+3th scan line; At least 2q sub-pixels in the fifth pixel and the sixth pixel are connected to the nth row of scan lines, and the remaining sub-pixels in the fifth pixel and the sixth pixel are connected to the n+1th row of scan lines; At least 2r sub-pixels in the seventh pixel and the eighth pixel are connected to the (n+2)th scan line, and the remaining sub-pixels in the seventh pixel and the eighth pixel are connected to the (n+3)th scan line; Wherein, n is a natural number greater than or equal to 1, m, p, q, and r are natural numbers greater than or equal to 2, and the 2m sub-pixels, 2p sub-pixels, 2q sub-pixels, and 2r sub-pixels come from different pixels.

2. The pixel driving circuit according to claim 1, wherein: in, Four sub-pixels in the first pixel and the second pixel are connected to the nth row of scan lines, and the other two sub-pixels in the first pixel and the second pixel are connected to the n+1th row of scan lines; four sub-pixels in the third pixel and the fourth pixel are connected to the n+2th row of scan lines, and the other two sub-pixels in the third pixel and the fourth pixel are connected to the n+3th row of scan lines; Two sub-pixels in the fifth pixel and the sixth pixel are connected to the n-th scan line, and the other four sub-pixels in the fifth pixel and the sixth pixel are connected to the n+1-th scan line; Two sub-pixels in the seventh pixel and the eighth pixel are connected to the (n+2)th row of scan lines, and the other four sub-pixels in the seventh pixel and the eighth pixel are connected to the (n+3)th row of scan lines.

3. The pixel driving circuit according to claim 1, wherein: in, Two sub-pixels in the first pixel and the second pixel are connected to the nth row of scan lines, and the other four sub-pixels in the first pixel and the second pixel are connected to the n+1th row of scan lines; four sub-pixels in the third pixel and the fourth pixel are connected to the n+2th row of scan lines, and the other two sub-pixels in the third pixel and the fourth pixel are connected to the n+3th row of scan lines; Four sub-pixels in the fifth pixel and the sixth pixel are connected to the n-th row of scan lines, and the other two sub-pixels in the fifth pixel and the sixth pixel are connected to the n+1-th row of scan lines; Two sub-pixels in the seventh pixel and the eighth pixel are connected to the (n+2)th row of scan lines, and the other four sub-pixels in the seventh pixel and the eighth pixel are connected to the (n+3)th row of scan lines.

4. The pixel driving circuit according to claim 1, wherein: in, Two sub-pixels in the first pixel and the second pixel are connected to the nth row of scan lines, and the other four sub-pixels in the first pixel and the second pixel are connected to the n+1th row of scan lines; two sub-pixels in the third pixel and the fourth pixel are connected to the n+2th row of scan lines, and the other four sub-pixels in the third pixel and the fourth pixel are connected to the n+3th row of scan lines; Four sub-pixels in the fifth pixel and the sixth pixel are connected to the n-th row of scan lines, and the other two sub-pixels in the fifth pixel and the sixth pixel are connected to the n+1-th row of scan lines; Four sub-pixels in the seventh pixel and the eighth pixel are connected to the (n+2)th row of scan lines, and the other two sub-pixels in the seventh pixel and the eighth pixel are connected to the (n+3)th row of scan lines.

5. The pixel driving circuit according to claim 1, wherein: in, Four sub-pixels in the first pixel and the second pixel are connected to the nth row of scan lines, and the other two sub-pixels in the first pixel and the second pixel are connected to the n+1th row of scan lines; two sub-pixels in the third pixel and the fourth pixel are connected to the n+2th row of scan lines, and the other four sub-pixels in the third pixel and the fourth pixel are connected to the n+3th row of scan lines; Two sub-pixels in the fifth pixel and the sixth pixel are connected to the n-th scan line, and the other four sub-pixels in the fifth pixel and the sixth pixel are connected to the n+1-th scan line; Four sub-pixels in the seventh pixel and the eighth pixel are connected to the (n+2)th row of scan lines, and the other two sub-pixels in the seventh pixel and the eighth pixel are connected to the (n+3)th row of scan lines.

6. The pixel driving circuit according to claim 1, wherein: When the DLG mode is turned on, the n+1th scan line and the n+3th scan line are turned on simultaneously, and then the n+2th scan line and the n+4th scan line are turned on simultaneously.

7. The pixel driving circuit according to claim 1, wherein: When the EVA mode is turned on, along the data line direction, the polarities of multiple sub-pixels are distributed according to positive, positive, negative, negative, positive, positive, negative, and negative; along the scan line direction, the polarities of multiple sub-pixels are distributed according to positive, negative, negative, positive, positive, negative, negative, and positive.

8. The pixel driving circuit according to claim 1, wherein: When performing pixel display, each of the data lines outputs data of the same polarity within a frame, and performs polarity inversion in a column inversion manner.

9. A driving circuit for a display panel, characterized in that: It comprises a gate driving circuit and the pixel driving circuit according to any one of claims 1 to 8, wherein the gate driving circuit comprises a plurality of gate driving units, and the plurality of gate driving units are respectively connected to the scan lines in the pixel driving circuit in a one-to-one correspondence.

10. A display panel, characterized in that: The device comprises the pixel driving circuit according to any one of claims 1 to 8 or the display panel driving circuit according to claim 9.

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