storage device

Abstract

In the storage device of this embodiment, first and second inverter circuits are connected between first and second nodes. The first inverter circuit includes second and third transistors connected at a third node. The second inverter circuit includes fourth and fifth transistors connected at a fourth node. A sixth transistor is connected between the gate of the fifth transistor and the third node. A seventh transistor is connected between the gate of the third transistor and the fourth node. An eighth transistor is connected between the gate of the third transistor and the third node. A ninth transistor is connected between the gate of the fifth transistor and the fourth node. At a first moment, the gate voltages of the eighth and ninth transistors decrease, forming a state where first and second voltages are applied to the first and second nodes at a second moment. At a third moment, intermediate between the first and second moments, the gate voltages of the sixth and seventh transistors increase.

Description

[0001] [Citation of relevant applications]

[0002] This application asserts priority based on the priority of a prior Japanese patent application No. 2022-093593 filed on June 9, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The implementation generally relates to a storage device. Background Technology

[0004] As a storage device, DRAM (Dynamic Random Access Memory) is known. DRAM storage cells contain capacitors and transistors. Data is stored in a storage cell based on the charge stored in the capacitor. The stored data is identified by amplifying the voltage of the storage cell containing the data to be read using a sense amplifier. Summary of the Invention

[0005] One embodiment aims to provide a storage device that suppresses erroneous operations.

[0006] One embodiment of the storage device includes a capacitor, a first transistor, a first inverter circuit, a second inverter circuit, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor.

[0007] The first transistor is connected to the capacitor at its first terminal. The first inverter circuit is connected between the first and second nodes, and includes a p-type second transistor and an n-type third transistor connected in series at the third node. The second inverter circuit is connected between the first and second nodes, and includes a p-type fourth transistor and an n-type fifth transistor connected in series at the fourth node. The sixth transistor is connected between the gate of the fifth transistor and the third node. The seventh transistor is connected between the gate of the third transistor and the fourth node, and between the second terminal of the first transistor and the fourth node. The eighth transistor is connected between the gate of the third transistor and the third node. The ninth transistor is connected between the gate of the fifth transistor and the fourth node. At time 1, the voltage applied to the gates of the eighth and ninth transistors decreases. This creates a state where at time 2, a first voltage is applied to the first node, while a second voltage lower than the first voltage is applied to the second node. From the first moment to the third moment, which is between the first moment and the second moment, the voltage applied to the gate of the sixth transistor and the gate of the seventh transistor increases.

[0008] Based on the aforementioned configuration, a storage device that suppresses malfunctions can be provided. Attached Figure Description

[0009] Figure 1 This is a diagram showing the functional modules and related components of the storage device according to the first embodiment.

[0010] Figure 2 This is a diagram showing the constituent elements of the storage unit in the first embodiment and the connections between the constituent elements.

[0011] Figure 3 This is a diagram showing some of the constituent elements of the sensing amplifier in the first embodiment and the connections between the constituent elements.

[0012] Figure 4 This diagram shows the components of the readout circuit of the storage device according to the first embodiment and the connections between the components.

[0013] Figure 5 This is a diagram showing the signal waveform in the sensing amplifier control circuit of the storage device according to the time.

[0014] Figure 6 It is a diagram illustrating the potentials during data readout of several elements of the storage device of the first embodiment in a time-based schematic representation.

[0015] Figure 7 This is a diagram schematically showing the connection of the components of the sensing amplifier circuit of the storage device according to the first embodiment during the equalization period.

[0016] Figure 8 This is a diagram schematically illustrating the connections of the components of the sensing amplifier circuit of the storage device according to the first embodiment during offset elimination.

[0017] Figure 9 This is a diagram schematically illustrating the connection of the components of the sensing amplifier circuit of the storage device according to the first embodiment during charge sharing.

[0018] Figure 10 It is a diagram illustrating the potential during data readout of several elements of the storage device for reference in the first embodiment according to time.

[0019] Figure 11 It is a diagram that schematically represents the potential during the data readout period of several elements of the reference storage device according to time.

[0020] Figure 12 This is a diagram illustrating the potentials during data readout of several elements of the storage device in a variation of the first embodiment, in a time-based manner. Detailed Implementation

[0021] Hereinafter, embodiments will be described with reference to the accompanying drawings. For multiple constituent elements having substantially the same function and structure in a particular embodiment or different embodiments, numbers or characters may be appended to the end of the reference numerals to distinguish them from each other. In embodiments described following a previously described embodiment, aspects that differ from the previously described embodiment will be primarily described. Unless explicitly stated or obviously excluded, descriptions related to a particular embodiment may also be entirely applicable to descriptions of other embodiments.

[0022] In this specification and claims, the term "connecting" a first element to another second element includes cases where the first element is directly or always, or selectively, connected to the second element via an element that is conductive.

[0023] 1. First Embodiment 1.1. Structure (Configuration) Figure 1 The functional modules of the storage device in the first embodiment are shown. The storage device 1 is a device for storing data. The storage device 1 includes a storage cell array 11, an input / output circuit 12, a control circuit 13, a voltage generation circuit 14, a row selection circuit 15, a column selection circuit 16, a write circuit 17, a readout circuit 18, and a sensing amplifier 19.

[0024] The memory cell array 11 includes multiple memory cells (MCs), multiple word lines (WLs), and multiple bit lines (BLs). Each memory cell (MC) can store 1 bit of data. Each memory cell (MC) is connected to one bit line (BL) and one word line (WL). The memory cell (MC) is connected between the bit line (BL) and a plate line (not shown). The word line (WL) is associated with a row. The bit line (BL) is associated with a column. A memory cell (MC) is specified by selecting one row and one column.

[0025] Input / output circuit 12 is a circuit for inputting and outputting data and signals. Input / output circuit 12 receives control signals CNT, instructions CMD, address signals ADD, and data DAT from outside the storage device 1, such as from a memory controller. Input / output circuit 12 outputs data DAT. Data DAT is written data when data is written to the storage device 1. Data DAT is read data when data is read from the storage device 1.

[0026] The control circuit 13 is a circuit that controls the operation of the storage device 1. The control circuit 13 receives the instruction CMD and the control signal CNT from the input / output circuit 12. Based on the control indicated by the instruction CMD and the control signal CNT, the control circuit 13 controls the write circuit 17 and the read circuit 18.

[0027] The voltage generation circuit 14 is a circuit that generates various voltages to be used in the storage device 1. The voltage generation circuit 14 generates multiple voltages of different magnitudes based on the control of the control circuit 13. The voltage generation circuit 14 supplies the generated voltages to the storage cell array 11, the write circuit 17, the read circuit 18, and the sense amplifier 19.

[0028] Row selection circuit 15 is a circuit that selects the row of memory cell MC. Row selection circuit 15 receives address signal ADD from input / output circuit 12. Row selection circuit 15 uses the voltage received from voltage generation circuit 14 to make one word line WL associated with the row specified by the received address signal ADD selected.

[0029] Column selection circuit 16 is a circuit that selects a column of memory cell MC. Column selection circuit 16 receives address signal ADD from input / output circuit 12. Column selection circuit 16 uses the voltage received from voltage generation circuit 14 to make bit line BL, which is associated with the column specified by the received address signal ADD, selected.

[0030] The write circuit 17 is a circuit that performs processing and control for writing data to the memory cell MC. The write circuit 17 receives the data to be written from the input / output circuit 12. Based on the control and data from the control circuit 13, the write circuit 17 supplies the voltage received from the voltage generation circuit 14 to the column selection circuit 16.

[0031] The readout circuit 18 is a circuit that performs processing and control to read data from the storage unit MC. The readout circuit 18 determines the data stored in the storage unit MC based on the control of the control circuit 13. The determined data is supplied to the input / output circuit 12. The readout circuit 18 also supplies multiple control signals to the sense amplifier 19.

[0032] The sense amplifier 19 is a circuit used to determine the data stored in the memory cell MC. The sense amplifier 19 includes multiple sense amplifier circuits SAC (not shown). The sense amplifier 19 receives multiple voltages from the voltage generation circuit 14 and operates using the received voltages. During data readout, the sense amplifier 19 amplifies the potential on the bit line BL to determine the data stored in the memory cell MC that is the target of data readout.

[0033] 1.1.1. Storage Unit Figure 2 This shows the constituent elements of the storage unit in the first embodiment and the connections between these constituent elements. For example... Figure 2As shown, each memory cell MC includes a cell capacitor CC and an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) CT. The cell capacitor CC is connected at one end to the board line PL and at the other end to one end of the transistor CT. The cell capacitor CC uses the charge stored at the node connected to the transistor CT to store data. The node of the cell capacitor CC connected to the transistor CT is sometimes referred to hereinafter as the storage node SN.

[0034] The state of whether the storage node SN stores charge is established as a correspondence with the state of the storage cell MC storing "1" data or storing "0" data. As an example, the state of the storage node SN with a relatively positive potential is treated as the state of the storage cell MC storing "1" data, and the state of the storage node SN without a relatively positive potential is treated as the state of the storage cell MC storing "0" data.

[0035] The transistor CT is connected to a bit line BL at one end and to a word line WL at the gate.

[0036] 1.1.2. Sensing Amplifier Figure 3 This diagram illustrates some of the constituent elements and connections of the sensing amplifier 19 according to the first embodiment. As described above, the sensing amplifier 19 includes a plurality of sensing amplifier circuits (SACs). Figure 3 A sense amplifier circuit (SAC) is shown.

[0037] like Figure 3 As shown, each sense amplifier circuit (SAC) is connected to a bit line BL and a node ˉBL. The node ˉBL is sometimes referred to as the complementary bit line ˉBL below. The complementary bit line ˉBL functions as a node with a reference potential (or reference potential). The reference potential is used to determine the data stored in the memory cell MC, which is the object of data readout.

[0038] The sense amplifier circuit SAC includes p-type MOSFETs TP1 and TP2, and n-type MOSFETs TN1 to TN6. The sense amplifier 19 also includes transistors TN11 and TN12.

[0039] Transistor TP1 is connected between node SAP and node SAt. Node SAP receives voltage, for example, from voltage generation circuit 14. Node SAP receives one dynamically switching voltage from a plurality of voltages, including power supply voltage Vddsa and voltage Vddsa / 2. The power supply voltage Vddsa may have the same magnitude as the power supply voltage Vdd used in storage device 1, or it may have a different magnitude. Transistor TP1 is connected to node SAc at its gate. Transistor TP1 has a certain on-resistance during turn-on. The on-resistance of the transistor is the resistance during the transistor's turn-on period.

[0040] Transistor TN1 is connected between node SAt and node SAN. Node SAN receives voltage, for example, from voltage generation circuit 14. Node SAN receives one dynamically switching voltage from a plurality of voltages, including the power supply voltage Vddsa / 2 and the ground voltage (common voltage) Vss. The ground voltage Vss is, for example, 0V, and the following description is based on this example. Transistor TN1 is connected to a bit line BL at its gate. Transistor TN1 has a certain on-resistance.

[0041] Transistor TP2 is connected between node SAP and node SAc. Transistor TP2 is connected to node SAt at its gate. Transistor TP2 has an on-resistance substantially the same as that of transistor TP1. In this specification, the term "substantially identical" for a certain characteristic of two elements means that although the two elements are formed with the aim of being identical, instances where they are not exactly identical are permitted due to unavoidable reasons such as the limitations of the techniques used to manufacture and / or measure these elements.

[0042] Transistor TN2 is connected between node SAc and node SAN. Transistor TN2 is connected to its gate and complementary bit line BL. Transistor TN2 has a turn-on resistance that is substantially the same as that of transistor TN1.

[0043] Transistor TN3 is connected between node SAt and the gate of transistor TN1. Transistor TN3 receives signal OC at its gate. Signal OC is supplied, for example, from readout circuit 18.

[0044] Transistor TN4 is connected between the gate of node SAc and the gate of transistor TN2. Transistor TN4 receives signal OC at its gate.

[0045] Transistor TN5 is connected between node SAt and complementary bit line BL. Transistor TN5 receives signal ISO at its gate. Signal ISO is supplied, for example, from readout circuit 18. Transistor TN5 has, for example, substantially the same dimensions as transistor TN3. In this example, the parasitic capacitance of one of the source and drain terminals of transistor TN5 to the gate is substantially the same as the parasitic capacitance of one of the source and drain terminals of transistor TN3 to the gate.

[0046] Transistor TN6 is connected between node SAc and bit line BL. Transistor TN6 receives signal ISO at its gate. Transistor TN6 has, for example, substantially the same dimensions as transistor TN4. In this example, the parasitic capacitance of one of the source and drain terminals of transistor TN6 to the gate is substantially the same as the parasitic capacitance of one of the source and drain terminals of transistor TN4 to the gate.

[0047] Transistor TN11 is connected between at least one bit line BL and node NBP. Node NBP receives a pre-charge voltage Vpc from voltage generation circuit 14. The pre-charge voltage Vpc is (Vddsa - Vss) / 2; in the example where Vss is 0V, then the pre-charge voltage Vpc is Vddsa / 2, which can also function as a reference voltage. Transistor TN11 receives a signal EQ at its gate. The signal EQ is supplied, for example, from readout circuit 18.

[0048] Transistor TN12 is connected between at least one complementary bit line BL and node NBP. Transistor TN12 receives the signal EQ at its gate.

[0049] Transistors TP1 and TN1 form inverter circuit IV1, and transistors TP2 and TN2 form inverter circuit IV2. While transistors TN5 and TN6 are on, inverter circuits IV1 and IV2 are cross-connected. That is, the input and output nodes of inverter circuit IV1 are connected to the output and input nodes of inverter circuit IV2, respectively.

[0050] 1.1.3. Readout Circuit Figure 4 This shows the constituent elements and connections of the readout circuit of the storage device according to the first embodiment. For example... Figure 4 As shown, the readout circuit 18 includes a sense amplifier control circuit 181. The sense amplifier control circuit 181 includes a delay circuit DC, a pulse generation circuit PG, a NAND gate ND1, and an even number of inverter circuits, such as four inverter circuits IV1 to IV4.

[0051] The delay circuit DC is a circuit that outputs a signal obtained by delaying the signal received by the delay circuit DC. The delay circuit DC receives the digital signal ACT. The signal ACT is generated, for example, by other components in the readout circuit 18 based on an instruction to read instruction data received from the storage device 1. When the delay circuit DC receives the signal ACT, it begins to output the digital signal DEL after a predetermined time has elapsed since the reception time. The logic level of the signal DEL follows the logic level of the signal ACT, and changes according to the change in the logic level of the signal ACT after the delay time.

[0052] The pulse generation circuit PG is a circuit that generates a pulse signal based on the reception of a signal. The pulse generation circuit PG receives the signal ACT. When the pulse generation circuit PG receives the signal ACT, it outputs a digital signal OCx. The signal OCx remains high for the entire predetermined period.

[0053] The NAND gate ND1 receives signals DEL and OCx and outputs a digital signal ISOx. The output of the NAND gate ND1 is connected to an even number of inverter circuits connected in series. Figure 4 This example illustrates two inverter circuits, IV1 and IV2. Inverter circuit IV1 receives the signal ISOx and its output is connected to the input of inverter circuit IV2. Inverter circuit IV2 outputs the digital signal ISO.

[0054] The output of the pulse generation circuit PG is connected to an even number of inverter circuits connected in series. The group of inverter circuits connected in series with the pulse generation circuit PG contains the same number of inverter circuits as the number connected in series with the NAND gate ND1. Taking the example where inverter circuits IV1 and IV2 are connected to the NAND gate ND1, the pulse generation circuit PG is connected to two inverter circuits IV3 and IV4 connected in series. Inverter circuit IV3 receives the signal OCx and its output is connected to the input of inverter circuit IV4. Inverter circuit IV4 outputs the digital signal OC.

[0055] 1.2. Operation 1.2.1. Sensing Amplifier Control Circuit Figure 5 The signal waveform in the sensing amplifier control circuit of the storage device according to the first embodiment is represented by time. In the following description, the level of a certain signal is maintained until a time when the signal is recorded to change to another level.

[0056] exist Figure 5At the beginning of the period, signal ACT is low. At time t0, signal ACT is set to high. As signal ACT transitions to high, signal OCx transitions to high at time t1. As signal OCx transitions to high, signal OC transitions to high at time t2. The interval between time t1 and time t2 depends on the inverter circuit connected in series with the pulse generation circuit PG. Figure 4 The number of inverter circuits IV3 and IV4 in the example.

[0057] As signal ACT transitions to a high level at time t0, signal DEL transitions to a high level at time t3. The interval between time t0 and time t3 is consistent with the delay time of the delay circuit DC.

[0058] As signal DEL transitions high at time t3, signal ISOx transitions low at time t4. As signal ISOx transitions low, signal ISOx transitions low at time t5. The interval between time t4 and time t5 depends on the inverter circuit connected in series with the NAND gate ND1. Figure 4 The number of inverter circuits IV1 and IV2 in the example.

[0059] At time t6, signal OCx transitions to a low level. The pulse width of the high-level signal OCx, that is, the interval between time t1 and time t6, depends on the interval specified by the pulse generation circuit PG.

[0060] As signal OCx transitions to a low level at time t6, signal OC transitions to a low level at time t7. The interval between time t6 and time t7 depends on the inverter circuit connected in series with the NAND gate ND1. Figure 4 The number of inverter circuits IV3 and IV4 in the example.

[0061] As signal OCx transitions to a low level at time t6, signal ISOx transitions to a high level at time t6. As signal ISOx transitions to a high level at time t6, signal ISO transitions to a high level at time t7. Thus, signal ISO transitions to a high level at essentially the same time as signal OC transitioning to a low level.

[0062] At time t8, the signal ACT is set to low. 1.2.2. Sensing Amplifier Circuit Figure 6 This diagram schematically represents the potentials of several elements of the storage device in the first embodiment during data readout, showing the potentials of several wirings, nodes, and signals. Hereinafter, the storage cell MC, which is the target of data readout, is sometimes referred to as the selected storage cell MC. Figure 6The word line WL shown in the diagram is the word line WL connected to the select memory cell MC, and is sometimes referred to as the select word line WL below. Figure 6 The bit line BL shown in the diagram is the bit line BL connected to the select memory cell MC during data readout, and is sometimes referred to hereinafter as the select bit line BL. The complementary bit line ˉBL connected to the sense amplifier circuit SAC connected to the select bit line BL is sometimes referred to as the select complementary bit line ˉBL. By applying a voltage to the wiring shown in the diagram or the wiring that transmits signals, the wiring has a potential substantially the same as the applied voltage. For example, to give a wiring a potential Vdd, a supply voltage Vdd is applied.

[0063] exist Figure 6 At the start of the period shown, the potentials of each wiring and node are as follows. The select word line WL is activated, meaning it has a power supply potential Vpp. The power supply potential Vpp is an internal power supply potential, for example, having a different magnitude than the power supply voltage Vdd. With the select word line WL having a power supply potential Vpp, the transistor CT of the select memory cell MC is turned on, and the cell capacitor CC of the select memory cell MC is connected to the select bit line BL.

[0064] The signal EQ is negated, meaning that the potential (ground potential) Vss with ground voltage Vss is negated. Therefore, transistors TN11 and TN12 are disconnected, and neither the select bit line BL nor the select complementary bit line ˉBL is connected to node NBP with the precharge potential Vpc.

[0065] The signal ISO is activated, meaning there is a power supply potential Vddiso. The power supply potential Vddiso is an internal power supply potential, for example, having a different magnitude than the power supply potential Vdd. With the power supply potential Vddiso at the gate, transistor TN5 is turned on, and the complementary select bit line BL is connected to node SAt via the turned-on transistor TN5. Thus, the complementary select bit line BL and node SAt have substantially the same potential. Similarly, with the power supply potential Vddiso at the gate, transistor TN6 is turned on, and the select bit line BL is connected to node SAc via the turned-on transistor TN6. Thus, the select bit line BL and node SAc have substantially the same potential.

[0066] Signal OC is negated, meaning it has a ground potential Vss. With a ground potential Vss at its gate, transistor TN3 is turned off, thereby cutting off the gate of transistor TN1 from node SAt. With a ground potential Vss at its gate, transistor TN4 is turned off, thereby cutting off the gate of transistor TN2 from node SAc.

[0067] The SAP node has a power supply potential Vddsa, and the SAN node has a ground potential Vss. Therefore, the sense amplifier circuit SAC is powered on and thus operational.

[0068] Based on the potential states described above, one of the selected bit line BL and the selected complementary bit line ˉBL has a power supply potential Vddsa, and the other has a ground potential Vss. Which bit line BL or the selected complementary bit line ˉBL has a power supply potential Vddsa depends on whether the selected memory cell MC stores "0" data or stores "1" data.

[0069] When the selected storage cell MC stores "0" data, the selection bit line BL has a ground potential Vss, and the storage node SN has a ground potential Vss. On the other hand, when the selected storage cell MC stores "1" data, the selection bit line BL has a power supply potential Vddsa, and the storage node SN has a power supply potential Vddsa. Hereinafter, when the selected storage cell MC stores "0" data, it is sometimes referred to as a "0" data storage instance, and when the selected storage cell MC stores "1" data, it is sometimes referred to as a "1" data storage instance.

[0070] At time t10, the select word line WL is negated, meaning its potential is set to ground Vss. Therefore, the transistor CT of the select memory cell MC is turned off, and the cell capacitor CC of the select memory cell MC is disconnected from the select bit line BL. The select word line WL can also be set to a negative potential instead of ground Vss.

[0071] During data readout, the period from time t11 to time t12 is the equalization period. At time t11, the potential of node SAP is set to Vddsa / 2, and the potential of node SAN is also set to Vddsa / 2. Therefore, the sense amplifier circuit SAC does not receive power and does not have the function of amplifying the potential. The voltage applied to node SAP and node SAN is (Vddsa + Vss) / 2. However, as mentioned above, since this is based on the example where the ground voltage Vss is 0V, the applied voltage is Vddsa / 2.

[0072] At time t11, the signal EQ is activated, meaning its potential is set to the power supply potential Vddeq. The power supply potential Vddeq is an internal power supply potential, for example, having a different magnitude than the power supply potential Vdd. By applying the power supply potential Vddeq, transistors TN11 and TN12 are turned on, and the select bit line BL and the select complementary bit line ˉBL are connected to node NBP. As a result, both the select bit line BL and the select complementary bit line ˉBL are equalized to the same potential. Specifically, both the select bit line BL and the select complementary bit line ˉBL are pre-charged to the potential of the pre-charge voltage Vpc, which is potential Vddsa / 2.

[0073] At time t11, signal OC is activated, meaning its potential is set to the power supply potential Vddoc. The power supply potential Vddoc is an internal power supply potential, for example, having a different magnitude than the power supply potential Vdd. With the power supply potential Vddoc at the gate, transistors TN3 and TN4 are turned on. Figure 7 This schematic diagram illustrates the connection of the components of the sense amplifier circuit (SAC) during equalization. Figure 7 and subsequent Figure 8 and Figure 9 In the diagram, the transistors that are turned on are represented by the wiring connecting their two ends. The transistors that are turned off are represented by dashed lines, or are not shown at all.

[0074] When transistor TN3 is turned on, transistor TN1 is connected to the diode. When transistor TN4 is turned on, transistor TN2 is connected to the diode.

[0075] When transistor TN5 is turned on, the complementary bit line BL is selected to connect to node SAt. When transistor TN6 is turned on, the bit line BL is selected to connect to node SAc.

[0076] The period from time t12 to time t13 is the offset cancellation period. At time t12, the signal EQ is negated. This ends the pre-charging of the selection bit line BL and the selection complementary bit line ˉBL.

[0077] At time t12, the signal ISO is negated, meaning that the potential of the signal ISO is set to ground potential Vss. As a result, transistors TN5 and TN6 are disconnected. Figure 8 The diagram illustrates the connection of the components of the sense amplifier circuit SAC during offset cancellation.

[0078] By disconnecting transistor TN5, the complementary bit line BL is cut off from node SAt, thus becoming isolated. Similarly, by disconnecting transistor TN6, the select bit line BL is cut off from node SAc, also becoming isolated. Therefore, inverter circuit IV1 (transistors TP1 and TN1) and inverter circuit IV2 (transistors TP2 and TN2) are not cross-connected.

[0079] On the other hand, as described above, node SAt is connected to the select bit line BL via the switched-on transistor TN3. Therefore, the potential of node SAt is transferred to the select bit line BL, and node SAt has a potential substantially the same as that of the select bit line BL. Additionally, node SAc is connected to the select complementary bit line ˉBL via the switched-on transistor TN4. Therefore, the potential of node SAc is transferred to the select complementary bit line ˉBL, and node SAc has a potential substantially the same as that of the select complementary bit line ˉBL.

[0080] like Figure 6 As shown, at time t12, the potential of node SAP is set to the power supply potential Vddsa, while the potential of node SAN is set to the ground potential Vss.

[0081] As pre-charging ends and isolation begins at time t12, the potentials of the select bit line BL and the select complementary bit line ˉBL change from the pre-charge potential (Vddsa / 2). During this change, offset cancellation is achieved through the operation of the already switched-on transistors TN3 and TN4. That is, transistor TN3 turns on transistor TN1, thereby creating an on-resistance of transistor TN1 between node SAt and node SAN. Therefore, a potential is generated at node SAt based on the ratio of the on-resistance of transistor TP1 to the on-resistance of transistor TN1. Generally, p-type MOSFETs and n-type MOSFETs have different on-resistances, with the on-resistance of an n-type MOSFET being less than that of a p-type MOSFET. Therefore, the potential at node SAt is not the midpoint of the difference between the potentials at node SAP and node SAN, but rather a potential lower than the midpoint.

[0082] Furthermore, transistor TN4 turns on transistor TN2, thereby creating an on-resistance of transistor TN2 between node SAc and node SAN. Therefore, a potential is generated at node SAc based on the ratio of the on-resistance of transistor TN2 to that of transistor TN2. Thus, for the same reasons as for node SAt, the potential of node SAc is not the midpoint of the difference between the potentials of node SAP and node SAN, but rather a potential lower than the midpoint.

[0083] The potential change at node SAt caused by offset cancellation also changes the potential of the select bit line BL, which is connected to node SAt via transistor TN3. In other words, the potential of node SAt is reflected in the potential of the select bit line BL. Similarly, the potential change at node SAc caused by offset cancellation also changes the potential of the select complementary bit line ˉBL, which is connected to node SAc via transistor TN4. In other words, the potential of node SAc is reflected in the potential of the select complementary bit line ˉBL. One of the potentials of select bit line BL and select complementary bit line ˉBL decreases from potential Vddsa / 2 by an amount equivalent to a positive value ΔV1, and the other decreases from potential Vddsa / 2 by an amount equivalent to a positive value ΔV2. The difference between ΔV1 and ΔV2 is caused by the difference in the on-resistance between transistors TP1 and TP2, and the difference in the on-resistance between transistors TN1 and TN2 (offset).

[0084] As described above, the difference between ΔV1 and ΔV2 is based on the difference in on-resistance between transistors TP1 and TP2, and the difference in on-resistance between transistors TN1 and TN2. Therefore, at the start of subsequent charge sharing, node SAt has a potential based on the on-resistance of transistors TP1 and TN1, and node SAc has a potential based on the on-resistance of transistors TP2 and TN2. Furthermore, the select bit line BL and the select complementary bit line ˉBL are charged through nodes SAt and SAc, which have these potentials. Sensing is performed based on the potentials of the select bit line BL and the select complementary bit line ˉBL charged to these potentials. The difference between the potentials of node SAt and node SAc, based on the difference in on-resistance between transistors TP1 and TP2 and the difference in on-resistance between transistors TN1 and TN2, is correlated with the deviation between the potentials of the select bit line BL and the select complementary bit line ˉBL. To address this, offset cancellation is achieved by charging the select bit line BL and the select complementary bit line ˉBL via nodes SAt and SAc before sensing, based on the difference in on-resistance between transistors TP1 and TP2 and the difference in on-resistance between transistors TN1 and TN2. Therefore, during sensing, the difference in on-resistance between transistors TP1 and TP2 and the difference in on-resistance between transistors TN1 and TN2 can be effectively eliminated (compensated).

[0085] The period from time t13 to time t14 is the charge sharing period. At time t13, the potential of node SAP is set to Vddsa / 2, and the potential of node SAN is also set to Vddsa / 2. As a result, the sense amplifier circuit SAC becomes unable to amplify the potential.

[0086] At time t13, signal OC is negated, meaning its potential is set to ground potential Vss. Consequently, transistors TN3 and TN4 are turned off. Additionally, at time t13, signal ISO is activated. Consequently, transistors TN5 and TN6 are turned on. Figure 9 The diagram illustrates the connection of the components of the sense amplifier circuit SAC during charge sharing.

[0087] When transistor TN3 is turned off, node SAt is disconnected from the select bit line BL. On the other hand, when transistor TN5 is turned on, node SAt is connected to the select complementary bit line BL.

[0088] When transistor TN4 is turned off, node SAc is disconnected from the select complementary bit line BL. On the other hand, when transistor TN6 is turned on, node SAc is connected to the select bit line BL.

[0089] Transistor TN5 has a parasitic capacitance between its gate and drain. Through this capacitance, when the gate potential of transistor TN5 rises and falls, the drain potential (the potential at node SAt) rises and falls, respectively. Similarly, transistor TN6 has a parasitic capacitance between its gate and drain. Through this capacitance, when the gate potential of transistor TN6 rises and falls, the drain potential (the potential at node SAc) rises and falls, respectively.

[0090] Furthermore, transistor TN3 has a parasitic capacitance between its gate and drain. Through this capacitance, when the potential of signal OC is set to ground Vss at time t13, causing the gate potential to decrease, the drain potential decreases. Thus, the potential of node SAt decreases due to the decrease in the potential of signal OC. On the other hand, as described above, at time t13, the potential of signal ISO rises, thereby causing the potential of node SAt to rise due to the parasitic capacitance between the gate and drain of transistor TN5. Therefore, by raising the potential of signal ISO, the potential drop of node SAt caused by the decrease in the potential of signal OC at time t13 is suppressed. For example, if the parasitic capacitance between the source and drain of transistor TN5 and its gate is substantially the same as the parasitic capacitance between the source and drain of transistor TN3 and its gate, then the magnitude of the potential drop of node SAt due to the decrease in the potential of signal OC is substantially the same as the magnitude of the potential rise of node SAt due to the increase in the potential of signal ISO. Under this situation, the potential of node SAt remains essentially unchanged at time t13 compared to before time t13. The potential change at node SAt is shown in Figure 10 In China, regarding Figure 10 This will be described in detail below.

[0091] Similarly, transistor TN4 has a parasitic capacitance between its gate and drain. Through this capacitance, when the potential of signal OC is set to ground Vss at time t13, causing the gate potential to drop, the drain potential will also drop. Therefore, the drop in the potential of signal OC leads to a drop in the potential of node SAc. On the other hand, as described above, by raising the potential of signal ISO at time t13, the potential of node SAc will rise through the parasitic capacitance between the gate and drain of transistor TN6. Therefore, by raising the potential of signal ISO, the drop in the potential of node SAc caused by the drop in the potential of signal OC at time t13 is suppressed. For example, if the parasitic capacitance between the source and drain of transistor TN6 and its gate is substantially the same as the parasitic capacitance between the source and drain of transistor TN4 and its gate, then the magnitude of the drop in the potential of node SAc caused by the drop in the potential of signal OC is substantially the same as the magnitude of the rise in the potential of node SAc caused by the rise in the potential of signal ISO. Under this situation, at time t13, the potential of node SAc remains substantially unchanged compared to before time t13.

[0092] Additionally, at time t13, the select word line WL is activated. This initiates charge sharing. Through charge sharing, the charge stored in the select bit line BL is shared with the charge stored in the storage node SN of the select memory cell MC. As a result, the potential of the select bit line BL rises or falls based on the data stored in the select memory cell MC. The potentials of the select bit line BL (and the storage node SN) become equal in magnitude to the potentials of the select bit line BL and the storage node SN.

[0093] In the "0" data storage instance, the potential of the select bit line BL decreases towards the potential of the storage node SN, while the potential of the storage node SN increases towards the potential of the select bit line BL. The select bit line BL and the storage node SN reach a state where the potential of the decreasing select bit line BL equals the potential of the increasing storage node SN, at a value of VB0. The potential of the select complementary bit line BL is maintained.

[0094] On the other hand, in the "1" data storage instance, the potential of storage node SN decreases towards the potential of select bit line BL, while the potential of select bit line BL increases towards the potential of storage node SN. Select bit line BL and storage node SN reach a state where the potential VB1 is equal to the potential of the rising select bit line BL and the falling potential of storage node SN. The potential of the complementary select bit line BL is maintained.

[0095] The select bit line BL is connected to node SAc via the switched-on transistor TN6. Therefore, the potential of node SAc follows the potential of select bit line BL. The complementary select bit line ˉBL is connected to node SAt via the switched-on transistor TN5. Therefore, the potential of node SAt follows the potential of complementary select bit line ˉBL.

[0096] The period following time t14 is the sensing and recovery period. At time t14, the potential of node SAP is set to the power supply potential Vddsa, while the potential of node SAN is set to the ground potential Vss. As a result, the sense amplifier circuit SAC becomes capable of amplifying the potential. The sense amplifier circuit SAC amplifies one of the potentials of node SAt and node SAc to the power supply potential Vddsa, and the other to the ground potential Vss. The potential of node SAt is transmitted to the select complementary bit line BL via transistor TN5. The potential of node SAc is transmitted to the select bit line BL via transistor TN6. Thus, the potentials of the select bit line BL and the select complementary bit line BL rise or fall. In the "0" data storage instance, the potential of the select bit line BL falls to the ground potential Vss, while the potential of the select complementary bit line BL rises to the power supply potential Vddsa. On the other hand, in the "1" data storage instance, the potential of the selected bit line BL rises to the power supply potential Vddsa, while the potential of the selected complementary bit line ˉBL falls to the ground potential Vss.

[0097] 1.3. Advantages (Effects) According to the first embodiment, as described below, a storage device is provided that can determine the data stored in the storage cell with high reliability.

[0098] A reference storage device is described for comparison. The reference storage device 100 (not shown) includes the sense amplifier circuit SAC of storage device 1. On the other hand, storage device 100 differs from storage device 1 in the potential change of a certain wiring.

[0099] Figure 10 It schematically represents the potential during data readout of several elements of the first embodiment and reference storage device according to time, and represents the potential of signals and nodes. Figure 10 Part (a) represents the potential of the signals and nodes of storage device 100, and part (b) represents the potential of the wiring, nodes, and signals of storage device 1.

[0100] In storage device 100, the potential of signal ISO is maintained at ground potential Vss at time t13. (See reference...) Figure 6As described, by setting the potential of signal OC to ground Vss at time t13, the potential of node SAt decreases. The potential of node SAt decreases rapidly from time t13 and continues to decrease thereafter. However, ideally, the potential of node SAt should remain at the level of the point before time t13, i.e., the level before time t13, even after time t13. An unexpected decrease in the potential of node SAt can interfere with the desired operation of the sense amplifier circuit SAC, resulting in the following phenomenon.

[0101] During charge sharing following offset cancellation, one of the nodes SAt and SAc must have a higher potential than the other, based on the data stored in the selected memory cell MC. In the "0" data storage instance, node SAt must have a higher potential than node SAc. However, as the potential of node SAt decreases, the switching on of transistor TP2 increases, causing the potential of node SAc to rise. As a result, there may be situations where the potential of node SAt is lower than that of node SAc. If the potential of node SAt is lower than that of node SAc, the sensing result is that the sensing amplifier circuit SAC forms the state formed when the selected memory cell MC stores "1" data. This means that the data stored in the selected memory cell MC is read incorrectly.

[0102] The storage device 1 of the first embodiment sets the signal ISO to a high level (potential Vddiso) at the end of offset cancellation, which is essentially the same time point as when the signal OC is set to a low level (ground potential Vss). Therefore, by raising the potential of the signal ISO, the potential drop of node SAt caused by the potential drop of the signal OC at time t13 is suppressed. Thus, as... Figure 10 As shown in part (b), at time t13, the potential of node SAt remains essentially unchanged compared to before time t13. Therefore, compared to instances in storage device 100, it is less likely that the potential of node SAt in a "0" data storage instance will be lower than the potential of node SAc. Thus, storage device 1 can read data from the selected storage cell MC with higher reliability than storage device 100.

[0103] 1.4. Variation Examples Thus far, as an example of the basic form of the first embodiment, an example in which the signal ISO is boosted at substantially the same time as the signal OC is de-voltaged. As long as malfunctions of the sense amplifier circuit SAC can be suppressed, especially in the case of "0" data storage, the potential of node SAt after offset cancellation is lower than the potential of node SAc, the times of signal ISO boosting and signal OC de-voltage reduction can be different. For example, as... Figure 11As shown, the ISO signal can also be boosted just before the OC signal is about to be bucked. Alternatively, the ISO signal can also be boosted after the OC signal is bucked. In this case, as... Figure 12 As shown, compared to the point in time when the sense amplifier circuit SAC becomes capable of amplification (i.e., time t14), the boosting of signal ISO is closer to the point in time when signal OC is de-voltaged (t13). In other words, compared to the midpoint t13' between time t13 and time t14, the boosting of signal ISO is closer to time t13. However, to better suppress malfunctions of the sense amplifier circuit SAC, the boosting time of signal ISO is preferably closer to the de-voltaged time of signal OC.

[0104] The sensing amplifier control circuit 181 is not limited to Figure 4 The components and connections are shown. The sense amplifier control circuit 181 can have any components and connections as long as it outputs a signal ISO that is boosted by the step-down of the signal OC. For example, the signal ISOx is boosted based on the step-down of the signal OCx; on the other hand, the boosted signal OCx and the step-down signal ISO can also come from different signals, instead of... Figure 4 In the example, the signal originates from the common signal ACT. Additionally, inverter circuits IV1, IV2, IV3, and IV4 are used to adjust the timing of the buck conversion of signal OC and the boost conversion of signal ISO. The number of inverters between the output of NAND gate ND1 and the node transmitting signal ISO can be any even number or zero. Similarly, the number of inverters between the output of pulse generation circuit PG and the node transmitting signal OC can be any even number or zero.

[0105] The statement that the potential of a certain element changes at a certain moment does not require that the potential change occurs at the exact same moment. For example, although it is stated that at time t14, the potentials of nodes SAP and SAN are set as power supply potential Vddsa and ground potential Vss, respectively, it is also possible that the potential change of one of them occurs successively with the potential change of the other within the error range.

[0106] Several embodiments of the present invention have been described, but these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways and can be omitted, substituted, or modified in various ways without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, as well as in the invention as described in the claims and its equivalents.

Claims

1. A storage device comprising: a capacitor; a first transistor connected to the capacitor at a first terminal; a first inverter circuit connected between a first node and a second node, including a p-type second transistor and an n-type third transistor connected in series at a third node; a second inverter circuit connected between the first node and the second node, including a p-type fourth transistor and an n-type fifth transistor connected in series at a fourth node; a sixth transistor connected between the gate of the fifth transistor and the third node; and a seventh transistor connected between the gate of the third transistor and the fourth node, wherein the second terminal of the first transistor is connected to the capacitor at a third node. Between the fourth node; the eighth transistor, connected between the gate of the third transistor and the third node; and the ninth transistor, connected between the gate of the fifth transistor and the fourth node; at time 1, the voltage applied to the gate of the eighth transistor and the gate of the ninth transistor decreases, forming a state at time 2 where a first voltage is applied to the first node and a second voltage lower than the first voltage is applied to the second node; from time 1 to time 3, between time 1 and time 2, the voltage applied to the gate of the sixth transistor and the gate of the seventh transistor increases.

2. The storage device according to claim 1, wherein the voltage applied to the gate of the 8th transistor and the gate of the 9th transistor at the first moment decreases from a voltage that turns on the 8th transistor and the 9th transistor to a voltage that turns off the 8th transistor and the 9th transistor.

3. The storage device according to claim 2, wherein from the first time moment to the third time moment, the voltage applied to the gate of the sixth transistor and the gate of the seventh transistor rises from a voltage that turns off the sixth transistor and the seventh transistor to a voltage that turns on the sixth transistor and the seventh transistor.

4. The storage device according to claim 3, wherein during the period prior to the first time moment, a voltage that turns on the eighth transistor and the ninth transistor is continuously applied to the gate of the eighth transistor and the gate of the ninth transistor, a voltage that turns off the sixth transistor and the seventh transistor is continuously applied to the gate of the sixth transistor and the gate of the seventh transistor, and a voltage of the magnitude that turns off the first transistor is continuously applied to the gate of the first transistor.

5. The storage device according to claim 4, wherein during the period prior to the second time point, a voltage that turns off the eighth transistor and the ninth transistor is continuously applied to the gate of the eighth transistor and the gate of the ninth transistor, a voltage that turns on the sixth transistor and the seventh transistor is continuously applied to the gate of the sixth transistor and the gate of the seventh transistor, and a voltage of the magnitude that turns on the first transistor is continuously applied to the gate of the first transistor.

6. A storage device comprising: a capacitor; a first transistor connected to the capacitor at a first terminal; a first inverter circuit connected between a first node and a second node, including a p-type second transistor and an n-type third transistor connected in series at a third node; a second inverter circuit connected between the first node and the second node, including a p-type fourth transistor and an n-type fifth transistor connected in series at a fourth node; a sixth transistor connected between the gate of the fifth transistor and the third node; and a seventh transistor connected between the gate of the third transistor and the fourth node, wherein the first... A first circuit is connected between the second terminal of a transistor and the fourth node; an eighth transistor is connected between the gate of the third transistor and the third node; a ninth transistor is connected between the gate of the fifth transistor and the fourth node; a first circuit supplies a first signal that is stepped down at a first moment or a second signal obtained by delaying the first signal to the gate of the eighth transistor and the gate of the ninth transistor; and a second circuit supplies a third signal that is stepped down and stepped up based on the first signal or a fourth signal obtained by delaying the third signal to the gate of the sixth transistor and the gate of the seventh transistor.

7. The storage device of claim 6, wherein the second circuit includes a NAND gate that receives the first signal at a first input and outputs the third signal.

8. The storage device of claim 7, wherein the first circuit includes a pulse generation circuit that outputs the first signal of the first level from the second time moment to the first time moment.

9. The storage device according to claim 8, further comprising a delay circuit, wherein when the fifth signal is received, the delay circuit outputs a sixth signal obtained by delaying the fifth signal, the gate of the NAND gate receives the sixth signal at the second input, and if the pulse generation circuit receives the fifth signal before the second time, then outputs the first signal at the first level from the second time to the first time.

10. The storage device of claim 9, wherein the first circuit comprises a first number of inverter circuits connected in series to receive the first signal and output the second signal, and the second circuit comprises the first number of inverter circuits connected in series to receive the third signal and output the fourth signal.

Images