On-chip efuse read-write control device and method for secure boot

By designing an on-chip efuse read/write control device for secure boot, various control requirements of the efuse module are met, improving chip yield and the reliability of secure boot, and solving the problems of single efuse control devices and resource waste in existing technologies.

CN117219146BActive Publication Date: 2026-07-24SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
View PDF 2 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
Filing Date
2023-09-15
Publication Date
2026-07-24

AI Technical Summary

Technical Problem

Existing efuse read/write control devices cannot simultaneously meet the multiple control requirements of chips, especially when the chip is powered on and safely started, they cannot perform effective functional testing and safety status judgment, resulting in decreased chip yield and wasted resources.

Method used

An on-chip EFUSE read/write control device for secure boot is designed, including a data test register, an instruction test register, a general-purpose EFUSE controller, and an EFUSE module. The general-purpose EFUSE controller parses EFUSE operation instructions and, in conjunction with a custom register, automatically compares the EFUSE data to be written with the data already written, meeting the read/write timing requirements of the EFUSE module, and performing functional testing and security status judgment.

Benefits of technology

It improved chip yield, avoided waste of manpower and resources, achieved flexible compatibility with business scenarios, and ensured the safe startup of SoC chips.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN117219146B_ABST
    Figure CN117219146B_ABST
Patent Text Reader

Abstract

The application discloses a security-starting-oriented on-chip efuse read-write control method and device. The device comprises: a data test data register configured to output to-be-burned efuse data according to a test protocol; an instruction test data register configured to output to-be-executed efuse operation instructions according to the test protocol; a general efuse controller comprising an efuse read-write control circuit and a self-defined register, the efuse read-write control circuit being configured to analyze the to-be-executed efuse operation instructions to determine corresponding command types, execute corresponding operations according to the command types, and generate and output corresponding first control signals and second control signals according to different execution states in the operations, the self-defined register being configured to store the to-be-burned efuse data, receive the second control signals and update storage information of the efuse data according to the second control signals; and an efuse module configured to receive the first control signals and burn the to-be-burned efuse data according to the first control signals, or store burned efuse data into the self-defined register. The application improves the chip yield.
Need to check novelty before this filing date? Find Prior Art