Display substrate and display device

Abstract

A display substrate and a display device, the display substrate comprises a display area and a frame area located around the display area, the display area comprises at least one corner area, the frame area comprises at least one corner area, the at least one corner area of the display area corresponds to the at least one corner area of the frame area; the display area is provided with a plurality of first sub-pixel rows, at least part of the sub-pixels in the first sub-pixel rows are located in the at least one corner area of the display area; the at least one corner area of the frame area is provided with a plurality of virtual sub-pixels, the plurality of virtual sub-pixels are located at the edge position corresponding to the corner area of the display area, and at least part of the first sub-pixel rows are provided with at least one virtual sub-pixel close to one side of the corner area corresponding to the frame area. The technical scheme provided by the embodiment of the present disclosure can overcome the problem that the edge position of the special-shaped display area in the special-shaped display device is not smooth and delicate.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, specifically to a display substrate and a display device. Background Technology

[0002] With the rapid development of display technology, irregularly shaped display devices have gradually gained market share. The emergence of irregularly shaped display devices has broken through the limitations of the single rectangular structure of display devices, making their applications increasingly widespread. For example, irregularly shaped display devices are currently widely used in smart wearables, smart vehicles, and common electronic devices (such as mobile phones and tablets).

[0003] In existing irregularly shaped display devices, there is a defect that the edges of the irregularly shaped display area are not displayed smoothly and delicately. Summary of the Invention

[0004] The problem to be solved by the embodiments of this disclosure is to provide a display substrate and a display device to solve the problem of uneven and unsmooth display at the edges of irregularly shaped display areas in irregularly shaped display devices. The following is an overview of the subject matter described in detail herein, which is not intended to limit the scope of the claims.

[0005] In a first aspect, this disclosure provides a display substrate, including a display area and a border area surrounding the display area, the display area including at least one corner area, the border area including at least one corner area, and the at least one corner area of ​​the display area and the at least one corner area of ​​the border area corresponding to each other.

[0006] The display area has a plurality of first sub-pixel rows, and at least a portion of the sub-pixels in the first sub-pixel rows are located in at least one corner area of ​​the display area; at least one corner area of ​​the border area has a plurality of virtual sub-pixels, and the plurality of virtual sub-pixels are located at the edge of the corner area of ​​the corresponding display area, and at least a portion of the first sub-pixel rows have at least one virtual sub-pixel on the side of the corner area of ​​the corresponding border area.

[0007] In an exemplary embodiment, the plurality of virtual sub-pixels are arranged in a stepped manner at the corners of the corresponding border areas.

[0008] In an exemplary embodiment, the border region further includes: a first border region and a second border region located on both sides of the display region along a second direction, and a third border region and a fourth border region located on both sides of the display region along a first direction; at least one corner region of the border region includes: a first corner region connecting the first border region and the third border region, a second corner region connecting the third border region and the second border region, a third corner region connecting the second border region and the fourth border region, and a fourth corner region connecting the fourth border region and the first border region, wherein the first direction intersects the second direction on a plane parallel to the display substrate.

[0009] In an exemplary embodiment, the display substrate further includes:

[0010] A plurality of first data lines are located in the display area and extend to at least one corner area of ​​the border area, the plurality of first data lines being electrically connected to at least a portion of the sub-pixels located in at least one corner area of ​​the display area and configured to provide data signals to the at least a portion of the sub-pixels;

[0011] Multiple first electrostatic discharge circuits are located in the second corner region and the third corner region, and are located on the side of the multiple virtual sub-pixels away from the display area. The multiple first electrostatic discharge circuits are electrically connected to the multiple first data lines respectively.

[0012] The first electrode connection line is located in the second corner area and the third corner area, and is located on the side of the plurality of first electrostatic discharge circuits away from the display area. The first electrode connection line is electrically connected to the plurality of first electrostatic discharge circuits.

[0013] The plurality of first electrostatic discharge circuits are configured to respectively discharge static electricity from the plurality of first data lines to the first electrode connection line, or to respectively discharge static electricity from the first electrode connection line to the plurality of first data lines.

[0014] In an exemplary embodiment, the display substrate further includes:

[0015] The second electrode connection line is located in the third frame area and the fourth frame area, and is located on the side of the first electrode connection line away from the display area. The second electrode connection line located in the third frame area extends to the first corner area and the second corner area, and the second electrode connection line located in the fourth frame area extends to the third corner area and the fourth corner area.

[0016] Multiple second electrostatic discharge circuits are located in the second corner region and the third corner region, and on the side of the second electrode connection line away from the display area; the multiple second electrostatic discharge circuits are electrically connected to the multiple first sub-pixel rows and the second electrode connection line respectively, and are configured to release the static electricity in the second electrode connection line to the multiple first sub-pixel rows respectively, or release the static electricity in the multiple first sub-pixel rows to the second electrode connection line respectively.

[0017] In an exemplary embodiment, the display substrate further includes a third electrostatic discharge circuit located in the second corner region and the third corner region, and located between the first electrode connection line and the second electrode connection line;

[0018] The third electrostatic discharge circuit is electrically connected to the corresponding first electrode connection line and the corresponding second electrode connection line, and is configured to discharge static electricity in the corresponding first electrode connection line to the corresponding second electrode connection line, or discharge static electricity in the corresponding second electrode connection line to the corresponding first electrode connection line.

[0019] In an exemplary embodiment, the plurality of first electrostatic discharge circuits and the plurality of second electrostatic discharge circuits are arranged in a stepped manner, and the edges of the first electrode connection line and the second electrode connection line are stepped.

[0020] In an exemplary embodiment, the stepped shape of the plurality of first electrostatic discharge circuits and the plurality of second electrostatic discharge circuits is consistent with the stepped shape of the plurality of virtual sub-pixels; the stepped shape of the edges of the first electrode connection line and the second electrode connection line is consistent with the stepped shape of the plurality of virtual sub-pixels.

[0021] In an exemplary embodiment, in the second direction, the third electrostatic discharge circuit is disposed on the side of the first electrostatic discharge circuit at the end that is away from the display area, and is electrically connected to the end of the first electrode connection line on the side away from the second frame area; in the first direction, on one side of the display area, the first electrostatic discharge circuit at the end is the first electrostatic discharge circuit farthest from the second center line among the plurality of first electrostatic discharge circuits, and the second center line is the center line of the display area extending along the second direction.

[0022] In an exemplary embodiment, the display substrate further includes:

[0023] The drive trace fan-out area is located in the third frame area and the fourth frame area, and is located on the side of the second electrode connection line away from the display area. The drive trace fan-out area located in the third frame area extends to the first corner area and the second corner area, and the drive trace fan-out area located in the fourth frame area extends to the third corner area and the fourth corner area.

[0024] The drive trace fan-out area fans out multiple drive traces, and the multiple drive traces located in the second corner area and the third corner area are respectively electrically connected to the multiple second electrostatic discharge circuits and the multiple first sub-pixel rows.

[0025] In an exemplary embodiment, the drive trace includes a plurality of first drive traces and a plurality of second drive traces, and in the drive trace fan-out area, the first drive traces and the second drive traces are arranged alternately.

[0026] In a direction perpendicular to the plane of the display substrate, the display substrate includes a substrate and a first gate metal layer and a second gate metal layer disposed on the substrate. The second gate metal layer is located on the side of the first gate metal layer away from the substrate. The first gate metal layer is provided with the plurality of first driving traces, and the second metal layer is provided with the plurality of second driving traces.

[0027] In an exemplary embodiment, the display substrate further includes a common electrode layer located on the side of the second gate metal layer away from the substrate;

[0028] The first gate metal layer further includes a plurality of first connection electrodes and a plurality of second connection electrodes corresponding to the plurality of first connection electrodes. The plurality of first connection electrodes are electrically connected to a plurality of first sub-pixel rows respectively. A portion of the second connection electrodes are electrically connected to the first driving trace, and another portion of the second connection electrodes are electrically connected to the second driving trace. The first connection electrodes and the corresponding second connection electrodes are spaced apart.

[0029] The common electrode layer includes a plurality of first transfer electrodes, which are electrically connected to the plurality of first connecting electrodes, the plurality of second connecting electrodes and the plurality of second electrostatic discharge circuits, respectively. The plurality of first connecting electrodes and the corresponding plurality of second connecting electrodes are electrically connected through the plurality of first transfer electrodes, and the plurality of first connecting electrodes are also electrically connected to the plurality of second electrostatic discharge circuits through the plurality of first transfer electrodes.

[0030] In an exemplary embodiment, the distance between the first electrode connection line and the second electrode connection line is greater than or equal to 20 micrometers; the distance between the first electrode connection line and the nearest virtual sub-pixel is greater than or equal to 20 micrometers.

[0031] In an exemplary embodiment, the display substrate further includes:

[0032] The first fan-out area of ​​the data trace is located in the first corner area and the fourth corner area, and is located between the second electrode connection line and the plurality of virtual sub-pixels. The plurality of first data lines are fanned out by the first fan-out area of ​​the data trace.

[0033] In an exemplary embodiment, the distance between the first fan-out area of ​​the data trace and the nearest virtual sub-pixel is greater than or equal to 10 micrometers, and the distance between the first fan-out area of ​​the data trace and the second electrode connection line is greater than or equal to 20 micrometers.

[0034] In an exemplary embodiment, the first frame area is provided with a bonding area, which includes a second fan-out area for data traces, a fourth electrostatic discharge circuit area, and two fifth electrostatic discharge circuit areas. In a plane parallel to the display substrate, in the second direction, the second fan-out area for data traces is located on the side of the fourth and fifth electrostatic discharge circuit areas away from the display area; in the first direction, the two fifth electrostatic discharge circuit areas are located between the fourth electrostatic discharge circuit area and the second electrode connection line, and the fourth electrostatic discharge circuit area is located between the two fifth electrostatic discharge circuit areas.

[0035] In an exemplary embodiment, the display area is provided with a plurality of first sub-pixel columns, a plurality of second sub-pixel columns, and a plurality of second data lines. The plurality of first data lines are electrically connected to the plurality of first sub-pixel columns, and the plurality of second data lines are electrically connected to the plurality of second sub-pixel columns. In the first direction, the area where the plurality of first sub-pixel columns are located is located on both sides of the area where the plurality of second sub-pixel columns are located, and at least some sub-pixels in the first sub-pixel columns are located in at least one corner area of ​​the display area.

[0036] The fourth electrostatic discharge circuit region includes a plurality of fourth electrostatic discharge circuits arranged along the first direction, and the fifth electrostatic discharge circuit region includes a plurality of fifth electrostatic discharge circuits arranged along the first direction. The second fan-out region of the data traces fans out a plurality of data traces, which include a plurality of third data lines and a plurality of fourth data lines. The plurality of fourth data lines are electrically connected to the plurality of fourth electrostatic discharge circuits and the plurality of second data lines, respectively. The plurality of third data lines are electrically connected to the plurality of fifth electrostatic discharge sub-circuits and the plurality of first data lines, respectively.

[0037] The plurality of fourth electrostatic discharge circuits are electrically connected to the second electrode connection line and are configured to respectively discharge the static electricity in the plurality of second data lines to the second electrode connection line, or respectively discharge the static electricity in the second electrode connection line to the plurality of second data lines.

[0038] The plurality of fifth electrostatic discharge circuits are electrically connected to the second electrode connection line and are configured to respectively discharge static electricity from the plurality of first data lines to the second electrode connection line, or to respectively discharge static electricity from the second electrode connection line to the plurality of first data lines.

[0039] In an exemplary embodiment, the first corner area to the fourth corner area are provided with the plurality of virtual sub-pixels, and the plurality of virtual sub-pixels are arranged in the same way as the plurality of sub-pixels in the first sub-pixel row of the corner area of ​​the corresponding display area.

[0040] This disclosure also provides a display device, including the display substrate described in any of the foregoing embodiments.

[0041] In an exemplary embodiment, the system further includes a first integrated circuit and a second integrated circuit. The display substrate includes a display area and a border area surrounding the display area. The border area on one side of the display area is provided with a bonding area. The bonding area includes a first integrated circuit bonding area and a second integrated circuit bonding area. The first integrated circuit is bonded to the first integrated circuit area, and the second integrated circuit is bonded to the second integrated circuit bonding area.

[0042] In an exemplary embodiment, the display device further includes a color filter substrate and conductive adhesive;

[0043] The color filter substrate and the display substrate are disposed together. The conductive adhesive is disposed between the color filter substrate and the display substrate and is electrically connected to the electrode traces in the color filter substrate and the ground line in the display substrate, respectively. It is configured to release static electricity in the electrode traces in the color filter substrate to the ground line in the display substrate.

[0044] In an exemplary embodiment, the first integrated circuit is a data driving circuit, the second integrated circuit is a gate driving circuit, and both the data driving circuit and the gate driving circuit are two in number. The conductive adhesive includes two conductive adhesive dots. In the first direction, the two gate driving circuits are located on both sides of the two data driving circuits, and the two data driving circuits are located on both sides of the two conductive adhesive dots.

[0045] In an exemplary embodiment, in the first direction, the distance between the centers of the two conductive adhesive dots is 30 mm to 45 mm, and the distance between the conductive adhesive dot and the nearest data driving circuit is 20 mm to 25 mm.

[0046] The display substrate and display device provided in the embodiments of this disclosure have at least one corner area of ​​the border area of ​​the display substrate with multiple virtual sub-pixels. The multiple virtual sub-pixels are located at the edge of the corner area of ​​the corresponding display area. At least a portion of the first sub-pixel row has at least one virtual sub-pixel on the side close to the corner area of ​​the corresponding border area. This can overcome the defect of uneven display at irregular display positions in irregular display devices.

[0047] Of course, implementing any product or method of this disclosure does not necessarily require achieving all the advantages described above simultaneously. Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description and embodiments, or may be learned by practicing this disclosure. The objects and other advantages of embodiments of this disclosure may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0048] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0049] Figure 1 The diagram shown is a cross-sectional view of a display device.

[0050] Figure 2 The diagram shown is a schematic representation of a planar structure of a display substrate.

[0051] Figure 3 The figure shown is a schematic diagram of the planar structure of a display device;

[0052] Figure 4 The diagram shown is a schematic representation of the planar structure of a display panel.

[0053] Figure 5 The diagram shown is a structural schematic of a binding area in a display panel;

[0054] Figure 6 The diagram shows the structure of the display panel bonding area after bending.

[0055] Figure 7 The above is a schematic diagram of a planar structure of a display substrate provided in an exemplary embodiment of this disclosure;

[0056] Figure 8 The figure shown is a schematic diagram of the planar structure of the corner area of ​​the display substrate provided in an embodiment of this disclosure;

[0057] Figure 9a The illustration shown is an exemplary embodiment of this invention. Figure 7A magnified structural diagram of position M1 in the middle;

[0058] Figure 9b The illustration shown is an exemplary embodiment of this invention. Figure 7 A magnified structural diagram of the M2 position in the middle;

[0059] Figure 9c The illustration shown is an exemplary embodiment of this invention. Figure 8 A magnified structural diagram of the M3 position;

[0060] Figure 10 The diagram shown is a partially enlarged schematic of the regions of the first electrostatic discharge circuit and the third electrostatic discharge circuit provided in an exemplary embodiment of the present invention.

[0061] Figure 11 The diagram shown is a circuit schematic of the second electrostatic discharge circuit provided in an exemplary embodiment of this invention.

[0062] Figure 12a The diagram shown is a schematic diagram of the planar structure of the active layer in the third electrostatic discharge circuit provided in an exemplary embodiment of the present invention.

[0063] Figure 12b The diagram shown is a schematic diagram of the planar structure of the third electrostatic discharge circuit provided by the exemplary embodiment of the present invention after the formation of the first gate metal layer;

[0064] Figure 12c The diagram shown is a schematic diagram of the planar structure of the third electrostatic discharge circuit provided in the exemplary embodiment of this invention after the formation of the second gate metal layer;

[0065] Figure 12d The diagram shown is a planar structure schematic of the third electrostatic discharge circuit after forming a via pattern provided in an exemplary embodiment of the present invention.

[0066] Figure 12e The diagram shown is a schematic diagram of the planar structure of the third electrostatic discharge circuit after the formation of the common electrode layer provided in the exemplary embodiment of this invention.

[0067] Figure 12f The diagram shown is a planar structure schematic of the third electrostatic discharge circuit after forming a via pattern provided in an exemplary embodiment of the present invention.

[0068] Figure 12g The diagram shown is a schematic diagram of the planar structure of the third electrostatic discharge circuit after the formation of the common electrode layer provided in the exemplary embodiment of this invention.

[0069] Figure 13 The diagram shown is an enlarged structural schematic of the corner region of the display substrate provided in an exemplary embodiment of the present invention;

[0070] Figure 14The illustration shown is an exemplary embodiment of this invention. Figure 13 A magnified structural diagram of the M4 position in the middle;

[0071] Figure 15 The diagram shown is a circuit schematic of an electrostatic discharge circuit provided by an exemplary embodiment of the present invention.

[0072] Figure 16a The diagram shown is a schematic diagram of the planar structure of the active layer at position M5 provided in an exemplary embodiment of this invention;

[0073] Figure 16b The diagram shown is a schematic diagram of the planar structure after the first gate metal layer is formed at position M5 according to an exemplary embodiment of the present invention;

[0074] Figure 16c The diagram shown is a schematic diagram of the planar structure after the second gate metal layer is formed at position M5 according to an exemplary embodiment of the present invention;

[0075] Figure 16d The diagram shown is a planar structure diagram of the M5 position after a via pattern is formed according to an exemplary embodiment of the present invention.

[0076] Figure 16e The diagram shown is a schematic diagram of the planar structure after a common electrode layer is formed at position M5 according to an exemplary embodiment of the present invention;

[0077] Figure 17 The diagram shown is a planar structural schematic of the sixth electrostatic discharge circuit and the fifth electrostatic discharge circuit provided for an exemplary embodiment of the present invention.

[0078] Figure 18a The figure shown is a schematic diagram of the planar structure of the display device provided in an embodiment of this disclosure;

[0079] Figure 18b The diagram shown is a planar structural schematic of a display device provided in an exemplary embodiment of the present disclosure. Detailed Implementation

[0080] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as being limited only to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0081] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the thickness and spacing of each film layer, and the width and spacing of each signal line, can be adjusted according to actual conditions. The drawings described in this disclosure are merely structural schematic diagrams, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0082] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0083] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0084] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0085] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0086] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged. In embodiments of this disclosure, the gate electrode can be referred to as the control electrode.

[0087] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0088] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0089] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0090] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0091] In the embodiments of this disclosure, "about" means a value that is not strictly limited and is within the range of process and measurement errors.

[0092] Figure 1 This is a schematic cross-sectional view of a display device. Figure 1 As shown, the display device may include a first substrate 100 and a second substrate 200 disposed opposite to each other, and a liquid crystal layer 300 disposed between the first substrate 100 and the second substrate 200. The first substrate 100 may include a first structural layer 102 disposed on the side of the first substrate 101 facing the second substrate 200, and the second substrate 200 may include a second structural layer 202 disposed on the side of the second substrate 201 facing the first substrate 100. For ADS display mode, in an exemplary embodiment, the first structural layer 102 may include gate lines, data lines, thin-film transistors, pixel electrodes, and common electrodes, and the second structural layer 202 may include a black matrix and a filter unit.

[0093] Figure 2 This is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, the display device may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the three sub-pixels may include a thin-film transistor, a pixel electrode, and a common electrode. In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel emitting red (R) light, the second sub-pixel P2 may be a green sub-pixel emitting green (G) light, and the third sub-pixel P3 may be a blue sub-pixel emitting blue (B) light. The shape of the sub-pixels in the pixel unit may be rectangular, rhomboid, pentagonal, or hexagonal, etc. The sub-pixels in the pixel unit may be arranged horizontally side by side, vertically side by side, or in a triangular arrangement, which is not limited herein. In an exemplary embodiment, the pixel unit may include four sub-pixels, which is not limited herein.

[0094] Figure 3 This is a schematic diagram of a planar structure of an array device. Figure 3 As shown, in an exemplary embodiment, the array substrate includes a display area and a border area. The display area may include multiple gate lines (S1 to Sm) and multiple data lines (D1 to Dn). The multiple gate lines may extend horizontally and be arranged sequentially in a vertical direction, and the multiple data lines may extend vertically and be arranged sequentially in a horizontal direction. The intersecting multiple gate lines and multiple data lines define a plurality of regularly arranged sub-pixels Pxij, where i and j can be natural numbers. In an exemplary embodiment, at least one sub-pixel Pxij may include a thin-film transistor, a pixel electrode, and a common electrode. The thin-film transistor is connected to the gate lines, data lines, and pixel electrode, respectively.

[0095] In an exemplary embodiment, the array substrate may further include multiple common electrode lines (E1 to Eo), which may extend horizontally and be arranged sequentially in the vertical direction, and the multiple common electrode lines are connected to the common electrodes in multiple sub-pixels Pxij.

[0096] In an exemplary embodiment, multiple gate lines are led out to the border area and connected to the scan driver, and multiple data lines are led out to the border area and connected to the data driver. At least a portion of the scan driver and the data driver may be formed on the array substrate.

[0097] In an exemplary embodiment, an external control device (such as a timing controller) can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver. The data driver can use the received grayscale values ​​and control signals to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The external control device can also provide clock signals, scan start signals, etc., of specifications suitable for the scan driver to the scan driver. The scan driver can use the clock signals, scan start signals, etc., to generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm, where m can be a natural number. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal.

[0098] Figure 4 This is a schematic diagram of the structure of a display substrate. (Example) Figure 4 As shown, the display panel may include a display area 100, a bonding area 200 located on one side of the display area 100, and a border area 300 located on the other sides of the display area 100. The display area 100 may include a plurality of regularly arranged sub-pixels Pxij, and the sub-pixels may include pixel driving circuits and light-emitting devices. The bonding area 200 may include bonding circuits that connect signal lines to external driving devices. The border area 300 may include gate driving circuits and a second power supply line VSS that transmits voltage signals to the plurality of sub-pixels.

[0099] Figure 5 This is a structural diagram of the binding area in the display panel. (Example) Figure 4 and Figure 5As shown, in a plane parallel to the display panel, the bonding area 200 is located on one side of the display area 100. The bonding area 200 includes a first fan-out area 201, a bending area 202, and a composite circuit area 2001 arranged sequentially along a direction away from the display area 100. The composite circuit area 2001 may include a second fan-out area 203, a driver chip area 205, and a bonding electrode area 206 arranged sequentially along a direction away from the bending area 202. The first fan-out area 201 includes a data fan-out line, a first power line, and a second power line. The data fan-out line is located in the middle of the first fan-out area 201 and includes multiple data connection lines. The multiple data connection lines are configured to connect to the data lines of the display area 100 in a fanout routing manner. The first power line is configured to connect to the high-voltage power line (VDD) of the display area 100, and the second power line is a low-voltage power line (VSS) located in the bezel area 300. The bending area 202 includes a composite insulating layer with grooves, configured to bend the bonding area 200 to the back side of the display area 100. The second fan-out area 203 includes multiple data connection lines led out in a fan-out routing manner. The driver chip area 205 includes an integrated circuit (IC) 400, configured to be connected to the multiple data connection lines. The bonding electrode area 206 includes multiple bonding pads, configured to be bonded to a flexible printed circuit (FPC) 500. In an exemplary embodiment, the integrated circuit (IC) 400 may be bonded to the driver chip area 205, and the flexible printed circuit (FPC) 500 may be bonded to the bonding electrode area 206. In an exemplary embodiment, the integrated circuit 400 may generate drive signals required to drive sub-pixels and may provide the drive signals to the sub-pixels in the display area 100. For example, the drive signal may be a data signal controlling the brightness of the sub-pixel. In an exemplary embodiment, the bonding electrode area 206 may be provided with pads including multiple pins, and the flexible circuit board 500 may be bonded to the pads.

[0100] In an exemplary implementation, such as Figure 6 As shown, the bending region 202 can be bent with a curvature, which can reverse the surface of the composite circuit region 2001, that is, the upward-facing surface of the composite circuit region 2001 can be transformed to face downward by bending the bending region 202. In an exemplary embodiment, when the bending region 202 is bent, the composite circuit region 2001 can overlap with the display area 100 in the thickness direction of the display panel.

[0101] In exemplary embodiments, for large-size display panels, multiple data driver ICs and multiple FPCs are required. Each FPC is connected to one of the multiple data driver ICs. For example, four data driver ICs can be connected to four FPCs respectively. However, this disclosure is not limited to four ICs and four FPCs; for instance, two data driver ICs and two FPCs can be used. In this disclosure, the number of data driver ICs and FPCs can be set according to the size and functional requirements of the display panel, and this disclosure does not impose any limitations.

[0102] With the widespread application of displays in various scenarios, their shapes are becoming increasingly diverse, and irregularly shaped display products are a clear trend. A smooth and delicate display in irregularly shaped areas is a required effect for all such products. Currently, many irregularly shaped displays suffer from a lack of smoothness and detail in these areas. Another design trend is narrow bezels. Narrower bezels offer a more comfortable viewing experience, a better visual experience, and reduce product size, making them increasingly popular with consumers. Theoretically, sufficiently fine wiring and small spacing can achieve narrow bezels, but due to limitations in manufacturing processes and some conventional design practices, achieving truly narrow bezels is quite challenging. As display technology advances, more and more display products seek both irregular shapes and ultra-narrow bezels. How to simultaneously achieve smooth and delicate display in irregularly shaped areas and narrow bezels is a crucial technical challenge that needs to be addressed.

[0103] This disclosure provides a display substrate that may include a display area and a border area surrounding the display area. The display area includes at least one corner area, and the border area includes at least one corner area. The at least one corner area of ​​the display area and the at least one corner area of ​​the border area correspond to each other.

[0104] The display area has multiple first sub-pixel rows, and at least a portion of the sub-pixels in the first sub-pixel rows are located in at least one corner area of ​​the display area; at least one corner area of ​​the border area has multiple virtual sub-pixels, and the multiple virtual sub-pixels are located at the edge of the corner area of ​​the corresponding display area, and at least a portion of the first sub-pixel rows have at least one virtual sub-pixel on the side of the corner area of ​​the corresponding border area.

[0105] The display substrate provided in this embodiment has at least one corner area of ​​the border region with multiple virtual sub-pixels. The multiple virtual sub-pixels are located at the edge of the corner area of ​​the corresponding display area. At least a portion of the first sub-pixel row has at least one virtual sub-pixel on the side close to the corner area of ​​the corresponding border region. This can overcome the defect in irregular display devices where the irregular display position is not smooth and delicate.

[0106] like Figure 7 and Figure 8 As shown, Figure 7 This is a schematic diagram of the planar structure of a display substrate provided in an exemplary embodiment of this disclosure. Figure 8 for Figure 7 An enlarged schematic diagram of at least one corner region is provided. The display substrate may include a display area 100 and a border area 300 surrounding the display area 100. The display area 100 includes at least one corner region, and the border area 300 includes at least one corner region. The at least one corner region of the display area 100 corresponds to the at least one corner region of the border area 300. The display area 100 is provided with a plurality of first sub-pixel rows PX1, and at least a portion of the sub-pixels in the first sub-pixel rows PX1 are located in at least one corner region of the display area 100. The at least one corner region of the border area 300 is provided with a plurality of virtual sub-pixels P0, and the plurality of virtual sub-pixels P0 are located at the edge position of the corner region corresponding to the display area 100. At least a portion of the first sub-pixel rows PX1 are provided with at least one virtual sub-pixel P0 on the side of the corner region corresponding to the border area 300.

[0107] In an exemplary implementation, such as Figure 7 As shown, the border area 300 may further include: a first border area B1 and a second border area B2 located on both sides of the display area 100 along the second direction Y, and a third border area B3 and a fourth border area B4 located on both sides of the display area 100 along the first direction X; at least one corner area of ​​the border area 300 may include: a first corner area C1 connecting the first border area B1 and the third border area B3, a second corner area C2 connecting the third border area B3 and the second border area B2, a third corner area C3 connecting the second border area B2 and the fourth border area B4, and a fourth corner area C4 connecting the fourth border area B4 and the first border area B1, wherein the first direction X intersects the second direction Y on a plane parallel to the display substrate.

[0108] In an exemplary implementation, such as Figure 7 As shown, the display substrate can be mirror-symmetrical with respect to the first center line Q1-Q1, which can be the center line extending along the second direction Y of the display substrate. In an exemplary embodiment, mirror symmetry can be absolute symmetry or approximately symmetry, meaning that the shapes on both sides of the first center line can be exactly the same or slightly different. In an exemplary embodiment, the second corner region C2 and the third corner region C3 can be mirror-symmetrical with respect to the first center line, and the first corner region C1 and the fourth corner region C4 can be mirror-symmetrical with respect to the first center line.

[0109] In an exemplary embodiment, the first corner region C1 to the fourth corner region C4 are provided with a plurality of virtual sub-pixels P0. The arrangement of the plurality of virtual sub-pixels P0 is consistent with the arrangement of a plurality of sub-pixels in the first sub-pixel row PX1 of the corner region of the corresponding display region 100. For example, the plurality of first virtual sub-pixels P0 located on the side of the first sub-pixel row PX1 near the border region 300 are located in the same row as a plurality of sub-pixels in the first sub-pixel row PX1. Among the plurality of virtual sub-pixels P0 in the same row, the distance between two adjacent virtual sub-pixels P0 is consistent with the distance between two adjacent sub-pixels in the first sub-pixel row PX1. In an exemplary embodiment, among the plurality of sub-pixels and the plurality of virtual sub-pixels P0 located in the same row, the distance between the virtual sub-pixel P0 closest to the display region 100 and the sub-pixel in the first sub-pixel row PX1 closest to the corner region of the corresponding border region 300 is consistent with the distance between two adjacent virtual sub-pixels, or consistent with the distance between two adjacent sub-pixels in the first sub-pixel row PX1.

[0110] In an exemplary implementation, such as Figures 8 to 9b As shown, multiple virtual sub-pixels P0 can form a virtual sub-pixel region P0X, which is located on the edge of the corner area of ​​the display area 100, close to the corner area of ​​the corresponding border area 300.

[0111] In an exemplary implementation, such as Figures 8 to 9b As shown, Figure 9a for Figure 7 An enlarged structural diagram of position M1. Figure 9b for Figure 7 The enlarged structural diagram of the M2 position shows that multiple virtual sub-pixels P0 are arranged in a stepped manner in the corner area of ​​the corresponding border area 300. The edges of the virtual sub-pixel area P0X near the border area 300 and near the display area 100 are both stepped.

[0112] In an exemplary embodiment, the edge of the corner region of the display area 100 is stepped. The edge of the corner region of the display area 100 near the corner region of the corresponding border region 300 has the same stepped shape as the edge of the virtual sub-pixel region POX near the display area 100. In an exemplary embodiment, as... Figure 9c As shown, Figure 8The enlarged structural diagram at position M3 shows that PJ is the boundary line between display area 100 and virtual sub-pixel area POX. The boundary line PJ can be stepped (the boundary line PJ can serve as the edge of virtual sub-pixel area POX near display area 100 and the edge of corner area of ​​display area 100 near the corner area of ​​corresponding border area 300). In an exemplary embodiment, the stepped shape of the edge of virtual sub-pixel area POX away from display area 100 can be consistent with the stepped shape of boundary line PJ.

[0113] In an exemplary implementation, spacing one or more first sub-pixel rows PX1 can create a staircase. Figure 9c In the diagram, the arc boundary J0 can be the line connecting the positions of multiple first sub-pixel rows PX1 closest to the corner area of ​​the corresponding border area 300. The larger the angle between the tangent of the arc boundary J0 and the extension direction of the first border B1 (i.e., the first direction X), the more first sub-pixel rows PX1 are needed to form a step in the corner area of ​​the display area 100. For example, multiple first sub-pixel rows PX1 need to be spaced to form a step. The smaller the angle between the tangent of the arc boundary J0 and the extension direction of the first border B1 (i.e., the first direction X), the fewer first sub-pixel rows PX1 are needed to form a step in the corner area of ​​the display area 100. For example, one first sub-pixel row PX1 is needed to form a step, that is, two adjacent first sub-pixel rows PX1 can form a step.

[0114] In an exemplary embodiment, Figure 7In the structure of the display substrate shown, the display area 100 may include two first display areas PX10 and one second display area PX20. In the second direction Y, the two first display areas PX10 are located on both sides of the second display area PX20. The first sub-pixel row PX1 is located in the first sub-pixel area PX10. The number of sub-pixels in the first sub-pixel row PX1 is less than the number of sub-pixels in a sub-pixel row of the second sub-pixel area PX20. Since the ratio between the size of the display substrate along the first direction X and the size along the second direction Y is relatively large, the number of missing sub-pixels in the first sub-pixel row PX1 is very small compared to the total number of sub-pixels in a first sub-pixel row PX1 (the number of missing sub-pixels can be ignored). As a result, the difference in resistance and capacitance between adjacent sub-pixel rows is very small, and there is no need to set a capacitor compensation structure, which can save space of the display substrate to a certain extent. In an exemplary embodiment, when the ratio between the size of the display substrate along the first direction X and the size along the second direction Y is relatively small, and the number of sub-pixels in the first sub-pixel row PX1 is less than the number of sub-pixels in a sub-pixel row of the second sub-pixel region PX20 (the number of missing sub-pixels in the first sub-pixel row PX1 cannot be ignored), resulting in a large difference in resistance and capacitance between adjacent sub-pixel rows, capacitance compensation can be performed. The specific capacitance compensation method can use existing commonly used technical solutions, which will not be described in detail in this embodiment.

[0115] In an exemplary implementation, such as Figure 8 As shown, the display substrate may further include:

[0116] A plurality of first data lines D1 are located in the display area 100 and extend to at least one corner area of ​​the border area 300. The plurality of first data lines D1 are electrically connected to at least some sub-pixels located in at least one corner area of ​​the display area 100 and are configured to provide data signals to at least some sub-pixels.

[0117] Multiple first electrostatic discharge circuits ST1 are located in the second corner region C2 and the third corner region C3, and are located on the side of multiple virtual sub-pixels P0 away from the display area 100. The multiple first electrostatic discharge circuits ST1 are electrically connected to multiple first data lines D1 respectively.

[0118] The first electrode connection line L1 is located in the second corner area C2 and the third corner area C3, and is located on the side of the multiple first electrostatic discharge circuits ST1 away from the display area 100. The first electrode connection line L1 is electrically connected to the multiple first electrostatic discharge circuits ST1.

[0119] The plurality of first electrostatic discharge circuits ST1 are configured to respectively discharge the static electricity in the plurality of first data lines D1 to the first electrode connection line L1, or to respectively discharge the static electricity in the first electrode connection line L1 to the plurality of first data lines D1.

[0120] In this embodiment of the disclosure, when there is too much focused charge in the first electrode connection line L1, it can be released to the multiple first data lines D1 through the first electrostatic discharge circuit ST1. When there is too much charge in the multiple first data lines D1, it can be released to the first electrode connection line L1 through the first electrostatic discharge circuit ST1, thereby preventing the first electrode connection line L1 and the multiple first data lines D1 from electrostatic breakdown due to excessive static accumulation.

[0121] In an exemplary implementation, such as Figure 8 As shown, the display substrate may further include:

[0122] The second electrode connection line L2 is located in the third frame area B3 and the fourth frame area B4, and is located on the side of the first electrode connection line L1 away from the display area 100. The second electrode connection line L2 located in the third frame area B3 extends to the first corner area C1 and the second corner area C2. The second electrode connection line L2 located in the fourth frame area B4 extends to the third corner area C3 and the fourth corner area C4.

[0123] Multiple second electrostatic discharge circuits ST2 are located in the second corner region C2 and the third corner region C3, and on the side of the second electrode connection line L2 away from the display area 100. The multiple second electrostatic discharge circuits ST2 are electrically connected to multiple first sub-pixel rows PX1 and the second electrode connection line L2 respectively, and are configured to release the static electricity in the second electrode connection line L2 to the multiple first sub-pixel rows PX1 respectively, or release the static electricity of the multiple first sub-pixel rows PX1 to the second electrode connection line L2 respectively.

[0124] In this embodiment of the present disclosure, when there is too much focused charge in the second electrode connection line L2, it can be released to multiple first sub-pixel rows PX1 through the second electrostatic discharge circuit ST2. When there is too much charge in the multiple first sub-pixel rows PX1, it can be released to the second electrode connection line L2 through the second electrostatic discharge circuit ST2, thereby preventing the second electrode connection line L2 and the multiple first sub-pixel rows PX1 from electrostatic breakdown due to excessive static accumulation.

[0125] In an exemplary implementation, such as Figure 8As shown, the distance h1 between the first electrode connection line L1 and the second electrode connection line L2 is greater than or equal to 20 micrometers; the distance h2 between the first electrode connection line L1 and the nearest virtual sub-pixel P0 is greater than or equal to 20 micrometers. In this embodiment, the distance h1 between the first electrode connection line L1 and the second electrode connection line L2 is greater than or equal to 20 micrometers, which can avoid signal interference between the first electrode connection line L1 and the second electrode connection line L2 and short circuit problems caused by metal residue. The distance h2 between the first electrode connection line L1 and the nearest virtual sub-pixel P0 is greater than or equal to 20 micrometers, which can avoid the first electrode connection line L1 and its metal residue causing the virtual pixel P0 to short circuit. The virtual pixel P0 does not participate in the display work, but its internal wiring is basically consistent with the wiring of the sub-pixels in the display area. During the preparation of the first electrode connection line L1, if the distance between the virtual sub-pixel P0 and the first electrode connection line L1 is too close, the first electrode connection line L1 and the residual metal in the preparation of the first electrode connection line L1 may cause the virtual sub-pixel P0 to short circuit, thereby affecting the normal operation of the display substrate. Therefore, the solution provided by this embodiment can avoid the problem of virtual sub-pixel P0 short circuit.

[0126] In an exemplary implementation, such as Figure 10 As shown, the display substrate may also include a third electrostatic discharge circuit ST3, located in the second corner region C2 and the third corner region C3, and located between the first electrode connection line L1 and the second electrode connection line L2.

[0127] The third electrostatic discharge circuit ST3 is electrically connected to the corresponding first electrode connection line L1 and the corresponding second electrode connection line L2, and is configured to discharge the static electricity in the corresponding first electrode connection line L1 to the corresponding second electrode connection line L2, or discharge the static electricity in the corresponding second electrode connection line L2 to the corresponding first electrode connection line L1.

[0128] In an exemplary embodiment, when there is too much focused charge in the second electrode connection line L2, it can be released to the first electrode connection line L1 through the third electrostatic discharge circuit ST3. When there is too much accumulated charge in the first electrode connection line L1, it can be released to multiple first data lines D1 through multiple first electrostatic discharge circuits ST1. When there is too much accumulated charge in the first electrode connection line L1, it can be released to the second electrode connection line L2 through the third electrostatic discharge circuit ST3, thereby preventing electrostatic breakdown caused by excessive accumulation of static electricity in the first electrode connection line L1 and the second electrode connection line L2.

[0129] In an exemplary implementation, such as Figure 10As shown, in the second direction Y, the third electrostatic discharge circuit ST3 is disposed on the side of the first electrostatic discharge circuit ST1 at the end that is away from the display area 100, and is electrically connected to the end of the first electrode connection line L1 on the side away from the second frame area B2; in the first direction X, on one side of the display area 100, the first electrostatic discharge circuit ST1 at the end is the one farthest from the second center line among a plurality of first electrostatic discharge circuits ST1, and the second center line is the center line extending from the display area 100 along the second direction Y. The third electrostatic discharge circuit ST3 can discharge static electricity in the first electrode connection line L1 to the second electrode connection line L2, and can also discharge static electricity in the second electrode connection line L2 to the first electrode connection line L1. It can also discharge static electricity to a plurality of first data lines D1 in the display area 100 through the first electrode connection line L1. Since there are a large number of first data lines D1, very little static electricity is discharged to each first data line D1, thereby avoiding the accumulation of static electricity on the first electrode connection line L1 and the second electrode connection line L2, which could lead to electrostatic breakdown.

[0130] In an exemplary implementation, such as Figure 8 As shown, multiple first electrostatic discharge circuits ST1 and multiple second electrostatic discharge circuits ST2 can be arranged in a stepped manner, and the edges of the first electrode connection line L1 and the second electrode connection line L2 are stepped.

[0131] In an exemplary implementation, such as Figure 8 As shown, the stepped shape of the plurality of first electrostatic discharge circuits ST1 and the plurality of second electrostatic discharge circuits ST2 is consistent with the stepped shape of the plurality of virtual sub-pixels P0; the stepped shape of the edges of the first electrode connection line L1 and the second electrode connection line L2 is consistent with the stepped shape of the plurality of virtual sub-pixels P0. In an exemplary embodiment, the plurality of sub-pixels located in at least one corner of the display area 100 can be arranged in a stepped manner, and the stepped shape of the plurality of virtual sub-pixels P0 is consistent with the stepped shape of the plurality of sub-pixels located in at least one corner of the display area 100. In an exemplary embodiment, the stepped shape of the plurality of virtual sub-pixels P0 and the plurality of sub-pixels in the corner area of ​​the display area 100, as well as the stepped shape of the edges of the first electrode connection line L1 and the second electrode connection line L2, are consistent, which can reduce the bezel of the display substrate and enable the irregularly shaped display substrate to simultaneously satisfy the requirements of smooth and delicate display at irregularly shaped display positions and narrow bezels.

[0132] In an exemplary implementation, such as Figure 8 As shown, the display substrate may further include:

[0133] The drive trace fan-out area g0 is located in the third frame area B3 and the fourth frame area B4, and is located on the side of the second electrode connection line L2 away from the display area 100. The drive trace fan-out area g0 located in the third frame area B3 extends to the first corner area C1 and the second corner area C2. The drive trace fan-out area g0 located in the fourth frame area B4 extends to the third corner area C3 and the fourth corner area C4.

[0134] The drive trace fan-out area g0 can fan out multiple drive traces. The multiple drive traces located in the second corner area C2 and the third corner area C3 are electrically connected to multiple second electrostatic discharge circuits ST2 and multiple first sub-pixel rows PX1, respectively.

[0135] In an exemplary embodiment, the drive routing package may include a plurality of first drive routings g01 and a plurality of second drive routings g02. In the drive routing fan-out area g0, the first drive routings g01 and the second drive routings g02 are arranged alternately.

[0136] In a direction perpendicular to the plane of the display substrate, the display substrate includes a substrate and a first gate metal layer and a second gate metal layer disposed on the substrate. The second gate metal layer is located on the side of the first gate metal layer away from the substrate. The first gate metal layer is provided with a plurality of first driving lines g01, and the second metal layer is provided with a plurality of second driving lines g02.

[0137] In an exemplary embodiment, the first electrode connection line L1 and the second electrode connection line L2 may be disposed on the second gate metal layer.

[0138] In an exemplary embodiment, the display substrate may further include a common electrode layer located on the side of the second gate metal layer away from the substrate;

[0139] The first gate metal layer may further include a plurality of first connecting electrodes and a plurality of second connecting electrodes corresponding to the plurality of first connecting electrodes. The plurality of first connecting electrodes are electrically connected to a plurality of first sub-pixel rows PX1 respectively. A portion of the second connecting electrodes are electrically connected to the first driving traces, and another portion of the second connecting electrodes are electrically connected to the second driving traces. The first connecting electrodes and the corresponding second connecting electrodes are spaced apart.

[0140] The common electrode layer includes multiple first transfer electrodes, which are electrically connected to multiple first connection electrodes, multiple second connection electrodes, and multiple second electrostatic discharge circuits ST2, respectively. The multiple first connection electrodes and the corresponding multiple second connection electrodes are electrically connected through multiple first transfer electrodes, and the multiple first connection electrodes can also be electrically connected to multiple second electrostatic discharge circuits ST2 through multiple first transfer electrodes.

[0141] In an exemplary embodiment, the first connecting electrode and the corresponding second connecting electrode are spaced apart and electrically connected through the first adapter electrode. The gate driving signal on the first driving line or the second driving line is transmitted to multiple sub-pixels in the corresponding first sub-pixel row through the second connecting electrode, the first adapter electrode, and the first connecting electrode. This can avoid the antenna effect caused by the first driving line or the second driving line connected to the second connecting electrode being too long.

[0142] In an exemplary implementation, such as Figure 11 As shown, the second electrostatic discharge circuit ST2 may include four transistors, which may include first transistor T1 to fourth transistor T4. The first terminal of the first transistor T1, the first terminal and the control terminal of the second transistor T2 are all electrically connected to the first sub-pixel row PX1 and the drive line fan-out area g0 (for example, electrically connected to the first drive line g01 fanned out by the drive line fan-out area g0, or electrically connected to the second drive line g02 fanned out by the drive line fan-out area g0). The second terminal and the control terminal of the first transistor T1, the second terminal of the second transistor T2 are electrically connected to the first terminal and the control terminal of the third transistor T3, and the first terminal of the fourth transistor T4. The second terminal of the third transistor T3, the second terminal and the control terminal of the fourth transistor T4 are all electrically connected to the second electrode connection line L2.

[0143] The following is combined with Figures 12a to 12e Detailed description of the structure of the second electrostatic discharge circuit ST2:

[0144] Figure 12a This is a schematic diagram of the planar structure of the active layer of the second electrostatic discharge circuit ST2. The active layer of the second electrostatic discharge circuit ST2 may include the active layer ACT1 of the first transistor T1, the active layer ACT2 of the second transistor T2, the active layer ACT3 of the third transistor T3, and the active layer ACT4 of the fourth transistor T4. The active layers ACT1 of the first transistor T1 to ACT4 of the fourth transistor T4 are rectangular. In the first direction X, the active layers ACT1 of the first transistor T1, ACT2 of the second transistor T2, ACT3 of the third transistor T3, and ACT4 of the fourth transistor T4 are arranged in sequence at intervals.

[0145] Figure 12bThe diagram shows a planar structure of the first gate metal layer of the second electrostatic discharge circuit. The first gate metal layer may include the control electrode S01 of the first transistor T1 to the control electrode S04 of the fourth transistor T4, a first connecting electrode R1, and a second connecting electrode R2. The second connecting electrode R2 and the first connecting electrode R1 are spaced apart along the first direction X. In the second direction Y, the first connecting electrode R1 and the second connecting electrode R2 are located on one side of the control electrode S01 of the first transistor T1 to the control electrode S04 of the fourth transistor T4. One end of the first connecting electrode R1 is integrally formed with the control electrode S01 of the first transistor T1, and the other end is electrically connected to multiple sub-pixels in one of the first sub-pixel rows PX1. The control electrode S02 of the second transistor T2 and the control electrode S03 of the third transistor T3 may be integrally formed. In the first direction X, the control electrodes S01 of the first transistor T1 to the control electrodes S04 of the fourth transistor T4 are arranged sequentially.

[0146] Figure 12c The diagram shows a planar structure of the second gate metal layer of the second electrostatic discharge circuit. The second gate metal layer may include a second driving trace g02, the first electrode d11 of the first transistor T1 to the first electrode d14 of the fourth transistor T4, and the second electrode d21 of the first transistor T1 to the second electrode d24 of the fourth transistor T4. The first electrode d11 of the first transistor T1 and the first electrode d12 of the second transistor T2 can be integrally formed; the second electrodes d21 of the first transistor T1, d12 of the second transistor T2, d13 of the third transistor T3, and d14 of the fourth transistor T4 can be integrally formed; the second electrodes d23 of the third transistor T3 and d24 of the fourth transistor T4 can be integrally formed. The driving trace g02 is fanned out from the driving trace fan-out area. The orthographic projection of the end of the driving trace away from the fan-out area on the substrate overlaps with the orthographic projection of the second connecting electrode R2 on the substrate. The orthographic projection of the first electrode d11 of the first transistor T1 on the substrate overlaps with the orthographic projection of the first connecting electrode R1 on the substrate. The orthographic projections of the second electrode d22 of the second transistor T2 and the first electrode d13 of the third transistor T3 on the substrate overlap with the orthographic projections of the control electrode S02 of the second transistor T2 and the control electrode S03 of the third transistor T3 on the substrate. The orthographic projections of the second electrode d23 of the third transistor T3 and the second electrode d24 of the fourth transistor T4 on the substrate overlap with the orthographic projection of the control electrode S04 of the fourth transistor T4 on the substrate.

[0147] Figure 12dThe diagram shows a planar schematic of a via pattern formed on a first gate metal layer and a second gate metal layer. The via pattern may include a first via V1 to an eighth via V8. The orthographic projection of the first via V1 onto the substrate lies within the range of the orthographic projection of the first connecting electrode R1 onto the substrate, exposing the surface of the first connecting electrode R1. The orthographic projection of the second via V2 onto the substrate lies within the range of the orthographic projections of the first electrode d11 of the first transistor T1 and the first electrode d12 of the second transistor T2 onto the substrate, exposing the surfaces of the first electrode d11 of the first transistor T1 and the first electrode d12 of the second transistor T2. The orthographic projection of the third via V3 onto the substrate lies within the range of the orthographic projections of the control electrode S02 of the second transistor T2 and the control electrode S03 of the third transistor T3 onto the substrate, exposing the surfaces of the control electrodes S02 of the second transistor T2 and the control electrode S03 of the third transistor T3. The orthographic projection of the fourth via V4 onto the substrate lies within the range of the orthographic projections of the second transistor T2 and the control electrode S03 of the third transistor T3. The second electrode d22 of transistor T2 and the first electrode d13 of transistor T3 are within the range of their orthogonal projections onto the substrate, exposing the surfaces of the second electrode d22 of transistor T2 and the first electrode d13 of transistor T3; the orthogonal projection of the fifth via V5 onto the substrate is within the range of the orthogonal projection of the control electrode S04 of transistor T4, exposing the surface of the control electrode S04 of transistor T4; the orthogonal projection of the sixth via V6 onto the substrate is within the range of the orthogonal projection of the second electrode d24 of transistor T4, exposing the surface of the second electrode d24 of transistor T4; the orthogonal projection of the seventh via V7 onto the substrate is within the range of the orthogonal projection of the second connection electrode R2, exposing the surface of the second connection electrode R2; the orthogonal projection of the eighth via V8 onto the substrate is within the range of the orthogonal projection of the second drive trace g02, exposing the surface of the second drive trace g02. In an exemplary embodiment, the number of first vias V1 to eighth vias V8 can be multiple to improve the robustness of the electrical connection.

[0148] Figure 12eThe diagram shows a planar structure of the common electrode layer of the second electrostatic discharge circuit. The common electrode layer may include a first transition electrode ZL1, a second transition electrode ZL2, and a third transition electrode ZL3. The orthographic projection of the first transition electrode ZL1 onto the substrate overlaps with the orthographic projections of the first connecting electrode R1, the second connecting electrode R2, the first electrode d11 of the first transistor T1, the first electrode d12 of the second transistor T2, and the second driving trace g02 onto the substrate. The first transition electrode ZL1 is electrically connected to the second connecting electrode R2 through a seventh via V7, and to the second connecting electrode R2 through an eighth via V8. The two driving traces g02 are electrically connected, and through the second via V2, they are electrically connected to the first electrode d11 of the first transistor T1 and the first electrode d12 of the second transistor T2. They are also electrically connected to the first connecting electrode R1 through the first via V1. Thus, through the first transition electrode ZL1, the electrical connections between the second connecting electrode R2, the first connecting electrode R1, the second driving trace g02, the first electrode d11 and control electrode S01 of the first transistor T1, and the first electrode d12 of the second transistor T2 are achieved. The orthogonal projection of the second transition electrode ZL2 onto the substrate is aligned with the second electrode d22 of the second transistor T2. The control electrode S02, the first electrode d13 of the third transistor T3, and the control electrode S03 have overlapping projections on the substrate. The second transfer electrode ZL2 is electrically connected to the control electrode S02 of the second transistor T2 and the control electrode S03 of the third transistor T3 through the third via V3, and to the second electrode d22 of the second transistor T2 and the first electrode d13 of the third transistor T3 through the fourth via V4. Thus, the second transfer electrode ZL2 enables the connection between the second electrode d22 of the second transistor T2 and the control electrode S02, and the first electrode d13 of the third transistor T3 and the control electrode S03. The electrical connection between them; the orthographic projection of the third transition electrode ZL3 on the substrate overlaps with the orthographic projections of the control electrode S04 and the second electrode d24 of the fourth transistor T4 and the second electrode d23 of the third transistor T2 on the substrate. The third transition electrode ZL3 is electrically connected to the control electrode S04 of the fourth transistor T4 through the fifth via V5 and to the second electrode d24 of the fourth transistor T4 through the sixth via V6. Thus, the electrical connection between the control electrode and the second electrode d24 of the fourth transistor T4 and the second electrode d23 of the third transistor T2 is realized through the third transition electrode ZL3.

[0149] In an exemplary embodiment, when the second connecting electrode R2 is electrically connected to the first driving trace g01, the second connecting electrode R2 and the first driving trace g01 can be an integrally formed structure, such as... Figure 12f As shown, the orthographic projection of the eighth via V8 on the substrate lies within the range of the orthographic projection of the second connecting electrode R2 on the substrate, and exposes the surface of the second connecting electrode R2; the first adapter electrode ZL1 is electrically connected to the second connecting electrode R2 through the eighth via V8, as shown. Figure 12g As shown.

[0150] In an exemplary implementation, such as Figure 12e As shown, the second electrode d23 of the third transistor T3 and the second electrode d24 of the fourth transistor T4, connected to the second electrode line L2, can be a single molded structure. The following section combines... Figure 11 and Figure 12e Describe the working principle of the second electrostatic discharge circuit ST2:

[0151] When a large amount of charge accumulates in the second electrode connection line L2, the voltage difference between the control electrode S04 and the first electrode d14 of the fourth transistor T4 due to the large amount of charge enables the fourth transistor T4 to conduct. The accumulated charge is transferred from the second electrode d24 of the fourth transistor T4 to the first electrode d14 of the fourth transistor T4. Since the first electrode d14 of the fourth transistor T4 is electrically connected to the control electrode S02 of the second transistor T2 and the control electrode S03 of the third transistor T3, the second transistor T2 and the third transistor T3 can conduct. The charge is transferred from the second electrode d22 of the second transistor T2 to the first electrode d12 of the second transistor T2. Since the first electrode d12 of the second transistor T2 is electrically connected to the control electrode S01 of the first transistor T1, the first transistor T1 conducts, thus enabling the first transistor to conduct. All transistors T1 to T4 are turned on. The charge on the second electrode connection line L2 can be transferred to the first electrode of the first transistor T1 and the second transistor T2 via the fourth transistor T4 and the third transistor T3. The first electrode of the first transistor T1 and the second transistor T2 is electrically connected to multiple sub-pixels in the first sub-pixel row PX1. The charge can be transferred from the first electrode of the first transistor T1 and the second transistor T2 to the first sub-pixel row PX1 corresponding to the display area 100. Since the second electrode connection line L2 is electrically connected to multiple second electrostatic discharge circuits ST2, and the multiple second electrostatic discharge circuits ST2 are electrically connected to multiple first sub-pixel rows PX1 respectively, the charge in the second electrode connection line L2 can be transferred to multiple sub-pixel rows PX1. The charge assigned to each sub-pixel row PX1 is not too large.

[0152] When a large amount of charge accumulates in the first sub-pixel row PX1 in the display area 100, it can be released into the second electrode connection line L2 based on the same principle. For example, when a large amount of charge accumulates in one of the sub-pixel rows PX1, the first transistor T1 can be turned on. The charge is transferred from the first terminal d11 to the second terminal d12 of the first transistor T1. The charge is transferred from the first terminal d11 to the second terminal d12 of the first transistor T1. Since the second terminal d12 of the first transistor T1 is connected to the second terminal d22 and the control terminal S02 of the second transistor T2, and the control terminal S03 and the first terminal of the third transistor T3, the charge can be transferred from the first terminal d11 to the second terminal d12. The d13 connection enables the second transistor T2 and the third transistor T3 to conduct, and charge is transferred from the first terminal d13 of the third transistor T3 to the second terminal d23 of the third transistor T3. Since the second terminal d23 of the third transistor T3 is electrically connected to the second terminal d24 of the fourth transistor T4 and the control terminal S04, the fourth transistor T4 is turned on. Therefore, the charge in the first sub-pixel row PX1 can be transferred via the first transistor T1 and the second transistor T2 to the second terminals of the third transistor T3 and the fourth transistor T4, and then transferred from the second terminals of the third transistor T3 and the fourth transistor T4 to the second electrode connection line L2. In an exemplary embodiment, as shown... Figure 13 As shown, the display substrate may further include:

[0153] The first fan-out area G1 of the data trace is located between the first corner area C1 and the fourth corner area C4, and between the second electrode connection line L2 and multiple virtual sub-pixels P0. Multiple first data lines D1 are fanned out from the first fan-out area G1 of the data trace.

[0154] In an exemplary embodiment, the distance h3 between the first fan-out area G1 of the data trace and the nearest virtual sub-pixel P0 is greater than or equal to 10 micrometers. In this embodiment, the distance h3 between the first fan-out area G1 of the data trace and the nearest virtual sub-pixel P0 is greater than or equal to 10 micrometers. This avoids short-circuiting of the virtual pixel P0 due to metal residue in the data traces within the first fan-out area G1. While the virtual pixel P0 does not participate in display operations, its internal traces are essentially consistent with the traces of the sub-pixels in the display area. During the fabrication of the data traces in the first fan-out area G1, if the distance between the virtual sub-pixel P0 and the first fan-out area G1 is too close, residual metal in the first fan-out area G1 and the fabrication process of the data traces may cause a short circuit in the virtual sub-pixel P0, thereby affecting the normal operation of the display substrate. Therefore, the solution provided in this embodiment can avoid the problem of short-circuiting the virtual sub-pixel P0.

[0155] In an exemplary embodiment, the distance h4 between the first fan-out area G1 of the data trace and the second electrode connection line L2 is greater than or equal to 20 micrometers. In this embodiment of the disclosure, the distance between the first fan-out area G1 of the data trace and the second electrode connection line L2 is greater than or equal to 20 micrometers, which can avoid signal interference between the first fan-out area G1 of the data trace and the second electrode connection line L2, as well as short circuit problems caused by metal residue.

[0156] In an exemplary implementation, such as Figure 7 and 13 As shown, the first frame area B1 is provided with a bonding area 200. The bonding area 200 includes a second fan-out area G2 for data traces, a fourth electrostatic discharge circuit area ST40, and two fifth electrostatic discharge circuit areas ST50. In a plane parallel to the display substrate, in the second direction Y, the second fan-out area G2 for data traces is located on the side of the fourth electrostatic discharge circuit area ST40 and the fifth electrostatic discharge circuit area ST50 away from the display area 100. In the first direction X, the two fifth electrostatic discharge circuit areas ST50 are located between the second electrode connection lines L2 of the fourth electrostatic discharge circuit area ST40, and the transient ST40 of the fourth electrostatic discharge circuit area is located between the two fifth electrostatic discharge circuit areas ST50.

[0157] In an exemplary implementation, such as Figure 14 As shown, Figure 13 A partially enlarged schematic diagram of the M4 position shows that the display area 100 is provided with multiple first sub-pixel columns PY1, multiple second sub-pixel columns PY2, and multiple second data lines D2. The multiple first data lines D1 are electrically connected to the multiple first sub-pixel columns PY1 respectively, and the multiple second data lines D2 are electrically connected to the multiple second sub-pixel columns PY2 respectively. In the first direction X, the area where the multiple first sub-pixel columns PY1 are located is located on both sides of the area where the multiple second sub-pixel columns PY2 are located. At least some sub-pixels in the first sub-pixel columns PY1 are located in at least one corner area of ​​the display area 100.

[0158] The fourth electrostatic discharge circuit area ST40 includes multiple fourth electrostatic discharge circuits ST4 arranged along the first direction X, and the fifth electrostatic discharge circuit area ST50 includes multiple fifth electrostatic discharge circuits ST5 arranged along the first direction X. The second fan-out area G2 of the data traces fans out multiple data traces, including multiple third data lines D3 and multiple fourth data lines D4. The multiple fourth data lines D4 are electrically connected to the multiple fourth electrostatic discharge circuits ST4 and the multiple second data lines D2, respectively. The multiple third data lines D3 are electrically connected to the multiple fifth electrostatic discharge sub-circuits ST5 and the multiple first data lines D1, respectively.

[0159] Multiple fourth electrostatic discharge circuits ST4 are electrically connected to the second electrode connection line L2, and are configured to respectively discharge the electrostatic discharge in the multiple second data lines D2 to the second electrode connection line L2, or respectively discharge the electrostatic discharge in the second electrode connection line L2 to the multiple second data lines D2.

[0160] Multiple fifth electrostatic discharge circuits ST5 are electrically connected to the second electrode connection line L2, and are configured to respectively discharge the static electricity in the multiple first data lines D1 to the second electrode connection line L2, or respectively discharge the static electricity in the second electrode connection line L2 to the multiple first data lines D1.

[0161] In an exemplary embodiment, in the second direction Y, multiple virtual sub-pixels P0 located on one side of multiple first sub-pixel columns PY1 can be located in the same sub-pixel column as their corresponding first sub-pixel columns PY1, and multiple virtual sub-pixels P0 located on one side of multiple second sub-pixel columns PY2 can be located in the same sub-pixel column as their corresponding second sub-pixel columns PY2. Figure 14 The PY1 and PY2 shown may include a sub-pixel located in the display area 100 and a virtual sub-pixel P0 located in the border area 300.

[0162] In an exemplary implementation, such as Figure 14 As shown, the display substrate may further include a plurality of first power connection lines VL1 and a plurality of second power connection lines VL2. The plurality of first power connection lines VL1 are electrically connected to a plurality of first sub-pixel columns PY1, and the plurality of second power connection lines VL2 are electrically connected to a plurality of second sub-pixel columns PY2. In an exemplary embodiment, the plurality of first power connection lines VL1 may also be electrically connected to a common electrode through an eleventh via V11, and the plurality of second power connection lines VL2 may also be electrically connected to a common electrode through a thirteenth via V13. Figure 13 and Figure 14 As shown, the first gate metal layer is also provided with a common electrode adapter line ZV. In the second direction Y, the common electrode adapter line ZV is located on the side of the fifth electrostatic discharge circuit area ST50 near the display area 100. In the first direction X, one end of the common electrode adapter line ZV is electrically connected to the common electrode through the tenth via V10, and the other end is electrically connected to the common electrode through the fourteenth via V14. The second electrode connection line L2 is electrically connected to the common electrode through the ninth via V9, thereby realizing the electrical connection between the common electrode adapter line ZV and the second electrode connection line L2.

[0163] In an exemplary embodiment, the circuit principles of the first electrostatic discharge circuit ST1, the third electrostatic discharge circuit ST3, the fourth electrostatic discharge circuit ST4, and the fifth electrostatic discharge circuit ST5 are described. Figure 1 To, as Figure 15As shown, the circuit may include two transistors: a fifth transistor T5 and a sixth transistor T6. The first electrode of the fifth transistor T5, the first electrode of the sixth transistor T6, and the control electrode are all electrically connected to the data trace DL. The second electrode of the fifth transistor T5 and the control electrode, as well as the second electrode of the sixth transistor T6, are all electrically connected to the data trace DL. When a large amount of static electricity accumulates in the data traces electrically connected to the display area 100, the static electricity can be released to the second electrode connection line L2. When a large amount of static electricity accumulates in the second electrode connection line L2, it can be released to multiple data traces DL. In an exemplary embodiment, in the fourth static discharge circuit ST4, the data trace DL can be the second data line D2, and in the fifth static discharge circuit ST5, the data trace DL can be the first data line D1.

[0164] The following is combined with Figures 16a to 16d Detailed description Figure 14 Structure of the M5 region:

[0165] Figure 16a The diagram shows a planar structure of the active layers of the fourth electrostatic discharge circuit ST4 and the fifth electrostatic discharge circuit ST5 at position M5. The active layers of the fourth electrostatic discharge circuit ST4 and the fifth electrostatic discharge circuit ST5 may include the active layer ACT5 of the fifth transistor T5 and the active layer ACT6 of the sixth transistor T6. The active layers ACT5 and ACT6 of the fifth transistor T5 in the fifth electrostatic discharge circuit ST5 are arranged along the second direction Y, and the active layers ACT5 and ACT6 of the fourth electrostatic discharge circuit ST4 are arranged along the first direction X.

[0166] like Figure 16b The diagram shows a planar structure after the first gate metal layer is formed at position M5. The first gate metal layer may include a common electrode adapter ZV, a control electrode S05 of the fifth transistor T5, a control electrode of the sixth transistor T6, a fourth adapter electrode ZL4, a third data line D3, and a fourth data line D4. In the second direction Y, the common electrode adapter ZV is located on the side of the fourth adapter electrode ZL4 away from the fourth electrostatic discharge circuit ST4. In the fifth electrostatic discharge circuit ST5, the fifth transistor T5 and the sixth transistor T6 are located on both sides of the common electrode adapter ZV. The control electrode S05 of the fifth transistor T5 in the fourth electrostatic discharge circuit ST4 and the fifth electrostatic discharge circuit ST5 can be integrally formed with the common electrode adapter ZV. Furthermore, in the second direction Y, the control electrode S05 of the fifth transistor T5 in the fourth electrostatic discharge circuit ST4 and the control electrode S05 in the fifth electrostatic discharge circuit ST5 are located on both sides of the common electrode adapter ZV. The third data line D3 and the fourth data line D4 located in the first gate metal layer can be integrally formed with the corresponding control electrode S06 of the sixth transistor.

[0167] like Figure 16cThe diagram shows a planar structure after the second gate metal layer is formed at position M5. The second gate metal layer may include a fifth transition electrode ZL5, a sixth transition electrode ZL6, a first power connection line VL1, a second voltage connection line VL2, a first data line D1, a second data line D2, a third data line D3, and a fourth data line D4. The third data line D3 in the second gate metal layer can be integrally formed with the first data line D1, and the fourth data line D4 in the second gate metal layer can be integrally formed with the second data line D2. The orthographic projections of the first power connection line VL1 and the second power connection line VL2 on the substrate overlap with the orthographic projection of the common electrode transition line ZV on the substrate. The second power connection line VL2 has an opening V0, configured to accommodate a via electrically connected to the common electrode.

[0168] like Figure 16dThe diagram shows a planar structure after a via pattern is formed at position M5. The via pattern can include eleventh via V11 to twenty-first via V21. The orthographic projection of the eleventh via V11 on the substrate overlaps with the orthographic projection of the first power connection line VL1 on the substrate, exposing the surface of the first power connection line VL1. The orthographic projection of the twelfth via V12 on the substrate overlaps with the orthographic projection of the common electrode adapter line ZV on the substrate, exposing the surface of the common electrode adapter line ZV. The orthographic projection of the thirteenth via V13 on the substrate overlaps with the orthographic projection of the second power connection line VL2 on the substrate, exposing the surface of the second power connection line VL2. The orthographic projection of the fourteenth via V14 on the substrate is within the range of the orthographic projection of the opening V0 on the substrate, exposing the surface of the common electrode adapter line ZV. The orthographic projection of the fifteenth via V15 on the substrate is within the range of the orthographic projection of the fifth adapter electrode ZL5 on the substrate, exposing the surface of the fifth adapter electrode ZL5. The sixteenth via V16 on the substrate... The orthographic projection of the 17th via V17 onto the substrate is within the range of the orthographic projection of the 4th via ZL4 onto the substrate, and exposes the surface of the 4th via ZL4. The orthographic projection of the 18th via V18 onto the substrate is within the range of the orthographic projection of the 1st data line D1 onto the substrate, and exposes the surface of the 1st data line D1. The orthographic projection of the 19th via V19 onto the substrate is within the range of the orthographic projection of the control electrode S06 of the 6th transistor T6 onto the substrate, and exposes the surface of the control electrode S06 of the 6th transistor T6. The orthographic projection of the 20th via V20 onto the substrate is within the range of the orthographic projection of the 2nd data line D2 onto the substrate, and exposes the surface of the 2nd data line D2. The orthographic projection of the 21st via V21 onto the substrate is within the range of the orthographic projection of the control electrode S06 of the 6th transistor T6 onto the substrate, and exposes the surface of the control electrode S06 of the 6th transistor T6.

[0169] like Figure 16eThe diagram shows a planar structure after the common electrode layer is formed at position M5. The common electrode layer may include a common electrode COM, a seventh transition electrode ZL7, an eighth transition electrode ZL8, and a ninth transition electrode ZL9. The orthographic projection of the seventh transition electrode ZL7 on the substrate overlaps with the orthographic projections of the fourth to sixth transition electrodes ZL4 to ZL6 on the substrate. The seventh transition electrode ZL7 is electrically connected to the fourth to sixth transition electrodes ZL4 to ZL6 through the fifteenth via V15 to the seventeenth via V16. The orthographic projection of the eighth transition electrode ZL8 on the substrate overlaps with the control electrode S06 of the sixth transistor T6 in the fifth electrostatic discharge circuit ST5 and the first data line D1. The eighth transition electrode ZL8 is connected to the control electrode S06 of the sixth transistor T6 in the fifth electrostatic discharge circuit ST5 through the eighteenth via V18 and the nineteenth via V19. 6 is electrically connected to the first data line D1; the orthographic projection of the ninth transfer electrode ZL9 on the substrate overlaps with the control electrode S06 of the sixth transistor T6 in the fourth electrostatic discharge circuit ST4 and the second data line D2. The ninth transfer electrode ZL9 is electrically connected to the control electrode S06 of the sixth transistor T6 in the fourth electrostatic discharge circuit ST4 and the second data line D2 through the twentieth via V20 and the twenty-first via V21; the orthographic projection of the tenth transfer electrode ZL10 on the substrate overlaps with the orthographic projections of the fourth transfer electrode ZL4, the fifth transfer electrode ZL5 and the sixth transfer electrode ZL6 in the fourth electrostatic discharge circuit ST4. The tenth transfer electrode ZL10 is electrically connected to the fourth transfer electrode ZL4, the fifth transfer electrode ZL5 and the sixth transfer electrode ZL6 in the fourth electrostatic discharge circuit ST4 through the seventeenth via V17 and the sixteenth via V16.

[0170] In an exemplary embodiment, the two transistors in the fifth electrostatic discharge circuit ST5 in the fifth electrostatic discharge circuit region ST50 are arranged along the second direction Y. This saves space in the first bezel area B1 of the display substrate, can accommodate a larger number of data traces, and can reduce the width of the third bezel area B3 and the fourth bezel area B4, thereby achieving a narrow bezel. In an exemplary embodiment, the orthographic projections of the common electrode adapter line ZV and the second electrode connection line L2 on the substrate overlap. The common electrode COM can be electrically connected to the common electrode adapter line ZV and the second electrode connection line L2 through the ninth via V9 and the tenth via V10, thereby achieving the electrical connection between the common electrode adapter line ZV and the second electrode connection line L2.

[0171] The following is combined with Figure 16e and Figure 15Explanation of the working principle of the fourth electrostatic discharge circuit: When a large amount of static electricity accumulates in the second electrode connection line L2, the electrical signal is transmitted to the control electrode S05 of the fifth transistor T5 through the tenth transfer electrode ZL10, causing the fifth transistor T5 to conduct. The accumulated charge is transferred from the second electrode of the fifth transistor T5 to the first electrode of the fifth transistor T5 (second data line D2). Since the first electrode of the fifth transistor T5 is electrically connected to the control electrode of the sixth transistor T6, the sixth transistor T6 conducts, thus the static electricity accumulated in the second electrode connection line L2 can be released to the second data line D2 (i.e., the first electrodes of the fifth transistor T5 and the sixth transistor T6) through the fifth transistor T5 and the sixth transistor T6. Because the second electrode connection line L2 is connected to multiple fourth electrodes through the fourth transfer electrode ZL4... Because of the electrostatic discharge connection, the static electricity accumulated in the second electrode connection line L2 can be transferred to multiple second data lines D2. The static charge acquired in each second data line D2 is not too large, and electrostatic breakdown will not occur. When a large amount of static electricity accumulates in the display area 100, it can be transferred to the control electrode of the sixth transistor T6 through multiple second data lines D2, causing the sixth transistor T6 to conduct. The static electricity is transferred from the first electrode of the sixth transistor T6 to the second electrode of the sixth transistor T6. Since the second electrode of the sixth transistor T6 is electrically connected to the control electrode of the fifth transistor T5, the fifth transistor T5 is turned on. Therefore, the static electricity in the second data line D2 can be transferred to the second electrode connection line L2 through the fourth transfer electrode ZL4 via the fifth transistor T5 and the sixth transistor T6.

[0172] In the exemplary embodiment, the working principle of the fifth electrostatic discharge circuit ST5, the first electrostatic discharge circuit ST1, and the third electrostatic discharge circuit ST3 is similar to that of the fourth electrostatic discharge circuit ST4, and will not be described again here.

[0173] In an exemplary embodiment, Figure 10 In the structure shown, the circuit schematic of the first electrostatic discharge circuit ST1 is similar to... Figure 15 The difference lies in that the second terminals of the fifth transistor T5 and the sixth transistor T6 are electrically connected to the first electrode connection line L1. In an exemplary embodiment, the first electrode connection line L1 can serve as the second terminals of the fifth transistor T5 and the sixth transistor T6 in the first electrostatic discharge circuit ST1; the circuit schematic of the third electrostatic discharge circuit ST3 is the same as... Figure 15 The difference is that the first electrode of the fifth transistor T5 and the sixth transistor T6 is electrically connected to the first electrode connection line L1; in an exemplary embodiment, the first electrode connection line L1 can be used as the first electrode of the fifth transistor T5 and the sixth transistor T6 in the third electrostatic discharge circuit ST3, and the second electrode connection line L2 can be used as the second electrode of the fifth transistor T5 and the sixth transistor T6 in the third electrostatic discharge circuit ST3.

[0174] In an exemplary embodiment, the first electrode connection line L1 and the second electrode connection line L2 can be electrically connected to the common electrode COM through a via.

[0175] In an exemplary embodiment, the fourth transfer electrode ZL4 can be electrically connected to the second electrode connection line L2 via a via, thus enabling the electrical connection of the fourth electrostatic discharge circuit ST4 and the fifth electrostatic discharge circuit ST5 to the second electrode connection line L2; alternatively, the display substrate may further include a sixth electrostatic discharge circuit ST6, located in the first corner region C1 and the fourth corner region C4, and on the side of the fifth electrostatic discharge circuit region ST50 near the second electrode connection line L2. In the first direction X, the sixth electrostatic discharge circuit ST6 is located between the second electrode connection line L2 and the fifth electrostatic discharge circuit region ST50, as shown below. Figure 17 The diagram shown is a structural schematic of the sixth electrostatic discharge circuit ST6. The circuit schematic of the sixth electrostatic discharge circuit ST6 is similar to... Figure 15The difference in the circuit schematic shown is that the first electrode of the fifth transistor T5, the first electrode and the control electrode of the sixth transistor T6 are all electrically connected to the second electrode connection line L2. The second electrode and the control electrode of the fifth transistor T5, and the second electrode of the sixth transistor T6 are electrically connected to the fourth transfer electrode ZL4. Correspondingly, the second electrode and the control electrode of the fifth transistor T5, and the second electrode of the sixth transistor T6 in the fifth electrostatic discharge circuit ST5 are electrically connected to the second electrode connection line L2 through the sixth electrostatic discharge circuit ST6. For example, the second electrode and the control electrode of the fifth transistor T5, and the second electrode of the sixth transistor T6 in the fifth electrostatic discharge circuit ST5 are all electrically connected to the fourth transfer electrode ZL4. Since the second electrode and the control electrode of the fifth transistor T5 and the second electrode of the sixth transistor T6 in the sixth electrostatic discharge circuit ST6 are electrically connected to the fourth transfer electrode ZL4, the fifth electrostatic discharge circuit ST5 is electrically connected to the second electrode connection electrode L2 through the sixth electrostatic discharge circuit ST6. The working principle of the sixth electrostatic discharge circuit ST6 is as follows: When a large amount of static electricity accumulates in the second electrode connection line L2, the sixth transistor T6 is turned on. The static electricity is transferred from the first terminal of the sixth transistor T6 to the second terminal. Since the second terminal of the sixth transistor T6 is electrically connected to the fourth transfer electrode ZL4, the fifth transistor T5 is turned on. The static electricity in the second electrode connection line L2 can be transferred to the fourth transfer electrode ZL4 through the fifth transistor T5 and the sixth transistor T6 in the sixth electrostatic discharge circuit ST6. After static electricity accumulates on the fourth transfer electrode ZL4, it can be released to multiple first data points through multiple fifth electrostatic discharge circuits ST5 respectively. In line D1, and through multiple fourth electrostatic discharge circuits ST4 to multiple second data lines D2; when a large amount of static electricity accumulates in the first data line D1, it can be released to the fourth transfer electrode ZL4 through the fifth electrostatic discharge circuit ST5; when a large amount of static electricity accumulates in the second data line D2, it can be released to the fourth transfer electrode ZL4 through the fourth electrostatic discharge circuit ST4, causing the fifth transistor T5 in the sixth electrostatic discharge circuit ST6 to conduct, thereby allowing the static electricity in the first data line D1 or the second data line D2 to be released to the second electrode connection line L2 through the fourth transfer electrode ZL4 and the fifth transistor T5 in the sixth electrostatic discharge circuit ST6.

[0176] In an exemplary embodiment, one end of the first electrode connecting line L1 can be directly connected to the second electrode connecting line L2. For example, one end of the first electrode connecting line L1 and the second electrode connecting line L2 can be an integrally formed structure; or, the first electrode connecting line L1 can be connected via... Figure 10 The third electrostatic discharge circuit ST3 shown is electrically connected.

[0177] This disclosure also provides a display device, including the display substrate described in any of the above embodiments.

[0178] In an exemplary implementation, such as Figure 18a and Figure 18b As shown, the display device may further include a first integrated circuit IC1 and a second integrated circuit IC2. The display substrate may include a display area 100 and a border area 300 surrounding the display area 100. The border area 300 on one side of the display area 100 is provided with a bonding area, which includes a first integrated circuit bonding area and a second integrated circuit bonding area. The first integrated circuit IC1 is bonded to the first integrated circuit area, and the second integrated circuit IC2 is bonded to the second integrated circuit bonding area.

[0179] In an exemplary embodiment Figure 18a The structures at positions M1 and M2 can be compared with... Figure 7 The structures of positions M1 and M2 are the same.

[0180] In an exemplary embodiment, the display device may further include a color filter substrate and conductive adhesive 600;

[0181] A color filter substrate and a display substrate are assembled together. Conductive adhesive is disposed between the color filter substrate and the display substrate, and is electrically connected to the electrode traces in the color filter substrate and the ground line GND in the display substrate, respectively. It is configured to release static electricity from the electrode traces in the color filter substrate to the ground line GND in the display substrate. In an exemplary embodiment, the electrode traces in the color filter substrate can be an electrode layer for collecting static electricity. In an exemplary embodiment, the first integrated circuit IC1 can be a data driving circuit (or can be called a data driving IC), and the second integrated circuit IC2 can be a gate driving circuit. Both the data driving circuit and the gate driving circuit can be two in number. The conductive adhesive can include two conductive adhesive dots 600. In the first direction X, the two gate driving circuits IC2 can be located on both sides of the two data driving circuits IC1, and the two data driving circuits IC1 can be located on both sides of the two conductive adhesive dots 600. Figure 18b As described above, IC1 is a data driving circuit, and IC2 is a gate driving circuit. The two data driving circuits, IC1, can be electrically connected to two flexible printed circuit boards (FPCs), respectively. Figure 18b for Figure 18a A schematic diagram of the structure in which the flexible circuit board FPC, the first integrated circuit IC1, and the second integrated circuit IC2 located in the bonding area 200 are bent to the back of the display substrate.

[0182] In an exemplary embodiment, in the first direction, the distance a2 between the centers of the two conductive adhesive dots 600 can be 30 mm to 45 mm, and the distance a1 between the conductive adhesive dot 600 and the nearest data driving circuit IC1 can be 20 mm to 25 mm. For example, the distance between the centers of the two conductive adhesive dots 600 is 35 mm, and the distance between the conductive adhesive dot 600 and the nearest data driving circuit IC1 is 22.9 mm. In embodiments of this disclosure, the distance between the two conductive adhesive dots 600 and the distance between the conductive adhesive dot 600 and the nearest data driving circuit IC1 can be set according to the size of the actual display device, and are not limited to the above-mentioned distances.

[0183] In an exemplary embodiment, since the second integrated circuit IC2 is disposed in the bonding area of ​​the display substrate, the conductive adhesive dots 600 disposed in the first corner area C1 and the fourth corner area C4 will interfere with the gate drive signal lines fanned out in the second integrated circuit IC2. Therefore, they need to be disposed between the two first integrated circuit IC1s to avoid interference between the conductive adhesive dots and the gate drive signal lines fanned out by the second integrated circuit IC2 and the data traces fanned out by the first integrated circuit IC1.

[0184] The display substrate and display device provided in the embodiments of this disclosure have at least one corner area of ​​the border area of ​​the display substrate with multiple virtual sub-pixels. The multiple virtual sub-pixels are located at the edge of the corner area of ​​the corresponding display area. At least a portion of the first sub-pixel row has at least one virtual sub-pixel on the side close to the corner area of ​​the corresponding border area. This can overcome the defect of uneven display at irregular display positions in irregular display devices.

[0185] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized in that, It includes a display area and a border area surrounding the display area. The display area includes at least one corner area, and the border area includes at least one corner area. The at least one corner area of ​​the display area and the at least one corner area of ​​the border area correspond to each other. The display area is provided with a plurality of first sub-pixel rows, and at least a portion of the sub-pixels in the first sub-pixel rows are located in at least one corner area of ​​the display area; at least one corner area of ​​the border area is provided with a plurality of virtual sub-pixels, and the plurality of virtual sub-pixels are located at the edge of the corner area of ​​the corresponding display area, and at least a portion of the first sub-pixel rows are provided with at least one virtual sub-pixel on the side of the corner area of ​​the corresponding border area. The border area further includes: a first border area and a second border area located on both sides of the display area along a second direction, and a third border area and a fourth border area located on both sides of the display area along a first direction; at least one corner area of ​​the border area includes: a second corner area connecting the third border area and the second border area, and a third corner area connecting the second border area and the fourth border area; The second corner area and the third corner area are provided with multiple first electrostatic discharge circuits, multiple second electrostatic discharge circuits, a third electrostatic discharge circuit, and a first electrode connection line; the third frame area and the fourth frame area are provided with a second electrode connection line. The plurality of first electrostatic discharge circuits are located on the side of the plurality of virtual sub-pixels away from the display area; the first electrode connection line is located on the side of the plurality of first electrostatic discharge circuits away from the display area; the second electrode connection line is located on the side of the first electrode connection line away from the display area; the second electrode connection line located in the third border area extends to the second corner area; the second electrode connection line located in the fourth border area extends to the third corner area; the plurality of second electrostatic discharge circuits are located on the side of the second electrode connection line away from the display area; the third electrostatic discharge circuit is located between the first electrode connection line and the second electrode connection line. The third electrostatic discharge circuit is electrically connected to the corresponding first electrode connection line and the corresponding second electrode connection line, and is configured to discharge static electricity in the corresponding first electrode connection line to the corresponding second electrode connection line, or discharge static electricity in the corresponding second electrode connection line to the corresponding first electrode connection line.

2. The display substrate according to claim 1, characterized in that, The multiple virtual sub-pixels are arranged in a stepped pattern at the corners of the corresponding border areas.

3. The display substrate according to claim 2, characterized in that, At least one corner region of the border area further includes: a first corner region connecting the first border area and the third border area, and a fourth corner region connecting the fourth border area and the first border area, wherein the first direction intersects the second direction on a plane parallel to the display substrate.

4. The display substrate according to claim 3, characterized in that, Also includes: A plurality of first data lines are located in the display area and extend to at least one corner area of ​​the border area, the plurality of first data lines being electrically connected to at least a portion of the sub-pixels located in at least one corner area of ​​the display area and configured to provide data signals to the at least a portion of the sub-pixels; The plurality of first electrostatic discharge circuits are respectively electrically connected to the plurality of first data lines; The first electrode connection line is electrically connected to the plurality of first electrostatic discharge circuits; The plurality of first electrostatic discharge circuits are configured to respectively discharge static electricity from the plurality of first data lines to the first electrode connection line, or to respectively discharge static electricity from the first electrode connection line to the plurality of first data lines.

5. The display substrate according to claim 4, characterized in that, The second electrode connection line located in the third frame area also extends to the first corner area, and the second electrode connection line located in the fourth frame area also extends to the fourth corner area; The plurality of second electrostatic discharge circuits are electrically connected to the plurality of first sub-pixel rows and the second electrode connection line, respectively, and are configured to release the static electricity in the second electrode connection line to the plurality of first sub-pixel rows, or release the static electricity in the plurality of first sub-pixel rows to the second electrode connection line.

6. The display substrate according to claim 5, characterized in that, The plurality of first electrostatic discharge circuits and the plurality of second electrostatic discharge circuits are arranged in a stepped manner, and the edges of the first electrode connection line and the second electrode connection line are stepped.

7. The display substrate according to claim 6, characterized in that, The stepped shape of the plurality of first electrostatic discharge circuits and the plurality of second electrostatic discharge circuits is consistent with the stepped shape of the plurality of virtual sub-pixels; the stepped shape of the edges of the first electrode connection line and the second electrode connection line is consistent with the stepped shape of the plurality of virtual sub-pixels.

8. The display substrate according to claim 5, characterized in that, In the second direction, the third electrostatic discharge circuit is disposed on the side of the first electrostatic discharge circuit at the end that is away from the display area, and is electrically connected to the end of the first electrode connection line on the side away from the second frame area; in the first direction, on one side of the display area, the first electrostatic discharge circuit at the end is the first electrostatic discharge circuit farthest from the second center line among the plurality of first electrostatic discharge circuits, and the second center line is the center line of the display area extending along the second direction.

9. The display substrate according to claim 5, characterized in that, Also includes: The drive trace fan-out area is located in the third frame area and the fourth frame area, and is located on the side of the second electrode connection line away from the display area. The drive trace fan-out area located in the third frame area extends to the first corner area and the second corner area, and the drive trace fan-out area located in the fourth frame area extends to the third corner area and the fourth corner area. The drive trace fan-out area fans out multiple drive traces, and the multiple drive traces located in the second corner area and the third corner area are respectively electrically connected to the multiple second electrostatic discharge circuits and the multiple first sub-pixel rows.

10. The display substrate according to claim 9, characterized in that, The drive trace includes a plurality of first drive traces and a plurality of second drive traces, and in the drive trace fan-out area, the first drive traces and the second drive traces are arranged alternately. In a direction perpendicular to the plane of the display substrate, the display substrate includes a substrate and a first gate metal layer and a second gate metal layer disposed on the substrate. The second gate metal layer is located on the side of the first gate metal layer away from the substrate. The first gate metal layer is provided with the plurality of first driving lines, and the second gate metal layer is provided with the plurality of second driving lines.

11. The display substrate according to claim 10, characterized in that, It also includes a common electrode layer, which is located on the side of the second gate metal layer away from the substrate; The first gate metal layer further includes a plurality of first connection electrodes and a plurality of second connection electrodes corresponding to the plurality of first connection electrodes. The plurality of first connection electrodes are electrically connected to a plurality of first sub-pixel rows respectively. A portion of the second connection electrodes are electrically connected to the first driving trace, and another portion of the second connection electrodes are electrically connected to the second driving trace. The first connection electrodes and the corresponding second connection electrodes are spaced apart. The common electrode layer includes a plurality of first transfer electrodes, which are electrically connected to the plurality of first connecting electrodes, the plurality of second connecting electrodes and the plurality of second electrostatic discharge circuits, respectively. The plurality of first connecting electrodes and the corresponding plurality of second connecting electrodes are electrically connected through the plurality of first transfer electrodes, and the plurality of first connecting electrodes are also electrically connected to the plurality of second electrostatic discharge circuits through the plurality of first transfer electrodes.

12. The display substrate according to claim 5, characterized in that, Also includes: The first fan-out area of ​​the data trace is located in the first corner area and the fourth corner area, and is located between the second electrode connection line and the plurality of virtual sub-pixels. The plurality of first data lines are fanned out by the first fan-out area of ​​the data trace.

13. The display substrate according to claim 12, characterized in that, The first frame area is provided with a bonding area, which includes a second fan-out area for data traces, a fourth electrostatic discharge circuit area, and two fifth electrostatic discharge circuit areas. In a plane parallel to the display substrate, in the second direction, the second fan-out area for data traces is located on the side of the fourth and fifth electrostatic discharge circuit areas away from the display area; in the first direction, the two fifth electrostatic discharge circuit areas are located between the fourth electrostatic discharge circuit area and the second electrode connection line, and the fourth electrostatic discharge circuit area is located between the two fifth electrostatic discharge circuit areas.

14. The display substrate according to claim 13, characterized in that, The display area is provided with a plurality of first sub-pixel columns, a plurality of second sub-pixel columns, and a plurality of second data lines. The plurality of first data lines are electrically connected to the plurality of first sub-pixel columns, and the plurality of second data lines are electrically connected to the plurality of second sub-pixel columns. In the first direction, the area where the plurality of first sub-pixel columns are located is located on both sides of the area where the plurality of second sub-pixel columns are located, and at least some sub-pixels in the first sub-pixel columns are located in at least one corner area of ​​the display area. The fourth electrostatic discharge circuit region includes a plurality of fourth electrostatic discharge circuits arranged along the first direction, and the fifth electrostatic discharge circuit region includes a plurality of fifth electrostatic discharge circuits arranged along the first direction. The second fan-out region of the data traces fans out a plurality of data traces, which include a plurality of third data lines and a plurality of fourth data lines. The plurality of fourth data lines are electrically connected to the plurality of fourth electrostatic discharge circuits and the plurality of second data lines, respectively. The plurality of third data lines are electrically connected to the plurality of fifth electrostatic discharge sub-circuits and the plurality of first data lines, respectively. The plurality of fourth electrostatic discharge circuits are electrically connected to the second electrode connection line and are configured to respectively discharge the static electricity in the plurality of second data lines to the second electrode connection line, or respectively discharge the static electricity in the second electrode connection line to the plurality of second data lines. The plurality of fifth electrostatic discharge circuits are electrically connected to the second electrode connection line and are configured to respectively discharge static electricity from the plurality of first data lines to the second electrode connection line, or to respectively discharge static electricity from the second electrode connection line to the plurality of first data lines.

15. The display substrate according to claim 3, characterized in that, The first corner area to the fourth corner area are provided with the plurality of virtual sub-pixels, and the plurality of virtual sub-pixels are arranged in the same way as the plurality of sub-pixels in the first sub-pixel row of the corner area of ​​the corresponding display area.

16. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 15.

17. The display device according to claim 16, characterized in that, It also includes a first integrated circuit and a second integrated circuit. The display substrate includes a display area and a border area surrounding the display area. The border area on one side of the display area is provided with a bonding area. The bonding area includes a first integrated circuit bonding area and a second integrated circuit bonding area. The first integrated circuit is bonded to the first integrated circuit area, and the second integrated circuit is bonded to the second integrated circuit bonding area.

18. The display device according to claim 17, characterized in that, It also includes color filter substrate and conductive adhesive; The color filter substrate and the display substrate are disposed together. The conductive adhesive is disposed between the color filter substrate and the display substrate and is electrically connected to the electrode traces in the color filter substrate and the ground line in the display substrate, respectively. It is configured to release static electricity in the electrode traces in the color filter substrate to the ground line in the display substrate.

19. The display device according to claim 18, characterized in that, The first integrated circuit is a data driving circuit, and the second integrated circuit is a gate driving circuit. Both the data driving circuit and the gate driving circuit are two in number. The conductive adhesive includes two conductive adhesive dots. In a first direction, the two gate driving circuits are located on both sides of the two data driving circuits, and the two data driving circuits are located on both sides of the two conductive adhesive dots.

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