Display substrate and display device

Abstract

A display substrate (91) comprises: a base substrate (10), a pixel circuit layer, a first flat layer (31), at least one transparent conductive layer (23) and a plurality of first light-emitting elements (13). The base substrate (10) comprises a first display area (A1) and a second display area (A2), wherein the first display area (A1) at least partially surrounds the second display area (A2). The pixel circuit layer is located in the first display area (A1) and comprises a plurality of pixel circuits, wherein the plurality of pixel circuits comprises a plurality of first pixel circuits (11). The plurality of first light-emitting elements (13) are located in the second display area (A2). The first flat layer (31) is located on a side of the pixel circuit layer away from the base substrate (10), and is located in the first display area (A1) and the second display area (A2). The transparent conductive layer (23) is located on a side of the first flat layer (31) away from the base substrate (10), and comprises a plurality of first transparent conductive lines and at least one auxiliary structure (233). The plurality of first light-emitting elements (13) and the plurality of first pixel circuits (11) are coupled via the plurality of first transparent conductive lines. The orthographic projection of the auxiliary structure (233) on the base substrate (10) overlaps with the orthographic projection of at least one pixel circuit on the base substrate (10).

Description

Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] Embodiments of the present disclosure provide a display substrate and a display device.

[0005] On the one hand, an embodiment of the present disclosure provides a display substrate, comprising: a base substrate, a pixel circuit layer, a first flat layer, at least one transparent conductive layer, and a plurality of first light-emitting elements. The base substrate comprises a first display area and a second display area, wherein the first display area at least partially surrounds the second display area. The pixel circuit layer is located in the first display area, and the pixel circuit layer comprises a plurality of pixel circuits, and the plurality of pixel circuits comprises a plurality of first pixel circuits. A plurality of first light-emitting elements are located in the second display area. The first flat layer is located on the side of the pixel circuit layer away from the base substrate, and is located in the first display area and the second display area. At least one transparent conductive layer is located on the side of the first flat layer away from the base substrate. The transparent conductive layer comprises: a plurality of first transparent conductive lines and at least one auxiliary structure, and the plurality of first light-emitting elements and the plurality of first pixel circuits are coupled through the plurality of first transparent conductive lines. The orthographic projection of the auxiliary structure on the base substrate overlaps with the orthographic projection of at least one pixel circuit among the plurality of pixel circuits on the base substrate.

[0006] In some exemplary embodiments, the display substrate further includes: a first conductive layer located between the pixel circuit layer and the first flat layer, the first conductive layer including: at least one blocking electrode, the blocking electrode being electrically connected to at least one pixel circuit among the plurality of pixel circuits, and an orthographic projection of the auxiliary structure on the base substrate overlaps with an orthographic projection of the blocking electrode on the base substrate.

[0007] In some exemplary embodiments, the pixel circuit layer includes: a second conductive layer, the second conductive layer includes a first power line, and the shielding electrode is electrically connected to the first power line.

[0008] In some exemplary embodiments, the auxiliary structure is electrically connected to the shielding electrode.

[0009] In some exemplary embodiments, the pixel circuit includes at least: a driving transistor, a threshold compensation transistor and a first reset transistor, wherein the driving transistor, the threshold compensation transistor and the first reset transistor are all electrically connected to the first node; the shielding electrode is configured to cover the orthographic projection of the first node of the pixel circuit on the substrate.

[0010] In some exemplary embodiments, the shielding electrode has an irregular shape as an orthographic projection on the base substrate.

[0011] In some exemplary embodiments, a second planar layer is disposed between the first conductive layer and the second conductive layer, and the first conductive layer is electrically connected to the second conductive layer through a first via hole penetrating the second planar layer; and an orthographic projection of at least one of the plurality of first transparent conductive lines on the base substrate overlaps with an orthographic projection of the first via hole on the base substrate.

[0012] In some exemplary embodiments, the first transparent conductive line includes an edge transparent conductive line, and the edge transparent conductive line is adjacent to the auxiliary structure.

[0013] In some exemplary embodiments, the auxiliary structure is located between two of the edge transparent conductive lines.

[0014] In some exemplary embodiments, a spacing between the auxiliary structure and the adjacent edge transparent conductive line is greater than or equal to 2 micrometers and less than or equal to 3 micrometers.

[0015] In some exemplary embodiments, the at least one auxiliary structure comprises: a plurality of regularly arranged auxiliary blocks.

[0016] In some exemplary embodiments, the plurality of auxiliary blocks of the auxiliary structure are arranged in an array, and the plurality of auxiliary blocks have substantially the same shape and size.

[0017] In some exemplary embodiments, an orthographic projection of the plurality of auxiliary blocks on the base substrate is a rectangle.

[0018] In some exemplary embodiments, the plurality of auxiliary blocks of the auxiliary structure are arranged in a ring shape.

[0019] In some exemplary embodiments, at least one auxiliary block of the auxiliary structure is electrically connected to the first power line.

[0020] In some exemplary embodiments, at least two adjacent auxiliary blocks of the auxiliary structure are connected by a connecting line.

[0021] In some exemplary embodiments, the plurality of auxiliary blocks of the auxiliary structure are divided into a plurality of groups, each group includes at least two auxiliary blocks, and the auxiliary blocks within a group are connected by connecting lines.

[0022] In some exemplary embodiments, the at least one auxiliary structure has an annular or mesh shape in an orthographic projection on the base substrate.

[0023] In some exemplary embodiments, the plurality of pixel circuits further include: a plurality of second pixel circuits located in the first display area; the display substrate further includes: a plurality of second light-emitting elements located in the first display area; at least one second pixel circuit among the plurality of second pixel circuits is electrically connected to at least one second light-emitting element among the plurality of second light-emitting elements, and the at least one second pixel circuit is configured to drive the at least one second light-emitting element.

[0024] On the other hand, an embodiment of the present disclosure provides a display device, including the display substrate as described above.

[0025] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shape and size of one or more components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0027] Figure 1 A schematic diagram of preparing a display substrate;

[0028] Figure 2 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0029] Figure 3 is a partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0030] Figure 4 is a schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure;

[0031] Figure 5 for Figure 4 Schematic diagram of a local section along the P-P' direction;

[0032] Figure 6 for Figure 4 A partial top view schematic diagram of a display substrate after a second conductive layer is formed;

[0033] Figure 7 for Figure 4 A partial top view schematic diagram of a display substrate after a transparent conductive layer is formed;

[0034] Figure 8 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure;

[0035] Fig. 9 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure;

[0036] Fig.10 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure;

[0037] Fig.11 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure;

[0038] Fig.12 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure;

[0039] Fig.13 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure;

[0040] Fig.14 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure;

[0041] Fig.15 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure;

[0042] Fig.16 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure;

[0043] Fig.17 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure;

[0044] Fig.18 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure;

[0045] Fig.19 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure;

[0046] Fig. 20 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure;

[0047] Fig.21 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure;

[0048] Fig. 22 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure;

[0049] Fig.23 for Fig. 22 Schematic diagram of a local cross section along the P-P' direction;

[0050] Fig.24 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure;

[0051] Fig.25 is a working timing diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0052] Fig.26 is a schematic top view of a pixel circuit according to at least one embodiment of the present disclosure;

[0053] Fig. 27 for Fig.26 A schematic diagram of a local cross section along the R-R' direction;

[0054] Fig.28A for Fig.26 A schematic top view of a display substrate after a semiconductor layer is formed;

[0055] Fig.28B for Fig.26 A schematic top view of a display substrate after a first gate metal layer is formed;

[0056] Fig.28C for Fig.26 A schematic top view of a display substrate after a second gate metal layer is formed;

[0057] Fig.28D for Fig.26 A schematic top view of a display substrate after a third insulating layer is formed;

[0058] Fig.28E for Fig.26 A schematic top view of a display substrate after a second conductive layer is formed;

[0059] Fig.29 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0060] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0061] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of one or more components in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0062] The ordinal numbers such as "first", "second", and "third" in this specification are provided to avoid confusion of constituent elements, and are not intended to limit the quantity. The "plurality" in this disclosure means two or more.

[0063] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the orientation of the constituent elements being described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the circumstances.

[0064] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this disclosure can be understood according to the circumstances.

[0065] In this specification, "electrically connected" and "coupled" include the case where the components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having multiple functions.

[0066] In this specification, a transistor refers to an element including at least three terminals: a gate, a drain, and a source. A transistor has a channel region between a drain (drain electrode terminal, a drain region, or a drain electrode) and a source (source electrode terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source. In this specification, a channel region refers to a region where current mainly flows.

[0067] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged. In addition, the gate electrode may also be called a control electrode.

[0068] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0069] The "light transmittance" in the present disclosure refers to the ability of light to pass through a medium, which is the percentage of the light flux passing through a transparent or translucent body to its incident light flux.

[0070] In the present disclosure, "about" and "substantially" mean that the limits are not strictly defined and the situation within the range of process and measurement errors is allowed. In the present disclosure, "substantially the same" means that the numerical values ​​differ by less than 10%.

[0071] In the present disclosure, “line length” refers to the length along the extension direction of the trace, and “line width” refers to the length in the plane where the trace is located and in a direction intersecting the extension direction of the trace (for example, a direction perpendicular to the extension direction).

[0072] In some implementations, the display substrate may include: an under-screen camera area and a normal display area located around the under-screen camera area. The under-screen camera area may only retain the light-emitting element, and the pixel circuit driving the light-emitting element of the under-screen camera area is set in the normal display area, and the light-emitting element of the under-screen camera area and the pixel circuit of the normal display area are electrically connected through the transparent conductive wires set in the transparent conductive layer. However, since the surrounding environment of the edge transparent conductive wire of the transparent conductive wire layer is relatively open, it is easy to be exposed to more exposure in the exposure process, which easily causes the line width of the edge transparent conductive wire to become thinner. Among them, the edge transparent conductive wire may refer to a transparent conductive wire having an open area on at least one side of the line width direction. The length of the open area along the line width direction of the transparent conductive wire may be greater than or equal to 8 microns. That is, the spacing between at least one side of the edge transparent conductive wire in the line width direction and the adjacent trace may be greater than or equal to 8 microns. For example, one side of the edge transparent conductive wire may be provided with an adjacent transparent conductive wire, and the spacing between the adjacent transparent conductive wire may be about 2 microns to 3 microns, such as 2.5 microns; the other side of the edge transparent conductive wire may have an open area. For another example, the edge transparent conductive line has open areas on both opposite sides in the line width direction.

[0073] In addition, in some implementations, there is also a situation where the width of the transparent conductive line becomes thinner or the line is broken due to the reflection and focusing effect of the conductive layer in the exposure process. Figure 1 Schematic diagram of the preparation of a display substrate. In some implementations, the display substrate may include: a base substrate 1, and a second conductive layer 2, a second flat layer 3, a first conductive layer 4, a first flat layer 5 and a transparent conductive layer disposed on the base substrate 1. Figure 1 FIG. 1 is a schematic diagram showing the principle of the exposure process in the preparation process of the transparent conductive layer. In some implementations, the preparation process of the transparent conductive layer includes: forming a transparent conductive film 6 on the first flat layer 5, forming a photoresist film 7 on the transparent conductive film 6, exposing the photoresist film 7 using a mask plate as a mask, so that the photoresist film forms a photoresist retaining portion and a photoresist to be removed portion, and performing a development process after the exposure process. In the development process, the photoresist to be removed portion is removed to form a photoresist pattern. The transparent conductive film 6 is etched using the photoresist pattern as a mask to form a transparent conductive layer. However, as Figure 1As shown, the first conductive layer 4 can overlap with the second conductive layer 2 through a via hole, and the overlapping structure of the first conductive layer 4 in the via hole can form a concave portion similar to a bowl. The opening direction of the concave portion is away from the substrate 1. Under light irradiation, the concave portion can form a focusing effect similar to a concave mirror. In the exposure process, the first conductive layer 4 of the metal material will reflect light and focus on the photoresist retention portion located above the concave portion of the first conductive layer 4, so that this part of the photoresist is exposed or partially exposed, and is washed away after development, so that the transparent conductive line formed after etching the transparent conductive film with the photoresist pattern as a mask is prone to disconnection or thinning. Therefore, at the via hole position of the second flat layer 3, due to the reflective focusing effect of the first conductive layer 4 in the exposure process, the photoresist film at the via hole position will become thinner, thereby causing the transparent conductive line finally formed to be disconnected or thinner, resulting in dark spots on the display.

[0074] The present embodiment provides a display substrate, comprising: a base substrate, a pixel circuit layer, a first flat layer, at least one transparent conductive layer, and a plurality of first light-emitting elements. The base substrate comprises a first display area and a second display area, and the first display area at least partially surrounds the second display area. The pixel circuit layer is located in the first display area, and comprises a plurality of pixel circuits, and the plurality of pixel circuits comprises a plurality of first pixel circuits. A plurality of first light-emitting elements are located in the second display area. The first flat layer is located on a side of the pixel circuit layer away from the base substrate, and is located in the first display area and the second display area. At least one transparent conductive layer is located on a side of the first flat layer away from the base substrate. The transparent conductive layer comprises: a plurality of first transparent conductive lines and at least one auxiliary structure. The plurality of first light-emitting elements and the plurality of first pixel circuits are coupled through the plurality of first transparent conductive lines. The orthographic projection of the auxiliary structure on the base substrate overlaps with the orthographic projection of at least one pixel circuit on the base substrate.

[0075] The display substrate provided in this embodiment can improve the exposure environment of the exposure process of the transparent conductive layer by arranging an auxiliary structure on the transparent conductive layer, thereby improving the situation where the first transparent conductive line of the transparent conductive layer is broken or the line width is thinned.

[0076] In some exemplary embodiments, the display substrate may further include: a first conductive layer located between the pixel circuit layer and the first flat layer. The first conductive layer may include: at least one shielding electrode, which may be electrically connected to at least one pixel circuit. The orthographic projection of the auxiliary structure on the base substrate may overlap with the orthographic projection of the shielding electrode on the base substrate. In this example, the auxiliary structure may be used to improve the situation where the transparent conductive line is broken or the line width is thinned due to the reflective focusing effect of the shielding electrode in the exposure process, thereby improving the yield of the display substrate.

[0077] In some exemplary embodiments, the pixel circuit layer may include: a second conductive layer, and the second conductive layer may include a first power line. The shielding electrode may be electrically connected to the first power line. In some examples, the auxiliary structure may be electrically connected to the shielding electrode. Among them, the auxiliary structure may be electrically connected to the first power line through the shielding electrode. However, this embodiment is not limited to this. For example, the auxiliary structure may be directly connected to the first power line, or the auxiliary structure may be connected to other signal lines that transmit direct current signals, or the auxiliary structure may not be electrically connected.

[0078] In some exemplary embodiments, the pixel circuit may include at least a driving transistor, a threshold compensation transistor, and a first reset transistor. The driving transistor, the threshold compensation transistor, and the first reset transistor are all electrically connected to the first node. The positive projection of the shielding electrode on the substrate substrate may be configured to cover the positive projection of the first node of the pixel circuit of the display substrate on the substrate substrate. In some examples, the positive projection of the shielding electrode on the substrate substrate may be an irregular shape. However, this embodiment is not limited to this.

[0079] In some exemplary embodiments, a second planar layer may be disposed between the first conductive layer and the second conductive layer, and the first conductive layer may be electrically connected to the second conductive layer through a first via hole penetrating the second planar layer. The orthographic projection of at least one of the plurality of first transparent conductive lines on the base substrate may overlap with the orthographic projection of the first via hole on the base substrate.

[0080] In some exemplary embodiments, the first transparent conductive line may include an edge transparent conductive line, and the edge transparent conductive line may be adjacent to the auxiliary structure. In this example, by providing an auxiliary structure adjacent to the edge transparent conductive line, the edge transparent conductive line may be reduced from receiving excessive exposure during the preparation process, and the edge transparent conductive line may be improved from being broken or having a thin line width, thereby improving the yield of the display substrate.

[0081] In some exemplary embodiments, the auxiliary structure may be located between two edge transparent conductive lines. For example, the auxiliary structure may be located between two edge transparent conductive lines, thereby improving the situation where the edge transparent conductive lines are broken or thinned, and improving the yield.

[0082] In some exemplary embodiments, the distance between the auxiliary structure and the adjacent edge transparent conductive line may be greater than or equal to 2 micrometers and less than or equal to 3 micrometers. For example, the distance between the auxiliary structure and the adjacent edge transparent conductive line may be about 2.5 micrometers.

[0083] In some exemplary embodiments, at least one auxiliary structure may include: a plurality of auxiliary blocks arranged in a regular pattern. In some examples, the plurality of auxiliary blocks of the auxiliary structure may be arranged in an array, and the shapes and sizes of the plurality of auxiliary blocks may be substantially the same. For example, the orthographic projections of the plurality of auxiliary blocks on the substrate substrate may be rectangular. In other examples, the plurality of auxiliary blocks of the auxiliary structure may be arranged in a ring shape, for example, in a rectangular ring shape. For example, the orthographic projections of the plurality of auxiliary blocks on the substrate substrate may be rectangular or L-shaped. However, this embodiment is not limited to this. For example, the orthographic projections of the auxiliary blocks on the substrate substrate may be circular, elliptical, quadrilateral, pentagonal or hexagonal, or other shapes.

[0084] In some exemplary embodiments, at least one auxiliary block of the auxiliary structure may be electrically connected to the first power line. For example, at least one auxiliary block may be electrically connected to the first power line through a shielding electrode.

[0085] In some exemplary embodiments, at least two adjacent auxiliary blocks of the auxiliary structure may be connected by a connecting line. In some examples, the plurality of auxiliary blocks of the auxiliary structure may be divided into a plurality of groups, each group may include at least two auxiliary blocks, and the auxiliary blocks within a group may be connected by connecting lines. The plurality of auxiliary blocks connected by the connecting lines may be electrically connected to the first power line, or the plurality of auxiliary blocks connected by the connecting lines may not be electrically connected to other signal lines.

[0086] In some exemplary embodiments, the orthographic projection of at least one auxiliary structure on the substrate may be annular or mesh-shaped. In this example, an auxiliary structure may be an integral structure. The auxiliary structure may be electrically connected to the first power line, or may not be electrically connected. However, this embodiment is not limited to this.

[0087] The solution of this embodiment is described below by means of some examples. The following description is made by taking the display substrate as a display substrate suitable for full screen and under-screen camera technology as an example. However, this embodiment is not limited to this.

[0088] Figure 2 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 3 FIG. 1 is a partial schematic diagram of a display substrate of at least one embodiment of the present disclosure. In some exemplary embodiments, Figure 2 and Figure 3As shown, the display substrate may include: a display area AA and a peripheral area BB. The peripheral area BB is a non-display area. The display area AA may include: a first display area A1 and a second display area A2. For example, hardware such as a photosensitive sensor (for example, a camera) is arranged on one side of the display substrate, and the orthographic projection of the photosensitive sensor on the display substrate overlaps with the second display area A2. The second display area A2 may be a light-transmitting display area, and may also be referred to as an under-screen camera (UDC, Under Display Camera) area; the first display area A1 may be a normal display area. For example, the first display area A1 is opaque and is only used for display. The display substrate of this embodiment can lay a solid foundation for the realization of a true full screen.

[0089] In some exemplary embodiments, Figure 2 As shown, the display area AA may be a rectangle, such as a rounded rectangle. The second display area A2 may be a rectangle, such as a rounded rectangle. However, this embodiment is not limited to this. For example, the second display area A2 may be a circle, other quadrilaterals or pentagons, etc.

[0090] In some exemplary embodiments, Figure 2 As shown, the display substrate may include: a base substrate and a plurality of sub-pixels located on the base substrate. The plurality of sub-pixels include: a plurality of first sub-pixels and a plurality of second sub-pixels. At least one first sub-pixel includes a first pixel circuit 11 and a first light-emitting element 13, and at least one second sub-pixel includes a second pixel circuit 12 and a second light-emitting element 14. The second pixel circuit 12 and the second light-emitting element 14 are both located in the first display area A1, the first pixel circuit 11 is located in the first display area A1, and the first light-emitting element 13 is located in the second display area A2. The plurality of first pixel circuits 11 may be distributed at intervals between the plurality of second pixel circuits 12. For example, the second pixel circuit 12 may be referred to as an in-situ pixel circuit, and the first pixel circuit 11 may be referred to as a non-in-situ pixel circuit. In the second display area A2, the area between adjacent first light-emitting elements 13 is a light-transmitting sub-area, and the area where the first light-emitting element 13 is located is a display sub-area. No pixel circuit is set in the second display area A2. Only light-emitting elements are set in the second display area A2, and the pixel circuit driving the light-emitting elements of the second display area A2 is set in the first display area A1. That is, the light transmittance of the second display area A2 can be improved by separating the light-emitting elements and the pixel circuit.

[0091] In some exemplary embodiments, the shape of the light-emitting element of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels may be arranged in parallel horizontally, vertically, or in a triangle; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels may be arranged in parallel horizontally, vertically, or in a square. However, this embodiment is not limited to this.

[0092] In some exemplary embodiments, Figure 2 As shown, at least one second pixel circuit 12 among the plurality of second pixel circuits 12 may be electrically connected to at least one second light-emitting element 14 among the plurality of second light-emitting elements 14, and the orthographic projection of at least one second pixel circuit 12 on the substrate substrate at least partially overlaps with the orthographic projection of at least one second light-emitting element 14 on the substrate substrate. The at least one second pixel circuit 12 may be configured to provide a driving signal to the electrically connected second light-emitting element 14 to drive the second light-emitting element 14 to emit light.

[0093] Figure 2 Taking the first pixel circuit 11 driving the first light-emitting element 13 to emit light as an example, the display substrate in this case can adopt a pixel circuit compression scheme, in which the size of the pixel circuit in the first direction X is reduced, so that the first pixel circuit 11 and the second pixel circuit 12 can be placed in the first direction X, and the first pixel circuit 11 can be dispersedly arranged in the second pixel circuit 12. For example, the first direction X is a row direction, and in the same row of pixel circuits, the first pixel circuit 11 can be arranged in the second pixel circuit 12 at intervals. However, this embodiment is not limited to this. For example, the first pixel circuit 11 can be located in the peripheral area, thereby forming a pixel circuit externalization scheme.

[0094] In some exemplary embodiments, Figure 2 As shown, the first display area A1 may be located on at least one side of the second display area A2. For example, the first display area A1 may surround the second display area A2. That is, the second display area A2 may be surrounded by the first display area A1. In other examples, the second display area A2 may be set at other positions, for example, it may be located at the top middle position of the substrate, or at the upper left corner position or the upper right corner position of the substrate. However, this embodiment is not limited to this.

[0095] In some exemplary embodiments, Figure 2 and Figure 3 As shown, at least one first pixel circuit 11 among the plurality of first pixel circuits 11 and at least one first light-emitting element 13 among the plurality of first light-emitting elements 13 may be electrically connected through a transparent conductive line L. One end of the transparent conductive line L is electrically connected to the first pixel circuit 11, and the other end is electrically connected to the first light-emitting element 13. The transparent conductive line L may extend from the first display area A1 to the second display area A2. For example, the transparent conductive line L may extend from the first display area A1 to the second display area A2 along the first direction X; or, the transparent conductive line L may first extend along the second direction Y in the first display area A1, and then extend along the first direction X to the second display area A2. However, this embodiment is not limited to this.

[0096] In some exemplary embodiments, the transparent conductive line L may be made of a transparent conductive material, for example, a conductive oxide material, such as indium tin oxide (ITO). However, this embodiment is not limited to this. In some examples, the transparent conductive line L may be arranged in a transparent conductive layer, or a plurality of transparent conductive lines L may be arranged in two or three transparent conductive layers. Each transparent conductive line L may connect a first pixel circuit 11 and a first light-emitting element 13. Alternatively, a first pixel circuit 11 and a first light-emitting element 13 may be electrically connected by connecting a plurality of transparent conductive lines L located in different transparent conductive layers in sequence.

[0097] In some exemplary embodiments, at least one first pixel circuit 11 may be configured to provide a driving signal to at least one first light-emitting element 13 electrically connected thereto, so as to drive the first light-emitting element 13 to emit light. The first pixel circuit 11 and the first light-emitting element 13 are located in different regions, and the orthographic projection of the first pixel circuit 11 on the substrate substrate may not overlap with the orthographic projection of the at least one first light-emitting element 13 on the substrate substrate. Figure 2 As shown, the first light-emitting element 13 and the first pixel circuit 11 electrically connected thereto may be located in the same row. That is, the driving signal of the first light-emitting element 13 comes from the first pixel circuit 11 in the same row. For example, the pixel circuits of the sub-pixels in the same row are electrically connected to the same gate line. However, this embodiment is not limited to this. For example, the first light-emitting element and the first pixel circuit electrically connected thereto may not be located in the same row.

[0098] Figure 4 The diagram is a top view of a local film layer of a display substrate according to at least one embodiment of the present disclosure. Figure 4 Can be Figure 3 A partial enlarged schematic diagram of the middle area S. Figure 5 for Figure 4 Schematic diagram of a partial cross section along the P-P' direction. In this example, one transparent conductive layer is used as an example for illustration. However, this embodiment is not limited to this. For example, the display substrate may include multiple transparent conductive layers. Figure 4 and Figure 5 The structure of multiple film layers on the side of the second conductive layer close to the display substrate and the multiple film layers on the side of the transparent conductive layer away from the base substrate are omitted.

[0099] In some exemplary embodiments, Figure 4 and Figure 5As shown, in a direction perpendicular to the display substrate, the display substrate of the first display area A1 may include: a base substrate 10, a pixel circuit layer (for example, including a second conductive layer 22) disposed on the base substrate 10, a second flat layer 32, a first conductive layer 21, a first flat layer 31, and a transparent conductive layer 23. A third flat layer, an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode layer may also be disposed on the side of the transparent conductive layer 23 away from the base substrate 10. In some examples, the pixel circuit layer may include: a semiconductor layer, a first insulating layer, a first gate metal layer, a second insulating layer, a second gate metal layer, a third insulating layer, and a second conductive layer disposed sequentially on the base substrate 10. In some examples, the second conductive layer 22 may also be referred to as a first source-drain metal layer, and the first conductive layer 21 may also be referred to as a second source-drain metal layer. The first flat layer 31 and the second flat layer 32 may be organic material layers. However, this embodiment is not limited thereto.

[0100] Figure 6 for Figure 4 A partial top view schematic diagram of a display substrate after the first conductive layer is formed in FIG. Figure 6 The first conductive layer 21 and the second conductive layer 22 are illustrated in FIG. Figure 7 for Figure 4 A partial top view schematic diagram of a display substrate after a transparent conductive layer is formed. Figure 7 The first conductive layer 21 and the transparent conductive layer 23 are illustrated in FIG.

[0101] In some exemplary embodiments, Figures 4 to 7 As shown, the second conductive layer 22 may include at least: a plurality of data lines (e.g., data lines DL), a plurality of first power lines (e.g., first power lines PL1), and a plurality of connection electrodes (e.g., including first anode connection electrodes 220). The data lines DL and the first power lines PL1 may extend along the second direction Y, and the data lines DL and the first power lines PL1 are adjacent to each other in the first direction X. The first direction X intersects the second direction Y, for example, the first direction X and the second direction Y are perpendicular to each other.

[0102] In some exemplary embodiments, Figures 4 to 7 As shown, the first conductive layer 21 may include at least: a plurality of shielding electrodes 211, a plurality of connecting electrodes (for example, including a second anode connecting electrode 210). The second anode connecting electrode 210 may be electrically connected to the first anode connecting electrode 220 via a first via hole K1b provided on the second flat layer 32. The shielding electrode 211 may be electrically connected to the first power line PL1 via a first via hole K1a provided on the second flat layer 32.

[0103] In some examples, such as Figures 4 to 7As shown, the transparent conductive layer 23 may include at least: a plurality of first transparent conductive lines (for example, edge transparent conductive lines 231a and 231b, non-edge transparent conductive lines 232), and an auxiliary structure 233. Among them, the edge transparent conductive lines 231a and 231b have an open area on one side in the direction of the line width, and the orthographic projection of the edge transparent conductive line 231a on the substrate substrate and the orthographic projection of the first via K1a on the substrate substrate may overlap. The non-edge transparent conductive line 232 has adjacent lines on both sides in the direction of the line width. For example, the non-edge transparent conductive line 232 may be located between the edge transparent conductive lines 231a and 231b. One side of the edge transparent conductive line 231a may be adjacent to the non-edge transparent conductive line 232, and an auxiliary structure 233 may be provided in the open area on the other side. The auxiliary structure 233 may be located between the edge transparent conductive lines 231a and 231b. The auxiliary structure 233 of this example may not be electrically connected and is an invalid (Dummy) structure.

[0104] In some examples, such as Figure 7 As shown, the edge transparent conductive lines 231a and 231b and the non-edge transparent conductive line 232 can all extend along the second direction Y. The line widths of the edge transparent conductive lines and the non-edge transparent conductive lines can be substantially the same, for example, can be approximately 2.0 microns to 2.5 microns, such as approximately 2.3 microns. However, this embodiment is not limited to this. For example, the line width of the edge transparent conductive line can be greater than the line width of the non-edge transparent conductive line.

[0105] In some examples, such as Figure 7 As shown, the spacing between the non-edge transparent conductive line 232 and the adjacent transparent conductive line in the first direction X can be substantially the same, for example, can be about 2.0 microns to 2.5 microns, such as about 2.2 microns. The length H1 of the open area between the edge transparent conductive lines 231a and 231b in the first direction X can be greater than or equal to 8 microns, for example, can be about 8 microns or 9 microns.

[0106] In some examples, such as Figure 7 As shown, the auxiliary structure 233 may be located in the open area between the edge transparent conductive lines 231a and 231b. The auxiliary structure 233 may include a plurality of auxiliary blocks 2330 arranged in a ring shape (e.g., a rectangular ring). The plurality of auxiliary blocks 2330 may be arranged in sequence along the second direction Y and close to the edge transparent conductive lines 231a and 231b. The orthographic projection of a portion of the auxiliary blocks 2330 of the auxiliary structure 233 on the substrate substrate may overlap with the orthographic projection of the shielding electrode 211 on the substrate substrate, and the orthographic projection of another portion of the auxiliary blocks 2330 on the substrate substrate may not overlap with the orthographic projection of the shielding electrode 211 on the substrate substrate. In other examples, the plurality of auxiliary blocks 2330 of the auxiliary structure 233 may be arranged in other shapes such as a circular ring, an elliptical ring, etc.

[0107] In some examples, such as Figure 7 As shown, the shapes and sizes of the multiple auxiliary blocks 2330 of the auxiliary structure 233 may be substantially the same. The orthographic projection of the auxiliary block 2330 on the substrate substrate may be a rectangle. The length of the auxiliary block 2330 along the first direction X may be greater than or equal to 1 micron and less than or equal to 2 microns, and the length along the second direction Y may be greater than or equal to 1 micron and less than or equal to 2 microns. For example, the orthographic projection of the auxiliary block 2330 on the substrate substrate may be a square of 1 micron × 1 micron size, or a square of 1 micron × 1 micron size. However, this embodiment does not limit the shape of the auxiliary block. For example, the orthographic projection of the auxiliary block on the substrate substrate may be a circle, an ellipse, a pentagon, a hexagon or other shapes. The auxiliary structure of this example may include a plurality of auxiliary blocks that are not electrically connected, and the size of the auxiliary block is not large, which can avoid affecting the signal transmission of the first transparent conductive line.

[0108] In some examples, such as Figure 7 As shown, the spacing H2 between adjacent auxiliary blocks 2330 in the first direction X and the spacing H3 between adjacent auxiliary blocks 2330 in the second direction Y may be substantially the same. For example, H2 and H3 may be greater than or equal to 1 micron and less than or equal to 2 microns, for example, may be approximately 1 micron or 1.5 microns. The spacing between the auxiliary structure 233 and the adjacent edge transparent conductive line 231a may be substantially the same as the spacing between the auxiliary structure 233 and the adjacent edge transparent conductive line 231b. Figure 7 In the embodiment, the distance between the auxiliary structure 233 and the adjacent edge transparent conductive line 231a is the distance H4 between the auxiliary block 2330 of the auxiliary structure 233 closest to the edge transparent conductive line 231a and the edge transparent conductive line 231a. In some examples, H4 may be greater than or equal to 2 microns and less than or equal to 3 microns, for example, may be approximately 2 microns, or 2.5 microns, or 3 microns. However, this embodiment is not limited thereto.

[0109] In this example, by providing a plurality of auxiliary blocks arranged in a ring in the open area outside the first transparent conductive line, the exposure environment of the exposure process for preparing the transparent conductive layer can be improved (for example, the reflection of light in the first via hole can be reduced, and the amount of exposure received by the first transparent conductive line can be reduced), thereby affecting the line width of the first transparent conductive line. In addition, the situation in which the first transparent conductive line is broken or thinned due to the reflective focusing effect of the first conductive layer in the exposure process can also be improved.

[0110] Figure 8 FIG. 1 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure. Figure 8In the figure, only the first conductive layer and the transparent conductive layer are shown, and other film layers are omitted. Figure 8 As shown, an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231a and 231b. The auxiliary structure 233 includes a plurality of auxiliary blocks 2330 arranged in a rectangular ring. Adjacent auxiliary blocks 2330 of the auxiliary structure 233 can be connected by connecting wires 2331. In this example, the connecting wires 2331 can sequentially connect the plurality of auxiliary blocks 2330 along the rectangular ring. The remaining structures of the display substrate of this embodiment can refer to the description of the aforementioned embodiment, so they are not described here in detail.

[0111] Fig. 9 FIG. 1 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure. Fig. 9 In the figure, only the first conductive layer and the transparent conductive layer are shown, and other film layers are omitted. Fig. 9 As shown, an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231a and 231b. The auxiliary structure 233 includes a plurality of auxiliary blocks 2330 arranged in a rectangular ring. Adjacent auxiliary blocks 2330 of the auxiliary structure 233 can be connected by connecting wires 2331. In this example, the connecting wires 2331 can sequentially connect the plurality of auxiliary blocks 2330 along the rectangular ring. At least one auxiliary block 2330 whose orthographic projection on the base substrate overlaps with the orthographic projection of the shielding electrode 211 of the first conductive layer on the base substrate can be electrically connected to the shielding electrode 211 through a second via K2 opened in the first flat layer. The shielding electrode 211 can be electrically connected to the first power line located in the second conductive layer. The plurality of auxiliary blocks 2330 of the auxiliary structure 233 can be electrically connected to the first power line through the connecting wires 2331 and the shielding electrode 211. In this example, by electrically connecting the auxiliary structure 233 to the first power line, the influence of the floating connection of the auxiliary structure 233 on other signal lines can be improved. The remaining structures of the display substrate of this embodiment can refer to the description of the aforementioned embodiment, and thus will not be described in detail here.

[0112] Fig.10 FIG. 1 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure. Fig.10 In the figure, only the first conductive layer and the transparent conductive layer are shown, and other film layers are omitted. Fig.10As shown, an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231a and 231b. The auxiliary structure 233 includes a plurality of auxiliary blocks 2330 arranged in a rectangular ring. The plurality of auxiliary blocks 2330 arranged in the width direction of the transparent conductive line can be connected by a connecting line 2331, and there is no connection between the adjacent auxiliary blocks 2330 arranged in the length direction of the transparent conductive line. For example, the plurality of auxiliary blocks 2330 of the auxiliary structure 233 can be divided into a plurality of groups according to the column direction, each group including a row of auxiliary blocks 2330 (for example, including two or three auxiliary blocks), and the auxiliary blocks 2330 in a group can be connected by a connecting line 2331. The auxiliary blocks 2330 between adjacent groups are not electrically connected. In this example, the auxiliary blocks 2330 of each group can be electrically connected to the first power line, or can be not electrically connected. However, this embodiment is not limited to this. The remaining structures of the display substrate of this embodiment can refer to the description of the aforementioned embodiment, so it is not repeated here.

[0113] Fig.11 FIG. 1 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure. Fig.11 In the figure, only the first conductive layer and the transparent conductive layer are shown, and other film layers are omitted. Fig.11 As shown, an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231a and 231b. The auxiliary structure 233 may include a plurality of auxiliary blocks 2330 arranged in a rectangular ring. For example, the plurality of auxiliary blocks 2330 of the auxiliary structure 233 may be divided into two groups, wherein the first group may include the first row and the first column of auxiliary blocks 2330, and the second group may include the last row and the second column of auxiliary blocks 2330, and the auxiliary blocks 2330 in each group may be electrically connected by connecting wires 2331. There may be no connection between the first group and the second group. In this example, the auxiliary blocks 2330 of each group may be electrically connected to the first power line, or may not be electrically connected. However, this embodiment is not limited to this. The remaining structures of the display substrate of this embodiment may refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0114] Fig.12 FIG. 1 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure. Fig.12 In the figure, only the first conductive layer and the transparent conductive layer are shown, and other film layers are omitted. Fig.12As shown, an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231a and 231b. The auxiliary structure 233 includes a plurality of auxiliary blocks 2330 arranged in a rectangular ring. A plurality of (for example, six) auxiliary blocks 2330 whose orthographic projections on the base substrate overlap with the orthographic projections of the shielding electrode 211 of the first conductive layer on the base substrate can be electrically connected to the shielding electrode 211 through the second via K2 opened in the first flat layer. The shielding electrode 211 can be electrically connected to the first power line located in the second conductive layer. A portion of the auxiliary blocks 2330 of the auxiliary structure 233 can be electrically connected to the first power line through the shielding electrode 211, and another portion of the auxiliary blocks 2330 can have no electrical connection. The remaining structures of the display substrate of this embodiment can refer to the description of the aforementioned embodiment, so they will not be repeated here.

[0115] Fig.13 FIG. 1 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure. Fig.13 In the figure, only the first conductive layer and the transparent conductive layer are shown, and other film layers are omitted. Fig.13 As shown, an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231a and 231b. The auxiliary structure 233 may include a plurality of auxiliary blocks 2330 arranged in an array. The auxiliary blocks 2330 of this example may be an invalid structure without electrical connection. A plurality of auxiliary blocks 2330 may be arranged in an array along the second direction Y and the first direction X. The orthographic projection of a part of the auxiliary blocks 2330 of the auxiliary structure 233 on the substrate substrate may overlap with the orthographic projection of the shielding electrode 211 located in the first conductive layer on the substrate substrate, and the orthographic projection of another part of the auxiliary blocks 2330 on the substrate substrate may not overlap with the orthographic projection of the shielding electrode 211 on the substrate substrate. The shapes and sizes of the plurality of auxiliary blocks 2330 of the auxiliary structure 233 may be substantially the same. The orthographic projection of the auxiliary block 2330 on the substrate substrate may be substantially rectangular. However, this embodiment is not limited thereto. The remaining structures of the display substrate of this embodiment may refer to the description of the aforementioned embodiment, so they will not be repeated here.

[0116] Fig.14 FIG. 1 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure. Fig.14 In the figure, only the first conductive layer and the transparent conductive layer are shown, and other film layers are omitted. Fig.14As shown, an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231a and 231b. The auxiliary structure 233 may include a plurality of auxiliary blocks 2330 arranged in an array. Adjacent auxiliary blocks 2330 may be connected by connecting lines 2331. The plurality of auxiliary blocks 2330 of the auxiliary structure 233 are connected to form a mesh structure. At least one auxiliary block 2330 where the orthographic projection of the base substrate overlaps with the orthographic projection of the shielding electrode 211 on the base substrate may be electrically connected to the shielding electrode 211 through a second via K2 provided in the first flat layer, thereby achieving electrical connection with the first power line through the shielding electrode 211. The remaining structures of the display substrate of this embodiment may refer to the description of the aforementioned embodiment, so they will not be described in detail here.

[0117] Fig.15 FIG. 1 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure. Fig.15 In the figure, only the first conductive layer and the transparent conductive layer are shown, and other film layers are omitted. Fig.15 As shown, an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231a and 231b. The auxiliary structure 233 may include a plurality of auxiliary blocks 2330 arranged in an array. The plurality of auxiliary blocks 2330 of the auxiliary structure 233 may be divided into a plurality of groups according to the column direction, and each group may include a row of auxiliary blocks 2330. The auxiliary blocks 2330 of each group may be connected by connecting lines 2331. The auxiliary blocks 2330 of adjacent groups may not be connected. At least one group of auxiliary blocks 2330 may be electrically connected to the first power line, or multiple groups of auxiliary blocks may not be electrically connected to the first power line. This embodiment does not limit this. The remaining structures of the display substrate of this embodiment may refer to the description of the aforementioned embodiment, so they will not be repeated here.

[0118] Fig.16 FIG. 1 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure. Fig.16 In the figure, only the first conductive layer and the transparent conductive layer are shown, and other film layers are omitted. Fig.16As shown, an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231a and 231b. The auxiliary structure 233 may include a plurality of auxiliary blocks 2330 arranged in an array. The plurality of auxiliary blocks 2330 of the auxiliary structure 233 may be divided into three groups; the first group may include a plurality of auxiliary blocks 2330 of the first column and exclude the auxiliary blocks of the penultimate row and the second row; the second group may include a plurality of auxiliary blocks 2330 of the second column and part of the auxiliary blocks of the penultimate row, and exclude the auxiliary blocks of the third column and the penultimate row; the third group may include a plurality of auxiliary blocks 2330 of the third column and the auxiliary blocks of the penultimate row. The auxiliary blocks of the first group may be connected to form a strip, and the auxiliary blocks of the second and third groups may be connected to form an L shape. The auxiliary blocks in each group may be connected by a connecting line 2331, and the auxiliary blocks of adjacent groups may not be connected. At least one group of auxiliary blocks may be electrically connected to the first power line, or multiple groups of auxiliary blocks may not be connected to the first power line. This embodiment is not limited to this. The remaining structures of the display substrate of this embodiment can refer to the description of the aforementioned embodiment, and thus will not be described in detail here.

[0119] Fig.17 FIG. 1 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure. Fig.17 In the figure, only the first conductive layer and the transparent conductive layer are shown, and other film layers are omitted. Fig.17 As shown, an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231a and 231b. The auxiliary structure 233 may include two auxiliary blocks 2330 arranged in a ring. The orthographic projection of the auxiliary block 2330 on the base substrate may be L-shaped. The orthographic projection of the auxiliary block 2330 on the base substrate may overlap with the orthographic projection of the shielding electrode 211 located on the first conductive layer on the base substrate. The auxiliary block 2330 may be electrically connected to the shielding electrode 211 through at least one second via K2 opened in the first flat layer, thereby achieving electrical connection with the first power line. In other examples, the auxiliary block 2330 may not be electrically connected to the first power line. The remaining structures of the display substrate of this embodiment can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0120] Fig.18 FIG. 1 is another schematic top view of a local film layer of a display substrate of at least one embodiment of the present disclosure. Fig.18 In the figure, only the first conductive layer and the transparent conductive layer are shown, and other film layers are omitted. Fig.18As shown, an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231a and 231b. The auxiliary structure 233 may include a plurality of auxiliary blocks 2330 arranged in an array. The orthographic projection of the auxiliary block 2330 on the base substrate may be in the shape of a strip. The auxiliary block 2330 may not be electrically connected and may be an invalid structure; or at least one auxiliary block 2330 may be electrically connected to the first power line. The remaining structures of the display substrate of this embodiment may refer to the description of the aforementioned embodiment, so they will not be described here.

[0121] Fig.19 FIG. 2 is another schematic top view of a partial film layer of a display substrate of at least one embodiment of the present disclosure. Fig.19 As shown, an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231a and 231b. The auxiliary structure 233 may include a plurality of regularly arranged auxiliary blocks 2330. The orthographic projection of the auxiliary block 2330 on the base substrate may be strip-shaped or L-shaped. The auxiliary block 2330 may not be electrically connected and may be an invalid structure; or at least one auxiliary block 2330 may be electrically connected to the first power line. The remaining structures of the display substrate of this embodiment may refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0122] Fig. 20 FIG. 2 is another schematic top view of a partial film layer of a display substrate of at least one embodiment of the present disclosure. Fig. 20 As shown, an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231a and 231b. The orthographic projection of the auxiliary structure 233 on the base substrate may be annular, such as a rectangular annular shape. The auxiliary structure 233 may not be electrically connected, may be an invalid structure; or, may be electrically connected to the first power line. However, this embodiment is not limited to this. For example, the orthographic projection of the auxiliary structure 233 on the base substrate may be other shapes such as a circular annular shape, an elliptical annular shape, etc. The remaining structures of the display substrate of this embodiment may refer to the description of the aforementioned embodiment, so they will not be repeated here.

[0123] Fig.21 FIG. 2 is another schematic top view of a partial film layer of a display substrate of at least one embodiment of the present disclosure. Fig.21 As shown, an auxiliary structure 233 is provided in the open area between the edge transparent conductive lines 231a and 231b. The orthographic projection of the auxiliary structure 233 on the base substrate may be a mesh. The auxiliary structure 233 may not be electrically connected and may be an invalid structure; or it may be electrically connected to the first power line. However, this embodiment is not limited to this. The remaining structures of the display substrate of this embodiment may refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0124] Fig. 22Another schematic top view of a local film layer of a display substrate according to at least one embodiment of the present disclosure is shown. Fig.23 for Fig. 22 A schematic diagram of a local cross section along the P-P' direction in FIG. In this example, a transparent conductive layer is used as an example for illustration. Fig. 22 and Fig.23 The structure of multiple film layers on the side of the second conductive layer close to the display substrate and the multiple film layers on the side of the transparent conductive layer away from the base substrate are omitted.

[0125] In some exemplary embodiments, Fig. 22 and Fig.23 As shown, in a direction perpendicular to the display substrate, the display substrate of the first display area A1 may include: a base substrate 10, a pixel circuit layer (for example, including a second conductive layer 22) disposed on the base substrate 10, a first flat layer 31, and a transparent conductive layer 23. The transparent conductive layer 23 may include an auxiliary structure 233 located in the open area between the edge transparent conductive lines 231a and 231b. The orthographic projection of the auxiliary structure 233 on the base substrate may overlap with the orthographic projection of the pixel circuit of the pixel circuit layer on the base substrate. The display substrate of this example may be a structure of a single source-drain metal layer, and the display substrate of the aforementioned embodiment may be a structure of a double source-drain metal layer. The remaining structures of the display substrate of this embodiment may refer to the description of the aforementioned embodiment, so they will not be repeated here.

[0126] The display substrate provided in this embodiment can improve the exposure environment of the exposure process for preparing the transparent conductive layer (for example, reducing the reflection of light in the first via hole and reducing the exposure amount received by the first transparent conductive line) by setting an auxiliary structure in the open area outside the first transparent conductive line, thereby affecting the line width of the edge transparent conductive line. In addition, it can also improve the situation where the first transparent conductive line is broken or thinned due to the reflection and focusing effect of the first conductive layer in the exposure process.

[0127] In other examples, the auxiliary structure disposed in the open area outside the first transparent conductive line may include a plurality of auxiliary blocks, and the plurality of auxiliary blocks may be arranged in a B-type, D-type, S-type, H-type, L-type, N-type, or M-type pattern. The orthographic projection of at least a portion of the plurality of auxiliary blocks on the base substrate may overlap with the orthographic projection of the shielding electrode on the base substrate.

[0128] In other examples, the shapes of the multiple auxiliary structures disposed in a transparent conductive layer may be substantially the same, or may be partially the same. For example, the multiple auxiliary structures included in a transparent conductive layer may all be similar. Figure 4 The auxiliary structure shown may include Figure 4 The auxiliary structures shown and Fig.13 However, this embodiment is not limited to this.

[0129] The following is an example of the film layer structure of the pixel circuit layer of the display substrate.

[0130] Fig.24 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. Fig.25 1 is a working timing diagram of a pixel circuit of at least one embodiment of the present disclosure. The pixel circuit of this exemplary embodiment is a 7T1C structure. However, this embodiment is not limited to this. For example, the pixel circuit can be a 3T1C, 5T1C, 8T1C or 8T2C structure.

[0131] In some exemplary embodiments, Fig.24 As shown, the pixel circuit of this example includes six switch transistors (T1, T2, T4 to T7), a drive transistor T3 and a storage capacitor Cst. The six switch transistors are respectively a data writing transistor T4, a threshold compensation transistor T2, a first light emission control transistor T5, a second light emission control transistor T6, a first reset transistor T1, and a second reset transistor T7. The light emitting element EL includes an anode, a cathode and an organic light emitting layer arranged between the anode and the cathode.

[0132] In some exemplary embodiments, the driving transistor and the six switching transistors may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product. In some possible implementations, the driving transistor and the six switching transistors may include P-type transistors and N-type transistors.

[0133] In some exemplary embodiments, the driving transistor and the six switching transistors may be low-temperature polysilicon thin film transistors, or may be oxide thin film transistors, or may be low-temperature polysilicon thin film transistors and oxide thin film transistors. The active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0134] In some exemplary embodiments, Fig.24As shown, the display substrate includes a scan line GL, a data line DL, a first power line PL1, a second power line PL2, a light emitting control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2. In some examples, the first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel circuit, the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel circuit, and the first voltage signal VDD is greater than the second voltage signal VSS. The scan line GL is configured to provide a scan signal SCAN to the pixel circuit, the data line DL is configured to provide a data signal DATA to the pixel circuit, the light emitting control line EML is configured to provide a light emitting control signal EM to the pixel circuit, the first reset control line RST1 is configured to provide a first reset control signal RESET1 to the pixel circuit, and the second reset control line RST2 is configured to provide a second reset control signal RESET2 to the pixel circuit. In some examples, in the nth row of pixel circuits, the first reset control line RST1 can be electrically connected to the scan line GL of the n-1th row of pixel circuits to be input with the scan signal SCAN(n-1), that is, the first reset control signal RESET1(n) is the same as the scan signal SCAN(n-1). The second reset control line RST2 can be electrically connected to the scan line GL of the nth row of pixel circuits to be input with the scan signal SCAN(n), that is, the second reset control signal RESET2(n) is the same as the scan signal SCAN(n). In some examples, the second reset control line RST2 electrically connected to the nth row of pixel circuits and the first reset control line RST1 electrically connected to the n+1th row of pixel circuits are an integrated structure. In this way, the signal lines of the display substrate can be reduced to achieve a narrow frame of the display substrate. However, this embodiment is not limited to this.

[0135] In some exemplary embodiments, the first initial signal line INIT1 is configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 is configured to provide a second initial signal to the pixel circuit. For example, the first initial signal and the second initial signal may be constant voltage signals, whose magnitudes may be, for example, between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto.

[0136] In some exemplary embodiments, Fig.24As shown, the driving transistor T3 is electrically connected to the light emitting element EL, and outputs a driving current under the control of the scanning signal SCAN, the data signal DATA, the first voltage signal VDD, the second voltage signal VSS and other signals to drive the light emitting element EL to emit light. The gate of the data writing transistor T4 is electrically connected to the scanning line GL, the first electrode of the data writing transistor T4 is electrically connected to the data line DL, and the second electrode of the data writing transistor T4 is electrically connected to the first electrode of the driving transistor T3. The gate of the threshold compensation transistor T2 is electrically connected to the scanning line GL, the first electrode of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the second electrode of the threshold compensation transistor T2 is electrically connected to the second electrode of the driving transistor T3. The gate of the first light emission control transistor T5 is electrically connected to the light emission control line EML, the first electrode of the first light emission control transistor T5 is electrically connected to the first power line PL1, and the second electrode of the first light emission control transistor T5 is electrically connected to the first electrode of the driving transistor T3. The gate of the second light emission control transistor T6 is electrically connected to the light emission control line EML, the first electrode of the second light emission control transistor T6 is electrically connected to the second electrode of the driving transistor T3, and the second electrode of the second light emission control transistor T6 is electrically connected to the anode of the light emitting element EL. The first reset transistor T1 is electrically connected to the gate of the driving transistor T3 and is configured to reset the gate of the driving transistor T3, and the second reset transistor T7 is electrically connected to the anode of the light emitting element EL and is configured to reset the anode of the light emitting element EL. The gate of the first reset transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first reset transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first reset transistor T1 is electrically connected to the gate of the driving transistor T3. The gate of the second reset transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the second reset transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the second reset transistor T7 is electrically connected to the anode of the light emitting element EL. The first electrode of the storage capacitor Cst is electrically connected to the gate of the driving transistor T3, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL1.

[0137] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first reset transistor T1, the driving transistor T3 and the threshold compensation transistor T2, the second node N2 is the connection point of the first light-emitting control transistor T5, the data writing transistor T4 and the driving transistor T3, the third node N3 is the connection point of the driving transistor T3, the threshold compensation transistor T2 and the second light-emitting control transistor T6, and the fourth node N4 is the connection point of the second light-emitting control transistor T6, the second reset transistor T7 and the light-emitting element EL.

[0138] Refer to the following Fig.25 right Fig.24 The working process of the pixel circuit is described as follows. Fig.24 The pixel circuit shown is illustrated by taking the case where the plurality of transistors included therein are all P-type transistors as an example.

[0139] In some exemplary embodiments, Fig.25 As shown, in a frame display time period, the working process of the pixel circuit of the first structure includes: a first stage S1, a second stage S2 and a third stage S3.

[0140] The first stage S1 is called the reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, which turns on the first reset transistor T1, and the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1, which initializes the first node N1 and clears the original data voltage in the storage capacitor Cst. The scan signal SCAN provided by the scan line GL is a high-level signal, and the light control signal EM provided by the light control line EML is a high-level signal, which turns off the data writing transistor T4, the threshold compensation transistor T2, the first light control transistor T5, the second light control transistor T6 and the second reset transistor T7. In this stage, the light emitting element EL does not emit light.

[0141] The second stage S2 is called the data writing stage or the threshold compensation stage. The scanning signal SCAN provided by the scanning line GL is a low level signal, the first reset control signal RESET1 provided by the first reset control line RST1 and the light control signal EM provided by the light control line EML are both high level signals, and the data line DL outputs the data signal DATA. In this stage, since the second electrode of the storage capacitor Cst is at a low level, the driving transistor T3 is turned on. The scanning signal SCAN is a low level signal, which turns on the threshold compensation transistor T2, the data writing transistor T4 and the second reset transistor T7. The threshold compensation transistor T2 and the data writing transistor T4 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on driving transistor T3, the third node N3, and the turned-on threshold compensation transistor T2, and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the driving transistor T3 is charged into the storage capacitor Cst, and the voltage of the first electrode of the storage capacitor Cst (i.e., the first node N1) is Vdata-|Vth|, where Vdata is the data voltage output by the data line DL, and Vth is the threshold voltage of the driving transistor T3. The second reset transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is provided to the anode of the light-emitting element EL, the anode of the light-emitting element EL is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and it is ensured that the light-emitting element EL does not emit light. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, which turns off the first reset transistor T1. The light emitting control signal EM provided by the light emitting control signal line EML is a high level signal, so that the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned off.

[0142] The third stage S3 is called the light-emitting stage. The light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, and the scan signal SCAN provided by the scan line GL and the first reset control signal RESET1 provided by the first reset control line RST1 are high-level signals. The light-emitting control signal EM provided by the light-emitting control signal line EML is a low-level signal, which turns on the first light-emitting control transistor T5 and the second light-emitting control transistor T6, and the first voltage signal VDD output by the first power line PL1 provides a driving voltage to the anode of the light-emitting element EL through the turned-on first light-emitting control transistor T5, the driving transistor T3 and the second light-emitting control transistor T6, driving the light-emitting element EL to emit light.

[0143] During the pixel circuit driving process, the driving current flowing through the driving transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the driving transistor T3 is:

[0144] I=K×(Vgs-Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2 .

[0145] Among them, I is the driving current flowing through the driving transistor T3, that is, the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the driving transistor T3, Vth is the threshold voltage of the driving transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0146] It can be seen from the above formula that the current flowing through the light emitting element EL has nothing to do with the threshold voltage of the driving transistor T3. Therefore, the pixel circuit of this embodiment can better compensate for the threshold voltage of the driving transistor T3.

[0147] Fig.26 It is a schematic top view of a pixel circuit according to at least one embodiment of the present disclosure. Fig. 27 for Fig.26 A schematic diagram of a partial cross section along the R-R' direction in FIG. In some exemplary embodiments, Fig.26 and Fig. 27 As shown, the pixel circuit layer of the display substrate of the first display area may include: a semiconductor layer 110, a first insulating layer 101, a first gate metal layer 111, a second insulating layer 102, a second gate metal layer 112, a third insulating layer 103 and a second conductive layer 22 sequentially arranged on the base substrate 10. A second flat layer 32 and a first conductive layer 21 are sequentially arranged on the side of the second conductive layer 22 away from the base substrate 10. In some examples, the first insulating layer 101, the second insulating layer 102 and the third insulating layer 103 may be inorganic insulating layers. However, this embodiment is not limited to this.

[0148] Fig.28A for Fig.26 A schematic top view of a display substrate after a semiconductor layer is formed in FIG. Fig.28B for Fig.26 A schematic top view of a display substrate after a first gate metal layer is formed. Fig.28C for Fig.26 A schematic top view of a display substrate after a second gate metal layer is formed. Fig.28D for Fig.26 Schematic diagram of a top view of a display substrate after a third insulating layer is formed. Fig.28E for Fig.26 A schematic top view of a display substrate after a second conductive layer is formed in FIG.

[0149] The structure of the display substrate is explained below by an example of the preparation process of the display substrate. The "patterning process" mentioned in the embodiment of the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0150] In some exemplary embodiments, a process of preparing a display substrate may include the following operations.

[0151] (1) Provide a substrate.

[0152] In some exemplary embodiments, the base substrate 10 may be a rigid substrate, such as a glass substrate. However, this embodiment is not limited thereto. For example, the base substrate 10 may be a flexible substrate.

[0153] (2) Forming a semiconductor layer.

[0154] In some exemplary embodiments, a semiconductor film is deposited on the base substrate 10 of the first display region, and the semiconductor film is patterned by a patterning process to form a semiconductor layer 110. Fig. 27 and Fig.28A As shown, the semiconductor layer 110 may include: active layers of multiple transistors of the pixel circuit (for example, including: active layer T10 of the first reset transistor T1, active layer T20 of the threshold compensation transistor T2, active layer T30 of the driving transistor T3, active layer T40 of the data writing transistor T4, active layer T50 of the first light emission control transistor T5, active layer T60 of the second light emission control transistor T6, and active layer T70 of the second reset transistor T7). The active layers of the seven transistors of a pixel circuit may be an integrated structure connected to each other.

[0155] In some exemplary embodiments, the material of the semiconductor layer 110 may include, for example, polysilicon. The active layer may include at least one channel region and a plurality of doped regions. The channel region may not be doped with impurities and may have semiconductor properties. The plurality of doped regions may be on both sides of the channel region and may be doped with impurities and may therefore have conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as a wiring doped with impurities, which may be used to electrically connect the transistors.

[0156] (3) Forming a first gate metal layer.

[0157] In some exemplary embodiments, on the base substrate 10 forming the aforementioned structure, a first insulating film and a first metal film are sequentially deposited, and the first metal film is patterned by a patterning process to form a first insulating layer 101 covering the semiconductor layer 110, and a first gate metal layer 111 disposed on the first insulating layer 101 in the first display area. Fig. 27 and Fig.28B As shown, the first gate metal layer 111 may include: gates of multiple transistors of the pixel circuit, and a first electrode Cst-1 of the storage capacitor Cst, a first reset control line RST1, a second reset control line RST2, a scan line GL, and a light-emitting control line EML. The first reset control line RST1 and the gate T11 of the first reset transistor T1 may be an integrated structure. The scan line GL and the gate T41 of the data writing transistor T4 and the gate T21 of the threshold compensation transistor T2 may be an integrated structure. The gate T31 of the driving transistor T3 and the first electrode Cst-1 of the storage capacitor Cst may be an integrated structure. The light-emitting control line EML, the gate T51 of the first light-emitting control transistor T5, and the gate T61 of the second light-emitting control transistor T61 may be an integrated structure. The second reset control line RST2 and the gate T71 of the second reset transistor T7 may be an integrated structure.

[0158] (4) Forming a second gate metal layer.

[0159] In some exemplary embodiments, on the base substrate 10 forming the aforementioned structure, a second insulating film and a second metal film are sequentially deposited, and the second metal film is patterned by a patterning process to form a second insulating layer 102 covering the first gate metal layer 111, and a second gate metal layer 112 disposed on the second insulating layer 102 in the first display area. Fig. 27 and Fig.28CAs shown, the second gate metal layer 112 may include: a second electrode Cst-2 of the storage capacitor Cst of the pixel circuit, a shielding electrode BK, a first initial signal line INIT1, and a second initial signal line INIT2. The shielding electrode BK is configured to shield the influence of the data voltage jump on the key nodes, avoid the data voltage jump from affecting the potential of the key nodes of the pixel circuit, and improve the display effect.

[0160] (5) Form a third insulating layer and a second conductive layer.

[0161] In some exemplary embodiments, a third insulating film is deposited on the base substrate 10 forming the aforementioned structure, and a third insulating layer 103 is formed by a patterning process. A plurality of pixel vias are provided in the third insulating layer 103. Subsequently, a third metal film is deposited, and the third metal film is patterned by a patterning process to form a second conductive layer 22 disposed on the third insulating layer 103 in the first display area.

[0162] like Figure 7 and Fig.28D As shown, the third insulating layer 103 is provided with a plurality of pixel vias, for example, including the first pixel via V1 to the fifteenth pixel via V15. The third insulating layer 103, the second insulating layer 102 and the first insulating layer 101 in the first pixel via V1 to the eighth pixel via V8 are removed to expose the surface of the semiconductor layer 110. The third insulating layer 103 and the second insulating layer 102 in the ninth pixel via V9 are removed to expose the surface of the first gate metal layer 111. The third insulating layer 103 in the tenth pixel via V10 to the fifteenth pixel via V15 is removed to expose the surface of the second gate metal layer 112.

[0163] like Fig. 27 and Fig.28EAs shown, the second conductive layer 22 may include: a data line DL, a first power line PL1, and a plurality of connection electrodes (e.g., a first anode connection electrode 220, a first connection electrode 221 to a fifth connection electrode 225). The first anode connection electrode 220 may be electrically connected to the second doped region of the active layer T60 of the second light emitting control transistor T6 through the fifth pixel via hole V5. The first connection electrode 221 may be electrically connected to the first doped region of the active layer T10 of the first reset transistor T1 through the first pixel via hole V1, and may also be electrically connected to the first initial signal line INIT1 through the tenth pixel via hole V10. The second connection electrode 222 may be electrically connected to the first doped region of the active layer of the second reset transistor of the previous row of pixel circuits through the eighth pixel via hole V18, and may also be electrically connected to the second initial signal line INIT2 through the eleventh pixel via hole V11. The third connection electrode 223 may be electrically connected to the gate T31 of the driving transistor T3 through the ninth pixel via hole V9, and may also be electrically connected to the first doped region of the active layer T20 of the threshold compensation transistor T2 through the second pixel via hole V2. The fourth connection electrode 224 can be electrically connected to the first doped region of the active layer of the first reset transistor of the next row of pixel circuits through the seventh pixel via V7, and can also be electrically connected to another first initial signal line INIT1 through the fourteenth via V14. The fifth connection electrode 225 can be electrically connected to the first doped region of the active layer T70 of the second reset transistor T7 through the sixth pixel via V6, and can also be electrically connected to another second initial signal line INIT2 through the fifteenth pixel via V15. The data line DL can be electrically connected to the first doped region of the active layer T40 of the data writing transistor T4 through the third pixel via V3. The first power line PL1 can be electrically connected to the shielding electrode BK through the twelfth pixel via V12, and can also be electrically connected to the first doped region of the active layer T50 of the first light emission control transistor T5 through the fourth pixel via V4, and can also be electrically connected to the second plate Cst-2 of the storage capacitor Cst through two thirteenth pixel vias V13 arranged in a vertical row.

[0164] At this point, the pixel circuit layer of the first display area A1 is prepared. The second display area A2 may include a base substrate 10 and a first insulating layer 101 , a second insulating layer 102 and a third insulating layer 103 stacked on the base substrate 10 .

[0165] (6) Forming a second planarizing layer and a first conductive layer.

[0166] In some exemplary embodiments, a first flat film is coated on the base substrate 10 forming the aforementioned structure, and a second flat layer 32 is formed by a patterning process. Subsequently, a fourth metal film is deposited, and the fourth metal film is patterned by a patterning process to form a first conductive layer 21 disposed on the second flat layer 32 in the first display area. Fig.26 and Fig. 27 As shown, the second flat layer 32 may be provided with a plurality of vias, such as first vias K1a and K1b. The second flat layer 32 in the first vias K1a and K1b is removed to expose the surface of the second conductive layer 22. The first conductive layer 21 may include: a shielding electrode 211 and a second anode connection electrode 210. The shielding electrode 211 may be electrically connected to the first power line PL1 through the first via K1a. The second anode connection electrode 210 may be electrically connected to the first anode connection electrode 220 through the first via K1a. In this example, the shielding electrode 211 may be an irregular shape so as to be configured to cover the first node N1 and reduce the crosstalk of the transparent conductive layer to the first node N1. However, this embodiment is not limited to this. In other examples, the shielding electrode 211 may be a regular shape such as a circle or a pentagon or a hexagon.

[0167] (7) Forming a first planarizing layer and a transparent conductive layer.

[0168] In some exemplary embodiments, a second flat film is coated on the base substrate 10 having the aforementioned structure, and a first flat layer 31 is formed by a patterning process. Subsequently, a transparent conductive film is deposited, and the transparent conductive film is patterned by a patterning process to form a transparent conductive layer disposed on the first flat layer 31, such as Figure 4 and Figure 5 shown.

[0169] In some examples, a third flat film is coated on the substrate substrate forming the aforementioned structure, and a third flat layer is formed by a patterning process. Subsequently, an anode conductive film is deposited, and the anode conductive film is patterned by a patterning process to form an anode layer disposed on the third flat layer. Subsequently, a pixel definition film is coated on the substrate base forming the aforementioned pattern, and a pixel definition layer (PDL, Pixel Define Layer) is formed by masking, exposure and development processes. The pixel definition layer is formed with a plurality of pixel openings exposing the anode layer. An organic light-emitting layer is formed in the aforementioned pixel openings, and the organic light-emitting layer is connected to the anode. Subsequently, a cathode film is deposited, and the cathode film is patterned by a patterning process to form a cathode pattern, and the cathode is electrically connected to the organic light-emitting layer and the second power line, respectively. Subsequently, an encapsulation layer is formed on the cathode, and the encapsulation layer may include a laminated structure of inorganic material / organic material / inorganic material.

[0170] In some exemplary embodiments, the first gate metal layer, the second gate metal layer, the first conductive layer, and the second conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The transparent conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO). The first insulating layer, the second insulating layer, and the third insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer. The first to fifth planar layers may be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer may be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The anode layer may be made of a reflective material such as a metal, and the cathode may be made of a transparent conductive material. However, this embodiment is not limited to this.

[0171] The structure of the display substrate of this embodiment and its preparation process are merely exemplary. In some exemplary embodiments, the corresponding structure may be changed and the patterning process may be increased or decreased according to actual needs. For example, multiple transparent conductive layers may be provided, such as forming another transparent conductive layer on the side of the first flat layer away from the base substrate, and then forming a third flat layer and an anode layer. However, this embodiment is not limited to this.

[0172] In some examples, when the display substrate includes multiple transparent conductive layers, each transparent conductive layer can be provided with an auxiliary structure adjacent to the edge transparent conductive line to improve the exposure environment of the exposure process for preparing each transparent conductive layer (for example, reducing the reflection of light in the first via hole and reducing the exposure amount received by the first transparent conductive line), thereby affecting the line width of the transparent conductive line, and can also improve the situation where the transparent conductive line is broken or thinned due to the reflective focusing effect of the first conductive layer in the exposure process.

[0173] The preparation process of this exemplary embodiment can be realized by using currently mature preparation equipment, and can be well compatible with existing preparation processes. The process is simple to realize, easy to implement, high in production efficiency, low in production cost, and high in yield rate.

[0174] This embodiment also provides a method for preparing a display substrate, comprising: forming a pixel circuit layer on a base substrate, the pixel circuit layer comprising a plurality of pixel circuits, the plurality of pixel circuits comprising a plurality of first pixel circuits; forming a first flat layer on a side of the pixel circuit layer away from the base substrate; forming at least one transparent conductive layer on a side of the first flat layer away from the base substrate; and forming a plurality of first light-emitting elements on a side of the transparent conductive layer away from the base substrate. The base substrate comprises a first display area and a second display area, the first display area at least partially surrounding the second display area. The plurality of first light-emitting elements are located in the second display area. The first flat layer is located in the first display area and the second display area. The transparent conductive layer comprises: a plurality of first transparent conductive lines and at least one auxiliary structure, the plurality of first light-emitting elements and the plurality of first pixel circuits are coupled through the plurality of first transparent conductive lines. The orthographic projection of the auxiliary structure on the base substrate overlaps with the orthographic projection of at least one pixel circuit among the plurality of pixel circuits on the base substrate.

[0175] The method for preparing the display substrate of this embodiment can refer to the description of the aforementioned embodiment, so it will not be described again here.

[0176] At least one embodiment of the present disclosure further provides a display device, comprising the display substrate as described above.

[0177] Fig.29 FIG. 1 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Fig.29 As shown, this embodiment provides a display device, including: a display substrate 91 and a light sensor 92 located on the light-emitting side of the display structure layer away from the display substrate 91. The orthographic projection of the light sensor 92 on the display substrate 91 overlaps with the second display area A2.

[0178] In some exemplary embodiments, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be any product or component with a display function, such as an OLED display, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc., but the embodiments of the present disclosure are not limited thereto.

[0179] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments.

[0180] Those skilled in the art should understand that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of the present disclosure.

Claims

1. A display substrate, comprising: A substrate, comprising a first display area and a second display area, wherein the first display area at least partially surrounds the second display area; A pixel circuit layer, located in the first display area, the pixel circuit layer includes a plurality of pixel circuits, and the plurality of pixel circuits include a plurality of first pixel circuits; A plurality of first light emitting elements, located in the second display area; A first planar layer, located on a side of the pixel circuit layer away from the base substrate, and located in the first display area and the second display area; At least one transparent conductive layer, located on a side of the first flat layer away from the substrate; The transparent conductive layer comprises: a plurality of first transparent conductive lines and at least one auxiliary structure, the plurality of first light-emitting elements and the plurality of first pixel circuits are coupled through the plurality of first transparent conductive lines; the orthographic projection of the auxiliary structure on the base substrate overlaps with the orthographic projection of at least one pixel circuit among the plurality of pixel circuits on the base substrate; The display substrate further comprises: a first conductive layer located between the pixel circuit layer and the first planar layer, the first conductive layer comprising: at least one shielding electrode, the shielding electrode being electrically connected to at least one pixel circuit among the plurality of pixel circuits, and an orthographic projection of the auxiliary structure on the base substrate overlaps with an orthographic projection of the shielding electrode on the base substrate; The pixel circuit includes at least: a driving transistor, a threshold compensation transistor and a first reset transistor, wherein the driving transistor, the threshold compensation transistor and the first reset transistor are all electrically connected to the first node; the orthographic projection of the blocking electrode on the substrate is configured to cover the orthographic projection of the first node of the pixel circuit on the substrate.

2. The display substrate according to claim 1, wherein: The pixel circuit layer includes: a second conductive layer, the second conductive layer includes a first power line, and the shielding electrode is electrically connected to the first power line.

3. The display substrate according to claim 2, wherein: The auxiliary structure is electrically connected to the shielding electrode.

4. The display substrate according to claim 1, wherein: The orthographic projection of the shielding electrode on the base substrate is an irregular shape.

5. The display substrate according to claim 2, wherein: A second flat layer is arranged between the first conductive layer and the second conductive layer, and the first conductive layer is electrically connected to the second conductive layer through a first via hole penetrating the second flat layer; the orthographic projection of at least one of the plurality of first transparent conductive lines on the base substrate overlaps with the orthographic projection of the first via hole on the base substrate.

6. The display substrate according to any one of claims 1 to 5, wherein: The first transparent conductive line includes an edge transparent conductive line, and the edge transparent conductive line is adjacent to the auxiliary structure.

7. The display substrate according to claim 6, wherein: The auxiliary structure is located between the two edge transparent conductive lines.

8. The display substrate according to claim 6, wherein: The distance between the auxiliary structure and the adjacent edge transparent conductive line is greater than or equal to 2 micrometers and less than or equal to 3 micrometers.

9. The display substrate according to any one of claims 1 to 5, wherein: The at least one auxiliary structure includes: a plurality of regularly arranged auxiliary blocks.

10. The display substrate according to claim 9, wherein: The auxiliary blocks of the auxiliary structure are arranged in an array, and the shapes and sizes of the auxiliary blocks are substantially the same.

11. The display substrate according to claim 10, wherein: The orthographic projections of the plurality of auxiliary blocks on the base substrate are rectangular.

12. The display substrate according to claim 9, wherein: The multiple auxiliary blocks of the auxiliary structure are arranged in a ring shape.

13. The display substrate according to claim 9, wherein: At least one auxiliary block of the auxiliary structure is electrically connected to the first power line.

14. The display substrate according to claim 9, wherein: At least two adjacent auxiliary blocks of the auxiliary structure are connected by a connecting line.

15. The display substrate according to claim 14, wherein: The plurality of auxiliary blocks of the auxiliary structure are divided into a plurality of groups, each group includes at least two auxiliary blocks, and the auxiliary blocks in a group are connected by connecting lines.

16. The display substrate according to any one of claims 1 to 5, wherein: The at least one auxiliary structure is in a ring shape or a mesh shape in an orthographic projection on the substrate.

17. The display substrate according to any one of claims 1 to 5, wherein: The multiple pixel circuits also include: multiple second pixel circuits located in the first display area; the display substrate also includes: multiple second light-emitting elements located in the first display area; at least one second pixel circuit among the multiple second pixel circuits is electrically connected to at least one second light-emitting element among the multiple second light-emitting elements, and the at least one second pixel circuit is configured to drive the at least one second light-emitting element.

18. A display device comprising the display substrate according to any one of claims 1 to 17.

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