I2C interface system based on I2C slave device and data read-write method

Abstract

The application provides an I2C interface system based on an I2C slave device, which comprises an I2C master controller, an I2C slave device, a first function module and a second function module; the I2C master controller is connected with the I2C slave device through an I2C clock line and an I2C data line; the I2C slave device is connected with the first function module, and the I2C slave device is connected with the second function module. The application realizes that only one I2C slave device is used to support two modes of command packet transmission and operation data byte transmission of I2C data, saves interface signals and solves the problem of insufficient chip pins in small package integrated circuits.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to an I2C interface system and data read / write method based on an I2C slave device. Background Technology

[0002] The I2C bus is a simple, bidirectional serial bus developed by Philips. Devices interconnected via the I2C bus are called I2C devices, and the interface through which I2C devices connect to the I2C bus is called the I2C interface. The design specifications of the I2C bus and its protocol (called the standard I2C specification) are usually based on the description in the document THE I2C-BUS SPECIFICATION VERSION 2.1 JANUARY 2000.

[0003] The I2C interface includes an I2C clock line (usually named SCL) and an I2C data line (usually named SDA). The I2C master controller connects to one or more I2C slave devices through the I2C clock line and the I2C data line. The I2C master controller drives the I2C clock line to initiate I2C write or read operations and uses the acknowledge bit to determine whether the data has been successfully sent. Bit errors that occur on the bus due to signal interference or other reasons cannot be recognized by the I2C slave devices.

[0004] The electrical characteristics of the I2C interface require that devices participating in I2C communication share a common ground; otherwise, transmission is impossible. Therefore, I2C communication is not suitable for applications with long transmission distances or significant signal interference. To solve this problem, a device for forwarding I2C data is typically added to the I2C bus. However, introducing a forwarding device introduces new problems:

[0005] The I2C communication mechanism requires that for every byte sent by the I2C master controller, the I2C slave device must reply with an acknowledgment bit. When the acknowledgment bit level is low, it is I2C ACK; when the acknowledgment bit level is high, it is I2CNAK.

[0006] Existing I2C communication mechanisms have two modes: one transmits I2C data in command packets, and the other transmits I2C data in operation data bytes. In the latter mode, each byte sent by the I2C master controller is passed to the receiving module (referred to as the functional module in this invention), which then generates an acknowledgment bit and sends it back to the I2C master controller. Transmitting I2C data in command packets offers the advantage of high speed, especially for long-distance transmission. Transmitting I2C data in operation data bytes offers good compatibility, being compatible with all current I2C master controllers without any modifications, but its disadvantage is slower speed.

[0007] In existing technologies, two I2C interfaces (two I2C slave devices) are required to support the two I2C data transmission modes, one supporting command packet transmission mode and the other supporting operation data byte transmission mode. Using two I2C interface signals results in wasted interface signals and insufficient chip pins in small-package integrated circuits. Summary of the Invention

[0008] To address the issues of wasted interface signals and insufficient chip pins in small-package integrated circuits caused by using two I2C interfaces to support command packet transmission mode and operation data byte transmission mode respectively in the existing technology, one objective of the present invention is to provide an I2C interface system based on an I2C slave device, the I2C interface system including an I2C master controller, an I2C slave device, a first functional module, and a second functional module;

[0009] The I2C master controller is connected to the I2C slave device via an I2C clock line and an I2C data line; the I2C slave device is connected to the first functional module and the I2C slave device is connected to the second functional module.

[0010] Another objective of this invention is to provide a data read / write method based on an I2C slave device, characterized in that data read / write is performed using the I2C interface system for the I2C slave device provided by this invention, including:

[0011] The I2C master controller initiates a first I2C write operation and a second I2C write operation. The first I2C write operation includes a first write address byte and a first write operation data, wherein the first write operation data includes a command packet. The second I2C write operation includes a second write address byte and a second write operation data. Both the first write address byte and the second write address byte include an I2C write address and a write operation indicator bit.

[0012] When the I2C write address received by the I2C slave device meets the first preset condition, the I2C slave device receives the command packet sent by the first I2C write operation, and after receiving the command packet, the I2C slave device sends the command packet to the first functional module.

[0013] The first functional module receives the command packet and executes the command. After the first functional module completes the command, it returns a feedback packet to the I2C slave device. The I2C slave device returns the information contained in the feedback packet to the I2C master controller.

[0014] When the I2C write address received by the I2C slave device meets the second preset condition, the I2C slave device receives the second I2C write operation, and after the I2C slave device receives each byte of the second write operation, it sends each byte of the second write operation to the second functional module.

[0015] After receiving each byte of the second write operation, the second functional module returns a second write status packet to the I2C slave device;

[0016] When the I2C slave device receives the second write status packet and the status information of the second write status packet is successful, the I2C slave device returns an I2C ACK to the I2C master controller;

[0017] When the I2C slave device receives the second write status packet and the status information of the second write status packet is failure, the I2C slave device returns an I2C NAK to the I2C master controller.

[0018] Preferably, the command packet received by the I2C slave device is a write command packet. After receiving the write command packet, the I2C slave device pulls the I2C clock line low and sends the write command packet to the first functional module.

[0019] The first functional module receives the write command packet and executes the write command. After the first functional module completes the write command, it returns a feedback packet to the I2C slave device as a first write status packet. The feedback packet contains the status information of the first write status packet. The I2C slave device returns the status information of the first write status packet to the I2C master controller.

[0020] Preferably, the I2C slave device returns the status information of the first write status packet to the I2C master controller, including:

[0021] When the I2C slave device receives the first write status packet and the status information of the first write status packet is successful, the I2C slave device stops pulling the I2C clock line low and returns an I2C ACK to the I2C master controller;

[0022] When the I2C slave device receives the first write status packet and the status information of the first write status packet is failure, the I2C slave device stops pulling the I2C clock line low and returns I2C NAK to the I2C master controller.

[0023] Preferably, the command packet received by the I2C slave device is a write command packet, and after receiving the write command packet, the I2C slave device sends the write command packet to the first functional module;

[0024] The first functional module receives the write command packet and executes the write command. After the first functional module completes the write command, it returns a feedback packet to the I2C slave device as a first write status packet. The feedback packet contains the status information of the first write status packet. The I2C slave device returns the status information of the first write status packet to the I2C master controller, including:

[0025] After the I2C slave device receives the write command packet,

[0026] If the subsequent I2C operation initiated by the I2C master controller is a first I2C write operation, and the I2C slave device receives the first write status packet returned by the first functional module to the I2C slave device and the status information of the first write status packet is successful, then the I2C slave device receives the subsequent first I2C write operation initiated by the I2C master controller.

[0027] If the subsequent I2C operation initiated by the I2C master controller is a first I2C write operation, and the I2C slave device receives the first write status packet returned by the first functional module to the I2C slave device and the status information of the first write status packet is failure, then the I2C slave device returns I2C NAK to the I2C master controller.

[0028] If the subsequent I2C operation initiated by the I2C master controller is a first I2C read operation, and the I2C slave device receives the first write status packet returned by the first functional module to the I2C slave device, then the I2C slave device returns the status information of the first write status packet to the I2C master controller.

[0029] Preferably, the command packet received by the I2C slave device is a read command packet. After receiving the read command packet, the I2C slave device pulls the I2C clock line low and sends the read command packet to the first functional module.

[0030] The first functional module receives the read command packet and executes the read command. After the first functional module completes the read command, it returns a feedback packet to the I2C slave device as a first read data packet. The feedback packet contains the read data in the first read data packet. The I2C slave device returns the read data in the first read data packet to the I2C master controller.

[0031] Preferably, the I2C slave device returns the read data in the first read data packet to the I2C master controller, including:

[0032] When the I2C slave device receives the first read data packet, the I2C slave device stops pulling the I2C clock line low;

[0033] If the subsequent I2C operation initiated by the I2C master controller is a first I2C read operation, then the I2C slave device returns the read data in the first read data packet to the I2C master controller.

[0034] Preferably, the command packet received by the I2C slave device is a read command packet, and after receiving the read command packet, the I2C slave device sends the read command packet to the first functional module;

[0035] The first functional module receives the read command packet and executes the read command. After the first functional module completes the read command, it returns a feedback packet to the I2C slave device as a first read data packet, the feedback packet containing the read data within the first read data packet. The I2C slave device returns the read data within the first read data packet to the I2C master controller, including:

[0036] After the I2C slave device receives the read command packet,

[0037] If the subsequent I2C operation initiated by the I2C master controller is a first I2C read operation, and the I2C slave device receives the first read data packet returned by the first functional module to the I2C slave device, the I2C slave device returns the read data in the first read data packet to the I2C master controller.

[0038] Preferably, the second functional module is also connected to a remote I2C slave device. When the I2C slave device receives the second write address byte, it sends the received second write address byte to the second functional module.

[0039] After receiving the second write address byte, the second functional module sends an I2CSTART signal and the second write address byte to the remote I2C slave device, and receives the I2CACK or I2C NAK returned by the remote I2C slave device to the second functional module.

[0040] If the remote I2C slave device returns an I2C ACK to the second functional module, then the status information of the second write status packet returned by the second functional module to the I2C slave device is success.

[0041] If the remote I2C slave device returns an I2C NAK to the second functional module, then the status information of the second write status packet returned by the second functional module to the I2C slave device is a failure.

[0042] Preferably, the second functional module is also connected to a remote I2C slave device. After receiving each second write operation data byte, the second functional module sends each received second write operation data byte to the remote I2C slave device, and after sending each second write operation data byte, receives the I2C ACK or I2C NAK returned by the remote I2C slave device to the second functional module.

[0043] If the remote I2C slave device returns an I2C ACK to the second functional module, then the status information of the second write status packet returned by the second functional module to the I2C slave device is success.

[0044] If the remote I2C slave device returns an I2C NAK to the second functional module, then the status information of the second write status packet returned by the second functional module to the I2C slave device is a failure.

[0045] Preferably, the second functional module is also connected to a remote I2C slave device, and the I2C master controller can also send an I2C STOP signal to the I2C slave device.

[0046] After receiving the I2C STOP signal, the I2C slave device sends the I2C STOP signal to the remote I2C slave device through the second functional module.

[0047] Another objective of this invention is to provide a data read / write method based on an I2C slave device, which uses the I2C interface system of this invention based on an I2C slave device for data read / write, including:

[0048] The I2C master controller initiates a first I2C read operation and a second I2C read operation. The first I2C read operation includes a first read address byte and a first read operation data. The second I2C read operation includes a second read address byte and a second read operation data. Both the first read address byte and the second read address byte include an I2C read address and a read operation indicator bit.

[0049] When the I2C read address received by the I2C slave device meets the third preset condition, the I2C slave device receives the first I2C read operation, and the I2C slave device returns the first read operation data to the I2C master controller.

[0050] When the I2C read address received by the I2C slave device meets the fourth preset condition, the I2C slave device receives the second I2C read operation, and after the I2C slave device receives the second read address byte, it sends the received second read address byte to the second functional module.

[0051] After receiving the second read address byte, the second functional module returns a second read data packet to the I2C slave device; wherein the second read data packet includes status information and / or one byte of second read operation data;

[0052] When the I2C slave device receives the second read data packet and the information status of the second read data packet is failure, the I2C slave device returns an I2C NAK to the I2C master controller;

[0053] When the I2C slave device receives a second read data packet containing one byte of second read operation data, the I2C slave device returns an I2C ACK and one byte of second read operation data to the I2C master controller;

[0054] When the I2C master controller receives one byte of second read operation data, it sends an I2C ACK or I2C NAK to the I2C slave device.

[0055] The I2C slave device sends the received I2C ACK or I2C NAK from the I2C master controller to the second functional module;

[0056] When the second functional module receives the I2C ACK, it returns a second read data packet containing one byte of second read operation data to the I2C slave device; after receiving the second read data packet containing one byte of second read operation data, the I2C slave device returns one byte of second read operation data to the I2C master controller.

[0057] Preferably, the second functional module is also connected to a remote I2C slave device. When the I2C read address received by the I2C slave device meets the fourth preset condition, the I2C slave device receives the second I2C read operation, and after the I2C slave device receives the second read address byte, it sends the received second read address byte to the second functional module.

[0058] After receiving the second read address byte, the second functional module sends an I2CSTART signal and the second read address byte to the remote I2C slave device, and receives an I2CACK or I2C NAK returned by the remote I2C slave device to the second functional module.

[0059] If the remote I2C slave device returns an I2C NAK to the second functional module, then the information status of the second read data packet returned by the second functional module to the I2C slave device is failure;

[0060] If the remote I2C slave device returns an I2C ACK to the second functional module, the second functional module reads one byte of second read operation data from the remote I2C slave device and returns a second read data packet containing one byte of second read operation data to the I2C slave device.

[0061] Preferably, the I2C slave device sends the received I2C ACK or I2C NAK from the I2C master controller to the second functional module;

[0062] When the second functional module receives the I2C ACK, it sends the I2C ACK to the remote I2C slave device, reads one byte of second read operation data from the remote I2C slave device, and returns a second read data packet containing one byte of second read operation data to the I2C slave device.

[0063] Preferably, the I2C slave device sends the received I2C ACK or I2C NAK from the I2C master controller to the second functional module;

[0064] When the second functional module receives the I2C NAK, it sends the I2C NAK to the remote I2C slave device.

[0065] Preferably, when the I2C read address received by the I2C slave device meets the fourth preset condition, the I2C slave device receives the second I2C read operation, and after receiving the second read address byte, the I2C slave device sends the received second read address byte to the second functional module;

[0066] After receiving the second read address byte, the second functional module returns a second read data packet with a status message of failure to the I2C slave device, or after receiving the second read address byte, the second functional module returns a second read data packet with a status message of success and a second read data packet containing one byte of second read operation data to the I2C slave device.

[0067] Preferably, the second functional module is also connected to a remote I2C slave device. When the I2C read address received by the I2C slave device meets the fourth preset condition, the I2C slave device receives the second I2C read operation, and after the I2C slave device receives the second read address byte, it sends the received second read address byte to the second functional module.

[0068] After receiving the second read address byte, the second functional module sends an I2CSTART signal and the second read address byte to the remote I2C slave device, and receives an I2CACK or I2C NAK returned by the remote I2C slave device to the second functional module.

[0069] If the remote I2C slave device returns an I2C NAK to the second functional module, then the second functional module returns a second read data packet with a failed information status to the I2C slave device.

[0070] If the remote I2C slave device returns an I2C ACK to the second functional module, then the second functional module returns a second read data packet with a success status to the I2C slave device.

[0071] Furthermore, the second functional module reads one byte of second read operation data from the remote I2C slave device.

[0072] Furthermore, the second functional module returns a second read data packet containing one byte of second read operation data to the I2C slave device.

[0073] Preferably, the functions of the second functional module and the first functional module can be integrated and implemented in the same module.

[0074] This invention provides an I2C interface system and data read / write method based on an I2C slave device, which enables the use of only one I2C slave device to support both command packet transmission and operation data byte transmission modes of I2C data, saving interface signals and solving the problem of insufficient chip pins in small package integrated circuits. Attached Figure Description

[0075] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0076] Figure 1 The diagram illustrates a schematic of an I2C interface system based on an I2C slave device according to the present invention.

[0077] Figure 2 The timing diagram of the I2C write operation of the present invention is shown.

[0078] Figure 3 The timing diagram of the I2C read operation of the present invention is shown.

[0079] Figure 4 The timing diagram of the I2C continuous read / write operation of the present invention is shown.

[0080] Figure 5 The timing diagram for initiating an I2C write operation by the I2C master controller of the present invention is shown.

[0081] Figure 6 The diagram illustrates a timing sequence in the first mode of the present invention, where the I2C master controller initiates the first I2C write operation, sends a write command packet, and the status information of the first write status packet indicates success.

[0082] Figure 7 The diagram illustrates a timing sequence in the first mode of the present invention, where the I2C master controller initiates the first I2C write operation, sends a write command packet, and the status information of the first write status packet is "failure".

[0083] Figure 8 The diagram illustrates a timing sequence in the second mode of the present invention, where the I2C master controller initiates the first I2C write operation, sends a write command packet, and the status information of the write status packet indicates success.

[0084] Figure 9 The diagram illustrates a timing sequence in the second mode of the present invention, where the I2C master controller initiates the first I2C write operation, sends a write command packet, and the status information of the write status packet indicates failure.

[0085] Figure 10 The diagram illustrates the timing of the I2C master controller initiating the first I2C write operation by sending a write command packet and receiving an I2C read operation in the second mode of the present invention.

[0086] Figure 11 The diagram shows a timing diagram of the I2C master controller initiating a first I2C write operation and sending a read command packet in the third mode of the present invention, and the subsequent I2C operation is the first I2C read operation.

[0087] Figure 12 The diagram shows a timing diagram of the I2C master controller initiating a first I2C write operation and sending a read command packet in the fourth mode of the present invention, and the subsequent I2C operation is the first I2C read operation.

[0088] Figure 13 The diagram shows the timing of the I2C master controller initiating a second I2C write operation and the I2C slave device receiving the second write operation.

[0089] Figure 14 The diagram illustrates the timing of the second read operation data returned by the second functional module to the I2C slave device after the I2C master controller of the present invention initiates a second I2C read operation, and the second read data packet contains one byte of second read operation data.

[0090] Figure 15 The diagram illustrates a timing sequence where the I2C master controller of the present invention initiates a second I2C read operation, and the second functional module returns a status information of a failed second read data packet to the I2C slave device after receiving the second read address byte.

[0091] Figure 16The diagram illustrates the timing of the second read data packet and the second read data packet containing one byte of second read operation data, after the I2C master controller of the present invention initiates a second I2C read operation and the second functional module receives the second read address byte and returns a status information of success to the I2C slave device.

[0092] The meanings of the text labels in the above attached diagrams are as follows:

[0093] 100: I2C master controller; 200: I2C slave device; 300: First functional module; 400: Second functional module; 500: Remote I2C slave device; 600: I2C data line (SDA); 700: I2C clock line (SCL);

[0094] S: Represents the I2C START signal. The corresponding I2C bus state is that when SCL is high, SDA transitions from high to low.

[0095] P: Represents the I2C STOP signal. The corresponding I2C bus state is that when SCL is high, SDA transitions from low to high.

[0096] Sr: The corresponding I2C bus state is the same as S;

[0097] Sr / P: The corresponding I2C bus state is Sr or P;

[0098] ADDR: I2C address (I2C write address or I2C read address);

[0099] R / W: Indicates the read / write operation indicator bit. When this bit is R, it indicates that the current operation is an I2C read operation. When this bit is W, it indicates that the current operation is an I2C write operation.

[0100] R: Represents the read operation indicator bit, and the corresponding I2C bus state is when SCL is high and SDA is high.

[0101] W: Indicates the write operation indicator bit, and the corresponding I2C bus state is when SCL is high and SDA is low.

[0102] BYTE: Write operation data or read operation data, usually a multi-byte sequence. The content in parentheses after it indicates the sequence number of the byte in the sequence. Write operation data sends write command packets or read command packets, and read operation data reads read data or status information. The smaller sequence number is sent first.

[0103] A: Indicates I2C ACK, the corresponding I2C bus state is that SCL is high and SDA is always low;

[0104] N: indicates I2C NAK, and the corresponding I2C bus state is that SDA is always high while SCL is high.

[0105] DATA: Contains the bytes of read data, and the sequence of I2C ACK / I2C NAK between bytes;

[0106] STATUS: A sequence of bytes containing status information and I2C ACK / I2C NAK sequences between bytes;

[0107] A / N: The corresponding I2C bus state is that SDA is always high or always low while SCL is high.

[0108] HOLD: SCL is a continuous low level;

[0109] IDLE: The corresponding I2C bus state includes the following two possibilities:

[0110] (1) Both SCL and SDA are high level;

[0111] (2) SCL and SDA may be in other level states, but no valid I2C operation occurs in the combination of these level states. When IDLE is about to end, both SCL and SDA are high. Detailed Implementation

[0112] To make the above and other features and advantages of the present invention clearer, the invention will be further described below with reference to the accompanying drawings. It should be understood that the specific embodiments given herein are for the purpose of explanation to those skilled in the art and are exemplary only, not restrictive.

[0113] The clock line (SCL) and the I2C data line (SDA) are collectively known as the I2C bus. The I2C bus has become a de facto international standard. The design specifications of the I2C bus and its protocol (called the standard I2C specification) are usually based on the description in the document THE I2C-BUSSPECIFICATION VERSION 2.1 JANUARY 2000.

[0114] like Figure 1 As shown in the embodiment of the present invention, an I2C interface system based on an I2C slave device is provided, including an I2C master controller 100, an I2C slave device 200, a first functional module 300, and a second functional module 400.

[0115] The I2C master controller 100 is connected to the I2C slave device 200 via the I2C clock line (SCL) 700 and the I2C data line (SDA) 600. The I2C slave device 200 is connected to the first functional module 300 and the second functional module 400.

[0116] The first functional module 300 and the second functional module 400 of this invention can be modules with different functions (therefore, they are two physical modules) or modules with the same function (in which case they can be two physical modules or one physical module). The first functional module 300 and the second functional module 400 are only for ease of description and can be two modules with different functions, two modules with the same function, or one module with the same function.

[0117] like Figure 1 The illustrated embodiment also includes a remote I2C slave device 500; the second functional module 400 is connected to the remote I2C slave device 500.

[0118] In other embodiments of the present invention, the remote I2C slave device 500 may be omitted, and the second functional module 400 may not be connected to the remote I2C slave device 500.

[0119] like Figure 1 The illustrated embodiment includes a first functional module 300 and a second functional module 400. In other embodiments of the present invention, there may be multiple first functional modules 300 and second functional modules 400. In the embodiments described below, one first functional module 300 and one second functional module 400 are used as an example.

[0120] An I2C master controller 100 can connect to one or more I2C slave devices 200 through the same I2C bus (clock line 500 and I2C data line 400), and transmit byte sequences carrying information through I2C read or write operations. This embodiment illustrates the example of an I2C master controller 100 connecting to one I2C slave device 200 through the same I2C bus (I2C clock line (SCL) 700 and I2C data line (SDA) 600).

[0121] like Figure 2 As shown, an I2C write operation includes a write address byte and one or more write operation data bytes (BYTE(1), ..., BYTE(N), shaded). The write address byte is the first byte sent. The write address byte includes the I2C write address (ADDR) and the write operation indicator bit (W). According to the standard I2C specification, the write operation indicator bit (W) is low.

[0122] In this embodiment, both the write address byte and the write operation data byte are 8 bits, wherein the write address byte includes a 7-bit I2C write address (ADDR) and a 1-bit write operation indicator (W). This invention does not limit the number of bits in the write address byte and the write operation data byte; in other embodiments, the write address byte and the write operation data byte can have other numbers of bits.

[0123] When the I2C master controller 100 initiates an I2C write operation, it first drives the I2C clock line (SCL) 700 and the I2C data line (SDA) 600 according to the standard I2C specification, generating an I2C START signal (S). Then, it sends a write address byte. After receiving the write address byte, the I2C slave device 200 drives the I2C data line (SDA) 600 to generate an acknowledge bit. According to the standard I2C specification, the acknowledge bit can be I2C ACK (I2C data line (SDA) 600 is low) or I2C NAK (I2C data line (SDA) 600 is high).

[0124] When the acknowledge bit of the write address byte is I2C ACK, the I2C master controller 100 can send one or more write operation data bytes. After receiving each write operation data byte, the I2C slave device 200 drives the I2C data line (SDA) 600 to generate an acknowledge bit. The acknowledge bit of the write operation data byte can be I2C ACK (I2C data line (SDA) 600 is low) or I2C NAK (I2C data line (SDA) 600 is high).

[0125] According to the standard I2C specification, when sending a write address byte and one or more write operation data bytes, the I2C master controller 100 sends the number of bits contained in the write address byte and the write operation data byte by driving the I2C data line (SDA) 600, and for each bit contained in the write address byte and the write operation data byte, the I2C master controller 100 drives the I2C clock line (SCL) 700 to generate a clock pulse.

[0126] According to the standard I2C specification, the I2C master controller 100 will also drive the I2C clock line (SCL) 700 to generate a clock pulse corresponding to the acknowledge bit of the write address byte and the acknowledge bit of the write operation data byte. The I2C master controller 100 terminates the current write operation by sending the I2C STOP signal (P) or I2C START signal (S) as defined in the standard I2C specification.

[0127] like Figure 3As shown, an I2C read operation includes a read address byte and one or more read operation data bytes (BYTE(1), ..., BYTE(N), without shading). The first byte of the read address byte is sent by the I2C master controller 100, and one or more read operation data bytes are sent by the I2C slave device 200. The read address byte includes the I2C read address (ADDR) and the read operation indicator bit (R). According to the standard I2C specification, the read operation indicator bit (R) is high.

[0128] In this embodiment, both the read address byte and the read operation data byte are 8 bits, wherein the read address byte includes a 7-bit I2C read address (ADDR) and a 1-bit read operation indicator (R). This invention does not limit the number of bits in the read address byte and the read operation data byte; in other embodiments, the read address byte and the read operation data byte can have other numbers of bits.

[0129] When the I2C master controller 100 initiates an I2C read operation, the I2C master controller 100 first drives the I2C clock line (SCL) 700 and the I2C data line (SDA) 600 according to the standard I2C specification to generate an I2C START signal (S), and then sends a read address byte. After receiving the read address byte, the I2C slave device 200 drives the I2C data line (SDA) 600 to generate an acknowledge bit. According to the standard I2C specification, the acknowledge bit can be I2C ACK (I2C data line (SDA) 600 is low) or I2C NAK (I2C data line (SDA) 600 is high).

[0130] When the acknowledge bit of the read address byte is I2C ACK, the I2C slave device 200 can return one or more read operation data bytes by driving the I2C data line (SDA) 600. After receiving each read operation data byte, the I2C master controller 100 drives the I2C data line (SDA) 600 to generate an acknowledge bit. The acknowledge bit of the read operation data byte can be I2C ACK (I2C data line (SDA) 600 is low) or I2C NAK (I2C data line (SDA) 600 is high).

[0131] According to the standard I2C specification, when the I2C master controller 100 sends a read address byte and the I2C slave device 20 returns one or more read operation data bytes, the I2C master controller 100 sends the number of bits contained in the read address byte by driving the I2C data line (SDA) 600, and the I2C slave device 200 returns the bits contained in the read operation data byte by driving the I2C data line (SDA) 600. For each bit contained in the read address byte and the read operation data byte, the I2C master controller 100 drives the I2C clock line (SCL) 700 to generate a clock pulse.

[0132] According to the standard I2C specification, the I2C master controller 100 will also drive the I2C clock line (SCL) 700 to generate a clock pulse corresponding to the acknowledge bit of the read address byte and the acknowledge bit of the read operation data byte. The I2C master controller 100 terminates the current read operation by sending the I2C STOP signal (P) or I2C START signal (S) as defined in the standard I2C specification.

[0133] An I2C write or read operation cycle begins with the I2C START signal (S), but it can end in two ways. The first is by ending with the I2C STOP signal (P), with timings as shown in Figures 2 and 3 respectively. Figure 3 As shown.

[0134] The second method involves generating a new I2C START signal (S) to initiate the next I2C write or read operation, with timing parameters as follows: Figure 4 As shown. Figure 4 The dashed line connecting the acknowledge bit (A / N) and the I2C START signal (Sr) (as seen in other attached diagrams) is because the timing diagram is too long to be described in a single line, so it is split into multiple lines to indicate a connection between the two timing diagrams.

[0135] Using any of the above termination methods will not affect the data writing method and data reading method of the present invention. For ease of description, in this embodiment, the termination of an I2C operation (I2C write operation or I2C read operation) is described with an I2C STOP signal (P).

[0136] Combination Figure 5 The I2C master controller 100 initiates an I2C write operation, sequentially writing 0xA0, 0x06, 0x11, 0x21, 0x31, 0x41, 0x51, and 0x61 to the I2C slave device 200. Byte 0xA0 corresponds to the write address byte; its high 7 bits correspond to the I2C write address (ADDR) 0x50, and its low 1 bit is the write operation indicator bit (W). A value of 0 for the write operation indicator bit (W) indicates a write operation. The value of this byte is the binary number 10100000, which is the hexadecimal number 0xA0. A total of 7 bytes, 0x06, 0x11, 0x21, 0x31, 0x41, 0x51, and 0x61, correspond to the write operation data.

[0137] According to an embodiment of the present invention, a data read / write method based on an I2C slave device is provided, which uses an I2C interface system based on an I2C slave device for data read / write, including:

[0138] The I2C master controller 100 initiates a first I2C write operation and a second I2C write operation. The first I2C write operation includes a first write address byte and a first write operation data, which includes a command packet.

[0139] The second I2C write operation includes a second write address byte and second write operation data. Both the first and second write address bytes include the I2C write address (ADDR) and a write operation indicator bit (W).

[0140] The I2C master controller 100 initiates a first I2C write operation and a second I2C write operation, and the I2C slave device 200 receives the first I2C write operation and the second I2C write operation.

[0141] When the I2C write address (ADDR) received by the I2C slave device 200 meets the first preset condition, the I2C write operation received by the I2C slave device 200 is the first I2C write operation. The I2C slave device 200 receives the command packet sent by the first I2C write operation, and after receiving the command packet, the I2C slave device 200 sends the command packet to the first functional module 300.

[0142] When the I2C write address (ADDR) received by the I2C slave device 200 meets the second preset condition, the I2C write operation received by the I2C slave device 200 is the second I2C write operation.

[0143] In this invention, no first or second preset condition is specified or limited. In one embodiment, if the I2C write address (ADDR) received by the I2C slave device 200 satisfies the first preset condition, it can be that the I2C write address (ADDR) received by the I2C slave device 200 is in the first preset address range. If the I2C write address (ADDR) received by the I2C slave device 200 satisfies the second preset condition, it can be that the I2C write address (ADDR) received by the I2C slave device 200 is in the second preset address range.

[0144] In this invention, the first preset condition or the second preset condition may or may not overlap. If the first preset condition or the second preset condition overlaps, it is necessary to further specify how to determine whether the I2C write operation received by the I2C slave device 200 is the first I2C write operation or the second I2C write operation when the I2C write address (ADDR) simultaneously meets both the first preset condition and the second preset condition. This invention does not impose any restrictions on this specification.

[0145] Combination Figure 5As shown, to illustrate the first preset condition, if the first preset condition is that the I2C write address (ADDR) received by the I2C slave device 200 is within the first preset address range, and the first preset address range contains the I2C address 0x50, when the value of the I2C write address (ADDR) byte received by the I2C slave device 200 is equal to the hexadecimal number 0xA0, the high 7 bits of the I2C write address (ADDR) byte correspond to the I2C write address (ADDR) 0x50, and ... the value of the I2C write address (ADDR) byte received by the I2C slave device 200 is equal to the hexadecimal number 0xA0, the high 7 bits of the I2C write address (ADDR) byte correspond to the I2C write address (ADDR) 0x50, the value of the I2C write address (ADDR) byte received by the I2C slave device 200 is equal to the hexadecimal number 0xA0, the high 7 If R) is in the first preset address range, thus satisfying the first preset condition, then the I2C slave device 200 receives the first I2C write operation. 0xA0 corresponds to the first write address byte, and 0x06, 0x11, 0x21, 0x31, 0x41, 0x51, and 0x61, a total of 7 bytes, correspond to the first write operation data. The first write operation data includes a command packet. The I2C slave device 200 receives the command packet sent by the first I2C write operation, and after receiving the command packet, the I2C slave device 200 sends the command packet to the first functional module 300.

[0146] The command packet includes a write command packet and a read command packet. The write command packet of this invention is sent via write operation data bytes (BYTE(1), ..., BYTE(N)). The read command packet of this invention is also sent via write operation data bytes (BYTE(1), ..., BYTE(N)).

[0147] For example, when the I2C master controller 100 sends a write command packet, the I2C master controller 100 initiates a first I2C write operation and sends a first write address byte and one or more first write operation data bytes (BYTE(1), ..., BYTE(N)) containing the write command packet to the I2C slave device 200.

[0148] When the I2C master controller 100 sends a read command packet, the I2C master controller 100 initiates a first I2C write operation and sends the first write address byte and one or more first write operation data bytes (BYTE(1), ..., BYTE(N)) containing the read command packet to the I2C slave device 200.

[0149] Figure 5 As shown, when I2C slave device 200 receives the last bit of byte 0x61, that is, I2C slave device 200 receives command packet, I2C slave device 200 pulls I2C clock line 500 low, I2C bus is in HOLD state (continuous low level state), and I2C slave device 200 sends command packet to first functional module 300.

[0150] The first functional module 300 receives the command packet and executes the command. After completing the command, the first functional module 300 returns a feedback packet to the I2C slave device 200. The I2C slave device 200 then returns the information from the feedback packet to the I2C master controller 100.

[0151] The feedback packet of this invention can be a first write status packet or a first read data packet. When the I2C master controller 100 sends a write command packet, the feedback packet is a first write status packet, and the information contained in the feedback packet is the status information of the first write status packet; when the I2C master controller 100 sends a read command packet, the feedback packet is a first read data packet, and the information contained in the feedback packet is the read data in the first read data packet.

[0152] In this invention, when the I2C slave device 200 sends a command packet to the first functional module 300, the contents of the command packet can be modified, added, or deleted. This invention does not impose any restrictions or regulations on this.

[0153] In this invention, the first write operation data includes a command packet. In some embodiments of this invention, when the I2C slave device 200 receives the command packet, it means that the I2C slave device 200 receives the last first write operation data byte BYTE(N). In other embodiments of this invention, if the command packet is only contained in a portion of the first write operation data, then receiving all the first write operation data bytes containing the command packet is considered as receiving the command packet.

[0154] In this invention Figure 5 In the following description, "when I2C slave device 200 receives a command packet" means that I2C slave device 200 receives the last first write operation data byte BYTE(N).

[0155] According to an embodiment of the present invention, when the I2C slave device 200 receives a write command packet, the I2C slave device 200 pulls the I2C clock line (SCL) 700 low and sends the write command packet to the first functional module 300.

[0156] The first functional module 300 receives the write command packet and executes the write command. After the first functional module 300 completes the write command, it returns a first write status packet to the I2C slave device 200. The I2C slave device 200 returns the status information of the first write status packet to the I2C master controller 100.

[0157] According to an embodiment of the present invention, the I2C slave device 200 returns the status information of the first write status packet to the I2C master controller 100, including:

[0158] When the I2C slave device 200 receives the first write status packet and the status information of the first write status packet is successful, the I2C slave device 200 stops pulling the I2C clock line (SCL) 700 low and returns I2CACK to the I2C master controller 100.

[0159] When the I2C slave device 200 receives the first write status packet and the status information of the first write status packet is failure, the I2C slave device 200 stops pulling the I2C clock line (SCL) 700 low and returns I2C NAK to the I2C master controller 100.

[0160] For example, such as Figure 6 As shown, the I2C master controller 100 initiates an I2C operation (the first I2C write operation) with sequence number m (m is a natural number).

[0161] like Figure 6 As shown, the I2C master controller 100 sends a write command packet through the first I2C write operation with sequence number m. After receiving the write command packet (after receiving BYTE(N)), the I2C slave device 200 pulls the I2C clock line (SCL) 700 low, and the I2C bus is in the HOLD state (a continuous low level state).

[0162] At moment ①, the I2C slave device 200 receives the first write status packet and the status information of the first write status packet is successful. The I2C slave device 200 stops pulling the I2C clock line (SCL) 700 low and terminates the HOLD state (terminating the continuous low level state).

[0163] At time ②, the I2C slave device 200 returns an I2C ACK to the I2C master controller 100, and the I2C master controller 100 terminates the I2C operation with sequence number m (the first I2C write operation).

[0164] like Figure 7 As shown, the I2C master controller 100 sends a write command packet through the first I2C write operation with sequence number m. After receiving the write command packet (after receiving BYTE(N)), the I2C slave device 200 pulls the I2C clock line (SCL) 700 low, and the I2C bus is in the HOLD state (a continuous low level state).

[0165] At moment ①, the I2C slave device 200 receives the first write status packet and the status information of the first write status packet is failure. The I2C slave device 200 stops pulling the I2C clock line (SCL) 700 low and terminates the HOLD state (terminating the continuous low level state).

[0166] At time ②, the I2C slave device 200 returns an I2C NAK to the I2C master controller 100, and the I2C master controller 100 terminates the I2C operation with sequence number m (the first I2C write operation).

[0167] In one embodiment, when the I2C slave device 200 receives a write command packet, the I2C slave device 200 sends the write command packet to the first functional module 300 after receiving the write command packet.

[0168] The first functional module 300 receives the write command packet and executes the write command. After completing the write command, the first functional module 300 returns a first write status packet to the I2C slave device 200. The I2C slave device 200 returns the first write status packet to the I2C master controller 100, including:

[0169] After the I2C slave device 200 receives the write command packet, if the subsequent I2C operation initiated by the I2C master controller 100 is the first I2C write operation, and the I2C slave device 200 receives the first write status packet returned by the first functional module 300 to the I2C slave device 200 and the status information of the first write status packet is success, then the I2C slave device 200 accepts the subsequent first I2C write operation initiated by the I2C master controller 100.

[0170] If the subsequent I2C operation initiated by the I2C master controller 100 is the first I2C write operation, and the I2C slave device 200 receives the first write status packet returned by the first functional module 300 to the I2C slave device 200 and the status information of the first write status packet is failure, then the I2C slave device 200 returns I2C NAK to the I2C master controller 100.

[0171] If the subsequent I2C operation initiated by the I2C master controller 100 is the first I2C read operation, and the I2C slave device 200 receives the first write status packet returned by the first functional module 300 to the I2C slave device 200, then the I2C slave device 200 returns the status information of the first write status packet to the I2C master controller 100.

[0172] When the I2C master controller 100 initiates an I2C read operation, and the I2C read address (ADDR) received by the I2C slave device 200 meets the third preset condition, then the I2C read operation received by the I2C slave device 200 is the first I2C read operation. When the I2C read address (ADDR) received by the I2C slave device 200 meets the fourth preset condition, then the I2C read operation received by the I2C slave device 200 is the second I2C read operation.

[0173] In this invention, no third or fourth preset condition is specified or limited. In one embodiment, if the I2C read address (ADDR) received by the I2C slave device 200 satisfies the third preset condition, it can be that the I2C read address (ADDR) received by the I2C slave device 200 is in the third preset address range. If the I2C read address (ADDR) received by the I2C slave device 200 satisfies the fourth preset condition, it can be that the I2C read address (ADDR) received by the I2C slave device 200 is in the fourth preset address range.

[0174] In this invention, the third preset condition or the fourth preset condition may or may not overlap. If the third preset condition or the fourth preset condition overlaps, it is necessary to further specify how to determine whether the I2C read operation received by the I2C slave device 200 is the first I2C read operation or the second I2C read operation when the I2C read address (ADDR) simultaneously meets the third preset condition and the fourth preset condition. This invention does not impose any restrictions on this specification.

[0175] The first I2C read operation includes a first read address byte and first read operation data. In this invention, the I2C slave device 200 can return the status information of the first write status packet to the I2C master controller 100 through the first read operation data. The I2C slave device 200 can also return the read data in the first read data packet (described below in this invention) to the I2C master controller 100 through the first read operation data. The I2C slave device 200 can also return other status information generated by itself due to errors related to the write command packet and read command packet to the I2C master controller 100 through the first read operation data.

[0176] like Figure 8 , Figure 9 and Figure 10 As shown, the I2C operation initiated by the I2C master controller 100 with sequence number m is the first I2C write operation, which sends the write command packet to the I2C slave device 200. For the first N-1 first write operation data bytes (BYTE(1), ..., BYTE(N-1)), after each first write operation data byte is sent, the I2C slave device 200 returns I2CACK to the I2C master controller 100.

[0177] After receiving the Nth first write operation data byte (BYTE(N)) (i.e., after receiving the complete write command packet), the I2C slave device 200 may return either an I2C ACK or an I2C NAK to the I2C master controller 100. The specific choice is determined by the agreement between the I2C master controller 100 and the I2C slave device 200. They can agree that after the Nth first write operation data byte (BYTE(N)), either an I2C ACK or an I2C NAK indicates successful reception of the Nth first write operation data byte (i.e., the complete write command packet). Alternatively, they can agree that... NAK indicates that the Nth first write operation data byte (BYTE(N)) was not successfully received (i.e., the complete write command packet was not successfully received). In the following description of the present invention, regardless of whether the I2C slave device 200 returns I2C ACK or I2C NAK to the I2C master controller 100 after the Nth first write operation data byte (BYTE(N)), it indicates that the Nth first write operation data byte (i.e., the complete write command packet) was successfully received.

[0178] After the I2C master controller 100 completes the transmission of the Nth first write operation data byte (BYTE(N)), regardless of whether the I2C slave device 200 returns an I2C ACK or an I2C NAK to the I2C master controller 100, the I2C master controller 100 terminates the I2C operation with sequence number m (the first I2C write operation) and can choose to initiate the I2C operation with sequence number m+1 (subsequent I2C operations).

[0179] When the I2C operation with sequence number m+1 (subsequent I2C operations) is the first I2C write operation, if the I2C slave device 200 receives the first write status packet (the first write status packet corresponding to the I2C operation with sequence number m) returned by the first functional module 300 to the I2C slave device 200 and the status information of the first write status packet is success, then after the I2C master controller 100 sends the first write address byte, the I2C slave device 200 returns an I2C ACK to the I2C master controller 100. The I2C slave device 200 receives the first write operation data byte sent by the I2C operation with sequence number m+1 (subsequent I2C operations / first I2C write operation) initiated by the I2C master controller 100, such as... Figure 8 As shown.

[0180] When the I2C operation with sequence number m+1 (subsequent I2C operations) is the first I2C write operation, if the I2C slave device 200 receives the first write status packet (the first write status packet corresponding to the I2C operation with sequence number m) returned by the first functional module 300 to the I2C slave device 200 and the status information of the first write status packet is failure, then after the I2C master controller 100 sends the first write address byte, the I2C slave device 200 returns an I2C NAK to the I2C master controller 100, and the master controller 100 terminates the initiation of the I2C operation with sequence number m+1 (subsequent I2C operations / first I2C write operation), such as Figure 9 As shown.

[0181] like Figure 10 As shown, when the I2C operation with sequence number m+1 initiated by the I2C master controller 100 is the first I2C read operation, if the I2C slave device 200 receives the first write status packet returned by the first functional module 300 to the I2C slave device 200 (the first write status packet corresponding to the I2C operation with sequence number m), then the I2C slave device 200 returns an I2C ACK to the I2C master controller 100 and returns the status information (STATUS) of the first write status packet to the I2C master controller 100.

[0182] In one embodiment, when the command packet received by the I2C slave device 200 is a read command packet, the I2C slave device 200 pulls the I2C clock line (SCL) 700 low after receiving the read command packet and sends the read command packet to the first functional module 300.

[0183] The first functional module 300 receives a read command packet and executes the read command. After completing the read command, the first functional module 300 returns a first read data packet to the I2C slave device 200, which includes the read data. The I2C slave device 200 then returns the read data in the first read data packet to the I2C master controller 100.

[0184] According to an embodiment of the present invention, the I2C slave device 200 returns the read data of the first read data packet to the I2C master controller 100, including:

[0185] When the I2C slave device 200 receives the first read data packet, the I2C slave device 200 stops pulling the I2C clock line (SCL) 700 low.

[0186] If the subsequent I2C operation initiated by the I2C master controller 100 is the first I2C read operation, then the I2C slave device 200 returns the read data in the first read data packet to the I2C master controller 100.

[0187] For example, such as Figure 11As shown, the I2C master controller 100 initiates a first I2C write operation with sequence number m, sending a read command packet to the I2C slave device 200. After receiving the read command packet (after receiving BYTE(N)), the I2C slave device 200 pulls the I2C clock line (SCL) 700 low, and the I2C bus is in the HOLD state (a continuous low level state).

[0188] At moment ①, the I2C slave device 200 receives the first read data packet, and the I2C slave device 200 stops pulling the I2C clock line (SCL) 700 low, terminating the HOLD state (terminating the continuous low level state).

[0189] At time ②, the I2C slave device 200 returns an I2C ACK or I2CNAK to the I2C master controller 100, and the I2C master controller 100 terminates the I2C operation with sequence number m (the first I2C write operation).

[0190] In this invention, the first read data packet includes data read by the first functional module 300 (read data), or status information generated by the first functional module 300 executing a read command, or both data read by the first functional module 300 (read data) and status information generated by the first functional module 300 executing a read command.

[0191] This invention does not limit or specify that after the I2C slave device 200 receives the first read data packet and stops pulling the I2C clock line low, it should return an I2C ACK or an I2C NAK to the I2C master controller 100. As an example, the I2C slave device 200 may choose to stop pulling the I2C clock line 500 low and return an I2C ACK to the I2C master controller 100 when the I2C slave device 200 receives the read data packet and the read data packet status information (read data) is successful, and stop pulling the I2C clock line 500 low and return an I2C ACK to the I2C master controller 100 when the I2C slave device 200 receives the read data packet and the read data packet status information is unsuccessful.

[0192] If the I2C operation (subsequent I2C operation) initiated by the I2C master controller 100 with sequence number m+1 is the first I2C read operation, then after the I2C slave device 200 receives the first read address byte, the I2C slave device 200 returns I2CACK to the I2C master controller 100 and continues to return the read data (DATA) in the first read data packet, so that the I2C master controller 100 continues to execute the I2C operation (subsequent I2C operation / I2C read operation) with sequence number m+1.

[0193] During the execution of the I2C operation with sequence number m+1 (subsequent I2C operation / I2C read operation), the I2C master controller 100 reads the data (DATA).

[0194] In one embodiment, when the I2C slave device 200 receives a read command packet, the I2C slave device 200 sends the read command packet to the first functional module 300 after receiving the read command packet.

[0195] The first functional module 300 receives a read command packet and executes the read command. After completing the read command, the first functional module 300 returns a first read data packet to the I2C slave device 200. The first read data packet includes read data. The I2C slave device 200 returns the read data in the first read data packet to the I2C master controller 100, including:

[0196] After the I2C slave device 200 receives the read command packet, if the subsequent I2C operation initiated by the I2C master controller 100 is the first I2C read operation, and the I2C slave device 200 receives the first read data packet returned by the first functional module 300 to the I2C slave device 200, the I2C slave device 200 returns the read data in the first read data packet to the I2C master controller 100.

[0197] For example, such as Figure 12 As shown, the I2C operation with sequence number m initiated by the I2C master controller 100 is the first I2C write operation, which sends a read command packet to the I2C slave device 200. For the first N-1 first write operation data bytes (BYTE(1), ..., BYTE(N-1)), after each first write operation data byte is sent, the I2C slave device 200 returns an I2CACK to the I2C master controller 100.

[0198] After receiving the Nth first write operation data byte (BYTE(N)) (i.e., after receiving the complete read command packet), the I2C slave device 200 may return either an I2C ACK or an I2C NAK to the I2C master controller 100. The specific choice is determined by the agreement between the I2C master controller 100 and the I2C slave device 200. They can agree that after the Nth first write operation data byte (BYTE(N)), either an I2C ACK or an I2C NAK indicates successful reception of the Nth first write operation data byte (i.e., the complete read command packet). Alternatively, they can agree that... NAK indicates that the Nth first write operation data byte (BYTE(N)) was not successfully received (i.e., the complete read command packet was not successfully received). In the following description of the present invention, regardless of whether the I2C slave device 200 returns I2C ACK or I2C NAK to the I2C master controller 100 after the Nth first write operation data byte (BYTE(N)), it indicates that the Nth first write operation data byte (i.e., the complete read command packet) was successfully received.

[0199] If the I2C operation initiated by the I2C master controller 100 with sequence number m+1 (subsequent I2C operations) is the first I2C read operation, and the I2C slave device 200 receives the first read data packet returned by the first functional module 300 to the I2C slave device 200 (the first read data packet corresponding to the I2C operation with sequence number m), after receiving the first read address byte, the I2C slave device 200 returns an I2C ACK to the I2C master controller 100 and returns the read data (DATA) in the first read data packet to the I2C master controller 100.

[0200] According to an embodiment of the present invention, the I2C master controller 100 is connected to the I2C slave device 200 via the I2C clock line (SCL) 700 and the I2C data line (SDA) 600. The I2C slave device 200 is connected to the first functional module 300 and the second functional module 400.

[0201] The I2C master controller 100 initiates a first I2C write operation and a second I2C write operation. The first I2C write operation includes a first write address byte and a first write operation data, which includes a command packet.

[0202] The second I2C write operation includes a second write address byte and second write operation data. Both the first and second write address bytes include the I2C write address (ADDR) and a write operation indicator bit (W).

[0203] The I2C master controller 100 initiates a first I2C write operation and a second I2C write operation, and the I2C slave device 200 receives the first I2C write operation and the second I2C write operation.

[0204] When the I2C write address received by the I2C slave device 200 meets the second preset condition, the I2C slave device 200 receives the second I2C write operation, and after the I2C slave device 200 receives each byte of the second write operation (including the second write address byte and each second write operation data byte), it sends each received byte of the second write operation to the second functional module 400.

[0205] Combination Figure 13 For example, according to an embodiment of the present invention, the I2C master controller 100 sends a second write operation. After the I2C slave device 200 receives each byte of the second write operation (including the second write address byte and the second write operation data bytes BYTE(1), ..., BYTE(N)), it sends each received byte of the second write operation to the second functional module 400. After receiving each byte of the second write operation, the second functional module 400 returns a second write status packet to the I2C slave device 200.

[0206] When the I2C slave device 200 receives the second write status packet and the status information of the second write status packet is successful, the I2C slave device 200 returns an I2C ACK to the I2C master controller 100.

[0207] When the I2C slave device 200 receives the second write status packet and the status information of the second write status packet is failure, the I2C slave device 200 returns an I2C NAK to the I2C master controller 100.

[0208] exist Figure 13 In the illustrated embodiment, after receiving the second write address byte and the second write operation data bytes BYTE(1), ..., BYTE(N-1), the second functional module 400 returns a status packet indicating success. After receiving the second write operation data byte BYTE(N), the second functional module 400 returns a status packet indicating either success or failure. According to an embodiment of the present invention, the I2C master controller 100 is connected to the I2C slave device 200 via the I2C clock line (SCL) 700 and the I2C data line (SDA) 600. The I2C slave device 200 is connected to the first functional module 300, and also to the second functional module 400. The second functional module 400 is further connected to a remote I2C slave device 500.

[0209] Furthermore, when the I2C write address received by the I2C slave device 200 meets the second preset condition, the I2C slave device 200 receives the second write operation, and after receiving the second write address byte, the I2C slave device 200 sends the received second write address byte to the second functional module 400.

[0210] After receiving the second write address byte, the second functional module 400 sends an I2C START signal and the second write address byte to the remote I2C slave device 500, and receives an I2C ACK or I2CNAK returned by the remote I2C slave device 500 to the second functional module 400.

[0211] If the remote I2C slave device 500 returns an I2C ACK to the second functional module 400, then the status information of the second write status packet returned by the second functional module 400 to the I2C slave device 200 is successful, and the I2C slave device 200 returns an I2C ACK to the I2C master controller 100.

[0212] If the remote I2C slave device 500 returns an I2C NAK to the second functional module 400, then the status information of the second write status packet returned by the second functional module 400 to the I2C slave device 200 is a failure, and the I2C slave device 200 returns an I2C NAK to the I2C master controller 100.

[0213] exist Figure 13 In the illustrated embodiment, the remote I2C slave device 500 returns an I2C ACK after receiving the second write address byte.

[0214] Furthermore, after receiving each second write operation data byte (BYTE(1), ..., BYTE(N)) from the I2C slave device 200, it sends the received second write operation data byte to the second functional module 400. After receiving each second write operation data byte (BYTE(1), ..., BYTE(N)), the second functional module 400 sends each received second write operation data byte (BYTE(1), ..., BYTE(N)) to the remote I2C slave device 500, and receives the I2C ACK or I2C NAK returned by the remote I2C slave device 500 to the second functional module 400.

[0215] If the remote I2C slave device 500 returns an I2C ACK to the second functional module 400, then the status information of the second write status packet returned by the second functional module 400 to the I2C slave device 200 is successful, and the I2C slave device returns an I2C ACK to the I2C master controller 100.

[0216] If the remote I2C slave device 500 returns an I2C NAK to the second functional module 400, then the status information of the second write status packet returned by the second functional module 400 to the I2C slave device 200 is a failure, and the I2C slave device 200 returns an I2C NAK to the I2C master controller 100.

[0217] exist Figure 13In the illustrated embodiment, after receiving the second write operation data bytes BYTE(1), ..., BYTE(N-1), the remote I2C slave device 500 returns an I2C ACK; after receiving the second write operation data byte BYTE(N), the remote I2C slave device 500 returns an I2C ACK or an I2C NAK. Further, as... Figure 13 As shown, the I2C master controller 100 can also send an I2C STOP signal to the I2C slave device 200. After receiving the I2C STOP signal, the I2C slave device 200 sends the I2C STOP signal to the remote I2C slave device 500 through the second function module 400.

[0218] According to an embodiment of the present invention, a data read / write method based on an I2C slave device is provided, which uses an I2C interface system based on the I2C slave device for data read / write, including:

[0219] The I2C master controller 100 initiates the first I2C read operation and the second I2C read operation. The first I2C read operation includes the first read address byte and the first read operation data.

[0220] In this invention, the I2C slave device 200 returns the status information of the first write status packet to the I2C master controller 100 through the first read operation data. The I2C slave device 200 can also return the read data in the first read data packet to the I2C master controller 100 through the first read operation data. The I2C slave device 200 can also return other status information generated by itself due to errors related to the write command packet and the read command packet to the I2C master controller 100 through the first read operation data.

[0221] The second I2C read operation includes a second read address byte and second read operation data. Both the first and second read address bytes include the I2C read address (ADDR) and the read operation indicator bit (R).

[0222] When the I2C read address received by the I2C slave device 200 meets the third preset condition, the I2C slave device 200 receives the first I2C read operation and returns the first read operation data to the I2C master controller 100.

[0223] When the I2C read address received by the I2C slave device 200 meets the fourth preset condition, the I2C slave device receives the second I2C read operation, and after the I2C slave device 200 receives the second read address byte, it sends the received second read address byte to the second functional module 400.

[0224] After receiving the second read address byte, the second functional module 400 returns a second read data packet to the I2C slave device 200. The second read data packet includes status information and / or one byte of second read operation data.

[0225] When the I2C slave device 200 receives the second read data packet and the information status of the second read data packet is failure, the I2C slave device 200 returns an I2C NAK to the I2C master controller 100.

[0226] When the I2C slave device 200 receives a second read data packet containing one byte of second read operation data, the I2C slave device 200 returns an I2C ACK and one byte of second read operation data to the I2C master controller 100.

[0227] exist Figure 14 In the illustrated embodiment, after receiving the second read address byte, the second functional module 400 returns a second read data packet containing one byte of second read operation data to the I2C slave device 200.

[0228] exist Figure 15 In the illustrated embodiment, after receiving the second read address byte, the second functional module 400 returns a second read data packet with a failed information status to the I2C slave device 200.

[0229] Combination Figure 14 According to an embodiment of the present invention, after the I2C master controller 100 receives one byte of second read operation data, it sends an I2C ACK or an I2C NAK to the I2C slave device 200. After receiving the I2C ACK or I2C NAK sent by the I2C master controller 100, the I2C slave device 200 sends the received I2C ACK or I2C NAK to the second functional module 400.

[0230] After receiving the I2C ACK, the second functional module 400 returns a second read data packet containing one byte of second read operation data to the I2C slave device 200. After receiving the second read data packet containing one byte of second read operation data, the I2C slave device 200 returns one byte of second read operation data to the I2C master controller 100.

[0231] According to an embodiment of the present invention, the I2C master controller 100 is connected to the I2C slave device 200 via the I2C clock line (SCL) 700 and the I2C data line (SDA) 600. The I2C slave device 200 is connected to the first functional module 300, and the I2C slave device 200 is connected to the second functional module 400. The second functional module 400 is also connected to the remote I2C slave device 500.

[0232] When the I2C read address received by the I2C slave device 200 meets the fourth preset condition, the I2C slave device 200 receives the second I2C read operation, and after receiving the second read address byte, the I2C slave device 200 sends the received second read address byte to the second functional module 400.

[0233] After receiving the second read address byte, the second functional module 400 sends an I2C START signal and the second read address byte to the remote I2C slave device 500, and receives an I2C ACK or I2CNAK returned by the remote I2C slave device 500 to the second functional module 400.

[0234] If the remote I2C slave device 500 returns an I2C NAK to the second functional module 400, then the second read data packet information status returned by the second functional module 400 to the I2C slave device 200 is a failure, and the I2C slave device 200 returns an I2C NAK to the I2C master controller 100.

[0235] If the remote I2C slave device 500 returns an I2C ACK to the second functional module 400, the second functional module 400 reads one byte of second read operation data from the remote I2C slave device 500 and returns a second read data packet containing one byte of second read operation data to the I2C slave device 200. The I2C slave device 200 returns an I2C ACK and one byte of second read operation data to the I2C master controller 100.

[0236] exist Figure 14 In the illustrated embodiment, after the remote I2C slave device 500 receives the second read address byte, it returns an I2C ACK to the second functional module 400. Then, the second functional module 400 reads one byte of second read operation data from the remote I2C slave device 500 and returns a second read data packet containing one byte of second read operation data to the I2C slave device 200. The I2C slave device 200 returns an I2C ACK and one byte of second read operation data to the I2C master controller 100.

[0237] exist Figure 15 In the illustrated embodiment, after the remote I2C slave device 500 receives the second read address byte, it returns an I2C NAK to the second functional module 400. Then, the information status of the second read data packet returned by the second functional module 400 to the I2C slave device 200 is failure, and the I2C slave device 200 returns an I2C NAK to the I2C master controller 100.

[0238] Combination Figure 14 According to an embodiment of the present invention, after the I2C master controller 100 receives one byte of second read operation data, it sends an I2C ACK or an I2C NAK to the I2C slave device 200. After receiving the I2C ACK or I2C NAK sent by the I2C master controller 100, the I2C slave device 200 sends the received I2C ACK or I2C NAK to the second functional module 400.

[0239] When the second functional module 400 receives the I2C ACK, it sends the I2C ACK to the remote I2C slave device 500, reads one byte of second read operation data from the remote I2C slave device 500, and returns a second read data packet containing one byte of second read operation data to the I2C slave device 200. After receiving the second read data packet containing one byte of second read operation data, the I2C slave device 200 returns one byte of second read operation data to the I2C master controller 100.

[0240] When the second functional module 400 receives the I2C NAK, it sends the I2C NAK to the remote I2C slave device 500.

[0241] In one embodiment, when the I2C read address received by the I2C slave device 200 meets the fourth preset condition, the I2C slave device 200 receives the second I2C read operation, and after receiving the second read address byte, the I2C slave device 200 sends the received second read address byte to the second functional module 400.

[0242] After receiving the second read address byte, the second functional module 400 returns a second read data packet with a status message of failure to the I2C slave device 200 (e.g., ...). Figure 15 (As shown), or after the second functional module 400 receives the second read address byte, it returns a second read data packet with a status message of success and a second read data packet containing one byte of second read operation data to the I2C slave device 200. After receiving the second read data packet containing one byte of second read operation data, the I2C slave device 200 returns an I2C ACK and one byte of second read operation data (as shown) to the I2C master controller 100. Figure 16 (As shown).

[0243] like Figure 16 As shown, after the I2C master controller 100 receives one byte of second read operation data, it... Figure 14 The processing method shown is the same, so it will not be repeated here.

[0244] According to an embodiment of the present invention, the I2C master controller 100 is connected to the I2C slave device 200 via the I2C clock line (SCL) 700 and the I2C data line (SDA) 600. The I2C slave device 200 is connected to the first functional module 300, and the I2C slave device 200 is connected to the second functional module 400. The second functional module 400 is also connected to the remote I2C slave device 500.

[0245] When the I2C read address received by the I2C slave device 200 meets the fourth preset condition, the I2C slave device 200 receives the second I2C read operation, and after receiving the second read address byte, the I2C slave device 200 sends the received second read address byte to the second functional module 400.

[0246] After receiving the second read address byte, the second functional module 400 sends an I2C START signal and the second read address byte to the remote I2C slave device 500, and receives an I2C ACK or I2CNAK returned by the remote I2C slave device 500 to the second functional module 400.

[0247] If the remote I2C slave device 500 returns an I2C NAK to the second functional module 400, then the second functional module 400 returns a second read data packet with a failed status to the I2C slave device 200, and the I2C slave device 200 returns an I2C NAK to the I2C master controller 100. Figure 15 As shown.

[0248] If the remote I2C slave device 500 returns an I2C ACK to the second functional module 400, the second functional module 400 returns a second read data packet with a status message of success to the I2C slave device 200, and the second functional module 400 reads one byte of second read operation data from the remote I2C slave device 500, and the second functional module 400 returns a second read data packet containing one byte of second read operation data to the I2C slave device 200.

[0249] After receiving a second read data packet containing one byte of second read operation data from the I2C slave device 200, it returns an I2C ACK and one byte of second read operation data to the I2C master controller 100, such as... Figure 16 As shown.

[0250] like Figure 16 As shown, after the I2C master controller 100 receives one byte of second read operation data, it... Figure 14 The processing method shown is the same, so it will not be repeated here.

[0251] In this invention, the I2C slave device 200 can pause the I2C bus (the I2C bus is in a HOLD state) by pulling the I2C clock line (SCL) 700 low. In addition to the situation explicitly described above where the I2C slave device 200 pulls the I2C clock line (SCL) 700 low to put the I2C bus in a HOLD state, the I2C slave device 200 can also pause the I2C bus by pulling the I2C clock line (SCL) 700 low in other situations (e.g., when the I2C slave device 200 is internally busy), in accordance with the standard I2C specification. This will not be elaborated further in this document.

[0252] In the above description of this invention, an example of a first functional module 300 and a second functional module 400 is used. This invention does not specify or limit the number or function of the first functional module 300 and the second functional module 400. The number of first functional modules 300 and second functional modules 400 can be one or more. The functions of the second functional module 400 and the first functional module 300 can also be integrated into the same module, with the I2C slave device 200 connected to this module. When embodiments of this invention also include a remote I2C slave device 500, the remote I2C slave device 500 is also connected to this module. Simple arrangements, combinations, and divisions of the functions of the second functional module 400 and the first functional module 300 are all within the scope of protection of this invention.

[0253] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Any changes, modifications, substitutions, and variations made by those skilled in the art to the above embodiments within the scope of the present invention are within the protection scope of the present invention.

Claims

1. A data read / write method based on an I2C slave device, characterized in that, Data read and write operations are performed using an I2C interface system based on an I2C slave device. The I2C interface system includes an I2C master controller, an I2C slave device, a first functional module, and a second functional module. The I2C master controller is connected to the I2C slave device via an I2C clock line and an I2C data line. The I2C slave device is connected to the first functional module, and the I2C slave device is connected to the second functional module; The method includes: The I2C master controller initiates a first I2C write operation and a second I2C write operation. The first I2C write operation includes a first write address byte and a first write operation data, wherein the first write operation data includes a command packet. The second I2C write operation includes a second write address byte and a second write operation data. Both the first write address byte and the second write address byte include an I2C write address and a write operation indicator bit. When the I2C write address received by the I2C slave device meets the first preset condition, the I2C slave device receives the command packet sent by the first I2C write operation, and after receiving the command packet, the I2C slave device sends the command packet to the first functional module. The first functional module receives the command packet and executes the command. After the first functional module completes the command, it returns a feedback packet to the I2C slave device. The I2C slave device returns the information contained in the feedback packet to the I2C master controller. When the I2C write address received by the I2C slave device meets the second preset condition, the I2C slave device receives the second I2C write operation, and after the I2C slave device receives each byte of the second write operation, it sends each byte of the second write operation to the second functional module. After receiving each byte of the second write operation, the second functional module returns a second write status packet to the I2C slave device; When the I2C slave device receives the second write status packet and the status information of the second write status packet is successful, the I2C slave device returns an I2C ACK to the I2C master controller; When the I2C slave device receives the second write status packet and the status information of the second write status packet is failure, the I2C slave device returns an I2C NAK to the I2C master controller.

2. The data read / write method according to claim 1, characterized in that, The command packet received by the I2C slave device is a write command packet. After receiving the write command packet, the I2C slave device pulls the I2C clock line low and sends the write command packet to the first functional module. The first functional module receives the write command packet and executes the write command. After the first functional module completes the write command, it returns a feedback packet to the I2C slave device as a first write status packet. The feedback packet contains the status information of the first write status packet. The I2C slave device returns the status information of the first write status packet to the I2C master controller.

3. The data read / write method according to claim 2, characterized in that, The I2C slave device returns the status information of the first write status packet to the I2C master controller, including: When the I2C slave device receives the first write status packet and the status information of the first write status packet is successful, the I2C slave device stops pulling the I2C clock line low and returns an I2C ACK to the I2C master controller; When the I2C slave device receives the first write status packet and the status information of the first write status packet is failure, the I2C slave device stops pulling the I2C clock line low and returns I2C NAK to the I2C master controller.

4. The data read / write method according to claim 1, characterized in that, The command packet received by the I2C slave device is a write command packet. After receiving the write command packet, the I2C slave device sends the write command packet to the first functional module. The first functional module receives the write command packet and executes the write command. After the first functional module completes the write command, the feedback packet returned to the I2C slave device is the first write status packet. The feedback packet contains the status information of the first write status packet. The I2C slave device returns the status information of the first write status packet to the I2C master controller, including: After the I2C slave device receives the write command packet, If the subsequent I2C operation initiated by the I2C master controller is a first I2C write operation, and the I2C slave device receives the first write status packet returned by the first functional module to the I2C slave device and the status information of the first write status packet is successful, then the I2C slave device receives the subsequent first I2C write operation initiated by the I2C master controller. If the subsequent I2C operation initiated by the I2C master controller is a first I2C write operation, and the I2C slave device receives the first write status packet returned by the first functional module to the I2C slave device and the status information of the first write status packet is failure, then the I2C slave device returns I2C NAK to the I2C master controller. If the subsequent I2C operation initiated by the I2C master controller is a first I2C read operation, and the I2C slave device receives the first write status packet returned by the first functional module to the I2C slave device, then the I2C slave device returns the status information of the first write status packet to the I2C master controller.

5. The data read / write method according to claim 1, characterized in that, The command packet received by the I2C slave device is a read command packet. After receiving the read command packet, the I2C slave device pulls the I2C clock line low and sends the read command packet to the first functional module. The first functional module receives the read command packet and executes the read command. After the first functional module completes the read command, the feedback packet returned to the I2C slave device is the first read data packet. The information contained in the feedback packet is the read data in the first read data packet. The I2C slave device returns the read data in the first read data packet to the I2C master controller.

6. The data read / write method according to claim 5, characterized in that, The I2C slave device returns the read data in the first read data packet to the I2C master controller, including: When the I2C slave device receives the first read data packet, the I2C slave device stops pulling the I2C clock line low; If the subsequent I2C operation initiated by the I2C master controller is a first I2C read operation, then the I2C slave device returns the read data in the first read data packet to the I2C master controller.

7. The data read / write method according to claim 1, characterized in that, The command packet received by the I2C slave device is a read command packet. After receiving the read command packet, the I2C slave device sends the read command packet to the first functional module. The first functional module receives the read command packet and executes the read command. After the first functional module completes the read command, the feedback packet returned to the I2C slave device is the first read data packet. The information contained in the feedback packet is the read data in the first read data packet. The I2C slave device returns the read data in the first read data packet to the I2C master controller, including: After the I2C slave device receives the read command packet, If the subsequent I2C operation initiated by the I2C master controller is a first I2C read operation, and the I2C slave device receives the first read data packet returned by the first functional module to the I2C slave device, the I2C slave device returns the read data in the first read data packet to the I2C master controller.

8. The data read / write method according to claim 1, characterized in that, The second functional module is also connected to a remote I2C slave device. When the I2C slave device receives the second write address byte, it sends the received second write address byte to the second functional module. After receiving the second write address byte, the second functional module sends an I2C START signal and the second write address byte to the remote I2C slave device, and receives the I2C ACK or I2C NAK returned by the remote I2C slave device to the second functional module. If the remote I2C slave device returns an I2C ACK to the second functional module, then the status information of the second write status packet returned by the second functional module to the I2C slave device is success. If the remote I2C slave device returns an I2C NAK to the second functional module, then the status information of the second write status packet returned by the second functional module to the I2C slave device is a failure.

9. The data read / write method according to claim 1, characterized in that, The second functional module is also connected to a remote I2C slave device. After receiving each second write operation data byte, the second functional module sends each received second write operation data byte to the remote I2C slave device, and after sending each second write operation data byte, receives the I2C ACK or I2C NAK returned by the remote I2C slave device to the second functional module. If the remote I2C slave device returns an I2C ACK to the second functional module, then the status information of the second write status packet returned by the second functional module to the I2C slave device is success. If the remote I2C slave device returns an I2C NAK to the second functional module, then the status information of the second write status packet returned by the second functional module to the I2C slave device is a failure.

10. The data read / write method according to claim 1, characterized in that, The second functional module is also connected to a remote I2C slave device, and the I2C master controller can also send an I2C STOP signal to the I2C slave device. After receiving the I2C STOP signal, the I2C slave device sends the I2C STOP signal to the remote I2C slave device through the second functional module.

11. The data read / write method according to claim 1, characterized in that, The functions of the second functional module and the first functional module are integrated and implemented in the same module.

12. A data read / write method based on an I2C slave device, characterized in that, Data read and write operations are performed using an I2C interface system based on an I2C slave device. The I2C interface system includes an I2C master controller, an I2C slave device, a first functional module, and a second functional module. The I2C master controller is connected to the I2C slave device via an I2C clock line and an I2C data line. The I2C slave device is connected to the first functional module, and the I2C slave device is connected to the second functional module; The method includes: The I2C master controller initiates a first I2C read operation and a second I2C read operation. The first I2C read operation includes a first read address byte and a first read operation data. The second I2C read operation includes a second read address byte and a second read operation data. Both the first read address byte and the second read address byte include an I2C read address and a read operation indicator bit. When the I2C read address received by the I2C slave device meets the third preset condition, the I2C slave device receives the first I2C read operation, and the I2C slave device returns the first read operation data to the I2C master controller. When the I2C read address received by the I2C slave device meets the fourth preset condition, the I2C slave device receives the second I2C read operation, and after the I2C slave device receives the second read address byte, it sends the received second read address byte to the second functional module. After receiving the second read address byte, the second functional module returns a second read data packet to the I2C slave device; wherein the second read data packet includes status information and / or one byte of second read operation data; When the I2C slave device receives the second read data packet and the information status of the second read data packet is failure, the I2C slave device returns an I2C NAK to the I2C master controller; When the I2C slave device receives a second read data packet containing one byte of second read operation data, the I2C slave device returns an I2C ACK and one byte of second read operation data to the I2C master controller; When the I2C master controller receives one byte of second read operation data, it sends an I2CACK or I2C NAK to the I2C slave device. The I2C slave device sends the received I2C ACK or I2C NAK from the I2C master controller to the second functional module; When the second functional module receives the I2C ACK, it returns a second read data packet containing one byte of second read operation data to the I2C slave device; after receiving the second read data packet containing one byte of second read operation data, the I2C slave device returns one byte of second read operation data to the I2C master controller.

13. The data read / write method according to claim 12, characterized in that, The second functional module is also connected to a remote I2C slave device. When the I2C read address received by the I2C slave device meets the fourth preset condition, the I2C slave device receives the second I2C read operation. After the I2C slave device receives the second read address byte, it sends the received second read address byte to the second functional module. After receiving the second read address byte, the second functional module sends an I2C START signal and the second read address byte to the remote I2C slave device, and receives an I2C ACK or I2CNAK returned by the remote I2C slave device to the second functional module. If the remote I2C slave device returns an I2C NAK to the second functional module, then the information status of the second read data packet returned by the second functional module to the I2C slave device is failure; If the remote I2C slave device returns an I2C ACK to the second functional module, the second functional module reads one byte of second read operation data from the remote I2C slave device and returns a second read data packet containing one byte of second read operation data to the I2C slave device.

14. The data read / write method according to claim 13, characterized in that, The I2C slave device sends the received I2C ACK or I2C NAK from the I2C master controller to the second functional module; When the second functional module receives the I2C ACK, it sends the I2C ACK to the remote I2C slave device, reads one byte of second read operation data from the remote I2C slave device, and returns a second read data packet containing one byte of second read operation data to the I2C slave device.

15. The data read / write method according to claim 13, characterized in that, The I2C slave device sends the received I2C ACK or I2C NAK from the I2C master controller to the second functional module; When the second functional module receives the I2C NAK, it sends the I2C NAK to the remote I2C slave device.

16. The data read / write method according to claim 12, characterized in that, When the I2C read address received by the I2C slave device meets the fourth preset condition, the I2C slave device receives the second I2C read operation, and after the I2C slave device receives the second read address byte, it sends the received second read address byte to the second functional module. After receiving the second read address byte, the second functional module returns a second read data packet with a status message of failure to the I2C slave device, or after receiving the second read address byte, the second functional module returns a second read data packet with a status message of success and a second read data packet containing one byte of second read operation data to the I2C slave device.

17. The data read / write method according to claim 16, characterized in that, The second functional module is also connected to a remote I2C slave device. When the I2C read address received by the I2C slave device meets the fourth preset condition, the I2C slave device receives the second I2C read operation. After the I2C slave device receives the second read address byte, it sends the received second read address byte to the second functional module. After receiving the second read address byte, the second functional module sends an I2C START signal and the second read address byte to the remote I2C slave device, and receives an I2C ACK or I2CNAK returned by the remote I2C slave device to the second functional module. If the remote I2C slave device returns an I2C NAK to the second functional module, then the second functional module returns a second read data packet with a failed information status to the I2C slave device. If the remote I2C slave device returns an I2C ACK to the second functional module, then the second functional module returns a second read data packet with a success status to the I2C slave device. Furthermore, the second functional module reads one byte of second read operation data from the remote I2C slave device. Furthermore, the second functional module returns a second read data packet containing one byte of second read operation data to the I2C slave device.

18. The data read / write method according to claim 12, characterized in that, The functions of the second functional module and the first functional module are integrated and implemented in the same module.

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