An improved yolov8 pedestrian detection system based on FPGA deployment

Abstract

The application discloses an improved Yolov8 pedestrian detection system based on FPGA deployment, which comprises a dense pedestrian dataset module, an improved Yolov8 algorithm module and an FPGA deployment module; the dense pedestrian dataset module comprises a data acquisition module, a data labeling module and a data enhancement module; the improved Yolov8 algorithm module comprises a depth separable convolution module, a double-path attention gate module and a feature enhancement module; and the FPGA deployment module comprises a neural network compression module and a software and hardware design module. The application relates to the technical field of FPGA acceleration target detection algorithms, in particular to an improved Yolov8 pedestrian detection system based on FPGA deployment.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of FPGA acceleration target detection algorithms, in particular to an improved Yolov8 pedestrian detection system based on FPGA deployment. BACKGROUND

[0002] Pedestrian detection has become one of the most important research directions in the field of computer vision and an important research topic of deep learning, and its core technology depends on security, intelligent video monitoring, scenic traffic statistics and the like, and its accuracy is of great significance to the development of security intelligent video monitoring systems. Surveillance cameras are widely installed in public places, and pedestrian detection can be achieved with the aid of big data and other Internet of Things systems. Although current detection algorithms have been developed better in terms of detection accuracy and speed, pedestrian detection still faces many challenges. For example, when there are multiple pedestrians in the same scene, two or more pedestrians may be occluded by each other, and accurate detection is still difficult. These uncertainties make the research of pedestrian detection technology extremely difficult.

[0003] FPGA is a low-cost, low-power, high-parallel and programmable chip, and at the same time, considering that the convolutional neural network model algorithm is constantly updated and iterated, and is suitable for application to various complex scenes, therefore, FPGA has become the best selection platform for neural network model inference acceleration. The traditional design method of FPGA is to generate a specific function RTL level circuit structure by writing a hardware description language Verilog, VHDL, but for neural networks of this kind of high-density calculation, high-frequency memory operation and control logic complex application, the complexity of the design method based on hardware language will become very large. However, the current High Level Synthesis (HLS) based on C / C++ implementation of neural network acceleration calculation model optimization synthesis into intellectual property (Intellectual Property, IP) and then layout and wiring has become a more efficient path, greatly reducing the development cycle of traditional FPGA. SUMMARY

[0004] In view of the above technical deficiencies, the improved Yolov8 pedestrian detection system based on FPGA deployment provided by the application greatly improves the detection speed of the Yolov8 convolutional neural network.

[0005] To solve the above technical problems, the application adopts the following technical solutions: an improved Yolov8 pedestrian detection system based on FPGA deployment, which comprises a dense pedestrian dataset module, an improved Yolov8 algorithm module and an FPGA deployment module; the dense pedestrian dataset module comprises a data acquisition module, a data labeling module and a data enhancement module, the data acquisition module is used to collect a large number of dense pedestrian picture dataset, and improve the precision of the training model, the data labeling module is used to label the state information of the pedestrians in the dataset with head bounding box, human visible bounding box and human whole body bounding box; the improved Yolov8 algorithm module comprises a depth separable convolution module, a double-path attention gate module and a feature enhancement module, the depth separable convolution module is used to replace some common convolutions in the original network, reduce the calculation cost and speed up the inference speed, the double-path attention gate module is used to balance the detection rate and the feature extraction capability, and allow more details to be retained when fusing low-level features into high-level features, the feature enhancement module is used to use different scales and quantities of regular convolution and extended convolution on multiple branches to construct a multi-branch structure, and splice multi-channel feature maps, thereby improving the feature extraction capability of the network; the FPGA deployment module comprises a neural network compression module and a software and hardware design module, the neural network compression module is used to compress the model by quantizing the algorithm, and the software and hardware design module is used to improve the calculation throughput, balance resource occupation and power consumption.

[0006] Among them, the dense pedestrian detection system is real-time detection and tracking.

[0007] Among them, the data acquisition module mainly uses the network open source SCUT FIR pedestrian detection dataset.

[0008] Among them, the data enhancement module introduces Gaussian noise, blurred images, randomly rotated images and scaled images with different means and variances in the training process to enhance the generalization ability and robustness of the model, thereby weakening the influence of overfitting.

[0009] Preferably, the improved YOLOv8 algorithm is evaluated by precision, recall rate and mAP (mean average precision).

[0010] Among them, the FEM feature enhancement module is used to improve the adaptability, sensitivity and receptive field of the network to small size objects.

[0011] Further, the built-in enhancement module adopts a feature enhancement module called FEM, which first expands the network width by using various convolutions and scales on multiple branches to connect multi-channel feature maps to construct a multi-branch structure. Secondly, the finite element module is included in the main network to extract global features, which works with the previous convolution layer to improve the detection performance. Then, the two intermediate branches are combined with the dilated convolution layer to expand the receptive field and increase the context information, thereby improving the effectiveness of the features.

[0012] Wherein, the DPAG integrates two continuous attention mechanisms, namely branch channel attention module (BCAM) and channel attention module (CAM); the former realizes double-path channel attention, and the latter learns image position information. BCAM and CAM interact closely to extract channel and spatial features, wherein BCAM enhances channel correlation and feature accuracy through channel relationship gates and position relationship gates, and CAM locates entities by mastering spatial information. Through the feature absorption and refinement process of DPAG, pixels obtain individual weights, and the importance thereof is identified according to the weight values. Therefore, the efficiency of feature utilization and recognition ability is improved through interaction.

[0013] Wherein, the FPGA deployment module includes camera and HDMI display screen driving configuration, the FPGA deployment module first trains the improved Yolov8 network using the dense pedestrian dataset. Then, a dynamic threshold structured pruning strategy based on binary search and a dynamic INT16 fixed-point quantization algorithm are combined to compress the model. Then, the dense pedestrian dataset is used to generate a re-identification dataset for training the appearance feature extraction network of the Deepsort algorithm, and the input size is modified to improve the pedestrian tracking performance. Then, the advanced synthesis (HLS) tool is used to design and implement the pedestrian detector deployed on the FPGA. On the hardware level, the Im2col+GEMM and Winograd algorithms, parameter rearrangement, multi-channel transmission and other optimization techniques are used to improve the calculation throughput and balance resource occupation and power consumption.

[0014] Wherein, the dense pedestrian detection system is designed into two parts of hardware design and software design. The hardware end mainly constructs and packages the YOLOv8 IP core through HLS, then imports the IP core into the hardware engineering to complete the whole Block Design design and verification, and finally generates a bit file for calling by the software end. The software end mainly trains parameters and exports weight files for the dense pedestrian dataset, and finally completes the software and hardware collaborative test in the PYNQ image.

[0015] The beneficial effects of the present application are:

[0016] 1. In order to solve the problems of high computational complexity, many model parameters and difficulty of low power consumption and high throughput for edge devices in multi-target detection and tracking algorithm, a low power consumption and low delay multi-target detection and tracking algorithm is designed and implemented. The high-precision and configurable dense pedestrian detection system is based on field programmable gate array (FPGA) and adopts improved YOLOv8 algorithm (You-Only-Look-Once-version8) and Deepsort algorithm.

[0017] 2. The improved Yolov8 algorithm module adopts deep separable convolution (DSConv) to replace the ordinary convolution in the original network backbone and neck part, reduces the model size and improves the inference speed. At the same time, the double path attention gate (DPAG) is introduced into the network to overcome the weakness of lightweight neural network in feature extraction. In addition, the model also contains a feature enhancement module (FEM) to facilitate the network to extract more fine target features.

[0018] 3. The hardware acceleration architecture level realizes the memory interlayer reuse, parameter rearrangement, ping-pong buffer, multi-channel transmission, pipeline, Im2col+GEMM, Winograd algorithm and other hardware optimization technologies to improve the resource utilization and calculation efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0020] Figure 1 The system module flowchart of the present application;

[0021] Figure 2 The detection system framework diagram of the present application;

[0022] Figure 3 The structure of the DSConv module principle diagram of the present application;

[0023] Figure 4 The structure diagram of the DPAG module of the present application;

[0024] Figure 5 The FEM structure diagram of the present application;

[0025] Figure 6 The overall architecture diagram of the accelerator of the present application;

[0026] Figure 7 The development flowchart of the HLS of the present application. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] This invention provides an improved Yolov8 pedestrian detection system based on FPGA deployment, specifically relating to the fields of computer vision and FPGA-accelerated object detection technology. It includes a dense pedestrian dataset module, an improved Yolov8 algorithm module, and an FPGA deployment module.

[0029] like Figure 1 As shown, the improved Yolov8 pedestrian detection system based on FPGA deployment mainly includes the following steps:

[0030] (1) Collect images of dense crowds in various scenes and environments to build a large dataset.

[0031] (2) The YOLOv8 detection model was selected as the basic framework of the dense pedestrian detection model. Based on this, the network model was improved. The specific improvements include: constructing a depthwise separable convolution (DSConv) module to replace ordinary convolution, generating a large number of feature maps with a small amount of computation, thus reducing computational complexity; secondly, designing a dual-path attention gate module (DPAG) to improve the detection accuracy of the model in complex environments by enhancing the network's ability to distinguish pedestrians from the background; and then adding a feature enhancement module (FEM) to highlight the details of the detected target and prevent the loss of effective features, thereby improving the detection accuracy.

[0032] (3) The improved YOLOv8 algorithm model is deployed to the FPGA module. The OV5640 camera is connected to the FPGA development board via DuPont wires, and the HDMI display is connected to the FPGA development board via an HDMI cable. The camera transmits the real-time detected data to the FPGA, and the results are transmitted to the HDMI display for output through the improved YOLOv8 algorithm model. Based on the heterogeneous characteristics of the Zynq platform, this invention is divided into hardware design and software design. The hardware side mainly uses HLS to build and package the YOLOv8 IP core, then imports the IP core into the hardware project to complete the entire Block Design and verification, and finally generates a bit file for the software side to call. The software side mainly trains parameters and exports weight files from the dense pedestrian dataset, and finally completes the hardware and software co-testing in the PYNQ image, thereby completing the construction of the dense pedestrian detection system.

[0033] The dense pedestrian dataset module is mainly composed of three steps of data acquisition module, data labeling module and data enhancement module.

[0034] S1: The data acquisition module mainly includes the following steps:

[0035] First, the network open source SCUT FIR pedestrian detection dataset is used, which can better evaluate the detection model in the crowd scene. SCUT FIR Pedestrian Datasets is a large pedestrian detection dataset. It consists of image sequences (frames) about 11 hours long, traveling at speeds below 80km / h in different traffic scenarios. The image sequences come from 11 road segments in 4 scenarios in the center, suburbs, highways and campuses of Guangzhou City, China. This dataset annotates 211,011 frames (normal description number is OK), a total of 477,907 bounding boxes, around 7,659 unique pedestrians. There are various occluded crowds in the dataset. Then it is used for training, verification and testing according to a certain proportion.

[0036] S2: The data labeling module mainly includes the following steps:

[0037] The head bounding box, body visible bounding box and body whole bounding box of the pedestrians in the dataset are labeled with labelme and other tools, and then converted to TXT format for using the improved YOLOv8 algorithm.

[0038] S3: The data enhancement module mainly includes the following steps:

[0039] Gaussian noise, blurred images, randomly rotated images and scaled images with different means and variances are introduced in the training process to enhance the generalization ability and robustness of the model, thereby reducing the influence of overfitting.

[0040] The improved Yolov8 algorithm module is mainly composed of three steps of depth separable convolution module, double path attention gate module and feature enhancement module.

[0041] S4: The depth separable convolution module mainly includes the following steps:

[0042] Conventional convolution applies a convolution kernel to each channel of an input feature map and adds the convolution results of each channel to create a single output feature map. This process is repeated across all channels of the input feature map to create multiple output feature maps. In contrast, depthwise separable convolution consists of two steps. First, a depthwise convolution is performed in which each channel of the input feature map is independently convolved using a corresponding convolution kernel, resulting in an intermediate feature map with the same number of channels as the input feature map. Then, in a pointwise convolution step, a 1x1 convolution kernel is applied to each channel of the intermediate feature map, resulting in the final output feature map. The main advantage of depthwise separable convolution is a significant reduction in the number of parameters and computational complexity. Compared to ordinary convolution, depthwise separable convolution can significantly reduce computational cost while maintaining similar performance. Therefore, depthwise separable convolution is preferred for mobile and edge computing devices with limited computing power and memory. Figure 3 The structure of the DSConv module schematic diagram is shown.

[0043] S5: The integrated dual-path gated attention module mainly includes the following steps:

[0044] To improve edge detection performance, first, place an attention module in the connection layer to build an attention gate AG. Thus, ensure that a large amount of detail is retained when low-level features are fused into high-level features. Second, add a dual-path attention mechanism in the neck connection layer (Concat) to balance detection speed and feature extraction capability. The dual-path attention gate module (DPAG) combines the advantages of AG and CBAM attention modules, and innovatively introduces an additional path at the channel layer to facilitate information extraction. The DPAG integrates two continuous attention mechanisms, namely the branch channel attention module (BCAM) and the channel attention module (CAM); the former realizes dual-path channel attention, and the latter learns image position information. BCAM and CAM interact closely to extract channel and spatial features, where BCAM enhances channel correlation and feature accuracy through channel relationship gates and position relationship gates, and CAM locates entities by mastering spatial information. The structure of the DPAG module is shown in Figure 4 As shown, through the feature absorption and refinement process of the DPAG, pixels obtain individual weights, and their importance is identified according to the weight values. Thus, interact to improve the efficiency of feature utilization and recognition capability. The present application represents the element-wise summation operation as "+" (element-wise summation), the element-wise multiplication operation as "x" (element-wise production), and the channel-wise summation as (Concatenation), denoted as C. The operation of the channel attention BCAM is as follows: the transmitted feature maps are respectively processed by standard convolution Conv3 and Conv5, and then the two are combined to obtain a shallow convolution layer, denoted as. After the reshaped row and column information is multiplied after global average pooling (GAP), a feature map is obtained, and then a set of learning weights is obtained through the Softmax layer, denoted as. The learned weights are multiplied with the standard convolution Conv and RepConv to obtain the channel attention output, denoted as. The spatial attention CAM is based on the output of the channel attention, using average pooling (Avgpool) and maximum pooling (Maxpool). The intermediate quantity is obtained by concatenating Avgpool and Maxpool. After 1*1 convolution and sigmoid layer, the final spatial attention is obtained as Δ. The formula is as follows:

[0045] φ = Conv3(x) + RepConv5(x) (1)

[0046]

[0047] Λ = δ × Conv(x) + δ × RepConv(x) (3)

[0048] Ω = Avgpool(Λ) + Maxpool(Λ) (4)

[0049] Δ = Sigmoid(Conv(Ω)) (5)

[0050] S6: The built-in function enhancement module mainly includes the following steps:

[0051] The application adopts a feature enhancement module called FEM, which first expands the network width by connecting multi-channel feature maps through a multi-branch structure constructed by using various convolutions and scales on multiple branches. Secondly, the finite element module is contained in the main network to extract global features, which work with the previous convolution layer to improve the detection performance. Then, the two intermediate branches are combined with the dilated convolution layer to expand the receptive field and increase the context information, thereby improving the effectiveness of the features. As shown in Figure 5 , it is composed of four branches. The first three branches perform 1*1 convolution operation to process and adjust the number of feature map channels for further processing. The fourth branch contains a residual structure that can generate equivalent maps at the output, preserving high-quality features that can effectively detect small targets. The remaining three branches are composed of cascaded 3*3 traditional convolution and dilated convolution, which obtain more fine-grained target features through various scale convolutions. The calculation process of FEM is as follows:

[0052]

[0053]

[0054]

[0055]

[0056] In the formula, the traditional convolution operation with the kernel size of 1*1 and 3*3 is represented as and The dilated convolution operation with the dilation rate of 1, 3 and 5 is represented as and The symbol "Concat" represents the feature map concatenation operation, and the symbol represents the element-wise feature map summation operation. In addition, Y represents the input feature map, while Y1, Y2 and Y3 represent the feature maps obtained after the first three branches perform the regular convolution and the dilated convolution, respectively. Finally, Y represents the enhanced feature map. The feature enhancement module processes the low-level feature map of the main network. It not only retains the resolution, but also improves the ability of the network to extract target features under the conditions of occlusion and overlap. Figure 5 The FEM structure diagram is shown in

[0057] The FPGA deployment module mainly consists of a neural network compression module and a software and hardware design module.

[0058] First, the improved Yolov8 network is trained using the dense pedestrian dataset. Then, the dynamic threshold structured pruning strategy based on binary search and the dynamic INT16 fixed-point quantization algorithm are combined to compress the model. Then, the dense pedestrian dataset is used to generate a re-identification dataset for training the appearance feature extraction network of the Deepsort algorithm, and the input size is modified to improve the performance of the pedestrian tracking. Then, the senior comprehensive (HLS) tool is used to design and implement the pedestrian detector deployed on the FPGA. On the hardware level, the Im2col+GEMM and Winograd algorithms, parameter rearrangement, multi-channel transmission and other optimization techniques are used to improve the calculation throughput and balance resource occupation and power consumption.

[0059] The software and hardware design module mainly includes the following steps:

[0060] Based on the improved Yolov8 model, all types of calculations required by the dense pedestrian detection accelerator designed by the application need to be optimized and packaged into the corresponding calculation modules in the FPGA. The overall architecture of the accelerator is shown in Figure 6 .

[0061] The accelerator is composed of a host computer and an FPGA. The host computer performs image preprocessing, data quantization, non-maximum suppression, Deepsort task scheduling, and OV5640 camera and HDMI display driving modules. The host computer uses a controller to schedule data flow and a memory manager to manage interactions between DRAM and DMA. The FPGA is responsible for accelerating various computationally intensive tasks. The host computer initially loads the configuration information of the current model and stores the pre-quantized weight and bias data of the model in continuous memory. Then the OV5640 camera extracts the video into frame images and sends them to the controller module in sequence. First, the control module sends the image to the data quantization module. Then it transmits the quantized image, weight, and bias data of the current layer to the FPGA on-chip memory through the optimization transmission method of ping-pong double buffering and multi-channel transmission. After the specific computation module is accelerated, the result is sent back to the off-chip DRAM through the above method. After completing the prediction of the image, the host computer performs the NMS (non-maximum suppression) operation and transmits the result to the Deepsort tracking module. Finally, it draws the tracking results in real time to the HDMI display screen.

[0062] (2) According to the heterogeneous characteristics of the Zynq platform, the design is divided into hardware design and software design. The hardware side mainly constructs and packages the YOLOv8 IP core through HLS, and then imports the IP core into the hardware engineering to complete the entire BlockDesign design and verification, and finally generates a bit file for the software side to call. The software side mainly trains the parameters of the dense pedestrian dataset and exports the weight file, and finally completes the hardware-software collaborative test in the PYNQ image.

[0063] The hardware of the invention system is a development board based on Xilinx FPGA Zynq-7020. Zynq adopts a System on Chip (SoC) design, integrating a dual-core ARM Cortex A9 processor and Xilinx Artix-7 series FPGA, i.e. a heterogeneous computing scheme of ARM+FPGA. First, YOLOv8 IP core design is performed in Vivado HLS using C++. This software platform can automatically convert high-level programming languages such as C, C++, and System C code into hardware description languages (Verilog or VHDL files). After verifying the correctness of the source code and adding constraints, it is packaged as an IP core for the hardware side to call. The development process of HLS is as follows: Figure 7After the IP core design is completed, the next step is to build the development environment of the whole system. The development board project of Zynq7020-clg400-2 is created using Vivado 2019.2, and the architecture design is carried out in the Block Design hardware design platform in the project. First, add the Zynq IP core and configure the corresponding parameters, such as clock frequency, reset signal, DDR, peripheral IP pin, PS-PL interaction, etc., and then add the improved YOLOv8 IP core imported by HLS, and connect it with the Zynq IP core. The AXI SmartConnect IP core provided by Xilinx is used for connection. The ZYNQ system communicates and exchanges data through the IP core on the PL side. The S_AXI_HP port and the m_axi_DATA_BUS port are interconnected, that is, the connection with the improved YOLOv8 IP core is established.

[0064] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application also intends to include these modifications and variations.

Claims

1. An improved Yolov8 pedestrian detection system based on FPGA deployment, characterized in that: The system comprises a dense pedestrian dataset module, an improved Yolov8 algorithm module and a deployment module FPGA; the dense pedestrian dataset module comprises a data acquisition module, a data labeling module and a data enhancement module, the data acquisition module is used to collect a large number of dense pedestrian picture dataset, the data labeling module is used to label the state information of the pedestrians in the dataset with a head bounding box, a human visible bounding box and a human whole body bounding box; the improved Yolov8 algorithm module comprises a depth separable convolution module, a double-path attention gate module and a feature enhancement module FEM, the depth separable convolution module is used to replace some common convolutions in the original network, the double-path attention gate module is used to balance the detection rate and feature extraction capability, and the feature enhancement module FEM is used to construct a multi-branch structure using different scales and quantities of conventional convolution and extended convolution on multiple branches; the deployment module FPGA comprises a neural network compression module and a software and hardware design module, the neural network compression module is used to compress the model by quantizing the algorithm, and the software and hardware design module is used to improve the calculation throughput; The feature enhancement module FEM is a built-in enhancement module; It firstly constructs a multi-branch structure using various convolutions and scales on multiple branches to horizontally expand the network width by connecting multi-channel feature maps; secondly, the main network comprises a finite element module to extract global features, which cooperates with the preceding convolution layers to improve the detection performance; then, the two intermediate branches are combined with the expanded convolution layers to expand the receptive field and increase the context information, thereby improving the effectiveness of the features; The double-path attention gate DPAG integrates two continuous attention mechanisms, namely a branch channel attention module BCAM and a channel attention module CAM; the former realizes double-path channel attention, and the latter learns image position information; BCAM and CAM interact closely to extract channel and spatial features, wherein BCAM enhances channel correlation and feature accuracy through a channel relationship gate and a position relationship gate, and CAM locates entities by mastering spatial information; through the feature absorption and refinement process of DPAG, pixels obtain individual weights, and their importance is identified according to the weight values; Thus, the efficiency of feature utilization and recognition ability is improved; The deployment module FPGA comprises a camera and an HDMI display screen driving configuration, the deployment module FPGA firstly trains the improved Yolov8 network using the dense pedestrian dataset; then, a dynamic threshold structured pruning strategy based on binary search and a dynamic INT16 fixed-point quantization algorithm are combined to compress the model; then, a re-identification dataset is generated using the dense pedestrian dataset, which is used to train the appearance feature extraction network of the Deepsort algorithm, and the input size is modified to improve the pedestrian tracking performance; then, a high-level synthesis HLS tool is used to design and implement the pedestrian detector deployed on the deployment module FPGA; on the hardware level, the Im2col+GEMM and Winograd algorithms, parameter rearrangement and multi-channel transmission optimization techniques are adopted to improve the calculation throughput and balance resource occupation and power consumption.

2. The improved Yolov8 pedestrian detection system based on FPGA deployment according to claim 1, characterized in that: The dense pedestrian detection system is real-time detection tracking.

3. The improved Yolov8 pedestrian detection system based on FPGA deployment according to claim 1, characterized in that: The data acquisition module adopts a network open source SCUT FIR pedestrian detection dataset.

4. The improved Yolov8 pedestrian detection system based on FPGA deployment according to claim 1, characterized in that: The data enhancement module introduces Gaussian noise, blurred images, randomly rotated images, and scaled images with different means and variances during the training process to enhance the generalization ability and robustness of the model, thereby reducing the influence of overfitting.

5. The improved Yolov8 pedestrian detection system based on FPGA deployment according to claim 1, characterized in that: The improved YOLOv8 algorithm is evaluated using precision, recall, and average precision.

6. The improved Yolov8 pedestrian detection system based on FPGA deployment according to claim 1, characterized in that: The feature enhancement module FEM improves the adaptability, sensitivity, and receptive field of the network in detecting small objects.

7. The improved Yolov8 pedestrian detection system based on FPGA deployment according to claim 1, characterized in that: The dense pedestrian detection system is designed in two parts: hardware design and software design. The hardware side constructs and packages the YOLOv8 IP core through HLS, then imports the IP core into the hardware engineering to complete the entire Block Design design and verification, and finally generates a bit file for the software side to call. The software side trains parameters and exports weight files on the dense pedestrian dataset, and finally completes the hardware-software co-testing in the PYNQ image.

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