A data communication system and operation method thereof

Abstract

The present invention provides a data communication system and an operation method thereof, wherein a first host transceiver module and a second slave transceiver module are connected via a first data line, a second data line and a third data line, and the data comprises a synchronization frame and a data frame; the synchronization frame comprises a synchronization frame header, a synchronization clock segment and a synchronization bit, and the data frame comprises a start bit, a data bit and a check bit; the first host transceiver module sends a synchronization frame to the second slave transceiver module; when two consecutive bits of the same level appear in the sent data bit, a bit of high level is inserted into the bit after the two consecutive bits of low level or a bit of low level is inserted into the bit after the two consecutive bits of high level; each bit of the data bit is sent once in sequence via the first data line to the third data line, the data bit sent via the first data line is one bit ahead of the data bit sent via the second data line, and the data bit sent via the third data line is one bit delayed than the data bit sent via the second data line.

Description

Technical Field

[0001] The present invention mainly relates to the field of information technology, and in particular to a data communication system and an operation method thereof. Background Art

[0002] The communication protocols currently used in microcontroller units (MCUs) include UART (Universal Asynchronous Receiver / Transmitter), SPI (Serial Peripheral Interface), IIC (I2C, Inter-Integrated Circuit), LIN (Local Interconnect Network), CAN (Controller Area Network), USB (Universal Serial Bus), etc. These communication protocols have done certain processing to ensure data accuracy. For example, UART is multi-sampling filtering, SPI and IIC transmit clock signals while transmitting data, LIN protocol has a baud rate synchronization field, CAN protocol has a bit timing adjustment synchronization mechanism, and USB protocol can use two fixed clock sources to ensure synchronization. However, when data transmission errors occur in the aforementioned communication protocols, the erroneous bits cannot be effectively corrected. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a data communication system and an operating method thereof, which can ensure the synchronization of data transmission while also being able to correct the erroneous data transmission, thereby achieving stability and high reliability of the communication process.

[0004] In order to solve the above technical problems, the present invention provides a data communication system, comprising a first host transceiver module and a second slave transceiver module; the first host transceiver module and the second slave transceiver module are connected through a first data line, a second data line and a third data line, and realize data transmission and reception, the data includes a synchronization frame and a data frame; the synchronization frame includes a synchronization frame header, a synchronization clock segment and a synchronization bit, and the data frame includes a start bit, a data bit and a check bit; wherein the synchronization frame is used to determine the baud rate of data transmission and reception between the first host transceiver module and the second slave transceiver module; when the first host transceiver module sends a data frame to the second slave transceiver module, or the second slave transceiver module sends a data frame to the second slave transceiver module, Before the module sends a data frame to the first host transceiver module, the first host transceiver module sends a synchronization frame to the second slave transceiver module; when two consecutive bits of low level or two consecutive bits of high level appear in the sent data bit, a bit of high level is inserted after the two consecutive bits of low level or a bit of low level is inserted after the two consecutive bits of high level; each bit of the data bit in the data frame is sent once in sequence through the first data line, the second data line and the third data line respectively, the data bit sent through the first data line is delayed by one bit than the data bit sent through the second data line, and the data bit sent through the third data line is one bit ahead of the data bit sent through the second data line.

[0005] In one embodiment of the present invention, the synchronization frame header includes three or more consecutive low-level bits sent through the first data line, the second data line and the third data line; the synchronization clock segment includes N unit time intervals, the synchronization clock segment sent through the first data line has M first edges, the synchronization clock segment sent through the second data line has M-2 first edges, and the synchronization clock segment sent through the third data line has M-1 first edge; M is greater than or equal to 2 and M is a positive integer; N is a positive integer; the first data line, the second data line and the third data line perform M, M-2 and M-1 time interval calculations according to the first edge in the synchronization clock segment.

[0006] In one embodiment of the present invention, determining the baud rate of data transmission and reception between the first host transceiver module and the second slave transceiver module includes: respectively counting the total durations t1, t2 and t3 of N unit time intervals corresponding to the time intervals of the M segments, M-2 segments and M-1 segments corresponding to the M first edges, M-2 first edges and M-1 first edges of the first data line, the second data line and the third data line at the synchronization bit position, and obtaining corresponding unit time interval measurement values ​​τ1, τ2 and τ3; selecting two unit time interval calculation values ​​whose difference is less than a first threshold ratio from the unit time interval measurement values ​​τ1, τ2 and τ3 corresponding to the first data line, the second data line and the third data line; obtaining a unit time interval check value based on the two selected unit time interval measurement values; and obtaining the baud rate of data transmission and reception between the first host transceiver module and the second slave transceiver module according to the unit time interval check value and the system main frequency.

[0007] In one embodiment of the present invention, the synchronization bit includes one or more high level bits sent through the first data line, the second data line and the third data line.

[0008] In one embodiment of the present invention, the start bit comprises a low level bit sent through the first data line, the second data line and the third data line; the check bit comprises a parity check value sent through the second data line and the inverse value of the parity check value sent through the third data line.

[0009] In an embodiment of the present invention, the data frame further includes an end bit after the check bit; the end bit includes one or more high level bits sent through the first data line, the second data line and the third data line.

[0010] In one embodiment of the present invention, the data communication system also includes a first controller module and a second controller module corresponding to the first host transceiver module and the second slave transceiver module; when the data frame is received, the first host transceiver module or the second slave transceiver module sends a first interrupt signal to the corresponding first controller module and second controller module.

[0011] In one embodiment of the present invention, the first host transceiver module and the second slave transceiver module include a data encoding circuit, a transmission data buffer, a synchronization frame transmission circuit, a baud rate synchronization circuit, a data decoding circuit and a control register; the data encoding circuit is used to encode the data frame to be transmitted; the data decoding circuit is used to decode the received data frame; the control register is used to store the host and slave information, and determine the order of sending the synchronization frame and the data frame and the sending baud rate.

[0012] In one embodiment of the present invention, the first host transceiver module and the second slave transceiver module also include a received data cache and a data correction circuit; the data correction circuit is used to check and correct the received data frame based on the parity check value and the data frame sent through the first data line, the second data line and the third data line.

[0013] In an embodiment of the present invention, the first threshold ratio is greater than zero and less than or equal to 20%.

[0014] The present invention also provides an operation method of a data communication system, the data communication system comprising a first host transceiver module and a second slave transceiver module; the first host transceiver module and the second slave transceiver module are connected through a first data line, a second data line and a third data line, and realize data transmission and reception, the data comprising a synchronization frame and a data frame; the synchronization frame comprises a synchronization frame header, a synchronization clock segment and a synchronization bit, the data frame comprises a start bit, a data bit and a check bit; the data communication system is configured to: determine the baud rate of data transmission and reception between the first host transceiver module and the second slave transceiver module based on the synchronization frame; when the first host transceiver module sends a data frame to the second slave transceiver module, or the first Before the second slave transceiver module sends a data frame to the first host transceiver module, the first host transceiver module sends a synchronization frame to the second slave transceiver module; when two consecutive bits of low level or two consecutive bits of high level appear in the transmitted data bit, a bit of high level is inserted after the two consecutive bits of low level or a bit of low level is inserted after the two consecutive bits of high level; each bit of the data bit in the data frame is sent once in sequence through the first data line, the second data line and the third data line respectively, the data bit sent through the first data line is delayed by one bit than the data bit sent through the second data line, and the data bit sent through the third data line is one bit ahead of the data bit sent through the second data line.

[0015] Compared with the prior art, the present invention has the following advantages: the technical solution of the present application can ensure higher communication stability, and can also detect and correct data errors when data transmission errors occur, thereby achieving high reliability of the communication process. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are provided to provide a further understanding of the present application. They are included in and constitute a part of the present application. The accompanying drawings illustrate embodiments of the present application and together with the description serve to explain the principles of the present application.

[0017] In the attached figure:

[0018] Figure 1 It is a schematic diagram of the composition of a data communication system according to an embodiment of the present application.

[0019] Figure 2 It is a schematic diagram of the composition of a data communication system according to an embodiment of the present application.

[0020] Figure 3 It is a schematic diagram of the communication process between a first host transceiver module and a second slave transceiver module of a data communication system according to an embodiment of the present application.

[0021] Figure 4 It is a schematic diagram of a synchronous frame sending process of a data communication system according to an embodiment of the present application.

[0022] Figure 5 It is a schematic diagram of a synchronous frame sending process of a data communication system according to another embodiment of the present application.

[0023] Figure 6 It is a schematic diagram of a data frame sending process of a data communication system according to an embodiment of the present application.

[0024] Figure 7 It is a flow chart of an operation method of a data communication system according to an embodiment of the present application.

[0025] Figure 8 It is a process flow chart of determining the baud rate of data transmission and reception between a first host transceiver module and a second slave transceiver module in a data communication system according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of the present application. For ordinary technicians in this field, the present application can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.

[0027] As shown in this application and claims, unless the context clearly indicates an exception, the words "a", "an", "an" and / or "the" do not refer to the singular and may also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0028] Unless otherwise specifically stated, the relative arrangement of the components and steps described in these embodiments, numerical expressions and numerical values ​​do not limit the scope of the present application. Meanwhile, it should be understood that for ease of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0029] In addition, it should be noted that the use of words such as "first" and "second" to define components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above words have no special meaning and cannot be understood as limiting the scope of protection of this application. In addition, although the terms used in this application are selected from well-known and commonly used terms, some terms mentioned in the specification of this application may be selected by the applicant at his or her discretion, and their detailed meanings are explained in the relevant parts of the description of this article. In addition, it is required to understand this application not only by the actual terms used, but also by the meaning implied by each term.

[0030] Flowcharts are used in the present application to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed accurately in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may be added to these processes, or one or more operations may be removed from these processes.

[0031] The embodiments of the present application describe a data communication system and an operation method thereof.

[0032] Figure 1 Schematic diagram of the data communication system according to an embodiment of the present application. Figure 1 The data communication system 100 includes a first host transceiver module 121 and a second slave transceiver module 221. The first host transceiver module 121 and the second slave transceiver module 221 are connected through a first data line DA2, a second data line DA1 and a third data line DA0 to implement data transmission and reception. Figure 2 It is a schematic diagram of the composition of a data communication system according to an embodiment of the present application. Figure 3 It is a schematic diagram of the communication process between a first host transceiver module and a second slave transceiver module of a data communication system according to an embodiment of the present application. Figure 4 It is a schematic diagram of a synchronous frame sending process of a data communication system according to an embodiment of the present application. Figure 5 It is a schematic diagram of a synchronous frame sending process of a data communication system according to another embodiment of the present application. Figure 6 It is a schematic diagram of a data frame sending process of a data communication system according to an embodiment of the present application.

[0033] refer to Figures 1 to 6 , the data includes a synchronization frame 400 and a data frame 600. The data frame 600 includes a start bit 601, a data bit 602 and a check bit 603.

[0034] The synchronization frame 400 is used to make the communication baud rate of the second slave transceiver module 221 consistent with that of the first host transceiver module 121, so as to keep the data transmission and reception process between the first host transceiver module 121 and the second slave transceiver module 221 synchronized. Each bit of the data bit 602 in the data frame 600 is sent once through the first data line DA2, the second data line DA1 and the third data line DA0 in sequence. The data bit 602 sent through the first data line DA2 is delayed by one bit than the data bit 602 sent through the second data line DA1, and the data bit 602 sent through the third data line DA0 is one bit ahead of the data bit 602 sent through the second data line DA1. When the transmitted data bit 602 has two consecutive low levels or two consecutive high levels, a high level is inserted after two consecutive low levels or a low level is inserted after two consecutive high levels.

[0035] In some embodiments, the data communication system 100 further includes a first controller module 111 and a second controller module 211 corresponding to the first host transceiver module 121 and the second slave transceiver module 221. When the data frame 600 is received, the first host transceiver module 121 or the second slave transceiver module 221 sends a first interrupt signal IRQ to the corresponding first controller module 111 and the second controller module 211. Figure 1 In FIG. 1 , 101 and 201 respectively denote a first host and a second slave.

[0036] In some embodiments, the first host transceiver module 121 and the second slave transceiver module 221 include a data encoding circuit 131, a transmission data buffer 133, a synchronization frame transmission circuit 132, a baud rate synchronization circuit 135, a data decoding circuit 136 and a control register 134. The data encoding circuit 131 is used to encode the data frame 600 to be transmitted. The data decoding circuit 136 is used to decode the received data frame 600. The control register 134 is used to store the host and slave information, and determine the order of sending the synchronization frame 400 and the data frame 600 and the communication baud rate.

[0037] The first host transceiver module 121 and the second slave transceiver module 221 further include a received data buffer 137 and a data correction circuit 138. The data correction circuit 138 is used to check and correct the received data frame 600 based on the parity check value and the data frame 600 sent through the first data line DA2, the second data line DA1 and the third data line DA0.

[0038] In some embodiments, the communication process between the first host transceiver module 121 and the second slave transceiver module 221 is configured as follows: before the first host transceiver module 121 sends a data frame 600 to the second slave transceiver module 221, or before the second slave transceiver module 221 sends a data frame 600 to the first host transceiver module 121, the first host transceiver module 121 sends a synchronization frame 400 to the second slave transceiver module 221. Figure 3 In the embodiment, the first host transceiver module is referred to as the host, and the second slave transceiver module is referred to as the slave.

[0039] In some embodiments, reference Figure 4 and Figure 5 , the synchronization frame 400 includes a synchronization frame header 401, a synchronization clock segment 402 and a synchronization bit 403. The synchronization frame header 401 includes three or more consecutive low-level bits sent through the first data line DA2, the second data line DA1 and the third data line DA0. The synchronization clock segment 402 includes N unit time intervals, the synchronization clock segment 402 sent through the first data line DA2 has M first edges, the synchronization clock segment 402 sent through the second data line DA1 has M-2 first edges, and the synchronization clock segment 402 sent through the third data line DA0 has M-1 first edges. M is greater than or equal to 2 and M is a positive integer. N is a positive integer. Figure 4 In the example, M is 4 and N is 8.

[0040] The first data line DA2, the second data line DA1 and the third data line DA0 perform time interval calculations of M segments, M-2 segments and M-1 segments according to the first edge in the synchronous clock segment 402. The first edge is, for example, a rising edge or a falling edge. Figure 4 , the first data line DA2 is calculated according to the number of rising edges to obtain four time intervals s1, s2, s3 and s4. The second data line DA1 is calculated according to the number of rising edges to obtain two time intervals p1 and p2. The third data line DA0 is calculated according to the number of rising edges to obtain three time intervals r1, r2 and r3.

[0041] Figure 8 is a flow chart of a process of determining the baud rate of data transmission and reception between a first host transceiver module and a second slave transceiver module in a data communication system according to an embodiment of the present application. Figure 8, determining the baud rate of data transmission and reception between the first host transceiver module 121 and the second slave transceiver module 221 includes: step 801, respectively counting the total duration t1, t2 and t3 of N unit time intervals corresponding to the time intervals of M segments, M-2 segments and M-1 segments corresponding to the M first edges, M-2 first edges and M-1 first edges of the first data line DA2, the second data line DA1 and the third data line DA0 at the synchronization bit position 403, and obtaining the corresponding unit time interval measurement values ​​τ1, τ2 and τ3. Figure 4 In the embodiment shown, t1 = (s1 + s2 + s3 + s4). t2 = (p1 + p2). t3 = (r1 + r2 + r3). ​​τ1 = t1 / N = (s1 + s2 + s3 + s4) / 8. τ2 = t2 / N = (p1 + p2) / 8. τ3 = t3 / N = (r1 + r2 + r3) / 8.

[0042] Step 802, select two unit time interval calculation values ​​whose difference is less than the first threshold ratio from the unit time interval measurement values ​​τ1, τ2 and τ3 corresponding to the first data line DA2, the second data line DA1 and the third data line DA0. The first threshold ratio is greater than zero and less than or equal to 20%, for example, 5%, 10% or 15%. Step 803, based on the two selected unit time interval measurement values, obtain a unit time interval check value. For example, take the average of the two unit time interval measurement values ​​or assign different weight values ​​to the two unit time interval measurement values ​​to calculate the unit time interval check value. Step 804, according to the unit time interval check value and the system main frequency, obtain the baud rate of data transmission and reception between the first host transceiver module 121 and the second slave transceiver module 221. The baud rate is the number of data bits (bits) transmitted in a unit time interval, or the number of bits.

[0043] In some embodiments, the synchronization bit 403 includes one or more high level bits transmitted through the first data line DA2 , the second data line DA1 , and the third data line DA0 .

[0044] In some embodiments, reference Figure 6 As mentioned above, the data frame 600 includes a start bit 601, a data bit 602, and a check bit 603. The start bit 601, for example, includes a one-bit low level sent through the first data line DA2, the second data line DA1, and the third data line DA0. The check bit 603, for example, includes a parity check value sent through the second data line DA1 and the inverse value of the parity check value sent through the third data line DA0.

[0045] The data frame 600 further includes, for example, an end bit 604 after the check bit 603. The end bit 604 includes one or more high level bits transmitted through the first data line DA2, the second data line DA1, and the third data line DA0.

[0046] refer to Figure 6 , each bit of the data bit 602 in the data frame 600 is sent once through the first data line DA2, the second data line DA1 and the third data line DA0 in sequence, the data bit 602 sent through the first data line DA2 is delayed by one bit than the data bit 602 sent through the second data line DA1, and the data bit 602 sent through the third data line DA0 is one bit earlier than the data bit 602 sent through the second data line DA1. When two consecutive bits of low level appear in the sent data bit 602, a bit of high level is inserted after the two consecutive bits of low level in the data bit 602. When two consecutive bits of high level appear in the sent data bit 602, a bit of low level is inserted after the two consecutive bits of high level in the data bit 602.

[0047] The present application also provides an operation method of a data communication system 100, wherein the data communication system 100 includes a first host transceiver module 121 and a second slave transceiver module 221. The first host transceiver module 121 and the second slave transceiver module 221 are connected via a first data line DA2, a second data line DA1, and a third data line DA0, and implement data transmission and reception, wherein the data includes a synchronization frame 400 and a data frame 600. Figure 6 The first interrupt signal IRQ in the control module is sent to the first controller module 111 or the second controller module 211, for example. Figure 6 Shift_reg in indicates the received data buffer of the second slave transceiver module 221. Rx_reg indicates the register that finally stores the received data after verification and correction. The data to be sent is 0xCA, and after verification and correction, the received data finally stored is 0xCA.

[0048] Figure 7 is a flow chart of the operation method of the data communication system according to an embodiment of the present application. Figure 7 The data communication system 100 is configured to perform the following steps: Step 701,

[0049] The baud rate of data transmission and reception between the first host transceiver module 121 and the second slave transceiver module 221 is determined based on the synchronization frame 400. Step 702: When two consecutive bits of low level or two consecutive bits of high level appear in the transmitted data bit 602, a bit of high level is inserted after the two consecutive bits of low level in the data bit 602, or a bit of low level is inserted after the two consecutive bits of high level. Step 703: Each bit of the data bit 602 is sent once through the first data line DA2, the second data line DA1 and the third data line DA0 respectively, and the data bit 6020 sent through the first data line DA2 is delayed by one bit than the data bit 602 sent through the second data line DA1, and the data bit 602 sent through the third data line DA0 is one bit ahead of the data bit 602 sent through the second data line DA1. The specific implementation process of steps 701 to 703 refers to the above description.

[0050] After the data is received, the data is first decoded to remove the '0' (low level) and '1' (high level) (or invalid '0' and '1') added by the encoding before sending, and then the received data frame 600 is checked and corrected based on the parity check value and the data frame 600 sent through the first data line DA2, the second data line DA1 and the third data line DA0. For example, first determine whether the parity check value is correct, and specifically determine whether the parity check value is correct through the parity check value of the second data line DA1 and the third data line DA0 and the inverse value of the parity check value. If necessary, the data can also be corrected by the data frame 600 sent by the first data line DA2, the second data line DA1 and the third data line DA0, specifically the data frame sent once in sequence. Remove the '0' (low level) and '1' (high level) added by the encoding before sending. For example, adopt the decoding rule opposite to that when adding low level or high level during encoding, that is, for every two consecutive low levels received, remove the high level received thereafter; for every two consecutive high levels received, remove the low level received thereafter.

[0051] The data communication system and the operating method of the data communication system of the present application can realize anti-interference in the data communication process, including effectively preventing communication errors caused by line jitter or electromagnetic interference; the technical solution of the present application can effectively prevent communication anomalies caused by communication interference, ensure high communication stability, and can also detect and correct data errors when data transmission errors occur, thereby realizing high reliability of the communication process.

[0052] The basic concepts have been described above. Obviously, for those skilled in the art, the above invention disclosure is only used as an example and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and amendments to the present application. Such modifications, improvements and amendments are suggested in the present application, so such modifications, improvements and amendments still belong to the spirit and scope of the exemplary embodiments of the present application.

[0053] At the same time, the present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0054] Some aspects of the present application can be performed entirely by hardware, entirely by software (including firmware, resident software, microcode, etc.), or by a combination of hardware and software. The above hardware or software can all be referred to as "data blocks", "modules", "engines", "units", "components" or "systems". The processor can be one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DAPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, or combinations thereof. In addition, various aspects of the present application may be expressed as a computer product located in one or more computer-readable media, which includes computer-readable program code.

[0055] Similarly, it should be noted that in order to simplify the description of the disclosure of this application and thus help understand one or more embodiments of the invention, in the above description of the embodiments of this application, multiple features are sometimes combined into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the object of this application are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

[0056] In some embodiments, numbers describing the number of components and attributes are used. It should be understood that such numbers used in the description of the embodiments are modified by the modifiers "about", "approximately" or "substantially" in some examples. Unless otherwise specified, "about", "approximately" or "substantially" indicate that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may change according to the required features of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and adopt the general method of retaining digits. Although the numerical domains and parameters used to confirm the breadth of their range in some embodiments of the present application are approximate values, in specific embodiments, the setting of such numerical values ​​is as accurate as possible within the feasible range.

[0057] Although the present application has been described with reference to the current specific embodiments, ordinary technicians in this technical field should recognize that the above embodiments are only used to illustrate the present application, and various equivalent changes or substitutions may be made without departing from the spirit of the present application. Therefore, as long as the changes and modifications to the above embodiments are within the essential spirit of the present application, they will fall within the scope of the claims of the present application.

Claims

1. A data communication system, comprising a first host transceiver module and a second slave transceiver module; The first host transceiver module and the second slave transceiver module are connected through a first data line, a second data line and a third data line to realize data transmission and reception, wherein the data includes a synchronization frame and a data frame; the synchronization frame includes a synchronization frame header, a synchronization clock segment and a synchronization bit, and the data frame includes a start bit, a data bit and a check bit; in, The synchronization frame is used to determine the baud rate of data transmission and reception between the first host transceiver module and the second slave transceiver module; Before the first host transceiver module sends a data frame to the second slave transceiver module, or before the second slave transceiver module sends a data frame to the first host transceiver module, the first host transceiver module sends a synchronization frame to the second slave transceiver module; When two consecutive low-level bits or two consecutive high-level bits appear in the transmitted data bit, a high-level bit is inserted after the two consecutive low-level bits, or a low-level bit is inserted after the two consecutive high-level bits; Each data bit in the data frame is sent once in sequence through the first data line, the second data line and the third data line respectively, the data bit sent through the first data line is delayed by one bit compared with the data bit sent through the second data line, and the data bit sent through the third data line is advanced by one bit compared with the data bit sent through the second data line.

2. The data communication system according to claim 1, characterized in that: The synchronization frame header includes three or more consecutive low-level bits sent through the first data line, the second data line and the third data line; The synchronous clock segment includes N unit time intervals, the synchronous clock segment sent through the first data line has M first edges, the synchronous clock segment sent through the second data line has M-2 first edges, and the synchronous clock segment sent through the third data line has M-1 first edges; M is greater than or equal to 2 and is a positive integer; N is a positive integer; The first data line, the second data line and the third data line respectively perform time interval calculations of M segments, M-2 segments and M-1 segments according to the first edge in the synchronous clock segment.

3. The data communication system according to claim 2, characterized in that: Determining the baud rate of data transmission and reception between the first host transceiver module and the second slave transceiver module includes: At the synchronization bit position, respectively count the total durations t1, t2 and t3 of N unit time intervals corresponding to the time intervals of the M segments, M-2 segments and M-1 segments corresponding to the M first edges, M-2 first edges and M-1 first edges of the first data line, the second data line and the third data line, and obtain corresponding unit time interval measurement values ​​τ1, τ2 and τ3; Select two unit time interval calculation values ​​whose difference is less than a first threshold ratio from the unit time interval measurement values ​​τ1, τ2 and τ3 corresponding to the first data line, the second data line and the third data line; Based on the two selected unit time interval measurement values, a unit time interval verification value is obtained; The baud rate of data transmission and reception between the first host transceiver module and the second slave transceiver module is obtained according to the unit time interval check value and the system main frequency.

4. The data communication system according to claim 2, characterized in that: The synchronization bit includes one or more high level bits sent through the first data line, the second data line and the third data line.

5. The data communication system according to claim 1, characterized in that: The start bit includes a one-bit low level sent through the first data line, the second data line and the third data line; The check bits include a parity check value sent through the second data line and a negated value of the parity check value sent through the third data line.

6. The data communication system according to claim 5, characterized in that: The data frame further includes a stop bit after the check bit; The end bit includes one or more high level bits sent through the first data line, the second data line and the third data line.

7. The data communication system according to claim 1, characterized in that: The data communication system further includes a first controller module and a second controller module corresponding to the first host transceiver module and the second slave transceiver module; When the data frame is received, the first host transceiver module or the second slave transceiver module sends a first interrupt signal to the corresponding first controller module and second controller module.

8. The data communication system according to claim 1, characterized in that: The first host transceiver module and the second slave transceiver module include a data encoding circuit, a transmission data buffer, a synchronization frame transmission circuit, a baud rate synchronization circuit, a data decoding circuit and a control register; The data encoding circuit is used to encode the data frame to be sent; The data decoding circuit is used to decode the received data frame; The control register is used to store the host and slave information, and determine the order of sending synchronization frames and data frames and the sending baud rate.

9. The data communication system according to claim 5, characterized in that: The first host transceiver module and the second slave transceiver module further include a received data buffer and a data correction circuit; The data correction circuit is used for checking and correcting the received data frame based on the parity check value and the data frame sent through the first data line, the second data line and the third data line.

10. The data communication system according to claim 3, characterized in that: The first threshold ratio is greater than zero and less than or equal to 20%.

11. A method for operating a data communication system, the data communication system comprising a first host transceiver module and a second slave transceiver module; the first host transceiver module and the second slave transceiver module are connected via a first data line, a second data line and a third data line, and realize data transmission and reception, the data comprising a synchronization frame and a data frame; the synchronization frame comprises a synchronization frame header, a synchronization clock segment and a synchronization bit, and the data frame comprises a start bit, a data bit and a check bit; The data communication system is configured as follows: Determine a baud rate for data transmission and reception between the first host transceiver module and the second slave transceiver module based on the synchronization frame; Before the first host transceiver module sends a data frame to the second slave transceiver module, or before the second slave transceiver module sends a data frame to the first host transceiver module, the first host transceiver module sends a synchronization frame to the second slave transceiver module; When two consecutive low-level bits or two consecutive high-level bits appear in the transmitted data bit, a high-level bit is inserted after the two consecutive low-level bits, or a low-level bit is inserted after the two consecutive high-level bits; Each bit of the data bits in the data frame is sent once in sequence through the first data line, the second data line and the third data line respectively, the data bit sent through the first data line is delayed by one bit than the data bit sent through the second data line, and the data bit sent through the third data line is advanced by one bit than the data bit sent through the second data line.

12. The operating method of the data communication system according to claim 11, characterized in that: The synchronization frame header includes three or more consecutive low-level bits sent through the first data line, the second data line and the third data line; The synchronous clock segment includes N unit time intervals, the synchronous clock segment sent through the first data line has M first edges, the synchronous clock segment sent through the second data line has M-2 first edges, and the synchronous clock segment sent through the third data line has M-1 first edges; M is greater than or equal to 2 and is a positive integer; N is a positive integer; The first data line, the second data line and the third data line respectively perform time interval calculations of M segments, M-2 segments and M-1 segments according to the first edge in the synchronous clock segment.

13. The method for operating a data communication system according to claim 12, characterized in that: Determining the baud rate of data transmission and reception between the first host transceiver module and the second slave transceiver module includes: At the synchronization bit position, respectively count the total durations t1, t2 and t3 of N unit time intervals corresponding to the time intervals of the M segments, M-2 segments and M-1 segments corresponding to the M first edges, M-2 first edges and M-1 first edges of the first data line, the second data line and the third data line, and obtain corresponding unit time interval measurement values ​​τ1, τ2 and τ3; Select two unit time interval calculation values ​​whose difference is less than a first threshold ratio from the unit time interval measurement values ​​τ1, τ2 and τ3 corresponding to the first data line, the second data line and the third data line; Based on the two selected unit time interval measurement values, a unit time interval verification value is obtained; The baud rate of data transmission and reception between the first host transceiver module and the second slave transceiver module is obtained according to the unit time interval check value and the system main frequency.

14. The method for operating a data communication system according to claim 11, characterized in that: The synchronization bit includes one or more high level bits sent through the first data line, the second data line and the third data line.

15. The operating method of the data communication system according to claim 11, characterized in that: The start bit includes a one-bit low level sent through the first data line, the second data line and the third data line; The check bits include a parity check value sent through the second data line and a negated value of the parity check value sent through the third data line.

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