Mask plate and electronic device, and manufacturing method thereof
By designing a combination of through holes and blind holes on the mask, the problems of stress concentration and short circuits on the solder pads during the welding process were solved, thus achieving welding stability and reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2022-06-17
- Publication Date
- 2026-07-07
AI Technical Summary
In the prior art, the flat mask is prone to damage to the backplane circuitry due to stress concentration during the welding process, and short circuits are easily caused between the pads, resulting in unstable connections.
A mask is designed, comprising through holes and blind holes surrounding the through holes. The dimensions of the blind holes in the thickness direction of the mask cover the protruding portion of the pads, ensuring that the mask does not contact the pads and that the soldering material is transferred to the pads through the through holes, thus avoiding stress concentration.
This effectively prevents stress concentration from damaging the backplane circuitry and avoids short circuits between solder pads, ensuring the stability and reliability of the soldering process.
Smart Images
Figure CN117295251B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of display technology, and more particularly to a mask plate and electronic device, and a method for manufacturing the same. Background Technology
[0002] SMT stands for Surface Mount Technology, a popular technology and process in the electronics assembly industry. It involves placing electronic components with leads on the surface of a substrate with pads and then soldering them using methods such as reflow soldering or dip soldering. To achieve a secure connection between the electronic components and the pads, solder is applied to the pads on the substrate, and then a series of processes are performed to securely connect the components to the pads. Summary of the Invention
[0003] The mask plate and electronic device, as well as their manufacturing method, provided in this disclosure are as follows:
[0004] On one hand, an embodiment of the present disclosure provides a mask configured to mask a backplane, the backplane including a substrate, an insulating layer and a pad group located on the substrate, the pad group including at least two pads, the insulating layer including an opening, the pads being disposed at the opening relative to the insulating layer toward a side away from the substrate;
[0005] The mask plate includes:
[0006] A through-hole, wherein the orthographic projection of the through-hole on the substrate overlaps with the orthographic projection of the pad on the substrate;
[0007] A blind via surrounds the through-hole. The size of the blind via in the thickness direction of the mask is greater than or equal to the size of the pad protruding from the insulating layer. The orthographic projection of the blind via on the substrate and the orthographic projection of the through-hole on the substrate are combined to cover the orthographic projection of the pad on the substrate.
[0008] In some embodiments, in the mask provided in the present disclosure, the size of the blind hole in the thickness direction of the mask is less than or equal to 1 / 3 of the thickness of the mask.
[0009] In some embodiments, in the mask provided in this disclosure, the orthogonal projection of the through hole on the substrate is located within the orthogonal projection of the pad on the substrate.
[0010] In some embodiments, in the mask provided in the present disclosure, the backplate includes a plurality of pixel regions, each pair of at least two vias constitutes a via group corresponding to a pad group, a pixel region corresponds to at least two via groups, and a blind via surrounds each of the vias in the at least two via groups corresponding to a pixel region.
[0011] In some embodiments, in the mask provided in the present disclosure, the orthographic projection of the via on the substrate is located within the orthographic projection of the pad group on the substrate, and the orthographic projection of the via on the substrate, the orthographic projection of the at least two pads in the pad group on the substrate, and the orthographic projection of the spacing between the pads on the substrate all overlap with each other.
[0012] In some embodiments, in the mask provided in this disclosure, one of the blind holes surrounds one of the through holes.
[0013] In some embodiments, in the mask provided in the present disclosure, the orthogonal projection of the blind hole on the substrate extends outward in a direction away from the orthogonal projection of the pad on the substrate.
[0014] In some embodiments, in the mask provided in this disclosure, the distance between the orthographic projection of the boundary of the blind hole away from the through hole on the substrate and the orthographic projection of the pad on the substrate is greater than or equal to 30 μm.
[0015] In some embodiments, in the mask provided in this disclosure, the distance between two adjacent blind holes is greater than or equal to 100 μm.
[0016] On the other hand, embodiments of this disclosure provide an electronic device, including: electronic components and a backplane, wherein the electronic components are electrically connected to the pad group, and the backplane is masked using the mask plate provided in the embodiments of this disclosure.
[0017] On the other hand, this disclosure provides a method for manufacturing the above-mentioned electronic device, including:
[0018] The mask plate and the back plate provided in the embodiments of this disclosure are aligned so that the through holes are directly opposite the pads.
[0019] The mask is controlled to prevent contact between the pad and the blind via in the area where the blind via is located, and to contact the insulating layer in the area outside the blind via;
[0020] A scraper is moved along a specific direction on the mask plate to push the welding material into the through hole, so that the welding material falls onto the pad through the through hole;
[0021] Remove the mask from the back plate;
[0022] Each pin of the electronic component is placed on the soldering material at each of the solder pads;
[0023] The soldering material is processed by a reflow soldering process, so that each pin of the electronic component is soldered together with each corresponding pad. Attached Figure Description
[0024] Figure 1 This is a schematic diagram showing the alignment and contact between the mask and the backplate in related technologies;
[0025] Figure 2 A schematic diagram of the structure of a backplate provided in an embodiment of this disclosure;
[0026] Figure 3 This is a schematic diagram of a mask provided in an embodiment of the present disclosure;
[0027] Figure 4 Figure 2 The backplate shown is Figure 3 The diagram shows the mask after alignment and contact.
[0028] Figure 5 For along Figure 4 Cross-sectional view of I-I';
[0029] Figure 6 For along Figure 4 Cross-sectional view of section II-II';
[0030] Figure 7 Another structural schematic diagram of the backplate provided in the embodiments of this disclosure;
[0031] Figure 8 A schematic diagram of yet another structure of the mask provided in an embodiment of this disclosure;
[0032] Figure 9 Figure 7 The backplate shown is Figure 8 The diagram shows the mask after alignment and contact.
[0033] Figure 10 For along Figure 9 Cross-sectional view of section III-III';
[0034] Figure 11 For along Figure 9 Cross-sectional view of IV-IV';
[0035] Figure 12 A schematic diagram showing the electrical connection between an electronic component and a pad group in a display device provided in an embodiment of this disclosure;
[0036] Figure 13 A flowchart illustrating a method for manufacturing an electronic device according to embodiments of this disclosure;
[0037] Figure 14 This is a schematic diagram showing the alignment of the mask plate and the back plate according to an embodiment of this disclosure;
[0038] Figure 15 A schematic diagram of the mask and backing plate provided in the embodiments of this disclosure during the masking process;
[0039] Figure 16 This is yet another schematic diagram of the mask plate and back plate provided in the embodiments of this disclosure during the masking process;
[0040] Figure 17 This is a schematic diagram illustrating the separation of the mask plate and the back plate according to an embodiment of this disclosure;
[0041] Figure 18 This is a schematic diagram showing the alignment of electronic components and pad groups provided in an embodiment of this disclosure. Detailed Implementation
[0042] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that the dimensions and shapes of the figures in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout the drawings.
[0043] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.
[0044] like Figure 1As shown, in the related technology, the insulating layer 101 has an opening K, and the surface of the pad 102 exposed by the opening K is 1μm to 3μm higher than the surface of the insulating layer 101. When using a flat mask M to set the soldering material, in order to avoid short circuits between adjacent pads, the area of the opening K of the flat mask M is smaller than the surface area of the pad 102, that is, the flat mask M contacts the edge of the pad 102. The scraper moves in a specific direction, so that the soldering material can fall from the opening K onto the pad. During the movement of the scraper, there will be stress concentration at the contact point S between the pad 102 and the flat mask M. Since the film layers of the backplane are thin and fragile, the backplane circuits are often damaged due to stress during the setting of the soldering material.
[0045] In this embodiment of the disclosure, the welding material includes either welding metal or welding auxiliary material.
[0046] Based on this, such as Figures 2 to 6 As shown, this embodiment of the present disclosure provides a mask plate 002 configured to mask a back plate 001. The back plate 001 includes a substrate 100, an insulating layer 101 and a pad group 102' located on the substrate 100. The pad group 102' includes at least two pads 102. The insulating layer 101 includes an opening K. The pads 102 are provided at the opening K to protrude from the insulating layer 101 toward the side away from the substrate 100.
[0047] Mask 002 includes:
[0048] Through hole 201, the orthographic projection of through hole 201 on substrate 100 overlaps with the orthographic projection of pad 102 on substrate 100;
[0049] Blind via 202 surrounds through via 201. The dimension a of blind via 202 in the thickness direction Z of mask 002 is greater than or equal to the dimension b of pad 102 protruding from insulating layer 101. The orthographic projection of blind via 202 on substrate 100 and the orthographic projection of through via 201 on substrate 101 are spliced together to cover the orthographic projection of pad 102 on substrate 100.
[0050] In the mask 002 provided in the embodiments of this disclosure, blind holes 202 are provided around the through holes 201 of the mask 002, and the dimension a (i.e., depth) of the blind holes 202 in the thickness direction Z of the mask 002 is greater than or equal to the dimension b of the pad 102 protruding from the insulating layer 101. The orthogonal projection of the blind holes 202 on the substrate 100 and the orthogonal projection of the through holes 201 on the substrate 100 are spliced together to cover the orthogonal projection of the pad 102 on the substrate 100. This allows the mask 002 to be placed on the back plate 001 after alignment. Specifically, the blind holes 202 of the mask 002 do not contact the pad 102, and the other parts of the mask 002 except for the blind holes 202 contact the insulating layer 101. This avoids stress concentration caused by the mask 002 overlapping the edge of the pad 102, and thus effectively solves the problem of stress concentration causing damage to the circuits of the back plate 001.
[0051] Optionally, the pad group 102' includes two pads 102, each being a first pad P electrically connected to the pins of a two-pin electronic component (e.g., a light-emitting diode). pad Second pad N pad The material of the pad 102 in this disclosure may include nickel and / or gold, etc. In some embodiments, a nickel (Ni) layer with a thickness of 3 μm to 5 μm may be first formed on the conductive pattern (e.g., a trace structure made of copper), and then a gold (Au) layer with a thickness of 0.03 μm may be plated on the surface of the nickel layer by a displacement reaction. The exposed area of the conductive pattern constitutes the pad 102.
[0052] In some embodiments, in the mask 002 provided in the present disclosure, such as Figure 5 and Figure 6As shown, the dimension a of the blind via 202 in the thickness direction Z of the mask 002 is less than or equal to 1 / 3 of the thickness c of the mask 002, to avoid the mask 002 being too thin and easily deformed, which would affect the lifespan and masking effect of the mask 002. Optionally, the thickness c of the mask 002 is 30 μm, and the dimension a of the blind via 202 in the thickness direction Z of the mask 002 is greater than the dimension b of the pad 102 protruding from the insulating layer 101 and less than or equal to 10 μm. Since the surface dimension b of the pad 102 in the thickness direction Z of the insulating layer 101 is greater than or equal to 1 μm and less than or equal to 3 μm, the distance between the blind via 202 and the pad 102 in the thickness direction Z of the mask 002 is equal to (ab), that is, greater than 0 and less than or equal to (7 μm to 9 μm), and the distance between the blind via 202 and the insulating layer 101 is equal to a, that is, greater than or equal to (1 μm to 3 μm) and less than or equal to 10 μm. As can be seen, the spacing between the blind via 202 and the pad 102, as well as the spacing between the blind via 202 and the insulating layer 101, is small. As a result, after the soldering metal (e.g., with solder paste) falls onto the pad 102 through the via 201, it is difficult for the solder paste to flow and enter the small space due to its viscosity, thus effectively preventing short circuits between adjacent pads 102 due to solder paste.
[0053] In some embodiments, in the mask 002 provided in the present disclosure, such as Figures 4 to 6 As shown, the orthographic projection of the via 201 on the substrate 100 lies within the orthographic projection of the pad 102 on the substrate 100. This allows solder metal (e.g., with solder paste) to fall onto the corresponding pad 102 through the via 201, preventing adjacent pads 102 from short-circuiting due to solder metal. Optionally, the size of the via 201 is the same as the pin size of the electronic component electrically connected to the pad 102. In some embodiments, the size of the via 201 can be finely adjusted based on the pin size of the electronic component to ensure that the solder metal transferred to the pad 102 through the via 201 is completely positioned between the pin of the electronic component and the pad 102 after the reflow soldering process, ensuring the electrical connection between the pin of the electronic component and the pad 102.
[0054] In some embodiments, in the mask 002 provided in the present disclosure, such as Figures 2 to 4As shown, the backplane 001 may include multiple pixel areas P, each pixel area P including three sub-pixels of different colors, each sub-pixel being a light-emitting diode (LED). A pad group 102' corresponds to one LED, and a pad group 102' includes two pads 102. A via group 201' includes the same number of vias 201 as the pads 102 in a pad group 102'. Each pair of adjacent vias 201 constitutes a via group 201' corresponding to a pad group 102'. A pixel area P corresponds to at least two via groups 201'. A blind via 202 surrounds each via 201 in the at least two via groups 201' corresponding to a pixel area P. This means that the blind vias 202 surrounding each via 201 in the at least two via groups 201' corresponding to a pixel area P are interconnected, thereby making the blind via 202 larger in size and easier to manufacture. Furthermore, because the spacing between the blind via 202 and the pad 102, as well as the spacing between the blind via 202 and the insulating layer 101, is small, the solder paste (e.g., with solder paste) has a certain viscosity and is difficult to flow into the small space after falling onto the pad 102 through the via 201. This effectively prevents short circuits from occurring between different pads 102 in the same area corresponding to the blind via 202 due to solder paste. In some other embodiments, a pad group 102' may include the same number of pads 102 as the pins of an electronic component, and a via group 201' may include the same number of vias 201 as the pads 102 in a pad group 102'.
[0055] In some embodiments, the mask 002 provided in this disclosure can be used to transfer welding auxiliary materials (e.g., flux). In this case, such as Figures 7 to 11 As shown, the orthogonal projection of the via 201 on the substrate 101 can be positioned within the orthogonal projection of the pad group 102' on the substrate 101, and the orthogonal projection of the via 201 on the substrate 101 overlaps with the orthogonal projections of at least two pads 102 in the pad group 102' on the substrate 101, as well as the orthogonal projection of the region g between adjacent pads 102 on the substrate 101. In a specific implementation, soldering auxiliary materials (e.g., flux) will simultaneously fall through the same via 201 onto at least two pads 102 of the pad group 102' and the region g between adjacent pads 102. However, since the flux only serves to promote the soldering process and prevent oxidation, and does not have electrical conductivity, the at least two pads 102 of the pad group 102' will not be short-circuited by the flux. Furthermore, compared to Figure 4 The orthographic projection shown is located in the through hole 201 within pad 102. Figure 9 The through-hole 201 shown in the orthographic projection located within pad group 102' has a larger diameter, making it easier to manufacture.
[0056] In some embodiments, in the mask 002 provided in the present disclosure, such as Figures 7 to 9 As shown, when the orthographic projection of the via 201 on the substrate 101 overlaps with the orthographic projections of at least two pads 102 in the pad group 102' on the substrate 101, and the orthographic projection of the region g between adjacent pads 102 on the substrate 101, a blind via 202 can surround a via 201. In some embodiments, a large blind via with the same depth as the blind via 202 can be formed first in the region where the blind via 202 is to be formed and the region of the via 201 to be formed that surrounds it. Then, a via 201 is formed in the region of the large blind via corresponding to the via 201, and the region of the large blind via corresponding to the blind via 202 can be used as the blind via 202. Thus, even if a blind via 202 only surrounds a via 201, because the diameter of the via 201 whose orthographic projection is located in the pad group 102' is larger, the diameter of the large blind via is also larger, making it easier to fabricate the large blind via and facilitating the fabrication of the blind via 202.
[0057] In some embodiments, in the mask 002 provided in the present disclosure, such as Figure 4 and Figure 9 As shown, the orthographic projection of the blind via 202 on the substrate 100 extends outward in a direction away from the orthographic projection of the pad 102 on the substrate 100 relative to the orthographic projection of the pad 102 on the substrate 100. This means that the orthographic projection of the blind via 202 on the substrate 100 will exceed the orthographic projection of the pad 102 on the substrate 100. In this way, the mask 002 can better avoid the pad 102 at the blind via 202, preventing stress concentration caused by the mask 002 overlapping the edge of the pad 102, thereby effectively avoiding stress concentration from damaging the circuitry of the backplane 001.
[0058] In some embodiments, the fabrication tolerance of the blind via 202 is 10 μm, and the alignment tolerance between the mask 002 and the backplate 001 is 20 μm. To prevent the mask 002 from overlapping the pad 102, in the mask 002 provided in the embodiments of this disclosure, as follows... Figure 4 and Figure 9 As shown, the distance d between the orthographic projection of the boundary of the blind via 202 away from the through via 201 on the substrate 100 and the orthographic projection of the pad 102 on the substrate 100 is greater than or equal to 30 μm.
[0059] In some embodiments, in the mask 002 provided in the present disclosure, such as Figure 11 As shown, the portion of the mask 002 between adjacent blind holes 202 contacts the insulating layer 101 of the backplate 001. To ensure a large contact area between the mask 002 and the insulating layer 101, effectively supporting the mask 002 from the insulating layer 101, and ensuring the structural stability of the mask 002, the dimensions of the portion of the mask 002 between adjacent blind holes 202 need to be appropriately set. In this disclosure, as... Figure 4 and Figure 9As shown, the distance e between two adjacent blind holes 202 is set to be greater than or equal to 100μm, for example, it can be 200μm, 300μm, etc.
[0060] Based on the same disclosed concept, embodiments of this disclosure also provide an electronic device, such as... Figure 12 As shown, it includes: electronic component 003, and the backplane 001 provided in the embodiments of this disclosure; wherein, the backplane 001 can be masked by the mask plate 002; the electronic component 003 is electrically connected to the pad group 102, and in some embodiments, one electronic component 003 is electrically connected to one pad group 102. The electronic component 003 can be a light-emitting diode, a driver chip, etc.
[0061] In some embodiments, such as Figure 5 , Figure 6 , Figure 10 and Figure 11 As shown, the backplane 001 provided in this embodiment may further include a first conductive layer 103, a planarization layer 104, and a second conductive layer 105, etc. The materials of the first conductive layer 103 and the second conductive layer 105 may include copper (Cu), etc. The first conductive layer 103 and the second conductive layer 105 are used to fabricate circuits that drive the electronic component 003 to operate. Other essential components of the backplane 001 are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.
[0062] In some embodiments, the electronic device provided in this disclosure can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. This electronic device includes, but is not limited to, components such as: radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, memory, processor, and power supply. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the electronic device provided in this disclosure; in other words, the electronic device provided in this disclosure may include more or fewer of the aforementioned components, or combine certain components, or have different component arrangements.
[0063] Based on the same disclosed concept, this disclosure also provides a method for manufacturing an electronic device, such as... Figure 13 As shown, it includes the following steps:
[0064] S1301. Align the mask plate 002 and the back plate 001 provided in this embodiment of the present disclosure, such that the through hole 201 and the pad 102 are directly opposite each other. Figure 14 As shown.
[0065] S1302, the control mask 002 does not contact the pad 102 in the area where the blind via 202 is located, and contacts the insulating layer 101 in the area outside the area where the blind via 202 is located, such as Figure 15 As shown.
[0066] S1303. Move the scraper along a specific direction on the mask 002 to push the welding material WM into the through hole 201, so that the welding material WM falls onto the pad 102 through the through hole 201. Figure 16 As shown.
[0067] S1304. Remove the mask 002 from the backplate 001, as follows: Figure 17 As shown.
[0068] S1305, Place each pin 301 of electronic component 003 onto the soldering material WM at each pad 102, such as... Figure 18 As shown.
[0069] S1306. The soldering material WM is processed by reflow soldering to solder each pin 301 of electronic component 003 to the corresponding pad 102. Figure 12 As shown.
[0070] It should be noted that the soldering material WM in this disclosure can be either solder metal (e.g., solder paste) or soldering auxiliary material (e.g., flux). When the soldering material WM is solder paste, flux can be applied to each pin 301 of the electronic component 003. After the reflow soldering process, each pin 301 of the electronic component 003 can be electrically connected to each pad 102 through the cured solder metal. When the soldering material WM is flux, since the flux only promotes the soldering process and has an anti-oxidation function, and does not have conductivity, solder metal (e.g., solder paste) needs to be applied to each pin 301 of the electronic component 003. After the reflow soldering process, each pin 301 of the electronic component 003 can be electrically connected to each pad 102 through the cured solder metal. In practical implementation, during the reflow soldering process, the solder metal first melts at a high temperature, partially forming an intermetallic compound (IMC) with the surface material of the pad 102. Then, during cooling, the solder metal and / or the intermetallic compound solidify, thereby forming a connection part WM'. This allows each pin 301 of the electronic component 003 to be electrically connected to each pad 102 through the connection part WM', such as... Figure 12 As shown. The orthographic shape of the connector WM' on the substrate 100 is limited by the orthographic shapes of the pin 301 and the pad 102 on the substrate 100. Generally, the orthographic shape of the connector WM' and the orthographic shape of the pin 301 to which it is electrically connected on the substrate 100 and the orthographic shape of the pad 102 on the substrate 100 are basically the same, for example, approximately circular or square.
[0071] Although preferred embodiments have been described in this disclosure, it should be understood that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, this disclosure is also intended to include such modifications and variations if they fall within the scope of the claims of this disclosure and their equivalents.
Claims
1. A mask configured to mask a backplane, the backplane including a substrate, an insulating layer and a pad group located on the substrate, the pad group including at least two pads, the insulating layer including an opening, the pads being disposed at the opening relative to the insulating layer toward a side away from the substrate; The mask plate includes: A through-hole, wherein the orthographic projection of the through-hole on the substrate overlaps with the orthographic projection of the pad on the substrate; A blind via surrounds the through-hole. The dimension of the blind via in the thickness direction of the mask is greater than or equal to the dimension of the pad protruding from the insulating layer. The orthographic projection of the blind via on the substrate and the orthographic projection of the through-hole on the substrate are combined to cover the orthographic projection of the pad on the substrate. The orthographic projection of the via on the substrate is located within the orthographic projection of the pad group on the substrate, and the orthographic projection of the via on the substrate, the orthographic projection of the at least two pads in the pad group on the substrate, and the orthographic projection of the spacing between the at least two pads on the substrate all overlap with each other.
2. The mask plate as claimed in claim 1, wherein, The size of the blind hole in the thickness direction of the mask plate is less than or equal to 1 / 3 of the thickness of the mask plate.
3. The mask plate as described in claim 1, wherein, One of the blind holes surrounds one of the through holes.
4. The mask plate according to any one of claims 1 to 3, wherein, The orthographic projection of the blind via on the substrate extends outward in a direction away from the orthographic projection of the pad on the substrate.
5. The mask plate as described in claim 4, wherein, The distance between the orthographic projection of the boundary of the blind via away from the through via on the substrate and the orthographic projection of the pad on the substrate is greater than or equal to 30 μm.
6. The mask plate as claimed in claim 5, wherein, The distance between two adjacent blind holes is greater than or equal to 100 μm.
7. An electronic device, wherein, include: Electronic components and a backplane, wherein the electronic components are electrically connected to the pad group, and the backplane is masked using a mask plate as described in any one of claims 1 to 6.
8. A method for manufacturing an electronic device as described in claim 7, wherein, include: The mask plate and the back plate as described in any one of claims 1 to 6 are aligned such that the through holes are directly opposite the pads; The mask is controlled to prevent contact between the pad and the blind via in the area where the blind via is located, and to contact the insulating layer in the area outside the blind via; A scraper is moved along a specific direction on the mask plate to push welding auxiliary material into the through hole, so that the welding auxiliary material falls onto the pad through the through hole; Remove the mask from the back plate; Each pin of the electronic component is placed on the soldering aid material at each of the solder pads; The welding auxiliary material is processed by reflow soldering so that each pin of the electronic component is soldered together with each corresponding pad.