Display panel and display device

Abstract

A display panel and a display device are disclosed. The display panel includes sub-pixels, data lines, and gate lines. Each sub-pixel includes a pixel circuit electrically connected to the data lines and the gate lines. The display panel includes a plurality of display zones and a plurality of selection signal line groups arranged in a one-to-one correspondence. Each display zone includes at least two sub-pixels, and each selection signal line group includes multiple selection signal lines. The selection signal lines corresponding to different display zones are insulated from each other. The pixel circuit includes a transistor, and the active semiconductor layer in the transistor includes a first portion and a second portion. The first portion overlaps with a gate line electrically connected to the transistor, and the second portion overlaps with at least one selection signal line. The gate line and the selection signal line are configured such that the transistor turns on when both are input with an input turn-on voltage. The display panel provided in this disclosure achieves zoned display while minimizing the impact on the aperture ratio of the sub-pixels.

Description

Technical Field

[0001] At least one embodiment of this disclosure relates to a display panel and a display device. Background Technology

[0002] With the development of the information society, three-dimensional (3D) displays are increasingly favored by users. Currently, 3D displays sometimes sacrifice resolution to achieve the effect of different content seen by the left and right eyes. Therefore, high-resolution displays have become a necessary condition for 3D displays; the higher the resolution, the better the user experience. However, higher resolution means higher system bandwidth and a larger amount of data processing is required, which leads to higher requirements for display technology and increased costs. Summary of the Invention

[0003] This disclosure provides a display panel and a display device.

[0004] This disclosure provides at least one embodiment of a display panel, comprising: a substrate; a plurality of sub-pixels located on the substrate, at least some of the sub-pixels including pixel circuits; a plurality of data lines located on the substrate and arranged along a first direction, wherein the pixel circuit of at least one sub-pixel is electrically connected to a data line; and a plurality of gate lines located on the substrate and arranged along a second direction, wherein the pixel circuit of the at least one sub-pixel is electrically connected to a gate line, wherein the first direction and the second direction intersect. The display panel includes multiple display zones and multiple selection signal line groups. The multiple display zones and the multiple selection signal line groups are arranged in a one-to-one correspondence. Each display zone includes at least two sub-pixels, and each selection signal line group includes multiple selection signal lines. The selection signal lines corresponding to different display zones are isolated from each other. The pixel circuit includes a transistor. Along a direction perpendicular to the substrate, the active semiconductor layer in the transistor of the at least one sub-pixel includes a first part and a second part. The first part overlaps with the gate line electrically connected to the transistor, and the second part overlaps with at least one selection signal line. The transistor is turned on when both the gate line and the selection signal line are input with an on-state voltage.

[0005] For example, in some examples, the plurality of display partitions includes M display partitions arranged along the first direction, with at least one grid line passing through the M display partitions arranged along the first direction, where M is a positive integer greater than or equal to 2.

[0006] For example, in some examples, in at least some selection signal line groups, all selection signal lines are electrically connected in each selection signal line group.

[0007] For example, in some examples, at least one selection signal line group includes multiple selection signal lines, which overlap with the second portion.

[0008] For example, in some examples, the first selected area signal line is located on the same layer as the gate line.

[0009] For example, in some examples, the first selected area signal line is located on a different layer from the gate line.

[0010] For example, in some examples, the extension direction of the first selection area signal line is the same as the extension direction of the gate line, and two adjacent display partitions arranged along the first direction include a first display partition and a second display partition. One of the plurality of first selection area signal lines set in the first display partition and one of the plurality of first selection area signal lines set in the second display partition are located on the same straight line and are spaced apart.

[0011] For example, in some examples, the plurality of selection signal lines in the at least one selection signal line group further includes at least one second selection signal line, which is located on a different layer from the first selection signal line and is electrically connected to the first selection signal line.

[0012] For example, in some examples, the extension direction of the first selection signal line is the same as the extension direction of the gate line, the extension direction of the second selection signal line intersects the extension direction of the first selection signal line, and at least one second selection signal line passes through multiple display zones.

[0013] For example, in some examples, each data line in at least a portion of the data lines is electrically connected to two sub-pixels arranged along the first direction; the plurality of gate lines include a first gate line and a second gate line arranged alternately along the second direction, and a gate line pair formed by the first gate line and the second gate line is provided between two adjacent sub-pixels arranged along the second direction; one of the two sub-pixels arranged along the first direction and electrically connected to the same data line is electrically connected to the first gate line, and the other is electrically connected to the second gate line; the second selection area signal line is located on the same layer as the data lines.

[0014] For example, in some examples, the second selection signal line extends in the same direction as the data line, the second selection signal line is located between two adjacent sub-pixels arranged along the first direction, and the two adjacent sub-pixels are electrically connected to different data lines respectively.

[0015] For example, in some examples, a first selection signal line is provided between each gate line pair, and the second portion of the transistor of the pixel circuit electrically connected to the first gate line and the second gate line in the same gate line pair overlaps with the same first selection signal line located between the same gate line pair.

[0016] For example, in some examples, the plurality of first selection area signal lines include a plurality of first selection area signal line pairs, and the first selection area signal line pairs are provided between two adjacent sub-pixels arranged along the second direction; a gate line pair is provided between each first selection area signal line pair, or a first selection area signal line pair is provided between each gate line pair.

[0017] For example, in some examples, the second selection signal line is located on a different layer than the data line.

[0018] For example, in some examples, the display panel further includes a light-shielding layer located between the data lines and the substrate. The second selection signal line is disposed in the same layer as the light-shielding layer.

[0019] For example, in some examples, the second selection signal line extends in the same direction as at least a portion of the data line, and overlaps with the data line in a direction perpendicular to the substrate.

[0020] For example, in some examples, the first selection area signal line includes at least one first sub-selection area signal line and multiple second sub-selection area signal lines electrically connected to each other, the second sub-selection area signal lines overlapping the second portion; the extension direction of the second sub-selection area signal lines intersects the extension direction of the gate lines, the extension direction of the first sub-selection area signal lines intersects the extension direction of the second sub-selection area signal lines, and the second sub-selection area signal lines corresponding to each display partition are insulated from the second sub-selection area signal lines corresponding to other display partitions.

[0021] For example, in some examples, the multiple selection signal lines in the at least one selection signal line group further include at least one second selection signal line, which is located on a different layer from the first selection signal line and is electrically connected to the first selection signal line, and the second selection signal line passes through at least one display partition.

[0022] For example, in some examples, each data line in at least a portion of the data lines is electrically connected to two sub-pixels arranged along the first direction; the plurality of gate lines include a first gate line and a second gate line arranged alternately along the second direction, a gate line pair formed by the first gate line and the second gate line is provided between two adjacent sub-pixels arranged along the second direction, one of two sub-pixels arranged along the first direction and connected to the same data line is electrically connected to the first gate line, and the other is electrically connected to the second gate line; the second selection area signal line is located on the same layer as the data lines.

[0023] For example, in some examples, the second selection signal line extends in the same direction as at least a portion of the data line, the second selection signal line is located between two adjacent sub-pixels arranged along the first direction, and the two adjacent sub-pixels are electrically connected to different data lines respectively.

[0024] For example, in some examples, the second selection signal line is located on a different layer than the data line.

[0025] For example, in some examples, at least one of the second sub-selection signal line and the second selection signal line overlaps with the data line along a direction perpendicular to the substrate.

[0026] For example, in some examples, the first sub-selection signal line and the second sub-selection signal line are an integrated structure.

[0027] For example, in some examples, the display panel further includes: a plurality of gate driver groups arranged along the second direction, the gate driver groups being electrically connected to the gate lines, and at least a portion of the plurality of gate driver groups being configured to each be individually input with a frame start signal. The plurality of display partitions include a plurality of display partition rows arranged along the second direction, each display partition row including display partitions arranged along the first direction, and the plurality of gate driver groups being electrically connected to the plurality of display partition rows in a one-to-one correspondence.

[0028] For example, in some examples, the display panel further includes multiple frame start signal lines. These multiple frame start signal lines are electrically connected to the multiple gate driver groups in a one-to-one correspondence.

[0029] For example, in some examples, the display panel further includes at least one frame start signal line. A plurality of control units are disposed between the plurality of gate driver groups and the at least one frame start signal line, the plurality of control units being electrically connected to the plurality of gate driver groups in a one-to-one correspondence; each frame start signal line is electrically connected to at least two control units of the plurality of control units to input a frame start signal to at least two control units of the plurality of control units.

[0030] For example, in some examples, the at least one frame start signal line includes only one frame start signal line, which is electrically connected to each of the plurality of control units to input a frame start signal to each of the plurality of control units individually.

[0031] For example, in some examples, at least one gate line includes two sub-gate lines and at least one connecting portion connecting the two sub-gate lines, the two sub-gate lines are arranged in parallel on the same layer, and the two sub-gate lines and the connecting portion are located on different layers, and the two sub-gate lines included in each gate line are electrically connected through the connecting portion; one of the two sub-gate lines overlaps with the first portion.

[0032] This disclosure provides at least one embodiment of a display device, including: an eye tracker; a content generation unit electrically connected to the eye tracker; a data processing unit electrically connected to the content generation unit; and any one of the above-mentioned display panels electrically connected to the data processing unit. The eye tracker is configured to determine a gaze point position on a display surface of the display panel corresponding to the eyeball by tracking the position of the eyeball. The gaze point position is located in a first region of the display surface, and the display surface further includes a second region located outside the first region. The first region includes at least one of the display partitions. The content generation unit is configured to generate adjustment data based on the gaze point position. The data processing unit is configured to generate display data based on the adjustment data. The display panel receives the display data to adjust the display resolution of the image displayed in the first region to be greater than the display resolution of the image displayed in the second region.

[0033] For example, in some examples, the first region includes a display partition where the gaze point is located; or, the gaze point is located in a display partition where the first region includes other display partitions surrounding the display partition.

[0034] For example, in some examples, the content generation unit is configured to acquire images displayed on the display surface at multiple different locations to generate multiple viewpoint images. These multiple viewpoint images include multiple first viewpoint images corresponding to the eyeball and multiple second viewpoint images in addition to the multiple first viewpoint images. At least one first viewpoint image includes an image formed in a first region and an image formed in a second region. Each second viewpoint image includes only an image formed in the second region. The content generation unit generates the adjustment data based on the gaze point position by adjusting data of the first viewpoint image formed in the second region and data of the second viewpoint image to generate at least a portion of the adjustment data. This at least a portion of the adjustment data is configured to reduce the display resolution of the image displayed in the second region.

[0035] For example, in some examples, the adjustment data includes first content data and compressed data. The first content data includes data corresponding to an image configured to be transmitted to the first region. The compressed data includes data generated by compressing second content data corresponding to an image configured to be transmitted to the second region by a factor of w, where w is a positive integer greater than 1. The display data includes first display data and second display data. The data processing unit is configured to process the received first content data to process the first content data into the first display data corresponding to the image in the first region. The data processing unit is also configured to process the compressed data w times to form the second display data corresponding to the image in the second region.

[0036] For example, in some examples, the second region includes a first sub-region located on at least one side of the first region in the row direction, and the adjustment data includes p*w row adjustment data; the data processing unit includes a row processing unit, and the p*w row adjustment data transmitted by the content generation unit to the row processing unit includes p row compressed data and q*w row first content data, the image corresponding to the q*w row first content data is located in the first region, and the image corresponding to the q row compressed data in the p row compressed data is located in the first sub-region; the row processing unit is configured to process the q row compressed data repeatedly w times to form q*w row second display data, and to process the q*w row first content data into q*w row first display data, 1≤q≤p, and p and q are both positive integers.

[0037] For example, in some examples, the second region further includes a second sub-region located on at least one side of the first region in the column direction; the image corresponding to the (pq) rows of compressed data other than the q rows of compressed data in the p rows of compressed data is located in the second sub-region, and the row processing unit is configured to process the (pq) rows of compressed data w times to form (pq)*w rows of second display data. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0039] Figure 1A This is a partial planar structure schematic diagram of a display panel provided according to an example of an embodiment of the present disclosure;

[0040] Figure 1B For along Figure 1A A schematic diagram of the local cross-sectional structure intercepted by line BB' shown;

[0041] Figure 1C For along Figure 1A A schematic diagram of the local cross-sectional structure intercepted by line DD' shown;

[0042] Figure 2 For including Figure 1A The diagram shows a planar partition of the display panel.

[0043] Figure 3 for Figure 1A The diagram shows the electrical connection relationship between sub-pixels and signal lines when no selection area signal line group is set in the display panel.

[0044] Figure 4 This is a schematic diagram illustrating the electrical connection relationship between sub-pixels and signal lines in a display panel without a selection signal line group, according to another example of an embodiment of this disclosure.

[0045] Figure 5 for Figure 4 The diagram shown illustrates the distribution relationship between sub-pixels and signal lines after setting up a selection area signal line group on the display panel in one example.

[0046] Figure 6 for Figure 5 The diagram shows the overlapping relationship between some sub-pixels, grid lines, and selection signal line groups in the display panel.

[0047] Figure 7 For along Figure 6 A schematic diagram of the local cross-sectional structure intercepted by line CC'.

[0048] Figure 8 for Figure 4 The diagram shown illustrates the distribution relationship between sub-pixels and signal lines after setting the selection area signal line group in another example.

[0049] Figure 9 for Figure 8 A schematic diagram showing the overlapping relationship between some sub-pixels and the grid lines and selection signal line groups in an example of the display panel shown;

[0050] Figure 10 for Figure 8 A schematic diagram showing the overlapping relationship between some sub-pixels and the grid lines and selection signal line groups in another example of the display panel shown;

[0051] Figure 11 and Figure 12 Schematic diagrams of partial sub-pixels, signal lines, and selection signal line groups of a display panel provided according to different embodiments of this disclosure;

[0052] Figure 13 This is a partial planar structure schematic diagram of a display panel provided according to another example of an embodiment of the present disclosure;

[0053] Figure 14 For along Figure 13 A schematic diagram of the local cross-sectional structure intercepted by line EE';

[0054] Figure 15 For along Figure 13 A schematic diagram of the local cross-sectional structure intercepted by the FF' line shown;

[0055] Figure 16 This is a schematic diagram illustrating the overlapping relationship between the active semiconductor layer and the gate lines in a display panel according to another example of an embodiment of this disclosure;

[0056] Figure 17 For along Figure 16 A schematic diagram of the local cross-sectional structure intercepted by line GG' shown;

[0057] Figure 18 This is a partial planar structure schematic diagram of a display panel provided according to an example of an embodiment of the present disclosure;

[0058] Figure 19 and Figure 20 for Figure 18 A schematic diagram showing the electrical connection relationship between the gate driver group and the frame start signal line in different examples of the display panel shown;

[0059] Figure 21 for Figure 20 The circuit diagram of an example control unit is shown.

[0060] Figure 22 for Figure 20 The display panel shown includes Figure 21 A schematic diagram of the control unit shown;

[0061] Figure 23 For including Figure 22 The display panel showing the connection relationship between the control unit and the frame start signal line;

[0062] Figure 24 for Figure 21 and Figure 22 The timing diagram corresponding to the circuit structure of the control unit shown;

[0063] Figure 25 This is another circuit diagram of the control unit;

[0064] Figure 26 for Figure 25 The timing diagram of the circuit structure shown;

[0065] Figure 27 This is another circuit diagram of the control unit;

[0066] Figure 28 for Figure 27The timing diagram of the circuit structure shown;

[0067] Figure 29 This is another circuit diagram of the control unit;

[0068] Figure 30 for Figure 29 The timing diagram of the circuit structure shown;

[0069] Figure 31 To be Figure 27 The circuit structure shown is part of the circuit structure and Figure 29 The circuit structure shown is a combination of some circuit structures.

[0070] Figure 32 This is a partial planar structural diagram of a display panel provided according to an embodiment of the present disclosure;

[0071] Figure 33 This is a schematic diagram of the display partitions of a display panel provided according to an embodiment of the present disclosure;

[0072] Figure 34 This is a structural block diagram of a display device provided according to an embodiment of the present disclosure;

[0073] Figure 35 for Figure 34 A schematic diagram of the partitioning of the display surface of the display device shown;

[0074] Figure 36 This is a block diagram of the eye tracker.

[0075] Figure 37 A schematic diagram showing a user viewing a display device;

[0076] Figure 38 This is a schematic diagram showing how the first region is determined on the display surface based on the position of the gaze point.

[0077] Figure 39 A diagram illustrating how the human eye views the display surface from different positions;

[0078] Figure 40 A schematic diagram showing multiple first viewpoint images corresponding to the eyeball and multiple second viewpoint images in addition to the multiple first viewpoint images;

[0079] Figure 41 This is a schematic diagram showing the positional relationship between the first and second areas in the display panel.

[0080] Figure 42 This is a structural block diagram of the data processing department;

[0081] Figure 43 This represents the correspondence between row processing units and sub-pixel rows;

[0082] Figure 44For row processing unit Figure 41 The diagram shows the process of processing data in region M2.

[0083] Figure 45 For row processing unit Figure 41 The diagram shows the process of processing data in regions M1 and M3.

[0084] Figure 46 This is a flowchart of the data processing workflow for the data processing department.

[0085] Figure 47 This is a schematic diagram of a plurality of first viewpoint images corresponding to an eyeball and a plurality of second viewpoint images in addition to the plurality of first viewpoint images, provided according to another example of an embodiment of the present disclosure. Detailed Implementation

[0086] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0087] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0088] The term "vertical" as used in the embodiments of this disclosure includes features such as "vertical" in a strict sense, as well as features such as "approximately vertical" that include a certain degree of error, taking into account measurement and errors associated with the measurement of a specific quantity (e.g., limitations of the measurement system), and represents a range of acceptable deviations for a specific value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value. Unless otherwise specified in the following embodiments of this disclosure, the quantity of a component is implied to mean that the component may be one or more, or can be understood as at least one. "At least one" means one or more, and "more" means at least two.

[0089] In this embodiment of the disclosure, "same layer" can refer to a layer structure formed using the same film deposition process to create a film layer for a specific pattern, and then using the same mask to form a single patterning process. That is, one patterning process corresponds to one mask. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may be at the same height or have the same thickness, or they may be at different heights or have different thicknesses.

[0090] In their research, the inventors of this application discovered that the display area of ​​a display panel can be partitioned and controlled by increasing the number of thin-film transistors (TFTs). For example, the display panel may include multiple sub-pixels, each sub-pixel including at least one TFT, with the newly added TFTs and the TFTs already present in the sub-pixels jointly controlling the input signal. However, increasing the number of TFTs can easily lead to a decrease in the aperture ratio of the sub-pixels. If the added TFTs are concentrated in the non-display area of ​​the display panel, it can also easily cause stripes to appear on the display panel during display.

[0091] This disclosure provides a display panel and a display device. The display panel includes a substrate and a plurality of sub-pixels, a plurality of data lines, and a plurality of gate lines located on the substrate. At least some sub-pixels include pixel circuits; the plurality of data lines are arranged along a first direction, and the pixel circuit of at least one sub-pixel is electrically connected to a data line; the plurality of gate lines are arranged along a second direction, and the pixel circuit of at least one sub-pixel is electrically connected to a gate line, the first direction and the second direction intersect. The display panel includes a plurality of display zones and a plurality of selection signal line groups, the plurality of display zones and the plurality of selection signal line groups are configured one-to-one, each display zone includes at least two sub-pixels, each selection signal line group includes a plurality of selection signal lines, and the selection signal lines corresponding to different display zones are insulated from each other; the pixel circuit includes a transistor, and along a direction perpendicular to the substrate, the active semiconductor layer in the transistor of at least one sub-pixel includes a first portion and a second portion, the first portion overlaps with a gate line electrically connected to the transistor, the second portion overlaps with at least one selection signal line, and the gate line and the selection signal line are configured such that when both are input with an input turn-on voltage, the transistor is turned on. In the display panel provided in this embodiment, by setting selection signal lines that overlap with the active semiconductor layer of the transistor, the impact on the aperture ratio of sub-pixels can be minimized while achieving partitioned display.

[0092] The display panel and display device provided in the embodiments of this disclosure are described below with reference to the accompanying drawings.

[0093] Figure 1A This is a partial planar structure schematic diagram of a display panel provided according to an example of an embodiment of the present disclosure. Figure 1B For along Figure 1A A schematic diagram of the local cross-section structure intercepted by line BB'. Figure 2 For including Figure 1A The diagram shows a planar partitioning of the display panel. Figure 3 for Figure 1A The diagram shows the electrical connection relationship between sub-pixels and signal lines when no selection area signal line group is set in the display panel.

[0094] Figure 2 Only a portion of the display area is shown schematically, and only a portion of the sub-pixels are shown within this portion of the display area. Figure 2 The number of subpixels included in the display partition is only shown schematically. The number of subpixels in the display partition is not limited to the number shown in the figure and can be set according to the actual product requirements.

[0095] like Figures 1A to 2 As shown, the display panel includes a substrate 100 and a plurality of sub-pixels 200, a plurality of data lines 300, and a plurality of gate lines 400 located on the substrate 100. At least some of the sub-pixels 200 include pixel circuitry 210; the plurality of data lines 300 are arranged along a first direction, and the plurality of gate lines 400 are arranged along a second direction, the first direction and the second direction intersecting. For example, the first direction can be... Figure 1A The X direction shown can be followed by a second direction. Figure 1A The Y direction shown is not limited to this, and the first and second directions can be interchanged. For example, the first and second directions can be perpendicular, but are not limited to this. For example, the angle between the first and second directions can be 30 to 120 degrees, 45 to 100 degrees, 60 to 90 degrees, etc.

[0096] like Figures 1A to 2 As shown, at least one pixel circuit 201 of a sub-pixel 200 is electrically connected to a data line 300; at least one pixel circuit 201 of a sub-pixel 200 is electrically connected to a gate line 400. For example, the pixel circuit 201 of a sub-pixel 200 is electrically connected to both a gate line 400 and a data line 300. For example, the area defined by the intersection of two adjacent gate lines 400 and two adjacent data lines 300 can be the area where the sub-pixel 200 is located.

[0097] like Figures 1A to 2As shown, the display panel includes multiple display zones 110 and multiple selection signal line groups 500. Each display zone 110 corresponds one-to-one with each selection signal line group 500. Each display zone 110 includes at least two sub-pixels 200, and each selection signal line group 500 includes multiple selection signal lines (such as the first selection signal line 510 and the second selection signal line 520 described later). The selection signal lines corresponding to different display zones 110 are insulated from each other. For example, a sub-pixel 200 within one display zone 110 is electrically connected to a selection signal line in one selection signal line group 500, and sub-pixels 200 within different display zones 110 are electrically connected to selection signal lines in different selection signal line groups 500. For example, the one-to-one correspondence between the multiple display partitions 110 and the multiple selection signal line groups 500 can mean that each sub-pixel 200 in each display partition 110 is electrically connected to a selection signal line group 500, and the sub-pixels 200 in different display partitions 110 are electrically connected to different selection signal line groups 500.

[0098] like Figures 1A to 2 As shown, the pixel circuit 201 includes transistors 210, along a direction perpendicular to the substrate 100 (such as a direction perpendicular to the main surface of the substrate 100, i.e., perpendicular to...). Figure 1A (As shown in the XY plane direction), the active semiconductor layer 220 in the transistor 210 of at least one sub-pixel 200 includes a first portion 221 and a second portion 222. The first portion 221 overlaps with a gate line 400 electrically connected to the transistor 210, and the second portion 222 overlaps with at least one selection signal line. When both the gate line 400 and the selection signal line are configured to be input with an on-state voltage, the transistor 210 is turned on. In the display panel provided in this embodiment, by providing a selection signal line that overlaps with the active semiconductor layer of the transistor, the impact on the aperture ratio of the sub-pixels can be minimized while achieving zoned display.

[0099] For example, pixel circuit 201 includes at least two transistors, the gate of at least one transistor is electrically connected to a gate line, and the gate of at least one transistor is electrically connected to a first selected area signal line.

[0100] For example, such as Figures 1A to 2As shown, the switching effect of gate line 400 and selection signal line group 500 on transistor 210 can be analogized to an AND gate. When both gate line 400 and selection signal line group 500 are connected to the turn-on voltage, transistor 210 is turned on. When at least one of gate line 400 and selection signal line group 500 is connected to the turn-off voltage, transistor 210 is turned off. For example, gate line 400 is configured to write row select signals, and selection signal line group 500 is configured to write area select signals. If the area select signal is valid, the row select signals written to gate line 400 function normally (i.e., function the same as in a conventional display). For example, when the transistor is a PMOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor), the valid signal for the area select signal is a low voltage; when the transistor is an NMOS transistor, the valid signal for the area select signal is a high voltage.

[0101] For example, such as Figure 2 As shown, taking the three display zones 111, 112, and 113 in display zone 110 as an example, when the selection signal line group 500 is not set, the gate line 400 is written with gate signals line by line. If data is written to display zone 111, display zone 112 will also be affected. The gate signal in display zone 113 needs to be written with gate signals only after display zones 111 and 112 have completed their gate signal writing. The display panel provided in this embodiment of the present disclosure, through the combined action of the gate line and the selection signal line group on the pixel circuit of the sub-pixel, can write data to any display zone individually according to display needs. For example, only the gate signal and data signal can be written to display zone 113, while display zones 111 and 112 keep the data of the previous frame unchanged, which is beneficial for saving bandwidth.

[0102] For example, such as Figures 1A to 2 As shown, the number of transistors 210 included in the pixel circuit 201 can be set according to product requirements.

[0103] For example, such as Figure 3 As shown, when no selection signal line group 500 is set in the display panel, the pixel circuit 201 can be equipped with at least two transistors. For example, a transistor includes a source, a drain, and a gate. The source and drain of the transistor can be symmetrical in structure, so their physical structures can be indistinguishable.

[0104] For example, such as Figure 1A As shown, the pixel circuit 201 may include four transistors, with the active semiconductor layers of two transistors overlapping the gate line 400, and the active semiconductor layers of the other two transistors overlapping the selection signal line. However, this embodiment is not limited to this; the pixel circuit 201 may include two transistors, with the active semiconductor layer of one transistor overlapping the gate line, and the active semiconductor layer of the other transistor overlapping the selection signal line.

[0105] For example, transistor 210 may include a thin-film transistor or a field-effect transistor or other switching devices with the same characteristics. The thin-film transistor may include an oxide semiconductor thin-film transistor, an amorphous silicon thin-film transistor, or a polycrystalline silicon thin-film transistor, etc.

[0106] For example, pixel circuit 201 may also include at least one capacitor.

[0107] For example, such as Figures 1A to 3 As shown, sub-pixel 200 may include pixel electrode 202, and transistor 210 includes a transistor electrically connected to pixel electrode 202.

[0108] For example, such as Figures 1A to 2 As shown, in each display partition 110, the selection signal line group 500 is insulated from the grid line 400 and the data line 300.

[0109] In some examples, such as Figure 2 As shown, the plurality of display partitions 110 include M display partitions 110 arranged along a first direction, and at least one grid line 400 passes through the M display partitions arranged along the first direction. For example, each grid line 400 passes through the M display partitions arranged along the first direction.

[0110] For example, such as Figure 2 As shown, the first direction can be the row direction, and the grid line 400 extends along the row direction and passes through multiple display partitions 110 arranged along the row direction, such as display partition 111 and display partition 112.

[0111] In some examples, such as Figure 2 As shown, in at least some of the selection signal line groups 500, all selection signal lines in each selection signal line group 500 are electrically connected. For example, the selection signal lines in each selection signal line group 500 are electrically connected.

[0112] In some examples, such as Figures 1A to 2 As shown, at least one selection signal line group 500 includes multiple first selection signal lines 510, which overlap with a second portion 222 of the active semiconductor layer 220 of transistor 210. For example, the gate of one of the transistors 210 is electrically connected to the first selection signal line 510.

[0113] In some examples, such as Figures 1A to 2 As shown, the first selection signal line 510 and the gate line 400 are located on the same layer. For example, both the first selection signal line 510 and the gate line 400 are located on the side of the active semiconductor layer 220 of the transistor 210 away from the substrate 100.

[0114] In some examples, such as Figures 1A to 2As shown, the extension direction of the first selection signal line 510 is the same as the extension direction of the gate line 400. For example, the first selection signal line 510 extends along the X direction. For example, both the first selection signal line 510 and the gate line 400 are located in the interval between two adjacent rows of sub-pixels 200. For example, the number of gate lines 400 corresponding to each display partition 110 and the number of corresponding second selection signal lines 510 can be the same. For example, along the Y direction, the gate lines 400 and the first selection signal lines 510 are alternately arranged.

[0115] For example, the lengths of the multiple first selection signal lines 510 corresponding to each display partition 110 are all equal, but not limited to this; at least some of the first selection signal lines corresponding to each display partition may have different lengths. For example, the lengths of the first selection signal lines 510 corresponding to different display partitions 110 may be the same or different, depending on product requirements.

[0116] In some examples, such as Figures 1A to 2 As shown, two adjacent display zones 110 arranged along the first direction include a first display zone 111 and a second display zone 112. One of the multiple first selection signal lines 510 provided in the first display zone 111 and one of the multiple first selection signal lines 510 provided in the second display zone 112 are located on the same straight line and are spaced apart. For example, a first selection signal line 510 corresponding to the first display zone 111 and a first selection signal line 510 corresponding to the second display zone 112 located on the same straight line can be two insulated parts of a single selection signal line that are broken.

[0117] For example, both the first display partition 111 and the second display partition 112 include A rows of sub-pixels 200. In each display partition 110, the second portion of the active semiconductor layer of the transistor 210 of each row of sub-pixels 200 overlaps with the same first selection signal line 510. The first display partition 111 and the second display partition 112 each correspond to A first selection signal lines 510, and the A'th first selection signal line 510 corresponding to the first display partition 111 and the A'th first selection signal line 510 corresponding to the second display partition 112 are located on the same straight line and are spaced apart. Here, A is a positive integer greater than or equal to 1, and A' is a positive integer greater than or equal to 1 and less than or equal to A.

[0118] In some examples, such as Figures 1A to 2 As shown, the multiple selection signal lines in at least one selection signal line group 500 also include at least one second selection signal line 520, which is located on a different layer from the first selection signal line 510 and is electrically connected to the first selection signal line 510.

[0119] For example, such as Figure 1BAs shown, the second selection area signal line 520 can be located between the first selection area signal line 510 and the substrate 100. For example, Figure 2 The illustration shows one second selection signal line 520 corresponding to each display partition 110, but is not limited to this; each display partition 110 may correspond to multiple second selection signal lines 520. For example, multiple first selection signal lines 510 corresponding to each display partition 110 may be electrically connected to the same second selection signal line 520 to achieve electrical connection of all selection signal lines corresponding to each display partition 110, thereby enabling each display partition to be controlled by the same signal.

[0120] For example, such as Figures 1A to 2 As shown, the lengths of the signal lines 510 for different first selection zones corresponding to different display partitions 110 can be the same or different.

[0121] In some examples, such as Figures 1A to 2 As shown, the extension direction of the first selection signal line 510 is the same as the extension direction of the gate line 400, and the extension direction of the second selection signal line 520 intersects the extension direction of the first selection signal line 510. At least one second selection signal line 520 passes through multiple display partitions 110. For example, a second selection signal line 520 electrically connected to a sub-pixel of display partition 111 passes through multiple display partitions arranged along the Y direction.

[0122] For example, such as Figures 1A to 2 As shown, the extension direction of the second selection signal line 520 is the same as the extension direction of the data line 300, and at least one second selection signal line 520 passes through at least a portion of the display partitions 110 arranged along the second direction.

[0123] In some examples, such as Figure 1A and Figure 1B As shown, the second selection area signal line 520 and data line 300 are located on different layers.

[0124] In some examples, such as Figure 1A and Figure 1B As shown, the extension direction of the second selection signal line 520 is the same as the extension direction of at least a portion of the data line 300, and along a direction perpendicular to the substrate 100, the second selection signal line 520 overlaps with the data line 300. Of course, the embodiments of this disclosure are not limited to the overlap of the second selection signal line 520 and the data line 300; the second selection signal line 520 and the data line 300 may also not overlap.

[0125] For example, such as Figure 1A and Figure 1BAs shown, the second selection signal line 520 can be located between the data line 300 and the substrate 100. For example, the orthographic projection of the second selection signal line 520 on the substrate 100 can overlap with the orthographic projection of the data line 300 on the substrate 100. For example, the orthographic projection of the data line 300 on the substrate 100 can be located within the orthographic projection of the second selection signal line 520 on the substrate 100.

[0126] For example, such as Figure 1B As shown, the active semiconductor layer 220 is located on the side of the second selection area signal line 520 away from the substrate 100, and an insulating layer 102 is disposed between the active semiconductor layer 220 and the second selection area signal line 520; the first selection area signal line 510 is located on the side of the active semiconductor layer 220 away from the substrate 100, and an insulating layer 103 is disposed between the first selection area signal line 510 and the active semiconductor layer 220; the data line 300 is located on the side of the first selection area signal line 510 away from the substrate 100, and an insulating layer 104 is disposed between the data line 300 and the first selection area signal line 510. For example, as... Figure 1B As shown, the first selection signal line 510 is electrically connected to the second selection signal line 520 through a via 101 located in insulating layers 102 and 103. For example, insulating layer 102 can be a buffer layer, insulating layer 103 can be a gate insulating layer, and insulating layer 104 can be an interlayer insulating layer.

[0127] Figure 1C For along Figure 1A A schematic diagram of the local cross-section structure intercepted by line DD'. Figure 1A The location of a light-shielding layer 600 is schematically shown. The display panel provided in this embodiment includes a plurality of light-shielding layers 600, at least a portion of the light-shielding layer 600 overlapping with a second portion 222 of the active semiconductor layer 220.

[0128] In some examples, such as Figure 1C As shown, the display panel also includes a light-shielding layer 600 located between the data line 300 and the substrate 100, and the second selection area signal line 520 is disposed on the same layer as the light-shielding layer 600. By disposing the second selection area signal line and the light-shielding layer on the same layer, this embodiment of the present disclosure allows the same material to be used to form the second selection area signal line and the light-shielding layer in the same patterning process, saving process steps.

[0129] For example, such as Figure 1C As shown, the light-shielding layer 600 overlaps with the active semiconductor layer 220 in a direction perpendicular to the substrate 100. For example, the light-shielding layer 600 overlaps with the first selected area signal line 510 in a direction perpendicular to the substrate 100.

[0130] For example, such as Figure 1AAs shown, the active semiconductor layer 220 of transistor 210 can be U-shaped. The U-shaped active semiconductor layer 220 includes two portions extending along the Y direction and a connection portion connecting these two portions. For example, a portion of the U-shaped active semiconductor layer 220 extending along the Y direction overlaps with the gate line 400 and the first selection signal line 510, while the other portion extending along the Y direction overlaps with both the second selection signal line 520 and the data line 300. For example, one end of the U-shaped active semiconductor layer 220 extending along the Y direction and overlapping with the gate line 400 is electrically connected to the pixel electrode, and one end of the U-shaped active semiconductor layer 220 extending along the Y direction and overlapping with the data line 300 is electrically connected to the data line 300.

[0131] For example, such as Figure 1A As shown, the second selection area signal line 520 includes a protrusion 521. Along a direction perpendicular to the substrate 100, the protrusion 521 overlaps with the first selection area signal line 510, and the protrusion 521 is electrically connected to the first selection area signal line 510 through a via 101. For example, a protrusion 521 may be provided between the active semiconductor layers 220 of adjacent transistors 210 arranged along the X direction. For example, along a direction perpendicular to the substrate 100, the active semiconductor layer 220 and the protrusion 521 may not overlap. For example, the orthographic projections of the active semiconductor layer 220 of the transistor 210 and the protrusion 521 on a straight line extending along the Y direction may overlap.

[0132] For example, such as Figure 1A As shown, a column of sub-pixels 200 is set between adjacent data lines 300, and a row of sub-pixels 200 is set between adjacent gate lines 400.

[0133] Figure 4 This is a schematic diagram illustrating the electrical connection relationship between sub-pixels and signal lines in a display panel without a selection signal line group, according to another example of an embodiment of this disclosure. Figure 5 for Figure 4 The diagram shown illustrates the distribution relationship between sub-pixels and signal lines after setting up a selection signal line group on the display panel in one example. Figure 6 for Figure 5 The diagram shows the overlapping relationship between some sub-pixels, grid lines, and selection signal line groups in the display panel. Figure 7 For along Figure 6 A schematic diagram of the local cross-sectional structure intercepted by line CC'.

[0134] Figure 4 The display panel shown in the example is... Figure 3 The differences in the display panels shown in the examples are the different electrical connections between sub-pixels and signal lines, the different positional relationships of the signal lines in the second selection area, and the different positional relationships between the signal lines in the first selection area and the gate lines. Figure 6The schematic diagram shows that transistor 210 includes two transistors, but is not limited thereto; the transistor may also be... Figure 1A The four transistors shown, or other numbers of transistors, such as three transistors or more transistors.

[0135] In some examples, such as Figures 4 to 7 As shown, at least some of the data lines 300 are electrically connected to two sub-pixels 200 arranged along a first direction. For example, the same data line 300 is electrically connected to two columns of sub-pixels 200, one column of sub-pixels 200 including a plurality of sub-pixels 200 arranged along the Y direction. For example, the two columns of sub-pixels 200 electrically connected to the same data line 300 may be located on opposite sides of the data line 300.

[0136] In some examples, such as Figures 4 to 7 As shown, the multiple gate lines 400 include a first gate line 410 and a second gate line 420 arranged alternately along a second direction. A gate line pair 4120 formed by the first gate line 410 and the second gate line 420 is provided between two adjacent sub-pixels 200 arranged along the second direction. One of the two sub-pixels 200 arranged along the first direction and electrically connected to the same data line 300 is electrically connected to the first gate line 410, and the other is electrically connected to the second gate line 420. Figure 4 The display panel shown employs dual-gate technology, which halves the number of data lines and doubles the number of gate lines. Specifically, it halves the number of source driver ICs connected to the data lines and doubles the number of gate driver ICs connected to the gate lines. Since the unit price of gate driver ICs is lower than that of source driver ICs, this results in cost reduction.

[0137] The display panel provided in this disclosure uses a pixel architecture based on dual-gate technology, which is not limited to... Figure 4 The pixel architecture shown includes multiple data lines, such as a first data line and a second data line alternately arranged along a first direction. Two rows of sub-pixels are arranged along a second direction between the first and second data lines. The first and second data lines are configured to transmit voltages of different polarities, and different sub-pixels connected to the same data line are connected to different gate lines. Two adjacent sub-pixels arranged along the first direction are respectively connected to the first data line and the second data line. A row of sub-pixels arranged along the second direction is entirely connected to the first data line, or a row of sub-pixels arranged along the second direction is entirely connected to the second data line. Alternatively, multiple data lines may include a first data line and a second data line alternately arranged along the first direction, two adjacent sub-pixels arranged along the first direction are respectively connected to the first data line and the second data line, and two adjacent sub-pixels arranged along the second direction are respectively connected to the first data line and the second data line.

[0138] For example, Figure 6 In the example shown, the overlap between the active semiconductor layer 220 of the transistor and the gate line 400 and the first selection signal line 510 can be compared with... Figure 1A The overlapping relationships shown are the same, and will not be repeated here. Figures 4 to 7 The display panel 110 in the example shown can have Figure 2 The partitions shown have the same characteristics, which will not be elaborated further here.

[0139] For example, such as Figures 4 to 7 As shown, the first selection area signal line 510 and the second selection area signal line 520 are located on different layers. The first selection area signal line 510 is electrically connected to the second selection area signal line 520 through a via 101 in the insulating layer between the first selection area signal line 510 and the second selection area signal line 520.

[0140] In some examples, such as Figure 6 As shown, the second selection area signal line 520 and the data line 300 are located on the same layer. For example, the data line 300 and the second selection area signal line 520 are arranged alternately along the X direction.

[0141] In some examples, such as Figure 5 and Figure 6 As shown, the extension direction of the second selection area signal line 520 is the same as the extension direction of the data line 300. The second selection area signal line 520 is located between two adjacent sub-pixels 200 arranged along the first direction, and the two adjacent sub-pixels 200 are electrically connected to different data lines 300 respectively.

[0142] For example, such as Figure 5 and Figure 6 As shown, two columns of sub-pixels 200 are arranged between two adjacent data lines 300, two columns of sub-pixels 200 are arranged between two adjacent second selection area signal lines 520, and a column of sub-pixels 200 is arranged between adjacent data lines 300 and second selection area signal lines 520.

[0143] In the display panel provided in this embodiment, by setting a second selection signal line between two adjacent columns of sub-pixels without data lines, zoned display control can be achieved without affecting the aperture ratio of the sub-pixels. Furthermore, the second selection signal line, set on the same layer as the data lines, can be made of the same material and formed in the same patterning process, thus not increasing the manufacturing process of the display panel.

[0144] In some examples, such as Figure 5 and Figure 6 As shown, the multiple first selection area signal lines 510 include multiple first selection area signal line pairs 5100, and the first selection area signal line pairs 5100 are arranged between two adjacent sub-pixels 200 arranged along the second direction.

[0145] In some examples, such as Figure 5 and Figure 6 As shown, a first selection area signal line pair 5100 is provided between each gate line pair 4120. Of course, the embodiments disclosed herein are not limited to this, and a gate line pair can also be provided between a first selection area signal line pair.

[0146] For example, such as Figure 7 As shown, the active semiconductor layer 220 is located between the first selection signal line 510 and the substrate 100. The data line 300 is located on the side of the first selection signal line 510 away from the substrate 100. The second selection signal line 520 is located on the side of the first selection signal line 510 away from the substrate 100. The second selection signal line 520 is electrically connected to the first selection signal line 510 through a via 101 located in the insulating layer 104. The gate line 400 and the first selection signal line 510 are both located on the insulating layer 103. The data line 300 and the second selection signal line 520 are both located on the insulating layer 104.

[0147] For example, such as Figure 5 and Figure 6 As shown, when the first selection area signal line 510 is connected to the turn-on voltage, the sub-pixel 200 in the display area is controlled by the horizontal scan signal on the grid line 400; when the first selection area signal line 510 is connected to the turn-off voltage, the sub-pixel 200 is not controlled by the horizontal scan signal on the grid line 400.

[0148] Figure 8 for Figure 4 The diagram shown illustrates the distribution relationship between sub-pixels and signal lines after setting the selection area signal line group in another example. Figure 9 for Figure 8 The diagram shown illustrates the overlapping relationship between some sub-pixels and the grid lines and selection signal line groups in an example of the display panel. Figure 10 for Figure 8 A schematic diagram showing the overlapping relationship between some sub-pixels and the grid lines and selection signal line groups in another example of the display panel shown. Figure 8 The electrical connection method between the first selection area signal line 510 and the second selection area signal line 520 in the example shown, and the positional relationship between the second selection area signal line 520 and the data line 300, can be compared with... Figure 6 and Figure 7 The corresponding features in the examples shown are the same, and will not be repeated here.

[0149] In some examples, such as Figure 8 and Figure 9As shown, a first selection area signal line 510 is provided between each gate line pair 4120, and the second part 222 of the active semiconductor layer 220 of the pixel circuit transistor, which is electrically connected to the first gate line 410 and the second gate line 420 in the same gate line pair 4120, overlaps with the same first selection area signal line 510 located between the same gate line pairs 4120.

[0150] For example, such as Figure 8 and Figure 9 As shown, the active semiconductor layer 220 of the transistors of two sub-pixels 200 located in adjacent rows of sub-pixels, which are electrically connected to the same data line 300, is configured to overlap with the same first selection area signal line 510. This allows for partitioned display using a smaller number of first selection area signal lines, which is beneficial for improving the aperture ratio of the sub-pixels.

[0151] For example, Figure 10 The display panel shown is Figure 9 The difference in the display panels shown lies in the pattern of the active semiconductor layer 220 of the transistors. Figure 9 The shape of the active semiconductor layer 220 of the transistor shown can be I-shaped, such as at least one sub-pixel including two transistors, such as the active semiconductor layer 220 including only a first part 221 overlapping with the gate line 400 and a second part 222 overlapping with the first selection area signal line 510. Figure 10 The active semiconductor layer 220 of the transistor shown can be U-shaped, such as at least one sub-pixel including four transistors, such as the active semiconductor layer 220 including two first portions 221 overlapping with the gate line 400 and two second portions 222 overlapping with the first selection area signal line 510.

[0152] For example, such as Figure 10 As shown, two first selection signal lines 510 corresponding to adjacent display partitions 110 arranged along the X direction and located on the same straight line extending along the X direction are disconnected, i.e., spaced apart. For example, a second selection signal line 520 can be provided at the space between the two first selection signal lines 510 corresponding to adjacent display partitions 110. For example, in the direction perpendicular to the substrate, at least one of the two first selection signal lines 510 corresponding to adjacent display partitions 110 does not overlap with the second selection signal line 520 provided at the space between them. However, the embodiments of this disclosure are not limited to this, and at least one of the two first selection signal lines can overlap with the second selection signal line provided at the space between them.

[0153] The above embodiments schematically show that the gate line, data line and first selection area signal line are all straight lines, but are not limited thereto. At least one of the gate line, data line and first selection area signal line can be a broken line.

[0154] Figure 11 and Figure 12 This is a schematic diagram of a display panel with partial subpixels, signal lines, and selection signal line groups provided according to different embodiments of this disclosure. Figure 11 and Figure 12 The distribution of sub-pixels in the example shown is... Figure 9 and Figure 1A The distribution of the sub-pixels shown is different. Figure 11 and Figure 12 The positional relationship between the first selection area signal line 510 and the grid line pair in the display panel shown can be compared with... Figure 9 The corresponding features shown are the same. Figure 11 The electrical connection between the first selection area signal line 510 and the second selection area signal line 520 in the example shown can be compared with... Figure 1A The corresponding features are the same in the examples shown. Figure 12 The electrical connection between the first selection area signal line 510 and the second selection area signal line 520, and the positional relationship between the second selection area signal line 520 and the data line 300 in the example shown can be compared with... Figure 9 The corresponding features in the examples shown are the same. Figure 11 and Figure 12 The sub-pixel shown includes two transistors, which will not be described further here.

[0155] For example, such as Figure 11 As shown, along a direction perpendicular to the substrate 100, a portion of the second selection signal line 520 overlaps with a portion of the data line 300. For example, the portion of the second selection signal line 520 located between adjacent sub-pixels 200 arranged along the X direction overlaps with the portion of the data line 300 located between adjacent sub-pixels 200 arranged along the X direction.

[0156] For example, such as Figure 11 As shown, the second selection area signal line 520 is disposed on the same layer as the light-shielding layer 600. For example, the light-shielding layer 600 overlaps with the data line 300 in a direction perpendicular to the substrate. For example, the light-shielding layer 600 overlaps with at least one of the first selection area signal line 510 and the active semiconductor layer 220 in a direction perpendicular to the substrate.

[0157] For example, such as Figure 11 As shown, adjacent rows of sub-pixels 200 are staggered along the X direction. For example, adjacent rows of sub-pixels 200 are staggered by half the pixel pitch along the X direction. Figure 11 The distribution of sub-pixels in the display panel shown is beneficial for improving the aperture ratio.

[0158] For example, such as Figure 11As shown, the line connecting the centers of the light-emitting areas of two sub-pixels 200 located in two adjacent sub-pixel rows, which are connected to the same data line 300, intersects the Y direction. For example, the data line 300 includes a broken line segment, where the portion of the data line 300 located between adjacent sub-pixels 200 arranged along the X direction extends along the Y direction, and the extension direction of the portion of the data line 300 located between two adjacent sub-pixel rows intersects the Y direction. For example, the second selection area signal line 520 includes a broken line segment, and the second selection area signal line 520 located between two adjacent sub-pixel rows does not overlap with the data line 300.

[0159] For example, Figure 12 The shape of the pixel electrode 202 of sub-pixel 200 in the example shown is different from that of the pixel electrode in the example above. In this example, the pixel electrode 202 of sub-pixel 200 includes two rectangles and a connecting structure connecting the two rectangles. For example, adjacent rows of sub-pixels 200 are staggered along the X direction. For example, adjacent rows of sub-pixels 200 are staggered by half the pixel pitch along the X direction. Figure 12 The distribution of subpixels in the display panel shown is beneficial for improving the aperture ratio. For example, both data line 300 and the second selection signal line 520 include broken line segments.

[0160] Figure 13 This is a partial planar structure schematic diagram of a display panel provided according to another example of an embodiment of the present disclosure. Figure 14 For along Figure 13 The diagram shows a partial cross-sectional structure cut by line EE'. Figure 15 For along Figure 13 The diagram shows a partial cross-sectional structure cut by line FF'. Figures 1A to 12 The transistors in the display panel of any of the examples shown can be either top-gate transistors or bottom-gate transistors. Figure 13 The transistors in the display panel shown are transistors that include a top gate and a bottom gate. The overlap relationship between the transistors and the signal lines of the first selection area in this example is different from the example above.

[0161] Figure 13 The arrangement of the gate lines and data lines adopts Figure 1A The arrangement of the grid lines and data lines shown in this example, as well as their electrical connection with the sub-pixels, is used as an example, but it is not limited to this. The display panel shown in this example can also adopt... Figure 6 or Figure 9 The arrangement of the gate lines and data lines, and their electrical connection with the sub-pixels, are shown. Figure 13 The data lines, gate lines, and electrical connections between the gate lines, data lines, and transistors in the display panel shown can be the same as the corresponding features in the display panel shown in any of the examples above. Figure 13The display zones in the display panel shown, and the correspondence between the display zones and the selection signal line groups, can be the same as the corresponding features in the display panel shown in any of the above examples.

[0162] In some examples, such as Figures 13 to 15 As shown, the first selection signal line 510 and the gate line 400 are located on different layers. For example, the first selection signal line 510 is located between the gate line 400 and the substrate 100. For example, the gate line 400 is located on the side of the active semiconductor layer 220 away from the substrate 100, and the first selection signal line 510 is located between the active semiconductor layer 220 and the substrate 100.

[0163] In some examples, such as Figures 13 to 15 As shown, the first sub-selection signal line 510 includes at least one first sub-selection signal line 511 and multiple second sub-selection signal lines 512 that are electrically connected to each other. The second sub-selection signal lines 512 overlap with the second portion 222 of the active semiconductor layer 220. The extension direction of the second sub-selection signal lines 512 intersects the extension direction of the gate line 400. The extension direction of the first sub-selection signal lines 511 intersects the extension direction of the second sub-selection signal lines 512. The second sub-selection signal lines 512 corresponding to each display partition 110 are insulated from the second sub-selection signal lines 512 corresponding to other display partitions 110.

[0164] This example uses a transistor with a top gate and a bottom gate, with one of the top gate and bottom gate overlapping with the gate line, and the other of the top gate and bottom gate overlapping with the first selected area signal line, which helps to save layout space.

[0165] For example, Figures 13 to 15 The diagram schematically shows that the top gate of the transistor is electrically connected to the gate line 400, and the bottom gate of the transistor is electrically connected to the first selection area signal line 510. The overlapping portion 220-1 with the gate line 400 is the intrinsic region, and the transistor is turned on by the turn-on voltage input to the gate line 400. The active semiconductor layer 220 also includes a heavily doped (such as N-doped or P-doped) region 220-2, which is a conductive region. The overlapping portion of the active semiconductor layer 220 with the first selection area signal line 510 is the intrinsic region, and the transistor is turned on by the turn-on voltage input to the first selection area signal line 510, thereby cooperating with the normal read and write of the row scan signal transmitted by the gate line 400.

[0166] For example, Figure 14 The top-gate structure of a transistor is schematically shown. Figure 15 The schematic diagram illustrates the bottom gate structure of a transistor. Figure 15The bottom gate structure shown includes two examples. For example, the active semiconductor layer 220 corresponding to the bottom gate is an intrinsic region, and whether the active semiconductor layer 220 in the intrinsic region is conductive is controlled by whether the bottom gate voltage is effective. For example, the part of the active semiconductor layer 220 corresponding to the bottom gate (i.e., the second part overlapping with the first selected area signal line 510) that is electrically connected to the data line 300 through the via 105 is doped using a heavily doped method. The area of ​​the active semiconductor layer 220 corresponding to the bottom gate other than the part overlapping with the via 105 is an intrinsic region, and whether the active semiconductor layer 220 in the intrinsic region is conductive is controlled by whether the bottom gate voltage is effective.

[0167] In some examples, such as Figures 13 to 15 As shown, the first sub-selection area signal line 511 and the second sub-selection area signal line 512 are an integrated structure. Of course, the embodiments disclosed herein are not limited to this; the first sub-selection area signal line and the second sub-selection area signal line may also be two independent structures electrically connected to each other.

[0168] For example, such as Figure 13 As shown, the number of first sub-selection signal lines 511 in the selection signal line group corresponding to the same display partition 110 is less than the number of second sub-selection signal lines 512. For example, the number of second sub-selection signal lines 512 is the same as the number of sub-pixel columns extending along the Y direction. For example, in the selection signal lines corresponding to each display partition 110, the first sub-selection signal lines 511 are electrically connected to all second sub-selection signal lines 512. Of course, the embodiments of this disclosure are not limited to this, and the number of first sub-selection signal lines can be set according to actual needs.

[0169] For example, such as Figure 13 As shown, the first sub-selection area signal lines 511 corresponding to two adjacent display zones 110 arranged along the X direction are insulated. For example, the two first sub-selection area signal lines 511 can be located on the same straight line and are spaced apart from each other.

[0170] For example, such as Figure 13 As shown, the second sub-selection area signal lines 512 corresponding to two adjacent display zones 110 arranged along the Y direction are insulated. For example, the second sub-selection area signal lines 512 corresponding to two adjacent display zones 110 can be located on the same straight line and are spaced apart from each other.

[0171] For example, such as Figure 13 As shown, each second selection area signal line 520 is electrically connected to only one second sub-selection area signal line 512 corresponding to one display zone 110. For example, a second sub-selection area signal line 512 corresponding to one display zone 110 can be electrically connected to at least one second selection area signal line 520.

[0172] For example, such as Figures 13 to 15As shown, the extension direction of the first sub-selection signal line 511 can be the same as the extension direction of the gate line 400, and the extension direction of the second sub-selection signal line 512 can be the same as the extension direction of the data line 300. For example, the second sub-selection signal line 512 overlaps with the data line 300 along a direction perpendicular to the substrate 100. For example, the second sub-selection signal line 512 is located between the data line 300 and the substrate 100.

[0173] For example, such as Figures 13 to 15 As shown, insulating layers 102 and 1031 are disposed between the active semiconductor layer 220 and the substrate 100, and insulating layer 1032 is disposed between the gate line 300 and the active semiconductor layer 220. For example, insulating layers 1031 and 1032 are both gate insulating layers, such as the first gate insulating layer and the second gate insulating layer, respectively. Insulating layer 102 is disposed between the active semiconductor layer 220 and the second selection signal line 520, insulating layer 1031 is disposed between the first selection signal line 510 and the active semiconductor layer 220, and insulating layers 1031 and 104 are disposed between the active semiconductor layer 220 and the data line 300.

[0174] In some examples, such as Figures 13 to 15 As shown, the multiple selection signal lines in at least one selection signal line group 500 also include at least one second selection signal line 520. The second selection signal line 520 is located on a different layer from the first selection signal line 510, and the second selection signal line 520 is electrically connected to the first selection signal line 510. The second selection signal line 520 passes through at least one display partition.

[0175] In some examples, the second selection area signal line 520 and the data line 300 are located on different layers.

[0176] In this example, the second selection area signal line 520 can be connected to... Figure 1A The second selection signal line 520 in the display panel shown has the same characteristics, and will not be described again here.

[0177] In some examples, such as Figures 13 to 15 As shown, at least one of the second sub-selection signal line 512 and the second selection signal line 520 overlaps with the data line 300 along a direction perpendicular to the substrate 100. For example, both the second sub-selection signal line 512 and the second selection signal line 520 overlap with the data line 300, and the second sub-selection signal line 512 is located between the second selection signal line 520 and the data line 300. For example, the second sub-selection signal line 512 is electrically connected to the second selection signal line 520 through a via 101 in the insulating layer 102.

[0178] For example, having Figure 13 The display panel with the transistors shown in the top and bottom gates can be used Figures 5 to 12The dual-gate design is shown. For example, at least some of the data lines 300 are electrically connected to two sub-pixels 200 arranged along a first direction; multiple gate lines 400 include alternating first gate lines 410 and second gate lines 420 arranged along a second direction, and a gate pair formed by the first gate line 410 and the second gate line 420 is provided between two adjacent sub-pixels 200 arranged along the second direction; one of the two sub-pixels 200 arranged along the first direction and connected to the same data line 300 is electrically connected to the first gate line 410, and the other is electrically connected to the second gate line 420; the second selection signal line 520 is located on the same layer as the data lines 300. The use of top-gate and bottom-gate transistors in conjunction with the dual-gate design is beneficial for increasing the aperture ratio of sub-pixels while saving layout space.

[0179] For example, having Figure 13 In the display panel with transistors in the top and bottom gates shown, when the second selection area signal line 520 is arranged on the same layer as the data line 300, the second selection area signal line 520 can be electrically connected to the first sub-selection area signal line 511 to achieve electrical connection with the first selection area signal line 510.

[0180] For example, having Figure 13 In the display panel with transistors in the top and bottom gates shown, when the second selection area signal line 520 and data line 300 are arranged on the same layer, the positional relationship between the second selection area signal line 520, data line 300, and sub-pixel 200 can be... Figure 5 The corresponding features in the display panel are the same, such as the extension direction of the second selection signal line 520 being the same as the extension direction of at least a portion of the data line 300, the second selection signal line 520 being located between two adjacent sub-pixels 200 arranged along the first direction, and the two adjacent sub-pixels 200 being electrically connected to different data lines 300 respectively.

[0181] For example, having Figure 13 In the display panel with transistors of the top and bottom gates shown, when the second selection area signal line 520 and the data line 300 are arranged on the same layer, only the second sub-selection area signal line can be arranged in the first selection area signal line. The second sub-selection area signal line is located between the active semiconductor layer and the substrate, extends along the X direction and does not overlap with the gate line, and is electrically connected to the second selection area signal line.

[0182] For example, such as Figures 1A to 15 As shown, the active semiconductor layer can be electrically connected to the pixel electrode through a connection portion (the square overlapping the pixel electrode in the figure) disposed on the same layer as the data line 300. The square at the overlap of the active semiconductor layer and the data line in the figure schematically illustrates the electrical connection between the two, and this square can be a protrusion of the data line.

[0183] have Figure 13In the display panel showing the transistors of the top and bottom gates, the first selection area signal line is not limited to... Figure 13 The diagram shows a first sub-selection area signal line and a second sub-selection area signal line with different extension directions. The first selection area signal line may only include signal lines extending along the X direction. The first selection area signal line may overlap with the gate line or be staggered from the gate line, and can be designed according to product requirements.

[0184] Figure 16 This is a partial planar structure schematic diagram of a display panel provided according to another example of an embodiment of the present disclosure. Figure 17 For along Figure 16 A schematic diagram of the local cross-sectional structure intercepted by line GG'. Figure 16 and Figure 17 The display panel shown is Figures 1A to 15 The difference in the display panel shown is the structure of the grid lines. In this example, the structure other than the grid lines can be the same as the structure in any of the above examples, and will not be described again here.

[0185] In some examples, such as Figure 16 and Figure 17 As shown, at least one gate line 400 includes two sub-gate lines 401 and at least one connecting portion 402 connecting the two sub-gate lines 401. The two sub-gate lines 401 are arranged in the same layer and parallel to each other, and the two sub-gate lines 401 and the connecting portion 402 are located in different layers. The two sub-gate lines 401 included in each gate line 400 are electrically connected through the connecting portion 402. Along a direction perpendicular to the substrate 100, one of the two sub-gate lines 401 overlaps with the first portion 221 of the active semiconductor layer 220. By setting the gate line to include sub-gate lines that overlap with the active semiconductor layer and sub-gate lines that do not overlap with the active semiconductor layer, and the two sub-gate lines are electrically connected, it is beneficial to reduce the resistance of the gate line. In addition, by setting the sub-gate lines and the connecting portion in different layers, compared with setting the sub-gate lines that are electrically connected to each other in the same layer, it is possible to prevent the gate line layer from forming a closed loop, which would obstruct the flow of wet etching solution, resulting in residues remaining in the closed loop and unable to flow out, as well as problems such as uneven etching and tailing of the current-voltage curve.

[0186] For example, such as Figure 16 and Figure 17 As shown, the connection portion 402 may be located between the gate line 400 and the substrate 100. For example, the connection portion 402 may be located in the same layer as the aforementioned light-shielding layer. For example, at least a portion of the connection portion 402 may overlap with the data line 300 in a direction perpendicular to the substrate 100.

[0187] For example, such as Figure 16 and Figure 17As shown, the linewidths of the two sub-gate lines 401 can be the same or different. For example, the linewidth of the sub-gate line 401 that overlaps with the active semiconductor layer 220 can be greater than the linewidth of the sub-gate line 401 that does not overlap with the active semiconductor layer 220, so as to reduce the gate line resistance and save layout space.

[0188] For example, such as Figure 16 and Figure 17 As shown, the connecting portion 402 does not overlap with the active semiconductor layer 220 in the direction perpendicular to the substrate 100.

[0189] For example, such as Figure 17 As shown, an insulating layer 102 and an insulating layer 103 are provided between the sub-grid line 401 and the connecting part 402. The sub-grid line 401 is electrically connected to the connecting part 402 through a through hole 106 that passes through the insulating layer 102 and the insulating layer 103.

[0190] For example, a connection portion 402 is provided between adjacent active semiconductor layers 220 arranged along the X direction. For example, all connection portions 402 provided between adjacent sub-gate lines 401 can be electrically connected to the sub-gate line 401. Embodiments of this disclosure are not limited to providing a connection portion between the active semiconductor layers of adjacent sub-pixels; connections may also be provided between the active semiconductor layers of only some adjacent sub-pixels. For example, when the second selection area signal line and the connection portion are arranged on the same layer, the positions of the second selection area signal line and the connection portion can be set as needed.

[0191] For example, in this example, when the second selection area signal line and the connecting portion 402 are arranged on the same layer, the second selection area signal line and the connecting portion 402 are insulated from each other. For example, the connecting portion 402 can be arranged at a position where no second selection area signal line is arranged between adjacent sub-pixels.

[0192] The embodiments disclosed herein are not limited to Figure 16 and Figure 17 The grid line 400 shown includes two sub-grid lines electrically connected to each other, and the first selection signal line may also include two sub-grid lines electrically connected to each other to reduce the resistance of the selection signal line group.

[0193] Figure 18 This is a partial planar structure schematic diagram of a display panel provided according to an example embodiment of the present disclosure. Figure 18 The display panel shown includes Figure 2 The display partitions shown are as follows. Figure 18 The arrangement of subpixels, the electrical connections between subpixels and data lines and gate lines, and the characteristics of the selection signal line group in the display panel shown can be compared with... Figures 1A to 17 The display panel in any of the examples shown is the same, and will not be described again here.

[0194] In some examples, such as Figure 18As shown, the display panel also includes a plurality of gate driver groups 710 arranged along a second direction. The gate driver groups 710 are electrically connected to gate lines 400, and at least a portion of each gate driver group 710 is configured to be individually input with a frame start signal. A plurality of display partitions 110 include a plurality of display partition rows 1100 arranged along the second direction, each display partition row 1100 including display partitions 110 arranged along a first direction. The plurality of gate driver groups 710 are electrically connected to the plurality of display partition rows 1100 in a one-to-one correspondence. In the display panel provided in this embodiment, by individually inputting a frame start signal to at least a portion of the gate driver groups, the display partitions in at least a portion of the plurality of display partition rows can be refreshed at individual frequencies.

[0195] For example, at least one gate driver group 710 includes multiple gate driver units (gate-on-array integration, GOA), each gate driver unit being electrically connected to a row of sub-pixels 200 to output a row scan signal driving the sub-pixels 200 in that row. For example, the gate driver unit may include voltage-dependent CLK and CLKB signal pairs, an input signal, a gate-off signal (Vss), a reset signal, and an output signal for the current row. For example, the gate driver unit may include a 4T1C (including 4 TFTs and 1 capacitor C) unit structure, an 8T1C (including 8 TFTs and 1 capacitor C) unit structure, etc.

[0196] Figure 19 and Figure 20 for Figure 18 The diagram shows the electrical connection relationship between the gate driver group and the frame start signal line in different examples of the display panel shown.

[0197] In some examples, such as Figure 19 As shown, the display panel also includes multiple frame start signal lines 720, which are electrically connected to multiple gate driver groups 710 in a one-to-one correspondence. For example, different gate driver groups 710 are electrically connected to different frame start signal lines 720. In this example, electrically connecting different gate driver groups to different frame start signal lines allows each gate driver group to receive a frame start signal individually, enabling each display partition row to be controlled independently, unaffected by other display partition rows, thus achieving partition control of the display panel.

[0198] In some examples, such as Figure 20As shown, the display panel also includes at least one frame start signal line 720, and multiple control units 730 are disposed between the multiple gate driver groups 710 and the at least one frame start signal line 720. The multiple control units 730 are electrically connected to the multiple gate driver groups 710 in a one-to-one correspondence. For example, the number of control units 730 is the same as the number of gate driver groups 710, and each display partition row 1100 is electrically connected to one control unit 730.

[0199] In some examples, such as Figure 20 As shown, each frame start signal line 720 is electrically connected to at least two of the plurality of control units 730 to input a frame start signal to at least two of the plurality of control units 730. For example, the number of frame start signal lines 720 is less than the number of gate driver groups 710. For example, at least one frame start signal line 720 is configured to transmit a frame start signal to at least two gate driver groups 730.

[0200] This example demonstrates how setting up a control unit to reduce the number of frame start signal lines can help reduce the number of pins on the chip-on-film (COF) or IC. For example, in large-size display devices, reducing the number of frame start signal lines by setting up a control unit can reduce the number of COF pins; in small-size display devices, it can reduce the number of IC pins. Furthermore, the CLK signal of the GOA between partitions can still be shared, without affecting the number of CLK signal traces.

[0201] In some examples, such as Figure 20 As shown, at least one frame start signal line 720 includes only one frame start signal line, which is electrically connected to multiple control units 710 to input a frame start signal to each of the multiple control units 710 individually. This example uses a single frame start signal line to implement the input of a frame start signal to each of the multiple control units, which can greatly reduce the number of frame start signal lines.

[0202] Figure 21 for Figure 20 The circuit diagram shown is an example of the control unit's circuit structure. For example, as... Figure 21 As shown, the control unit 730 may include a 2T1C unit structure, which includes transistor T1, transistor T2, and capacitor C. For example, both transistor T1 and transistor T2 include a first electrode, a second electrode, and a gate, where one of the first and second electrodes is the source and the other is the drain.

[0203] For example, such as Figure 21As shown, the first terminal of transistor T2 is electrically connected to the frame start signal line 720 (STV_Bus line shown in the figure), the second terminal of transistor T2 is electrically connected to the corresponding gate driver group 710 (STV_Xzone shown in the figure), the gate of transistor T2 is electrically connected to the second terminal of transistor T1, the first terminal of transistor T1 is electrically connected to other signal lines (such as an externally provided enable signal Zone1_stv) or the last Goutput of the previous display zone row (Goutput_up in the figure), and the gate of transistor T1 is connected to the control signal VGH. For example, transistor T2 is used for the input of the STV bus signal, and transistor T1 is used to reduce leakage current and control STV writing. Capacitor C is used for charge storage and voltage bootstrapping to fully turn on transistor T2. For example, transistor T1 can share other VGH voltages on the display panel.

[0204] For example, such as Figure 20 and Figure 21 As shown, the gates of transistors T1 in all control units 730 can be connected to the same control signal VGH, and this VGH voltage can be shared with the VGH voltage in the GOA unit.

[0205] Figure 22 for Figure 20 The display panel shown includes Figure 21 A schematic diagram of the control unit shown. Figure 23 For including Figure 22 The display panel shows the connection relationship between the control unit and the frame start signal line.

[0206] For example, such as Figures 21 to 23 As shown, the gates of transistors T1 in all control units 730 can be connected to control signal lines 750 to receive control signals VGH. The same frame start signal line 720 can be electrically connected to multiple control units 730. The first terminal of transistor T1 in the first control unit 730 is connected to the enable signal Zone1_stv. The first terminal of transistor T1 in the second control unit 730 is electrically connected to the last Goutput of the first display partition line. The first terminal of transistor T1 in the third control unit 730 is electrically connected to the last Goutput of the second display partition line, and so on.

[0207] For example, such as Figure 23As shown, the display panel includes a frame start signal line 720 and multiple enable signal lines 740. Multiple control units 730 can be divided into multiple control unit groups, each control unit group including at least two control units 730. The first terminal of the transistor T1 of the first control unit 730 in each control unit group is connected to the enable signal line 740. The first terminals of the transistors T1 of the other control units 730 in each control unit group (excluding the first control unit 730) are connected to the last Goutput signal of the display partition corresponding to the previous control unit. For example, the number of control unit groups can be four, then the enable signal line 740 can include four enable signal lines 741, 742, 743, and 744. This embodiment schematically shows different control unit groups electrically connected to the same frame start signal line 720, but is not limited thereto; different control unit groups can also be electrically connected to different frame start signal lines.

[0208] For example, the multiple control units 730 can be divided into multiple control unit groups 700, each control unit group 700 includes at least one control unit 730, and each control unit group 700 is electrically connected to a frame start signal line 720, and different control unit groups 700 are electrically connected to different frame start signal lines 720.

[0209] For example, the display partition row corresponding to the control unit group 700 electrically connected to different frame start signal lines 720 can be controlled independently, without being affected by the display partition rows corresponding to other frame start signal lines 720.

[0210] Figure 24 for Figure 21 and Figure 22 The timing diagram corresponding to the circuit structure of the control unit shown is as follows. For example, as... Figures 21 to 24 As shown, the control signal VGH is always high, and the transistor T1 of each control unit 730 is always on. When the enable signal Zone1_stv is high, the transistor T2 is turned on. When the enable signal STV_Bus is high, the first gate driver group 710 transmits the signal STV_Xzone1 through the transistor T2 of the first control unit 730 which is in the on state. When the first terminal of the transistor T1 of the second control unit 730 receives the control signal Goutput_up, the transistor T2 of the second control unit 730 is turned on. When the enable signal STV_Bus is high again, the second gate driver group 710 receives the signal STV_Xzone2 through the transistor T2 of the second control unit 730 which is in the on state.

[0211] For example, the types of transistors T1 and T2 can be selected according to the control signal. They can be N-type metal-oxide-semiconductor (NMOS) transistors, but are not limited to this. They can also be PMOS (positive channel metal-oxide-semiconductor) transistors or complementary metal-oxide-semiconductor (NMOS) transistors. This disclosure does not limit them.

[0212] Figure 25 This is another circuit diagram of the control unit. Figure 26 for Figure 25 The timing diagram of the circuit structure shown. Figure 25 The circuit structure shown is similar to Figure 21 The difference in the circuit structure shown is that transistor T1 is replaced with transmission gate TG, and the control signal VGH of transistor T1 is replaced with CK_TG signal (such as clock signal). The CK_TG signal needs to match the timing of each partition. Transmission gate TG includes an NMOS transistor and a PMOS transistor.

[0213] For example, such as Figure 26 As shown, when the enable signal Zone1_stv is high, transistor T2 is turned on; when the enable signal STV_Bus is high, the first gate driver group 710 transmits the signal STV_Xzone1 through the transistor T2 of the first control unit 730, which is in the turned-on state; when the CK_TG signal is high, the transmission gate TG of the second control unit receives the control signal Goutput_up, the transistor T2 of the second control unit is turned on, and when the enable signal STV_Bus is high again, the second gate driver group 710 receives the signal STV_Xzone2 through the transistor T2 of the second control unit 730, which is in the turned-on state.

[0214] For example, when Goutput-up is high, STV_Bus is low, and when STV_Bus is high again, STV_Xzone2 is high. Therefore, STV_Xzone2 and Goutput-up can differ by 1H (the time required for one scan line, such as when the display device refreshes 60 frames per second, and each frame includes 1080 lines of image, 1H = 1 / 60 / 1080) or more H.

[0215] Figure 27 This is another circuit diagram of the control unit. Figure 28 for Figure 27The timing diagram of the circuit structure shown. Figure 27 The circuit structure shown is similar to Figure 21 The circuit structure shown differs in that it adds two transistors, T3 and T4, and a capacitor C2. The enable signal configured to be transmitted to the gate driver group is temporarily stored in capacitor C2, and only one initial signal is needed for each frame of STV_bus. Furthermore, using two transistors, T3 and T4, helps reduce leakage current and simplifies the complexity of the control signals.

[0216] For example, such as Figure 27 As shown, the frame start signal line is electrically connected to the gate of transistor T3 and the gate of transistor T4 to provide gate control signals for the two transistors. The first terminal of transistor T4 is connected to the VGH signal, the second terminal of transistor T4 is connected to the first terminal of transistor T3, the second terminal of transistor T3 is connected to one plate of capacitor C2, and the other plate of capacitor C2 is connected to the VGL signal; the second terminal of transistor T3 is connected to the first terminal of transistor T2.

[0217] For example, such as Figure 28 As shown, when the control signal VGH is constantly high, the transistor T1 of each control unit is normally on. When the enable signal on the frame start signal line is high, transistors T3 and T4 are on. The control signal VGH is stored in capacitor C2 as the STV_bus signal. When the enable signal Zone1_stv is high, transistor T2 is on. When the enable signal STV_Bus is high, the first gate driver group 710 transmits the signal STV_Xzone1 through the on-state transistor T2 of the first control unit 730. When the signal Goutput_up is high, the first terminal of the transistor T1 of the second control unit receives the control signal Goutput_up, the transistor T2 of the second control unit is on, and the enable signal STV_Bus stored in capacitor C2 is transmitted to the second gate driver group through the transistor T2 of the second control unit, so that the second gate driver group receives the signal STV_Xzone2.

[0218] For example, such as Figure 28 As shown, X-zone2-G1 refers to the Goutput1 signal output from the second gate driver group. Figure 27 The circuit structure shown stores the enable signal in capacitor C2 beforehand. When the Goutput-up signal is at a high level, STV-xone2 immediately outputs a high level.

[0219] For example, Figure 27 The transistor T1 shown can be replaced with Figure 25 The transmission gate TG is shown.

[0220] Figure 29 This is another circuit diagram of the control unit. Figure 30 for Figure 29 The timing diagram of the circuit structure shown. Figure 29 The circuit structure shown only includes Figure 21 The transistor T2 and capacitor C1 are shown.

[0221] For example, such as Figure 29 As shown, the circuit structure also includes transistors T5 and T6. The gate of transistor T5 is connected to the Ctr2 signal, the first terminal of transistor T5 is connected to the second terminal of transistor T6, the second terminal of transistor T5 is connected to the Goutput-own-end signal, the gate of transistor T6 is connected to the Ctr1 signal, the first terminal of transistor T6 is connected to the Goutput-up signal or the enable signal Zone1_stv, and the gate of transistor T2 is connected to the first terminal of transistor T5 and the second terminal of transistor T6. Goutput-up is the signal of the last line of the GOA output corresponding to the previous display zone, and Goutput-own-end is the signal of the last line of the GOA output corresponding to the current display zone.

[0222] The circuit structure provided in this example can adapt to changes in the refresh rate of certain display zones on the display panel, such as the viewing area (described later), where a high refresh rate can be achieved.

[0223] For example, such as Figure 30 As shown, Ctr1 and Ctr2 signals are not high at the same time, so transistors T5 and T6 are not turned on at the same time. When transistor T5 is on, transistor T6 is off; when transistor T5 is off, transistor T6 is on.

[0224] For example, when the Ctr1 signal is high, transistor T6 of the first control unit is turned on. The enable signal Zone1_stv received by the first terminal of transistor T6 is high, transistor T2 of the first control unit is turned on, and when the enable signal STV_Bus is high, the second terminal of transistor T2 of the first control unit transmits the signal STV_Xzone1 to the first gate driver group. When the Ctr1 signal is high, transistor T6 of the second control unit is turned on. The Goutput-up signal received by the first terminal of transistor T6 is high, transistor T2 of the second control unit is turned on, and the enable signal STV_Bus... When _Bus is high again, the second terminal of transistor T2 in the second control unit transmits the signal STV_Xzone2 to the second gate driver group. The X-zone2-G1 signal output by the second gate driver group to the first GOA is high, and then the normal scanning of the second row of display partitions is performed. After the second row of display partitions is scanned, the Ctr2 signal is high, the Goutput-own-end (Xzone2-Gend in the figure) is high, and STV_Bus is high again (that is, STV-Xzone2 outputs high again), and the second row of display partitions is scanned again.

[0225] For example, if a display partition wants to achieve a high refresh rate, the Ctr2 signal is set high before the Gend (such as Xzone2-Gend, Xzone3-Gend, etc.) signal is output.

[0226] For example, such as Figure 29 and Figure 30 As shown, if X-zone2 refreshes twice, when the last line of output is displayed during the first refresh, Ctr1 is set to low level and Ctr2 is set to high level. At this time, the gate of transistor T2 is at high level. Combined with the high level of the STV-bus signal, an enable signal can be given to the X-zone2 partition again, and it will refresh once more.

[0227] Figure 31 To be Figure 27 The circuit structure shown is part of the circuit structure and Figure 29 The circuit structure shown is a combination of partial circuit structures, which includes... Figure 27 The circuit structure shown includes transistors T2, T3, and T4, as well as capacitors C1 and C2. Figure 29 The circuit structure shown includes transistors T2, T5, and T6, and capacitor C1. Figure 31 The circuit structure shown has Figure 27 and Figure 29 Corresponding features, and can be achieved Figure 27 and Figure 29 The effect of the circuit structure shown.

[0228] Figure 25 , Figure 27 , Figure 29 as well as Figure 31 The circuit structure shown is applied to Figure 22 The control unit 730 shown is used as an example for description, but it is not limited to this. These circuit structures can also be applied to display panels where the control unit does not receive the last row of signals from the previous stage gate driver group.

[0229] Figure 25 , Figure 27 , Figure 29 as well as Figure 31 The circuit structure shown is only schematically illustrated for use in a control unit that can implement partitioned display; the control unit may also employ other forms of circuit structure.

[0230] The embodiments disclosed herein employ Figures 18 to 31 The gate driving method shown is the same as Figures 1A to 15 The combination of the selected area signal line groups shown can achieve a high refresh rate for display zones arranged in the row and column directions, which helps to reduce the power consumption of the display panel.

[0231] Figure 32 This is a partial planar structural diagram of a display panel provided according to an embodiment of the present disclosure. Figure 32 The display panel shown can be any of the display panels in the examples above, for example, such as... Figure 32 As shown, the display panel includes multiple pixel islands 2000, and each pixel island 2000 includes multiple sub-pixels 200.

[0232] For example, each pixel island 2000 includes a plurality of first-color sub-pixels 2100, a plurality of second-color sub-pixels 2200, and a plurality of third-color sub-pixels 2300. For example, the first-color sub-pixels 2100, second-color sub-pixels 2200, and third-color sub-pixels 2300 may include red sub-pixels, green sub-pixels, and blue sub-pixels. For example, in each pixel island 2000, sub-pixels of the same color are arranged along a first direction, and sub-pixels of different colors are arranged along a second direction. Of course, the embodiments of this disclosure are not limited to this; the arrangement of sub-pixels in the pixel island can be set according to product requirements.

[0233] For example, such as Figure 32 As shown, each pixel island 2000 may include 16 first color sub-pixels 2100, 16 second color sub-pixels 2200 and 16 third color sub-pixels.

[0234] For example, Figure 3 The two rows and six columns of sub-pixels shown can be sub-pixels within the same pixel island. For example, Figure 4The two rows and six columns of sub-pixels shown can be sub-pixels in the same pixel island.

[0235] Figure 33 This is a schematic diagram of the display partitions of a display panel provided according to an embodiment of the present disclosure. Figure 33 The display panel shown can be any of the display panels in the examples above, for example, such as... Figure 33 As shown, the display panel includes 9 display partition rows 1100 and 16 display partition columns 1200, which means it includes 144 display partitions 110. For example, each display partition row 1100 can include 240 rows of pixel islands, and each display partition column 1200 can include 240 columns of pixel islands. For example, the number of pixel islands can be 3840*2160.

[0236] For example, each display partition row 1100 is electrically connected to a gate driver group 710, and every two display partition columns 1200 are electrically connected to a chip-on-film (COF) film.

[0237] For example, such as Figure 33 As shown, the display panel can have a display surface size of 32 inches and a 4K resolution.

[0238] Of course, the embodiments disclosed herein are not limited to this. The display panel may also include 12 display partition rows and 16 display partition columns, that is, 192 display partitions, etc., which can be set according to product requirements.

[0239] For example, such as Figure 33 As shown, the display panel includes nine high-definition display zones 110-1, 110-2, 110-3, 110-4, 110-5, 110-6, 110-7, 110-8 and 110-9. The display zones other than these nine high-definition display zones 110 can be low-definition display zones 110.

[0240] Currently, people demand increasingly higher resolutions and refresh rates for monitors. The current method is to refresh line by line. This full-screen display method requires a large amount of display data. As screen resolution and refresh rate continue to increase, it poses a great challenge to content generation and data transmission. At the same time, due to the viewing characteristics of the human eye, if the area of ​​human eye focus is at the bottom of the screen, the screen needs to refresh the content that the human eye is not focused on before it can refresh the line that the human eye is focused on, resulting in high latency issues.

[0241] By employing the aforementioned combination of the selected signal line group and the gate driver group, it is possible to target only... Figure 33Nine of the 144 display zones 110 achieve high refresh rates, eliminating the need to refresh previously unrelated content in these nine zones. This intelligent partitioning significantly reduces the hardware requirements for content rendering and transmission. The aforementioned "intelligent partitioning" refers to a partitioning design implemented in the display panel through selection signal groups, combined with system signal control, to achieve the purpose of independent local refresh or scanning.

[0242] In their research, the inventors of this application also discovered that current displays are primarily two-dimensional (2D) planar displays. These displays generally cannot provide users with true three-dimensional information, only information about the surface of an object from a certain angle. Existing 2D display technology is no longer sufficient for industries with high requirements for spatial depth, such as 3D design, 3D games, and 3D medical surgery. With the rapid development of science and technology, light field displays have gradually become the mainstream development trend in the display industry.

[0243] Light field display is a three-dimensional (3D) display technology that uses 3D display devices to reproduce the light in a real scene, allowing the human eye to view highly realistic 3D images. To achieve a 3D effect similar to a real scene, the 3D display device needs to be able to reproduce light from various angles in space, which places high demands on the resolution of the display device. However, excessively high display resolution can bring huge challenges to content rendering, transmission, and screen driving.

[0244] This disclosure provides a display device, which includes an eye tracker, a content generation unit, a data processing unit, and the aforementioned components. Figures 1A to 33 The display panel in any of the examples shown. A content generation unit is electrically connected to an eye tracker; a data processing unit is electrically connected to the content generation unit; and the display panel is electrically connected to the data processing unit. The eye tracker is configured to determine the gaze point position on the display surface of the display panel corresponding to the eye by tracking the position of the eyeball. The gaze point position is located in a first area of ​​the display surface, which also includes a second area outside the first area. The first area includes at least one display partition. The content generation unit is configured to generate adjustment data based on the gaze point position. The data processing unit is configured to generate display data based on the adjustment data. The display panel receives the display data to adjust the display resolution of the image displayed in the first area to be greater than the display resolution of the image displayed in the second area.

[0245] The display device provided in this disclosure employs intelligent zonal light field display technology based on human eye characteristics. It captures the foveal viewing needs of the human eye through eye-tracking technology, generates and transmits 3D content, and performs intelligent zonal display on the display end. This allows for high refresh rate and high resolution in the first region where the gaze point is located, while still meeting the human eye's viewing needs. This significantly reduces the hardware requirements for content rendering, transmission, and display, as well as system latency. Furthermore, the 3D light field display allocates different resolution ratios to the gazing and non-gazing areas where the gaze point is located, which is beneficial for matching different visual acuity levels in the user's field of vision.

[0246] Figure 34 This is a structural block diagram of a display device provided according to an embodiment of the present disclosure. Figure 35 for Figure 34 A schematic diagram of the partitioning of the display surface of the display device shown. (See diagram below.) Figure 34 and Figure 35 As shown, the display device includes an eye tracker 20, a content generation unit 30, a data processing unit 40, and a display panel 10. The content generation unit 30 is electrically connected to the eye tracker 20, the data processing unit 40 is electrically connected to the content generation unit 30, and the display panel 10 is electrically connected to the data processing unit 40. The eye tracker 20 is configured to determine the gaze point position E of the eye on the display surface 10-1 of the display panel 10 by tracking the position of the eye. The gaze point position E is located in a first region 011 of the display surface 10-1. The display surface 10-1 also includes a second region 012 located outside the first region 011. The first region 011 includes at least one display partition 110. Here, the display partition 110 is the display partition 110 in the display panel in any of the above examples. The content generation unit 30 is configured to generate adjustment data based on the gaze point position E; the data processing unit 40 is configured to generate display data based on the adjustment data; the display panel 10 receives the display data to adjust the display resolution of the image displayed in the first region 011 to be greater than the display resolution of the image displayed in the second region 012. For example, zone 011 is a high-definition zone, and zone 012 is a low-definition zone. For example, the refresh rate of zone 011 is higher than that of zone 012.

[0247] The display device provided in this disclosure adopts intelligent partitioned light field display technology based on human eye characteristics. It captures the foveal viewing needs of the human eye through eye-tracking technology, generates and transmits 3D content, and performs intelligent partitioned display on the display end. This significantly reduces the hardware requirements for content rendering, transmission, and display while still meeting the viewing needs of the human eye. Furthermore, the 3D light field display allocates different resolution ratios to the fixation zone and non-fixation zone where the gaze point is located, which is beneficial for matching different visual acuity levels in the user's field of vision.

[0248] For example, such as Figure 35As shown, the display surface 10-1 may include m rows of display partitions 110 and n columns of display partitions 110 to form m*n display partitions 110. By setting the selection signal line group and the gate driver group, each display partition 110 can be selected and controlled individually. For example, the first area 011 where the gaze point position E is located in the display surface 10-1 can be refreshed in real time to achieve high-definition display at the gaze point of the human eye. This method can reduce display latency, and by only displaying the data in the area where the human eye is gazed, the bandwidth of data transmission can be reduced.

[0249] When the human eye observes an object, the pupil and lens image the object onto the retina. The image is then resolved by the retina and transmitted to the brain. The retina has different resolution zones, with the fovea region having the highest resolution, and the resolution decreasing sequentially around the fovea. When the eye moves, the object to be seen is imaged in the fovea region of the retina, while surrounding objects are imaged around the fovea region. This results in the human eye only being able to clearly see objects within its gaze area, and not objects outside the gaze area. Due to the characteristics of the human eye, when a user views an image, part of the image is imaged in the fovea region, while another part is blurred because it is not imaged in the fovea region. Therefore, the display device provided in this embodiment can reduce the bandwidth of data transmission by displaying only the image of the area the eye is gazing in high definition, based on the location of the gaze point.

[0250] Figure 36 This is a block diagram of an eye tracker. For example, as shown... Figures 34 to 36 As shown, the eye tracker 20 includes an image acquisition unit 021 and an image processing unit 022 electrically connected to the image acquisition unit 021. For example, the image acquisition unit 021 is configured to acquire eye position information, and the image processing unit 022 includes an eye spatial position calculation unit 0221 and a gaze point position calculation unit 0222. The image processing unit 022 receives the eye position information acquired by the image acquisition unit 021 and calculates the gaze point position E of the eye on the display surface 10-1 based on the eye position information.

[0251] For example, eye trackers are used to provide the position of the human eye in space relative to the screen (such as to determine the view being viewed, reducing the amount of rendering data and rendering latency), and to provide the position of the human eye's gaze point on the display screen (such as to render the area where the gaze point is being viewed in high definition and the non-viewed area in low definition, reducing the amount of rendering data and rendering latency). At the same time, screen display partitions need to be determined based on the gaze position.

[0252] For example, the image acquisition unit 021 may include a camera, which can be a color camera (such as an RGB camera) or an infrared camera, and the camera can be placed at the edge of the screen (such as below or above the display surface). To reduce latency, the camera frame rate must be ≥120FPS, and the number of cameras can be single or multiple, in order to capture clear images of the human eye.

[0253] For example, an infrared camera may include an infrared light source, which can be a ring light source with multiple infrared light-emitting diodes (LEDs) mounted on it. When the light emitted by the infrared light source shines on the eyeball, it produces a reflected spot on the cornea. As the eye gazes in different directions, the center of the pupil changes accordingly, while the position of the corneal reflection point remains constant. The camera captures the reflected spot to track the eyeball.

[0254] Figure 37 This is a diagram illustrating how a user views a display device. For example, such as... Figure 36 and Figure 37 As shown, the image processing unit 022 extracts the pupil position in the face image obtained from the image acquisition unit 021, and calculates the spatial coordinates (x1, y1, z1) and (x2, y2, z2) of the human eye relative to the image acquisition unit 021 based on the position of the human eye relative to the image acquisition unit 021; through the calibration relationship between the pupil image coordinates and the screen, the coordinates (X, Y) of the gaze point position E of the human eye on the display surface 10-1 can be obtained.

[0255] For example, the image processing unit 022 can extract gaze feature parameters (such as the pupil center and the corneal reflective spot center) by utilizing the characteristics of the corneal reflective point. Through a corresponding fixation point estimation method, the position of the gaze point can be obtained. That is, the image processing unit 022 can calculate the eye's fixation point position E within the display surface 10-1 by calculating the eye's rotation angle. This position information can be coordinate information. For example, a region centered on the coordinates of the fixation point position E can be divided based on the perimeter or radius of the region containing the fixation point position E, i.e., the first region 011.

[0256] Figure 38 This is a schematic diagram showing how the first region is determined on the display surface based on the position of the gaze point.

[0257] In some examples, such as Figure 38 As shown, the first region 011 includes a display partition 110, and the gaze point position E, such as E1, is located in the display partition 110.

[0258] In some examples, such as Figure 38As shown, the fixation point position E, such as E2 or E3, is located in a display partition 110, and the first region 011 includes other display partitions 110 surrounding a display partition 110.

[0259] For example, as Figure 38 shown, the fixation point E2 is located in a display partition 110, and the display partition 110 where the fixation point position E2 is located can be at the central position of the first region 011. For example, the fixation point E3 is located in a display partition 110, and the display partition 110 where the fixation point position E3 is located can be at a corner position of the first region 011.

[0260] For example, as Figure 38 shown, the display surface 10-1 can include m*n display partitions 110, and the display surface 10-1 can include a*b sub-pixels, then one display partition 110 includes (a / m)*(b / n) sub-pixels.

[0261] For example, the display partition 110 where the fixation point position E1 is located is in the first row and the first column, and the coordinates of the fixation point position E1 are (X, Y), then the sub-pixel coordinate range in the first region 011 can be (0, 0) to (a / m, b / n), 0 < X < a / m and 0 < Y < b / n, and this first region 011 can include only one display partition 110.

[0262] For example, the display partition 110 where the fixation point position E2 is located is in the fifth row and the seventh column. If the first region 011 is set to include 9 display partitions 110, it expands around the display partition 110 where the fixation point position E2 is located.

[0263] For example, the display partition 110 where the fixation point position E3 is located is in the last row and the first column. If the first region 011 is set to include 9 display partitions 110, it expands with the display partition 110 where the fixation point position E3 is located as the edge.

[0264] Figure 38 The method of determining the first region according to the fixation point position shown is only illustrative. The fixation point position can be at the center of the first region or at the edge of the first region. The embodiments of the present disclosure do not limit this. The embodiments of the present disclosure are also not limited to the first region including 1 display partition or 9 display partitions. The number of display partitions included in the first region can be determined according to actual needs, such as 2, 4, 6, 16, 25, etc.

[0265] The embodiments of the present disclosure collect the fixation point position of the human eye, and perform high-definition display on the first region where the display partition including the fixation point position of the human eye in the display device is located, and perform low-definition display on other display partitions, which is beneficial to reducing the transmission bandwidth.

[0266] For example, the content generation unit renders a multi-view image based on the viewpoint of the human eye; simultaneously, it rearranges the content of the multi-view image according to the spatial position of the human eye to obtain display content that satisfies the light field display rules. After rearranging the multi-view image as described above, it can adapt to the positional relationship between sub-pixels and beam-splitting structures (such as cylindrical lenses) on the display surface to achieve the display of a three-dimensional (3D) image. For example, the content generation unit can be located on a PC, such as a content generation module within a PC.

[0267] Figure 39 This is a diagram illustrating how the human eye views the display surface from different positions. For example, as shown... Figure 39 As shown, in light field display, in order to satisfy the 3D effect when the human eye views from different view angles, the content needs to be generated according to the number of views set by the display device. In light field display, the human eye can only see the images of a fixed number of corresponding views at a fixed position, and the human eye at other view positions can only see the images at other corresponding angle positions.

[0268] Figure 40 This is a schematic diagram of multiple first viewpoint images corresponding to the eyeball and multiple second viewpoint images in addition to the multiple first viewpoint images.

[0269] In some examples, such as Figure 34 , Figure 35 , Figure 39 and Figure 40 As shown, the content generation unit 30 is configured to acquire images displayed on the display surface 10-1 at multiple different locations to generate multiple viewpoint images. The multiple viewpoint images include multiple first viewpoint images V01 corresponding to the eyeball EB and multiple second viewpoint images V02 in addition to the multiple first viewpoint images V01. At least one first viewpoint image V01 includes an image formed in a first region 011 and an image formed in a second region 012. Each second viewpoint image V02 includes only an image formed in the second region 012.

[0270] For example, the content generation unit 30 may include a virtual camera array. The viewpoint image can be an image obtained by capturing images of the target object through the virtual camera array, and different viewpoint images have different acquisition angles. For example, the acquisition angle can be configured according to the user's possible viewing position, so that each viewing position can match at least one viewpoint image, and different viewing positions can match viewpoint images with different angles. For example, the user may be viewing the display surface of the display device directly or from the side. For a face image, when the user is directly facing the display surface of the display device, the viewpoint image matching the user's viewing position can be the front of the face; when the user moves to the left or right, the viewpoint image matching the user's viewing position can be the side of the face.

[0271] In some examples, such as Figure 34 , Figure 35 and Figure 40 As shown, the content generation unit 30 generates adjustment data based on the gaze point position E, including: the content generation unit 30 is configured to adjust the data of the first viewpoint image V01 formed in the second region 012 and the data of the second viewpoint image V02 to generate at least a portion of the adjustment data, wherein at least a portion of the adjustment data is configured to reduce the display resolution of the image displayed in the second region 012.

[0272] For example, based on the characteristics of the human eye's fixation point, the resolution of the fovea region of the retina is the highest, decreasing sequentially in the surrounding areas. When the eye moves, the object to be seen is imaged in the fovea region, while surrounding objects are imaged around the fovea region. This means the eye can only clearly see objects within the area of ​​the fixation point, and not those around it. Typically, the high-resolution area around the fixation point forms an angle of 5° with the pupil, and the eye's resolution rapidly decreases for areas centered on the fixation point and at an angle greater than 5° to the pupil.

[0273] For example, such as Figure 40As shown, considering the potential errors during eye tracking, the area within the error range during eye tracking can be seen by the human eye. This area can be the first viewpoint image V01, also known as the sensitive area view. The viewpoint images at other locations can be the second viewpoint image V02, also known as the non-sensitive area view. The foveal characteristic of the human eye determines that the human eye image is only clear in the fovea. Based on this characteristic, during light field content rendering, the foveal region corresponding to the first viewpoint image V01 uses the high-definition original resolution, while the non-foveal regions of the human eye use a resolution reduction method, reducing the resolution in the first and second directions, such as reducing each to 1 / w of the original. The original data of the corresponding first viewpoint image V01 is rendered according to this rule. For the non-sensitive areas of the human eye, a resolution reduction method is used, and the resolution of the corresponding second viewpoint image in the first and second directions is reduced, such as reducing each to 1 / w of the original.

[0274] For example, while using high-definition original resolution in the fovea region of the human eye corresponding to the first viewpoint image V01, the first viewpoint image V01 can also have a high refresh rate relative to the second viewpoint image V02 by controlling the selected area signal line group.

[0275] For example, such as Figure 40 As shown, the number of first viewpoint images V01 and second viewpoint images V02 is q, the main lobe angle is θ, the angle corresponding to each viewpoint image is θ / q, and the viewing angle corresponding to the visual sensitive area of ​​the eyeball EB is ±β. Therefore, the number of first viewpoint images V01 is 2*(β*q / θ). The aforementioned main lobe angle can refer to the field of view angle of viewing all viewpoint images.

[0276] In some examples, such as Figure 34 and Figure 35 As shown, the adjustment data includes first content data and compressed data. The first content data includes data corresponding to the image configured to be transmitted to the first region 011, and the compressed data includes data generated by compressing the second content data corresponding to the image configured to be transmitted to the second region 012 by a factor of w, where w is a positive integer greater than 1.

[0277] For example, the first content data and the second content data are the original data corresponding to the first region and the second region, respectively. When transmitting data, transmitting the original data corresponding to the first region and the compressed data corresponding to the second region helps to reduce bandwidth.

[0278] In some examples, such as Figure 34 and Figure 35As shown, the display data includes first display data and second display data. The data processing unit 40 is configured to process the received first content data to process the first content data into first display data corresponding to the image of the first region 011. The data processing unit 40 is also configured to process the compressed data repeatedly w times to form second display data corresponding to the image of the second region.

[0279] For example, the data processing unit 40 is used, on the one hand, to decode the multi-view gaze point compressed image sent by the content generation unit 30, and, in conjunction with the gaze point position, to restore it into a data format that the display can directly receive and display; on the other hand, it is used to drive the display panel for display. For example, the data processing unit can be a timing controller (TCON).

[0280] For example, data transmission between the PC containing the content generation unit and the data processing unit occurs via various standard interfaces, such as HDMI and DisplayPort (DP). The bandwidth of the interface determines the amount of data transmitted per unit of time. For instance, if the maximum transmission resolution of the interface is W*H, the data volume is calculated based on this. If the display panel requires multi-view images, and the data output from the interface between the PC containing the content generation unit and the data processing unit is less than the display panel's requirements, a display partitioning scheme can be adopted. Based on the viewer's gaze point, the display partition at the gaze point location is adjusted for high-definition display, while other display partitions are used for low-definition display.

[0281] For example, in the aforementioned viewpoint images, such as the first viewpoint image and the second viewpoint image, each first viewpoint image includes a high-resolution image formed in a first region and a low-resolution image formed in a second region. For example, the resolution of the first region can be W*H. For example, the image in the second region can be compressed by rw times horizontally and rh times vertically, then the resolution of the second region can be (W / rw)*(H / rh). The above rw times and rh times only represent the compression ratio, and can also be represented by w times.

[0282] Figure 41 This is a schematic diagram showing the positional relationship between the first and second areas of the display panel. Figure 42 This is a structural block diagram of the data processing department. Figure 43 This represents the correspondence between row processing units and sub-pixel rows. Figure 44 For row processing unit Figure 41 The diagram shown illustrates the process of processing the data in region M2. Figure 45 For row processing unit Figure 41 The diagram shows the process of processing data in regions M1 and M3.

[0283] For example, the data processing unit 40 may include a plurality of row processing units 41, each row processing unit 41 being able to process image data of one row of subpixels.

[0284] In some examples, such as Figure 34 , Figures 41 to 44 As shown, the second region 012 includes a first sub-region 0121 located on at least one side of the first region 011 in the row direction, where the row direction can refer to the X direction in the figure. The adjustment data includes p*w row adjustment data; the p*w row adjustment data transmitted by the content generation unit 30 to the row processing unit 41 includes p row compressed data and q*w row first content data, the image corresponding to the q*w row first content data is located in the first region 011, and the image corresponding to the q row compressed data in the p row compressed data is located in the first sub-region 0121; the row processing unit 41 is configured to process the q row compressed data repeatedly w times to form q*w row second display data, and to process the q*w row first content data into q*w row first display data, where 1≤q≤p, and p and q are both positive integers.

[0285] For example, such as Figure 34 , Figures 41 to 44 As shown, when the content generation unit 30 transmits data of region M2 to the line processing unit 41, this data includes compressed data corresponding to the first sub-region 0121 and uncompressed data corresponding to the first region 011. For example, when the content generation unit 30 transmits data of region M2, which includes both compressed data corresponding to the first sub-region 0121 and w lines of first content data corresponding to the first region 011, the line processing unit 41 processes the compressed data of region M2 w times to generate w lines of second display data, and processes the w lines of first content data to generate w lines of first display data, ultimately forming w lines of data. Figure 44 The example shown uses column W of data. For instance, the row of data used for low-definition display can correspond to row w of data used for high-definition display. During the row processing unit's processing, the data used for low-definition display can be filled into the row processing unit first, and then the data used for high-definition display can be merged and filled into the row processing unit separately for transmission.

[0286] For example, such as Figure 43 As shown, row processing unit R can process three rows of red sub-pixels, row processing unit G can process three rows of green sub-pixels, and row processing unit B can process three rows of blue sub-pixels, and so on in a loop. For example, the number of rows of sub-pixels is H, and the number of columns of sub-pixels is W.

[0287] In some examples, such as Figure 34 , Figures 41 to 45As shown, the second region 012 also includes a second sub-region 0122 located on at least one side of the first region 011 in the column direction, where the column direction is the Y direction shown in the figure. The image corresponding to the (pq) rows of compressed data other than the q rows of compressed data in the p rows of compressed data is located in the second sub-region 0122, and the row processing unit 41 is configured to process the (pq) rows of compressed data w times to form (pq)*w rows of second display data.

[0288] For example, such as Figure 34 , Figures 41 to 45 As shown, when the content generation unit 30 transmits data from regions M1 and M3 to the line processing unit 41, this data only includes the compressed data corresponding to the second region 012 to reduce bandwidth. For example, when the content generation unit 30 transmits a compressed line of data corresponding to the second sub-region 0122 in region M1 or M3 to the line processing unit 41, the line processing unit 41 processes the compressed line of data w times to generate w lines of second display data. If the data entered into the line processing unit is insufficient, extra positions can be padded with black (or zeros).

[0289] For example, when the content generation unit 30 transmits data of areas M1, M2 and M3 to the line processing unit 41, the data of area M2 after processing by the data processing unit can fill the data of the line processing unit. At this time, the data of areas M1 and M3 after processing by the data processing unit may fill the data of the line processing unit or may not fill it, depending on the amount of first display data corresponding to the first area and the compression factor when compressing the compressed data corresponding to the second area.

[0290] For example, such as Figure 45 As shown, when the content generation unit transmits data from areas M1 and M3 to the line processing unit, it can transmit n lines of compressed data to the line processing unit, and each line of compressed data is processed into w lines of second display data. Figure 45 The example shown uses data in column W.

[0291] For example, such as Figure 43 As shown, before the line processing unit 41 processes the data in areas M1 to M3, the content generation unit transmits the first line header data to the data processing unit. The header data includes the maximum resolution of the interface, the number of viewpoint images, the resolution of the viewpoint images, the horizontal compression ratio of the second area image, the vertical compression ratio of the second area image, the resolution of the second area, the resolution of the first area, the position of the display partition on the display surface, the size of the display partition on the display surface, the number of lines in the line processing unit, the coordinates of the human eye's brow, etc. Other data is padded with zeros to form a line of data of length W, which is then transmitted to the data processing unit.

[0292] Figure 46 This is a flowchart of the data processing workflow for the data processing department. For example, such as... Figure 46 As shown, the processing flow of the data processing unit may include storing the data transmitted by the content generation unit in the data processing unit, and the data processing unit performing one or more 3D layouts. For example, the PC line processing unit transmits the data to the TCON, the TCON stores the line processing unit data, and the TCON performs one or more 3D sub-pixel layouts.

[0293] For example, it determines whether multiple lines are displayed simultaneously. If so, multi-line simultaneous display control is applied, displaying multiple rows of pixel islands; otherwise, single-line display control is applied, displaying one row of pixel islands. For instance, when multiple lines are displayed simultaneously, the TCON sends line data to the integrated circuit (IC) of the display panel, and simultaneously sends a multi-line simultaneous display control signal. The aforementioned multi-line simultaneous display can be applied to the second area to achieve low-definition image display, while the aforementioned single-line display can be applied to the first area to achieve high-definition image display.

[0294] For example, each pixel island in the display surface includes sub-pixels for which the View's grayscale value is calculated and assigned, i.e., sub-pixel arrangement is performed. For example, sub-pixel arrangement methods can include arrangement methods based on angular spectrum measurement and arrangement methods based on the period of a beam splitting structure (such as a lens).

[0295] For example, the data processing unit can send the processed data to the display panel's drive circuit according to the display panel's data display requirements, and the drive circuit can control the display.

[0296] Figures 40 to 46 The content generation unit in the example shown uses a multi-view rendering method to process data. Figure 47 This is a schematic diagram of a plurality of first viewpoint images corresponding to an eyeball and a plurality of second viewpoint images in addition to the plurality of first viewpoint images, provided according to another example of an embodiment of the present disclosure.

[0297] For example, such as Figure 47 As shown, this example renders only the left and right viewpoint maps, and copies and extends the sub-pixel content of the left and right viewpoint maps to all viewpoint maps. This facilitates the viewing experience where the left eye sees the left view and the right eye sees the right view, allowing the viewer to perceive the 3D scene content through the principle of binocular parallax. Furthermore, rendering only the left and right viewpoint maps further reduces rendering and transmission load and latency.

[0298] For example, both the left and right viewpoint maps include at least one first viewpoint image V01 corresponding to the eyeball EB and multiple second viewpoint images V02 in addition to the at least one first viewpoint image V01. The first viewpoint image V01 includes an image formed in a first region 011 and an image formed in a second region 012. For example, only one first viewpoint image V01 corresponding to the left eye in the eyeball EB can be copied to form the left viewpoint map, and only one first viewpoint image V01 corresponding to the right eye in the eyeball EB can be copied to form the right viewpoint map. For example, if the number of viewpoint images is r, the viewpoint image V01 corresponding to the left eye is repeated r / 2 times to form the left eye viewpoint image V011, and the viewpoint image V01 corresponding to the right eye is repeated r / 2 times to form the right eye viewpoint image V012.

[0299] The display method in this example, which forms a display surface including a first region and a second region, can be compared with... Figures 40 to 46 The display method shown is the same, so it will not be repeated here.

[0300] For example, for a 3D light field display scheme that requires left and right images, the left and right viewpoint images can be decomposed into red, green and blue three-channel images according to the driving requirements of the display panel. The resolution of the red, green and blue three-channel images corresponding to the left viewpoint image and the red, green and blue three-channel images corresponding to the right viewpoint image are the same, such as w0*h.

[0301] For example, at least one of the data processing unit and the content generation unit can refer to the implementation of control functions in hardware. That is, without considering cost, those skilled in the art can build the corresponding hardware circuit to implement the control functions. For example, the hardware circuit includes conventional very large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors such as logic chips, transistors, or other discrete components. For example, the controller can also be implemented using programmable hardware devices, such as field-programmable gate arrays, programmable array logic, programmable logic devices, etc., which is not limited in this embodiment.

[0302] For example, at least one of the data processing unit and the content generation unit may refer to control functions implemented using software algorithms so that they can be executed by various types of processors. For example, considering the level of current hardware technology, the controller may be a module implemented using software algorithms.

[0303] In the display device provided in this embodiment, after tracking the gaze point position of the human eye on the display surface of the display panel by an eye tracker, first content data corresponding to the high-definition image of the first area where the gaze point position is located and compressed data corresponding to the low-definition image of the second area where the non-gaze point position is located are generated by content generation data. The first content data and compressed data are processed by the data processing unit and then transmitted to the driving circuit of the display panel to drive the display partition including sub-pixels to display. This can greatly reduce the hardware requirements for content rendering, transmission and display while meeting the viewing needs of the human eye.

[0304] The following points need to be explained:

[0305] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0306] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0307] The above are merely exemplary embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A display panel, comprising: Substrate; Multiple sub-pixels are located on the substrate, and at least some of the sub-pixels include pixel circuitry. Multiple data lines are located on the substrate and arranged along a first direction, and the pixel circuit of at least one sub-pixel is electrically connected to one data line. Multiple gate lines are located on the substrate and arranged along a second direction. The pixel circuit of the at least one sub-pixel is electrically connected to one gate line. The first direction intersects the second direction. The display panel includes multiple display zones and multiple selection signal line groups. The multiple display zones and the multiple selection signal line groups are configured in a one-to-one correspondence. Each display zone includes at least two sub-pixels, and each selection signal line group includes multiple selection signal lines. The selection signal lines corresponding to different display zones are insulated. The pixel circuit includes a transistor. Along a direction perpendicular to the substrate, the active semiconductor layer in the transistor of the at least one sub-pixel includes a first portion and a second portion. The first portion overlaps with the gate line electrically connected to the transistor, and the second portion overlaps with at least one selection signal line. The gate line and the selection signal line are configured such that when both are input with an input turn-on voltage, the transistor is turned on. At least one selection signal line group includes multiple selection signal lines, including multiple first selection signal lines and at least one second selection signal line. The first selection signal lines overlap with the second part, the second selection signal line is located on a different layer from the first selection signal line, and the second selection signal line is electrically connected to the first selection signal line. The second selection signal line passes through at least one display partition.

2. The display panel of claim 1, wherein, The plurality of display partitions includes M display partitions arranged along the first direction, and at least one grid line passes through the M display partitions arranged along the first direction, where M is a positive integer greater than or equal to 2.

3. The display panel of claim 1, wherein, In at least some of the selected signal line groups, all selected signal lines in each selected signal line group are electrically connected.

4. The display panel of claim 1, wherein, The first selected area signal line and the gate line are located on the same layer.

5. The display panel of claim 1, wherein, The first selected area signal line and the gate line are located on different layers.

6. The display panel according to claim 4, wherein, The extension direction of the first selection area signal line is the same as the extension direction of the gate line. The two adjacent display partitions arranged along the first direction include a first display partition and a second display partition. One of the multiple first selection area signal lines set in the first display partition and one of the multiple first selection area signal lines set in the second display partition are located on the same straight line and are spaced apart.

7. The display panel of claim 4, wherein, The extension direction of the first selection area signal line is the same as the extension direction of the gate line, and the extension direction of the second selection area signal line intersects with the extension direction of the first selection area signal line. At least one second selection area signal line passes through multiple display zones.

8. The display panel of claim 4, wherein, At least some of the data lines are electrically connected to two sub-pixels arranged along the first direction; The plurality of gate lines include a first gate line and a second gate line arranged alternately along the second direction. A gate line pair formed by the first gate line and the second gate line is provided between two adjacent sub-pixels arranged along the second direction. One of the two sub-pixels arranged along the first direction and electrically connected to the same data line is electrically connected to the first gate line, and the other is electrically connected to the second gate line. The second selection area signal line is located on the same layer as the data line.

9. The display panel of claim 8, wherein, The second selection area signal line extends in the same direction as the data line. The second selection area signal line is located between two adjacent sub-pixels arranged along the first direction, and the two adjacent sub-pixels are electrically connected to different data lines respectively.

10. The display panel of claim 8, wherein, A first selection signal line is provided between each gate line pair, and the second portion of the transistor of the pixel circuit electrically connected to the first gate line and the second gate line in the same gate line pair overlaps with the same first selection signal line located between the same gate line pair.

11. The display panel of claim 8, wherein, The plurality of first selection area signal lines include a plurality of first selection area signal line pairs, and a pair of first selection area signal lines is provided between two adjacent sub-pixels arranged along the second direction; A grid line pair is provided between each first selection zone signal line pair, or a first selection zone signal line pair is provided between each grid line pair.

12. The display panel according to claim 4, wherein, The second selection area signal line is located on a different layer from the data line.

13. The display panel according to claim 12, further comprising: A light-shielding layer is located between the data line and the substrate. The second selection area signal line is disposed in the same layer as the light-shielding layer.

14. The display panel of claim 12, wherein, The second selection signal line extends in the same direction as at least a portion of the data line, and in a direction perpendicular to the substrate, the second selection signal line overlaps with the data line.

15. The display panel of claim 5, wherein, The first selection area signal line includes at least one first sub-selection area signal line and multiple second sub-selection area signal lines that are electrically connected to each other, and the second sub-selection area signal lines overlap with the second portion; The extension direction of the second sub-selection area signal line intersects with the extension direction of the gate line, the extension direction of the first sub-selection area signal line intersects with the extension direction of the second sub-selection area signal line, and the second sub-selection area signal line corresponding to each display partition is insulated from the second sub-selection area signal line corresponding to other display partitions.

16. The display panel according to claim 15, wherein, At least some of the data lines are electrically connected to two sub-pixels arranged along the first direction; The plurality of gate lines include a first gate line and a second gate line arranged alternately along the second direction. A gate line pair formed by the first gate line and the second gate line is provided between two adjacent sub-pixels arranged along the second direction. One of the two sub-pixels arranged along the first direction and connected to the same data line is electrically connected to the first gate line, and the other is electrically connected to the second gate line. The second selection area signal line is located on the same layer as the data line.

17. The display panel of claim 16, wherein, The second selection area signal line extends in the same direction as at least a portion of the data line. The second selection area signal line is located between two adjacent sub-pixels arranged along the first direction, and the two adjacent sub-pixels are electrically connected to different data lines respectively.

18. The display panel according to claim 15, wherein, The second selection area signal line is located on a different layer from the data line.

19. The display panel according to claim 18, wherein, Along a direction perpendicular to the substrate, at least one of the second sub-selection signal line and the second selection signal line overlaps with the data line.

20. The display panel according to any one of claims 15-19, wherein, The first sub-selection area signal line and the second sub-selection area signal line are integrated into one structure.

21. The display panel according to any one of claims 1-19, further comprising: A plurality of gate driver groups are arranged along the second direction, the gate driver groups being electrically connected to the gate lines, and at least some of the plurality of gate driver groups being configured to each be individually input with a frame start signal. The plurality of display partitions include a plurality of display partition rows arranged along the second direction, each display partition row includes display partitions arranged along the first direction, and the plurality of gate driver groups are electrically connected to the plurality of display partition rows in a one-to-one correspondence.

22. The display panel according to claim 21, further comprising: Multiple frame start signal lines, The multiple frame start signal lines are electrically connected to the multiple gate driver groups in a one-to-one correspondence.

23. The display panel according to claim 21, further comprising: At least one frame start signal line, Among them, a plurality of control units are provided between the plurality of gate driver groups and the at least one frame start signal line, and the plurality of control units are electrically connected to the plurality of gate driver groups in a one-to-one correspondence. Each frame start signal line is electrically connected to at least two of the plurality of control units to input a frame start signal to at least two of the plurality of control units.

24. The display panel according to claim 23, wherein, The at least one frame start signal line includes only one frame start signal line, which is electrically connected to each of the plurality of control units to input a frame start signal to each of the plurality of control units individually.

25. The display panel of any one of claims 1-19, wherein, At least one gate line includes two sub-gate lines and at least one connecting portion connecting the two sub-gate lines. The two sub-gate lines are arranged in parallel on the same layer, and the two sub-gate lines and the connecting portion are located on different layers. The two sub-gate lines included in each gate line are electrically connected through the connecting portion. One of the two sub-gate lines overlaps with the first portion.

26. A display device, comprising: Eye tracker; The content generation unit is electrically connected to the eye tracker; The data processing unit is electrically connected to the content generation unit; as well as The display panel according to any one of claims 1-25 is electrically connected to the data processing unit. The eye tracker is configured to determine the gaze point position of the eye on the display surface of the display panel by tracking the position of the eye. The gaze point position is located in a first area of ​​the display surface, and the display surface also includes a second area located outside the first area. The first area includes at least one of the display partitions. The content generation unit is configured to generate adjustment data based on the gaze point position; The data processing unit is configured to generate display data based on the adjustment data; The display panel receives the display data to adjust the display resolution of the image displayed in the first area to be greater than the display resolution of the image displayed in the second area.

27. The display device according to claim 26, wherein, The first region includes a display partition, and the gaze point is located within the display partition; or, The gaze point is located in a display partition, and the first region includes other display partitions surrounding the one display partition.

28. The display device according to claim 26 or 27, wherein, The content generation unit is configured to acquire images displayed on the display surface at multiple different locations to generate multiple viewpoint images. The multiple viewpoint images include multiple first viewpoint images corresponding to the eyeball and multiple second viewpoint images in addition to the multiple first viewpoint images. At least one first viewpoint image includes an image formed in a first region and an image formed in a second region. Each second viewpoint image includes only an image formed in the second region. The content generation unit generates the adjustment data based on the gaze point position, including: The content generation unit is configured to adjust the data of the image formed by the first viewpoint image in the second region and the data of the second viewpoint image to generate at least a portion of the adjusted data, wherein the at least a portion of the adjusted data is configured to reduce the display resolution of the image displayed in the second region.

29. A display device according to claim 26 or 27, wherein, The adjustment data includes first content data and compressed data. The first content data includes data corresponding to the image configured to be transmitted to the first region. The compressed data includes data generated by compressing the second content data corresponding to the image configured to be transmitted to the second region by a factor of w, where w is a positive integer greater than 1. The display data includes first display data and second display data. The data processing unit is configured to process the received first content data to process the first content data into the first display data corresponding to the image of the first region. The data processing unit is also configured to process the compressed data repeatedly w times to form the second display data corresponding to the image of the second region.

30. A display device according to claim 29, wherein, The second region includes a first sub-region located on at least one side of the first region in the row direction, and the adjustment data includes p×w row adjustment data; The data processing unit includes a line processing unit. The p×w line adjustment data transmitted by the content generation unit to the line processing unit includes p line compressed data and q×w line first content data. The image corresponding to the q×w line first content data is located in the first region, and the image corresponding to the q line compressed data in the p line compressed data is located in the first sub-region. The row processing unit is configured to process the compressed data of the q rows repeatedly w times to form the second display data of q×w rows, and to process the first content data of the q×w rows into the first display data of q×w rows, where 1≤q≤p, and p and q are both positive integers.

31. A display device according to claim 30, wherein, The second region also includes a second sub-region located on at least one side of the first region in the column direction; The image corresponding to the (pq) rows of compressed data other than the q rows of compressed data in the p rows of compressed data is located in the second sub-region. The row processing unit is configured to process the (pq) rows of compressed data w times to form (pq)×w rows of second display data.

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