Low-power driving circuit, method and display screen

Abstract

This invention discloses a low-power driving circuit, method, and display screen. The circuit includes an N-stage GOA circuit, a timing controller, and a level control module. The timing controller and the level control module are electrically connected. The level control module is electrically connected to each stage of the GOA circuit. The GOA circuits are cascaded sequentially, and the first terminal of each GOA circuit is electrically connected to the forward scan signal line, the reverse scan signal line, and the start signal line, respectively. The second terminal of each GOA circuit is electrically connected to the first clock signal line, the second clock signal line, the high-level signal line, and the low-level signal line, respectively. The level control module is used to perform graded potential control on the GOA circuit according to the clock signal and pulse signal provided by the timing controller. By performing graded potential control on the GOA circuit, the potential of some units in the GOA circuit is reduced, thereby reducing the overall power consumption of the display screen and improving the display quality.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a low-power driving circuit, method, and display screen. Background Technology

[0002] GOA technology is one of the gate driving technologies for LCD panels. Its basic concept is to integrate the shift register units of the LCD panel onto the array substrate to form a scanning drive for the LCD panel. Compared with the traditional COF (Chip On Flexible Printed Circuit) process, which fixes the chip on a flexible printed circuit, and COG (Chipon Glass) process, which fixes the chip on glass, GOA technology not only saves costs, but also allows for a symmetrical and aesthetically pleasing design of the LCD panel. It also eliminates the bonding area of ​​the shift register units and the fan-out wiring space, enabling a narrow bezel design. At the same time, since it eliminates the gate direction bonding process, it is also more beneficial for improving production capacity and yield.

[0003] The existing driving method generally uses VGH as the high-level state and VGL as the low-level state of the entire GOA driving unit. The potential of all gate control signals is between VGH and VGL. Considering the boost method of the IC, higher voltage will lead to higher power consumption, resulting in an increase in the overall power consumption of the display screen, thereby reducing the standby time of the product and also reducing the user's product experience. Summary of the Invention

[0004] Existing displays consume too much power, resulting in short standby time and a poor user experience.

[0005] To address the aforementioned issues, a low-power driving circuit, method, and display screen are proposed. By implementing graded potential control on the GOA circuit, the potentials of the forward and reverse scan units and the latch shift unit in the GOA circuit are adjusted between a first low level and a first high level, and the potential of the buffer output unit is adjusted between a second low level and a second high level. This reduces the potential of some units in the GOA circuit, thereby reducing the overall power consumption of the display screen and improving the display quality.

[0006] In a first aspect, a low-power driving circuit includes:

[0007] N-level GOA circuit;

[0008] Timing controller;

[0009] Level control module;

[0010] The timing controller is electrically connected to the level control module;

[0011] The level control module is electrically connected to each stage of the GOA circuit;

[0012] The GOA circuits are cascaded in sequence, and the first terminal of the GOA circuit is electrically connected to the forward scan signal line, the reverse scan signal line, and the start signal line, respectively. The second terminal of the GOA circuit is electrically connected to the first clock signal line, the second clock signal line, the high-level signal line, and the low-level signal line, respectively.

[0013] The level control module is used to perform graded level control on the GOA circuit according to the clock signal and pulse signal provided by the timing controller.

[0014] In conjunction with the low-power driving circuit described in the first aspect of the present invention, in a first possible embodiment, the GOA circuit includes:

[0015] Forward and reverse scanning units;

[0016] Latch shift unit;

[0017] and buffered output unit;

[0018] The forward and reverse scan unit is used to control the forward or reverse scan of the GOA circuit, inputting a start signal and outputting it to the latch shift unit;

[0019] The latch shift unit is used to latch and shift the signal output by the forward and reverse scan unit, and at the same time pass it to the forward and reverse scan unit module of the next stage GOA circuit;

[0020] The buffer output unit is used to buffer and amplify the signal obtained by the latch shift unit, and output Gout to the display area to drive the transistor to turn on and off.

[0021] The first end of the forward and reverse scan unit is electrically connected to the forward scan signal line, the reverse scan signal line, and the start signal line, respectively. The second end is electrically connected to the first end of the latch shift unit. The second end of the latch shift unit is electrically connected to the first end of the buffer output unit. The second end of the buffer output unit is electrically connected to the first clock signal line, the second clock signal line, the high-level signal line, and the low-level signal line, respectively.

[0022] In conjunction with the first possible embodiment of the first aspect of the present invention, in the second possible embodiment, the cascade relationship between the nth stage and the (n+1th)th stage GOA circuit of the display driving circuit is as follows:

[0023] The second terminal of the nth stage latch shift unit, the first terminal of the nth stage buffer output unit, and the first terminal of the (n+1)th stage forward and reverse scan unit are electrically connected.

[0024] The third terminal of the nth-level forward and reverse scan unit is connected to the second terminal of the (n+1)th-level latch shift unit and the first terminal of the (n+1)th-level buffer output unit.

[0025] In conjunction with the second possible embodiment of the first aspect of the present invention, in the third possible embodiment, the graded potential control includes:

[0026] The potentials of the forward and reverse scan units and the latch shift unit are adjusted between the first low level and the first high level;

[0027] Adjust the potential of the buffer output unit between the second low level and the second high level;

[0028] Wherein, the first low level is greater than the second low level, and the first high level is less than the second high level.

[0029] Secondly, a low-power display screen driving method, employing the driving circuit described in the first aspect, includes:

[0030] Step 100: Electrically connect the timing controller to the level control module, electrically connect the level control module to each stage of the GOA circuit, and cascade the GOA circuits in sequence. The first terminal of the GOA circuit is electrically connected to the forward scan signal line, the reverse scan signal line, and the start signal line, respectively. The second terminal of the GOA circuit is electrically connected to the first clock signal line, the second clock signal line, the high-level signal line, and the low-level signal line, respectively.

[0031] Step 200: Perform graded potential control on the GOA circuit based on the clock signal and pulse signal provided by the timing controller and using the level control module.

[0032] In conjunction with the low-power display driving method described in the second aspect of the present invention, in a first possible embodiment, step 100 includes:

[0033] Step 110: Electrically connect the first end of the forward and reverse scan unit to the forward scan signal line, the reverse scan signal line, and the start signal line, respectively; electrically connect the second end to the first end of the latch shift unit; and electrically connect the second end of the latch shift unit to the first end of the buffer output unit.

[0034] Step 120: Electrically connect the second terminal of the buffer output unit to the first clock signal line, the second clock signal line, the high-level signal line, and the low-level signal line, respectively;

[0035] The GOA circuit includes a forward and reverse scan unit, a latch shift unit, and a buffer output unit.

[0036] In conjunction with the first possible embodiment of the second aspect of the present invention, in the second possible embodiment, step 100 further includes:

[0037] Step 130: Electrically connect the second terminal of the nth stage latch shift unit, the first terminal of the nth stage buffer output unit, and the first terminal of the (n+1)th stage forward and reverse scan unit;

[0038] Step 140: Connect the third terminal of the nth-level forward and reverse scan unit to the second terminal of the (n+1)th-level latch shift unit and the first terminal of the (n+1)th-level buffer output unit.

[0039] In conjunction with the second possible embodiment of the second aspect of the present invention, in a third possible embodiment, step 100 further includes:

[0040] Step 150: Use the forward and reverse scanning unit to acquire forward and reverse scanning signals and output them to the latch shift unit;

[0041] Step 160: Use the latch shift unit to latch and shift the forward and reverse scan signals, and simultaneously transmit them to the forward and reverse scan unit of the next stage GOA circuit;

[0042] Step 170: Use the buffer output unit to buffer and amplify the signal obtained by the latch shift unit, and output Gout to the display area to drive the transistor to turn on and off.

[0043] In conjunction with the third possible implementation of the second aspect of the present invention, in the fourth possible implementation, step 200 includes:

[0044] Step 210: Adjust the potential of the forward and reverse scan unit and the latch shift unit between the first low level and the first high level;

[0045] Step 220: Adjust the potential of the buffer output unit between the second low level and the second high level;

[0046] Wherein, the first low level is greater than the second low level, and the first high level is less than the second high level.

[0047] Thirdly, a low-power display screen includes the driving circuit described in the first aspect, and drives the GOA circuit using the driving method described in the second aspect.

[0048] The low-power driving circuit, method, and display screen described in this invention reduce the power consumption of the display screen and improve the display quality by performing graded potential control on the GOA circuit: adjusting the potentials of the forward and reverse scan units and the latch shift unit in the GOA circuit between a first low level and a first high level, and adjusting the potential of the buffer output unit between a second low level and a second high level. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a schematic diagram of the low-power drive circuit module connection in this invention;

[0051] Figure 2 This is a schematic diagram of the low-power driving circuit structure in this invention;

[0052] Figure 3 This is a timing control diagram of the potential of each signal line in this invention;

[0053] Figure 4 This is a first schematic diagram of the low-power driving method in this invention;

[0054] Figure 5 This is a second schematic diagram of the low-power driving method in this invention;

[0055] Figure 6 This is a third schematic diagram of the low-power driving method in this invention;

[0056] Figure 7 This is a fourth schematic diagram of the low-power driving method in this invention;

[0057] Figure 8 This is the fifth schematic diagram of the low-power driving method in this invention. Detailed Implementation

[0058] The technical solutions of this invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are all within the scope of protection of this invention.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0060] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0061] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0062] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0063] Existing displays consume too much power, resulting in short standby time and a poor user experience.

[0064] To address the above problems, a low-power driving circuit, method, and display screen are proposed.

[0065] Example 1

[0066] First, as Figure 1 , Figure 1This is a schematic diagram of the low-power drive circuit module connection in this invention. A low-power drive circuit includes an N-stage GOA circuit 30, a timing controller 10, and a level control module 20. The timing controller 10 is electrically connected to the level control module 20. The level control module 20 is electrically connected to each stage of the GOA circuit. The GOA circuits are cascaded sequentially, and the first terminal of the GOA circuit is electrically connected to the forward scan signal line FW, the reverse scan signal line BW, and the start signal line STV, respectively. The second terminal of the GOA circuit is electrically connected to the first clock signal line CK, the second clock signal line CKB, the high-level signal line VGH, and the low-level signal line VGL, respectively. The level control module 20 is used to perform graded level potential control on the GOA circuit according to the clock signal and pulse signal provided by the timing controller 10.

[0067] The N-stage GOA circuits 30 are cascaded together, and the two ends of each GOA circuit are electrically connected to the corresponding signal lines.

[0068] In the existing technology, the high level state of the entire GOA circuit is VGH potential, and the low level is VGL potential. The potential of all gate control signals is between VGH and VGL. Considering the boost method of the IC, higher voltage will lead to higher power consumption, resulting in an increase in overall power consumption.

[0069] In this embodiment, a level control module 20 is used to perform hierarchical control of the module potential in the GOA circuit, thereby reducing the voltage fluctuation of some module circuits and thus reducing the overall power consumption of the GOA circuit.

[0070] Specifically, such as Figure 2 , Figure 2 This is a schematic diagram of the low-power driving circuit structure in this invention. The GOA circuit includes a forward and reverse scan unit, a latch shift unit, and a buffer output unit. The forward and reverse scan unit controls the forward or reverse scan of the GOA circuit, inputs a start signal, and outputs it to the latch shift unit. The latch shift unit latches and shifts the signals output by the forward and reverse scan signals, and simultaneously transmits them to the forward and reverse scan unit module of the next stage GOA circuit. The buffer output unit buffers and amplifies the signal obtained by the latch shift unit, and outputs Gout to drive the display area transistors to turn on and off. The connected circuit structure is as follows: Figure 2 The first end of the forward and reverse scan unit is electrically connected to the forward scan signal line FW, the reverse scan signal line BW, and the start signal line STV, respectively. The second end is electrically connected to the first end of the latch shift unit. The second end of the latch shift unit is electrically connected to the first end of the buffer output unit. The second end of the buffer output unit is electrically connected to the first clock signal line CK, the second clock signal line CKB, the high-level signal line VGH, and the low-level signal line VGL, respectively.

[0071] like Figure 2The cascaded relationship of the GOA circuits in the driving circuit is as follows: The cascaded relationship of the GOA circuits of the nth stage and the (n+1)th stage in the display driving circuit is as follows:

[0072] The second terminal of the nth stage latch shift unit, the first terminal of the nth stage buffer output unit, and the first terminal of the (n+1)th stage forward and reverse scan unit are electrically connected.

[0073] The third terminal of the nth-level forward and reverse scan unit is connected to the second terminal of the (n+1)th-level latch shift unit and the first terminal of the (n+1)th-level buffer output unit.

[0074] Specifically, the graded potential control includes adjusting the potentials of the forward and reverse scan unit and the latch shift unit between the first low level AVEE and the first high level AVDD; and adjusting the potential of the buffer output unit between the second low level VGL and the second high level VGH; wherein the first low level AVEE is greater than the second low level VGL, and the first high level AVDD is less than the second high level VGH.

[0075] The entire GOA unit is divided into three parts: forward and reverse scan unit, latch and shift unit, and buffered output unit. The potentials of the forward and reverse scan and latch and shift units are between AVEE and AVDD. The input potential of the buffered output unit is between VGL and VGH.

[0076] like Figure 3 , Figure 3 The timing control diagram for the potentials of each signal line in this invention shows that the potentials of the start signal line STV, forward scan signal line FW, reverse scan signal line BW, and set signal line RST are all between the first low level AVEE and the first high level AVDD.

[0077] The potentials of the first clock signal line CK and the second clock signal line CKB are both between VGL and VGH. By performing graded potential control on the GOA circuit: adjusting the potentials of the forward and reverse scan units and the latch shift unit in the GOA circuit between the first low level and the first high level, and adjusting the potential of the buffer output unit between the second low level and the second high level, the potentials of some units in the GOA circuit are reduced, thereby reducing the overall power consumption of the display screen and improving the display quality.

[0078] Example 2

[0079] Secondly, such as Figure 1 , Figure 4This is a first schematic diagram of the low-power driving method of the present invention; a low-power display screen driving method, using a driving circuit of the first aspect, includes: step 100, electrically connecting the timing controller 10 and the level control module 20, electrically connecting the level control module 20 to each stage of the GOA circuit and cascading the GOA circuits sequentially, wherein the first terminal of the GOA circuit is electrically connected to the forward scan signal line FW, the reverse scan signal line BW, and the start signal line STV respectively, and the second terminal of the GOA circuit is electrically connected to the first clock signal line CK, the second clock signal line CKB, the high-level signal line VGH, and the low-level signal line VGL respectively; step 200, performing graded potential control of the GOA circuit according to the clock signal and pulse signal provided by the timing controller 10 and using the level control module 20.

[0080] Preferably, such as Figure 5 , Figure 5 This is a second schematic diagram of the low-power driving method of the present invention; step 100 includes: step 110, electrically connecting the first end of the forward and reverse scan unit to the forward scan signal line FW, the reverse scan signal line BW, and the start signal line STV respectively, and electrically connecting the second end to the first end of the latch shift unit, and electrically connecting the second end of the latch shift unit to the first end of the buffer output unit; step 120, electrically connecting the second end of the buffer output unit to the first clock signal line CK, the second clock signal line CKB, the high-level signal line VGH, and the low-level signal line VGL respectively; wherein, the GOA circuit includes the forward and reverse scan unit, the latch shift unit, and the buffer output unit.

[0081] Preferably, such as Figure 6 , Figure 6 This is a third schematic diagram of the low-power driving method in this invention; step 100 further includes: step 130, electrically connecting the second end of the nth stage latch shift unit, the first end of the nth stage buffer output unit, and the first end of the (n+1)th stage forward and reverse scan unit; step 140, connecting the third end of the nth stage forward and reverse scan unit together with the second end of the (n+1)th stage latch shift unit and the first end of the (n+1)th stage buffer output unit.

[0082] Preferably, such as Figure 7 , Figure 7 This is a fourth schematic diagram of the low-power driving method in this invention; step 100 further includes: step 150, acquiring forward and reverse scan signals using a forward and reverse scan unit and outputting them to a latch shift unit; step 160, latching and shifting the forward and reverse scan signals using a latch shift unit, and simultaneously transmitting them to the forward and reverse scan unit of the next stage GOA circuit; step 170, buffering and amplifying the signal obtained by the latch shift unit using a buffer output unit, and outputting Gout to the display area to drive the transistor to turn on and off.

[0083] Preferably, such as Figure 8 , Figure 8 This is a fifth schematic diagram of the low-power driving method in this invention. Step 200 includes: Step 210, adjusting the potentials of the forward and reverse scan unit and the latch shift unit between the first low level AVEE and the first high level AVDD; Step 220, adjusting the potential of the buffer output unit between the second low level VGL and the second high level VGH; wherein, the first low level AVEE is greater than the second low level VGL, and the first high level AVDD is less than the second high level VGH.

[0084] Example 3

[0085] Thirdly, a low-power display screen includes the driving circuit of the first aspect and drives the GOA circuit using the driving method of the second aspect.

[0086] The present invention provides a low-power driving circuit, method, and display screen. By performing graded potential control on the GOA circuit, the potentials of the forward and reverse scan units and the latch shift unit in the GOA circuit are adjusted between a first low level and a first high level, and the potential of the buffer output unit is adjusted between a second low level and a second high level. This reduces the potential of some units in the GOA circuit, thereby reducing the overall power consumption of the display screen and improving the display quality.

[0087] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A low-power driving circuit, characterized in that, include: N-level GOA circuit; Timing controller; Level control module; The timing controller is electrically connected to the level control module; The level control module is electrically connected to each stage of the GOA circuit; The GOA circuits are cascaded in sequence, and the first terminal of the GOA circuit is electrically connected to the forward scan signal line, the reverse scan signal line, and the start signal line, respectively. The second terminal of the GOA circuit is electrically connected to the first clock signal line, the second clock signal line, the high-level signal line, and the low-level signal line, respectively. The level control module is used to perform graded level control on the GOA circuit according to the clock signal and pulse signal provided by the timing controller; The GOA circuit includes: Forward and reverse scanning units; Latch shift unit; and buffered output unit; The forward and reverse scan unit is used to control the forward or reverse scan of the GOA circuit, inputting a start signal and outputting it to the latch shift unit; The latch shift unit is used to latch and shift the signal output by the forward and reverse scan unit, and at the same time pass it to the forward and reverse scan unit module of the next stage GOA circuit; The buffer output unit is used to buffer and amplify the signal obtained by the latch shift unit, and output Gout to the display area to drive the transistor to turn on and off. The first end of the forward and reverse scan unit is electrically connected to the forward scan signal line, the reverse scan signal line, and the start signal line, respectively. The second end is electrically connected to the first end of the latch shift unit. The second end of the latch shift unit is electrically connected to the first end of the buffer output unit. The second end of the buffer output unit is electrically connected to the first clock signal line, the second clock signal line, the high-level signal line, and the low-level signal line, respectively. The cascade relationship between the nth and (n+1)th GOA circuits of the display driver circuit is as follows: The second terminal of the nth stage latch shift unit, the first terminal of the nth stage buffer output unit, and the first terminal of the (n+1)th stage forward and reverse scan unit are electrically connected. The third terminal of the nth-level forward and reverse scan unit is connected to the second terminal of the (n+1)th-level latch shift unit and the first terminal of the (n+1)th-level buffer output unit. The graded potential control includes: The potentials of the forward and reverse scan units and the latch shift unit are adjusted between the first low level and the first high level; Adjust the potential of the buffer output unit between the second low level and the second high level; Wherein, the first low level is greater than the second low level, and the first high level is less than the second high level.

2. A low-power display screen driving method, employing the driving circuit described in claim 1, characterized in that, include: Step 100: Electrically connect the timing controller to the level control module, electrically connect the level control module to each stage of the GOA circuit, and cascade the GOA circuits in sequence. The first terminal of the GOA circuit is electrically connected to the forward scan signal line, the reverse scan signal line, and the start signal line, respectively. The second terminal of the GOA circuit is electrically connected to the first clock signal line, the second clock signal line, the high-level signal line, and the low-level signal line, respectively. Step 200: Perform graded potential control on the GOA circuit based on the clock signal and pulse signal provided by the timing controller and using the level control module; Step 100 includes: Step 110: Electrically connect the first end of the forward and reverse scan unit to the forward scan signal line, the reverse scan signal line, and the start signal line, respectively; electrically connect the second end to the first end of the latch shift unit; and electrically connect the second end of the latch shift unit to the first end of the buffer output unit. Step 120: Electrically connect the second terminal of the buffer output unit to the first clock signal line, the second clock signal line, the high-level signal line, and the low-level signal line, respectively; The GOA circuit includes a forward and reverse scan unit, a latch shift unit, and a buffer output unit. Step 100 further includes: Step 130: Electrically connect the second terminal of the nth stage latch shift unit, the first terminal of the nth stage buffer output unit, and the first terminal of the (n+1)th stage forward and reverse scan unit; Step 140: Connect the third terminal of the nth-level forward and reverse scan unit to the second terminal of the (n+1)th-level latch shift unit and the first terminal of the (n+1)th-level buffer output unit. Step 100 further includes: Step 150: Use the forward and reverse scanning unit to acquire forward and reverse scanning signals and output them to the latch shift unit; Step 160: Use the latch shift unit to latch and shift the forward and reverse scan signals, and simultaneously transmit them to the forward and reverse scan unit of the next stage GOA circuit; Step 170: Buffer and amplify the signal obtained from the latch shift unit using the buffer output unit, and output Gout to the display area to drive the transistor to turn on and off; Step 200 includes: Step 210: Adjust the potential of the forward and reverse scan unit and the latch shift unit between the first low level and the first high level; Step 220: Adjust the potential of the buffer output unit between the second low level and the second high level; Wherein, the first low level is greater than the second low level, and the first high level is less than the second high level.

3. A low-power display screen, characterized in that, It includes the driving circuit as described in claim 1, and is driven by the driving method as described in claim 2.

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