Pulse width modulation based voltage regulation circuit

Abstract

This invention discloses a voltage regulation circuit based on pulse width modulation (PWM), comprising: a first voltage-to-current conversion circuit for converting a reference voltage into a reference current; a second voltage-to-current conversion circuit for converting a first input voltage into a first input current; a third voltage-to-current conversion circuit for converting a second input voltage into a second input current, wherein the ratio of the second input voltage to the first input voltage is the duty cycle represented by a square wave signal; a current subtractor for obtaining the difference current between the first input current and the second input current; a current calculation circuit for performing calculations on the reference current, the difference current, and the second input current; and a current-to-voltage conversion circuit for converting the output current of the current calculation circuit into a voltage. The voltage regulation circuit of this invention can simultaneously achieve boost, buck, and buck-boost regulation functions without requiring additional hardware or circuit design, which is beneficial for improving circuit flexibility.

Description

Technical Field

[0001] This invention relates to the field of voltage control technology, and more specifically to a voltage regulation circuit based on pulse width modulation. Background Technology

[0002] In modern electronic applications, pulse width modulation (PWM) technology is widely used in voltage regulation and control of electronic devices. However, traditional voltage output control methods typically require the use of switching and inductor elements to transfer and store power, thereby regulating the output voltage. However, these solutions may be limited by inductor size, cost, and energy loss, failing to achieve dynamic regulation and efficient energy conversion.

[0003] To address these issues, some existing technologies attempt to convert square wave signals into analog voltages using components such as proportional-integral (PI) converters and amplifiers to regulate the output voltage. For example, existing solutions use a PI converter to integrate the input PWM signal, obtaining a voltage proportional to the input signal's duty cycle D. The integrator's output voltage is then compared to a reference voltage VREF. The comparator's output controls a switching element connected to the PI converter, thus stabilizing the integrator's output voltage at the value of VREF / D based on the comparator's output level. Ultimately, this method achieves dynamic regulation of the output voltage based on the duty cycle of the input square wave signal.

[0004] However, these existing methods may be limited by issues such as circuit complexity, accuracy loss, and energy waste, especially in applications requiring high precision and efficiency. Furthermore, existing solutions can only regulate the output voltage in one direction (e.g., boost or buck regulation) based on the duty cycle of the input pulse, and cannot simultaneously achieve buck-boost regulation. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a voltage regulation circuit based on pulse width modulation, which can simultaneously realize the regulation functions of boost, buck, and buck-boost based on the duty cycle of square wave signal, can flexibly cope with different application scenarios, and does not require additional hardware or circuit design.

[0006] According to one aspect of the present invention, a voltage regulation circuit based on pulse width modulation is provided, comprising: a first voltage-to-current conversion circuit for converting a reference voltage into a reference current linearly related thereto; a second voltage-to-current conversion circuit for converting a first input voltage into a first input current linearly related thereto, the first input voltage having a voltage value corresponding to the period time of a square wave signal; a third voltage-to-current conversion circuit for converting a second input voltage into a second input current linearly related thereto, the second input voltage having a voltage value corresponding to the high-level time of the square wave signal, the ratio of the second input voltage to the first input voltage being the duty cycle represented by the square wave signal; a current subtractor for obtaining the difference current between the first input current and the second input current; a current calculation circuit for performing calculations on the reference current, the difference current, and the second input current to obtain an output current; and a current-to-voltage conversion circuit for converting the output current into an output voltage.

[0007] Optionally, the current calculation circuit is configured to obtain the output current according to the following formula: Iout = Iref × (It - Iton) ÷ Iton, where Iout represents the output current, Iref represents the reference current, It represents the first input current, and Iton represents the second input current.

[0008] Optionally, the first voltage-to-current conversion circuit includes: a first transistor; a first resistor, with a first terminal connected to the first transistor and a second terminal connected to ground; a first operational amplifier, with its non-inverting input terminal connected to the reference voltage, its inverting input terminal connected to the common node of the first transistor and the first resistor, and its output terminal connected to the control terminal of the first transistor, the first operational amplifier being used to generate the reference current in the first transistor based on the reference voltage and the resistance value of the first resistor; and a first current mirror circuit, connected to the first terminal of the first transistor, for outputting the reference current to the current calculation circuit. The second voltage-to-current conversion circuit includes: a second transistor; a second resistor, with a first terminal connected to the second transistor and a second terminal connected to ground; a second operational amplifier, with its non-inverting input terminal connected to the first input voltage, its inverting input terminal connected to the common node of the second transistor and the second resistor, and its output terminal connected to the control terminal of the second transistor, the second operational amplifier being used to generate the first input current in the second transistor based on the first input voltage and the resistance value of the second resistor, the current subtractor being connected to the second current mirror circuit. The second current mirror circuit receives the first input current and the second input current at its current input terminal, and outputs the difference current between them to the current calculation circuit. The third voltage-to-current conversion circuit includes: a third transistor; a third resistor, with its first terminal connected to the third transistor and its second terminal connected to ground; a third operational amplifier, with its non-inverting input terminal connected to the second input voltage, its inverting input terminal connected to the common node of the third transistor and the third resistor, and its output terminal connected to the control terminal of the third transistor. The third operational amplifier is used to generate the second input current in the third transistor based on the second input voltage and the resistance value of the third resistor; and a third current mirror circuit connected to the first terminal of the third transistor, which outputs the second input current to the current subtractor and the current calculation circuit. The current-to-voltage conversion circuit includes: an eighth current mirror circuit; and a fourth resistor, with its first terminal connected to the eighth current mirror circuit and its second terminal connected to ground. The eighth current mirror circuit mirrors the output current onto the fourth resistor to generate the output voltage at their common node.

[0009] Optionally, the current calculation circuit includes: a first bipolar transistor, whose first terminal is connected to the reference current and whose second terminal is connected to ground; a second bipolar transistor, whose first terminal is connected to the differential current and whose second terminal is connected to the control terminal and the first bias current of the first bipolar transistor; a third bipolar transistor, whose first terminal is connected to the second input current, whose second terminal is connected to the second bias current, and whose control terminal is connected to the control terminal of the second bipolar transistor; a fourth bipolar transistor, whose first terminal is used to provide the output current, whose control terminal is connected to the second terminal and the second bias current of the third transistor, and whose second terminal is connected to ground; a fourth transistor, whose first terminal is connected to the power supply voltage, whose control terminal is connected to the first terminal of the first bipolar transistor, and whose second terminal is connected to the control terminal of the first bipolar transistor, the fourth transistor being used to provide voltage bias to the first bipolar transistor; and a fifth transistor, whose control terminal is connected to the first terminal of the second bipolar transistor, and whose second terminal is connected to the control terminal of the second bipolar transistor. The system comprises: a fourth current mirror circuit, whose current input terminal is connected to the first terminal of the fifth transistor, and whose current output terminal is used to feed back the control terminal current of the second bipolar transistor; a fifth current mirror circuit, connected to the differential current, the current output terminal of the fourth current mirror circuit, and the second terminal of the second bipolar transistor, used to obtain the first bias current based on the sum of the differential current and the control terminal current of the second bipolar transistor; a sixth transistor, whose control terminal is connected to the first terminal of the third bipolar transistor, and whose second terminal is connected to the control terminal of the third bipolar transistor; a sixth current mirror circuit, whose current input terminal is connected to the first terminal of the sixth transistor, and whose current output terminal is used to feed back the control terminal current of the third bipolar transistor; and a seventh current mirror circuit, connected to the second input current, the current output terminal of the sixth current mirror circuit, and the second terminal of the third bipolar transistor, used to obtain the second bias current based on the sum of the second input current and the control terminal current of the third bipolar transistor.

[0010] Optionally, the current operation circuit further includes: a fourth operational amplifier, whose non-inverting input terminal is connected to the second terminal of the third bipolar transistor, and whose inverting input terminal and output terminal are connected to the control terminal of the fourth bipolar transistor, the fourth operational amplifier being used to form a first voltage follower between the third bipolar transistor and the fourth bipolar transistor.

[0011] Optionally, it further includes: a square wave to voltage converter circuit, used to convert the square wave signal into the first input voltage and the second input voltage, the square wave signal having adjacent sampling periods and holding periods, wherein the square wave to voltage converter circuit includes: a ramp voltage generation module, used to generate a linearly rising ramp voltage signal during the sampling period of the square wave signal; a first sample-and-hold module, used to sample the ramp voltage signal during the sampling period of the square wave signal to obtain a first sampled voltage signal, wherein the sampling duration of the first sample-and-hold module is equal to the time of the sampling period; a second sample-and-hold module, used to sample the ramp voltage signal during the sampling period of the square wave signal to obtain a second sampled voltage signal, wherein the sampling duration of the second sample-and-hold module is equal to the high-level time of the square wave signal; and an output module, used to obtain the first input voltage based on the first sampled voltage signal and the second input voltage based on the second sampled voltage signal after a preset time following the end of the sampling period of the square wave signal.

[0012] Optionally, the ramp voltage generation module is further configured to reset the ramp voltage signal to the reference ground during the hold period of the square wave signal, and the first sample hold module and the second sample hold module are further configured to hold the first sample voltage signal and the second sample voltage signal during the hold period of the square wave signal.

[0013] Optionally, the square wave to voltage converter further includes: a logic control module, configured to generate first to fourth control signals based on the square wave signal, wherein the first control signal is used to control the operation of the ramp voltage generation module, and the first control signal has an invalid control level corresponding to the sampling period of the square wave signal and an valid control level corresponding to the hold period of the square wave signal; a second control signal is used to control the operation of the first sample-and-hold module, and the second control signal has an valid control level corresponding to the sampling period of the square wave signal and an invalid control level corresponding to the hold period of the square wave signal; a third control signal is used to control the operation of the second sample-and-hold module, and the third control signal has an valid control level corresponding to the high level time of the sampling period of the square wave signal and an invalid control level corresponding to the low level time of the sampling period of the square wave signal and the hold period; and a fourth control signal is used to control the operation of the output module, and the fourth control signal is a narrow pulse signal.

[0014] Optionally, the ramp voltage generating module includes: a current source and a first capacitor connected in series between the power supply voltage and ground; a first switch connected in parallel between the two ends of the first capacitor, and the first control signal is applied to the control terminal of the first switch; and a second voltage follower, the input terminal of which is connected to the common node of the current source and the first capacitor, and the output terminal of which is used to output the ramp voltage signal. The ramp voltage generating module is configured to turn off the first switch during the invalid control level phase of the first control signal to generate the linearly rising ramp voltage signal, and to turn on the first switch during the valid control level phase of the first control signal to generate the ramp voltage signal. Reset to ground, the first sample-and-hold module includes: a second switch and a second capacitor connected in series between the ramp voltage signal and ground, and the second control signal is applied to the control terminal of the second switch; and a third voltage follower, the input of which is connected to the common node of the second switch and the second capacitor, and the output of which is used to output the first sampled voltage signal. The first sample-and-hold module is configured to turn on the second switch during the valid control level phase of the second control signal to sample the ramp voltage signal, and to turn off the second switch during the invalid control level phase of the second control signal to hold the first sampled voltage signal. The module includes: a third switch and a third capacitor connected in series between the ramp voltage signal and ground, and the third control signal is applied to the control terminal of the third switch; and a fourth voltage follower, the input of which is connected to the common node of the third switch and the third capacitor, and the output of which is used to output the second sampled voltage signal. The second sample-and-hold module is used to turn on the third switch during the valid control level phase of the third control signal to sample the ramp voltage signal, and to turn off the third switch during the invalid control level phase of the third control signal to hold the second sampled voltage. The output module includes: a third switch connected in series with the first sampled voltage signal... A fourth switch and a fourth capacitor are connected between the second sampled voltage signal and ground, and their common node is used to output the first input voltage; and a fifth switch and a fifth capacitor are connected in series between the second sampled voltage signal and ground, and their common node is used to output the second input voltage, wherein the fourth control signal is applied to the control terminals of the fourth switch and the fifth switch, and the logic control module includes: a first D flip-flop, whose clock terminal is used to receive the square wave signal, whose data terminal is connected to the second output terminal, and whose first output terminal is used to output the first control signal; a second D flip-flop, whose clock terminal is used to receive the square wave signal, and whose data terminal is connected to the data terminal and the second output terminal of the first D flip-flop;A first inverter is connected to the first output of the second D flip-flop, and the first inverter is used to provide the second control signal based on the output of the second D flip-flop; a third D flip-flop has its clock terminal used to receive the inverted square wave signal, and its data terminal connected to the first output of the first D flip-flop; an AND gate circuit has its first input terminal connected to the second control signal, and its second input terminal connected to the first output of the third D flip-flop, and the AND gate circuit is used to provide the third control signal based on the second control signal and the output of the third D flip-flop; a first buffer has its input terminal connected to the first output of the first D flip-flop; and a narrow pulse module has its input connected to the output of the first buffer, and is used to generate the fourth control signal based on the output of the first buffer.

[0015] Optionally, the first D flip-flop and the third D flip-flop further include an enable setting terminal for receiving an enable signal. The voltage regulation circuit further includes a second buffer connected between the square wave signal and the clock terminal of the first D flip-flop. The logic control module further includes a delay module connected to the second output terminal and the enable / reset terminal of the second D flip-flop. The delay module is used to reset the second D flip-flop according to the output of the second D flip-flop.

[0016] In summary, the voltage regulation circuit of this invention can dynamically adjust the output voltage based on the pulse width of a square wave signal, exhibiting a fast response speed. Furthermore, this voltage regulation circuit can simultaneously achieve boost, buck, and buck-boost adjustments based on the duty cycle of the square wave signal. Compared to traditional circuits that can only achieve single-direction adjustment, this voltage regulation circuit offers greater flexibility, adapting to different application scenarios without requiring additional hardware or circuit design. Moreover, compared to needing to design two separate boost or buck circuits, this voltage regulation circuit saves costs and occupies less circuit space, contributing to reduced cost and size of electronic devices. Attached Figure Description

[0017] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings.

[0018] Figure 1 A schematic structural diagram of a voltage regulation circuit based on pulse width modulation according to a first embodiment of the present invention is shown.

[0019] Figure 2 A schematic circuit diagram of a first voltage-to-current conversion circuit in a voltage regulation circuit according to a first embodiment of the present invention is shown.

[0020] Figure 3A schematic circuit diagram of a second voltage-to-current conversion circuit and a current subtractor in a voltage regulation circuit according to a first embodiment of the present invention is shown.

[0021] Figure 4 A schematic circuit diagram of a third voltage-to-current conversion circuit in a voltage regulation circuit according to a first embodiment of the present invention is shown.

[0022] Figure 5 A schematic circuit diagram of the current calculation circuit in the voltage regulation circuit according to the first embodiment of the present invention is shown.

[0023] Figure 6 A schematic circuit diagram of a current-to-voltage conversion circuit in a voltage regulation circuit according to a first embodiment of the present invention is shown.

[0024] Figure 7 A schematic circuit diagram of a square wave to voltage converter according to a second embodiment of the present invention is shown.

[0025] Figure 8 A schematic circuit diagram of a logic control module in a square wave to voltage converter circuit according to a second embodiment of the present invention is shown.

[0026] Figure 9 A schematic waveform diagram of a square wave to voltage converter circuit according to a second embodiment of the present invention is shown. Detailed Implementation

[0027] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown in the drawings.

[0028] Many specific details of the invention, such as the structure, materials, dimensions, processing methods, and techniques of the components, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0029] It should be understood that, in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by an electrical or electromagnetic link. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to the other element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0030] Figure 1A schematic structural diagram of a voltage regulation circuit based on pulse width modulation according to a first embodiment of the present invention is shown. Figure 1 As shown, the voltage regulation circuit 100 includes: a first voltage-to-current conversion circuit 110, a second voltage-to-current conversion circuit 120, a third voltage-to-current conversion circuit 130, a current calculation circuit 140, a current-to-voltage conversion circuit 150, and a current subtractor 160. The first voltage-to-current conversion circuit 110 converts a reference voltage Vref into a linearly related reference current Iref. The second voltage-to-current conversion circuit 120 converts a first input voltage Vt into a linearly related first input current It, where the first input voltage Vt has a voltage value corresponding to the period of a square wave signal PWM. The third voltage-to-current conversion circuit 130 converts a second input voltage Vton into a linearly related second input current Iton, where the second input voltage Vton has a voltage value corresponding to the high-level time of the square wave signal, and the ratio of the second input voltage Vton to the first input voltage Vt is the duty cycle represented by the square wave signal PWM. The current subtractor 160 obtains the difference current It-Iton between the first input current It and the second input current Iton. The current calculation circuit 140 is used to calculate the reference current Iref, the difference current It-Iton, and the second input current Iton to obtain the output current Iout. The current-to-voltage conversion circuit 150 is used to convert the output current Iout into the output voltage Vout.

[0031] For example, the current calculation circuit 140 of this embodiment can implement multiplication, division, and other arithmetic functions. Further, the current calculation circuit 140 is exemplarily a multiplication and division arithmetic circuit.

[0032] The voltage regulation circuit 100 in this embodiment works as follows: It converts a square wave signal PWM into a first input voltage Vt and a second input voltage Vton. The first input voltage Vt has a voltage value corresponding to the period of the square wave signal PWM, and the second input voltage Vton has a voltage value corresponding to the high-level time of the square wave signal PWM. The specific conversion process will be described below. The ratio of the second input voltage Vton to the first input voltage Vt is equal to the duty cycle D of the square wave signal PWM, i.e., Vton / Vt = D. Then, the first input voltage Vt and the second input voltage Vton are converted into a first input current It and a second input current Iton through the second voltage-to-current conversion circuit 120 and the third voltage-to-current conversion circuit 130, respectively. The ratio of the second input current Iton to the first input current It is equal to the duty cycle D of the square wave signal PWM, i.e., Iton / It = D.

[0033] Simultaneously, the reference voltage Vref is converted into a unified reference current Iref by the first voltage-to-current conversion circuit 110 for convenient subsequent processing. Then, the difference It-Iton between the first input current It and the second input current Iton is obtained by the current subtractor 160. Finally, the reference current Iref, the difference current It-Iton, and the second input current Iton are provided to the current calculation circuit 140 for calculation to obtain the output current. Finally, the current-to-voltage conversion circuit 150 converts the obtained output current Iout into the output voltage Vout, resulting in... Therefore, the output voltage Vout can be dynamically adjusted based on the pulse width of the square wave signal PWM. When the duty cycle D of the square wave signal PWM is less than 50%, the voltage regulation circuit 100 of this embodiment can obtain an output voltage Vout greater than the reference voltage Vref, that is, realize boost regulation. When the duty cycle of the square wave signal PWM is greater than 50%, the voltage regulation circuit 100 of this embodiment can obtain an output voltage Vout less than the reference voltage Vref, that is, realize buck regulation.

[0034] It should be noted that the input signal of the voltage regulation circuit 100 in this embodiment is not only the reference voltage Vref and the square wave signal PWM with a duty cycle of D, but also the reference current Iref and the square wave signal PWM with a duty cycle of D. In this case, the input reference current Iref does not need to go through the voltage-to-current conversion circuit and can be directly input to the current calculation circuit 140.

[0035] Figure 2 A schematic circuit diagram of the first voltage-to-current conversion circuit 110 in the voltage regulation circuit 100 according to a first embodiment of the present invention is shown. Figure 2 As shown, the first voltage-to-current conversion circuit 110 of this embodiment includes a transistor Mn1, an operational amplifier Amp1, a resistor R1, and a current mirror circuit 101. The non-inverting input of the operational amplifier Amp1 is connected to the reference voltage Vref, the inverting input of the operational amplifier Amp1 is connected to the source of the transistor Mn1 and the first terminal of the resistor R1, the second terminal of the resistor R1 is connected to ground, and the output of the operational amplifier Amp1 is connected to the gate of the transistor Mn1. In this embodiment, the transistor Mn1 is an N-type MOSFET. In this embodiment, the voltage can be converted into corresponding current information through the buffer structure formed by the operational amplifier Amp1 and the N-type MOSFET Mn1. In this embodiment, the operational amplifier Amp1 is used to clamp the reference voltage Vref onto the resistor R1 to obtain a reference current Iref, which can be expressed by the following formula:

[0036]

[0037] A current mirror circuit 101 is connected to the drain of transistor Mn1 and is used to mirror the reference current Iref to the current calculation circuit 140. The current mirror circuit 101 includes transistors Mp1 and Mp2. In this embodiment, transistors Mp1 and Mp2 are, for example, P-type MOSFETs. The sources of transistors Mp1 and Mp2 are connected to the power supply voltage Vdd. The gates of transistors Mp1 and Mp2 are connected to each other and to the drain of transistor Mp1. The drain of transistor Mp1 is also connected to the drain of transistor Mn1. The drain of transistor Mp2 is connected to the current calculation circuit 140 to output the reference current Iref.

[0038] Figure 3 A schematic circuit diagram of the second voltage-to-current conversion circuit 120 and the current subtractor 160 in the voltage regulation circuit 100 according to a first embodiment of the present invention is shown. Figure 3 As shown, the second voltage-to-current conversion circuit 120 in this embodiment includes a transistor Mn2, an operational amplifier Amp2, and a resistor R2. The non-inverting input terminal of the operational amplifier Amp2 is connected to the first input voltage Vt. The inverting input terminal of the operational amplifier Amp2 is connected to the source of the transistor Mn2 and the first terminal of the resistor R2. The second terminal of the resistor R2 is connected to ground. The output terminal of the operational amplifier Amp2 is connected to the gate of the transistor Mn2. In this embodiment, the transistor Mn2 is an N-type MOSFET. In this embodiment, the voltage can be converted into corresponding current information through the buffer structure formed by the operational amplifier Amp2 and the N-type MOSFET Mn2. In this embodiment, the operational amplifier Amp2 clamps the first input voltage Vt across the resistor R2 to obtain the first input current It, which can be expressed by the following formula:

[0039]

[0040] Furthermore, the current subtractor 160 in this embodiment can be implemented, for example, by a current mirror circuit, such as... Figure 3As shown, the current subtractor 160 includes transistors Mp3 to Mp5, which are, for example, P-type MOSFETs. The sources of transistors Mp3 to Mp5 are connected to the power supply voltage Vdd, and the gates of transistors Mp3 to Mp5 are connected to each other and to the drain of transistor Mp3. The drain of transistor Mp3 serves as the current input terminal of a current mirror circuit, connected to the first input current It and the second input current Iton. The drains of transistors Mp4 and Mp5 serve as the current output terminals of the current mirror circuit, providing the difference current It-Iton between the first input current It and the second input current Iton to the current calculation circuit 140.

[0041] Figure 4 A schematic circuit diagram of a third voltage-to-current conversion circuit 130 in a voltage regulation circuit 100 according to a first embodiment of the present invention is shown. Similarly, the third voltage-to-current conversion circuit 130 of this embodiment includes a transistor Mn10, an operational amplifier Amp3, a resistor R3, and a current mirror circuit 103. The non-inverting input terminal of the operational amplifier Amp3 is connected to the second input voltage Vton, the inverting input terminal of the operational amplifier Amp3 is connected to the source of the transistor Mn10 and the first terminal of the resistor R3, the second terminal of the resistor R3 is connected to ground, and the output terminal of the operational amplifier Amp3 is connected to the gate of the transistor Mn10. In this embodiment, the transistor Mn10 is an N-type MOSFET. In this embodiment, the voltage can be converted into corresponding current information through the buffer structure formed by the operational amplifier Amp3 and the N-type MOSFET Mn10. In this embodiment, the operational amplifier Amp3 is used to clamp the second input voltage Vton onto the resistor R3 to obtain a reference current Iref, wherein the reference current Iref can be expressed by the following formula:

[0042]

[0043] A current mirror circuit 103 is connected to the drain of transistor Mn10 and is used to mirror the second input current Iton to the current subtractor 160 and the current calculation circuit 140. The current mirror circuit 103 includes transistors Mp10 to Mp13. In this embodiment, transistors Mp10 to Mp13 are, for example, P-type MOSFETs. The sources of transistors Mp10 to Mp13 are connected to the power supply voltage Vdd. The gates of transistors Mp10 to Mp13 are connected to each other and to the drain of transistor Mp13. The drain of transistor Mp13 is also connected to the drain of transistor Mn10. The drain of transistor Mp10 is connected to the current subtractor 160 to output the second input current Iton. The drains of transistors Mp11 and Mp12 are connected to the current calculation circuit 140 to output the second input current Iton.

[0044] Figure 5 A schematic circuit diagram of the current calculation circuit 140 in the voltage regulation circuit 100 according to a first embodiment of the present invention is shown. Figure 5 As shown, the current calculation circuit 140 of this embodiment includes bipolar transistors Qn1 to Qn4, which are, for example, NPN bipolar transistors, wherein the current I... Q1 to I Q4 These are the collector currents of bipolar transistors Qn1 through Qn4. The collector of bipolar transistor Qn1 is connected to the reference current Iref, the emitter of bipolar transistor Qn1 is connected to ground, and the base of bipolar transistor Qn1 is connected to the emitter of bipolar transistor Qn2 and a bias current. The collector of bipolar transistor Qn2 is connected to the differential current It-Iton, the base of bipolar transistor Qn2 is connected to the base of bipolar transistor Qn3, the collector of bipolar transistor Qn3 is connected to the second input current Iton, the emitter of bipolar transistor Qn3 is connected to another bias current and the base of bipolar transistor Qn4, the emitter of bipolar transistor Qn4 is connected to ground, and the collector of bipolar transistor Qn4 is used to provide the output current Iout.

[0045] Based on the closed loop formed by bipolar transistors Qn1 to Qn4, and using Kirchhoff's voltage law, the following relationship can be obtained:

[0046] V be1 +V be2 =V be3 +V be4 (4)

[0047] Among them, V be1 -V be4Let Qn1 to Qn4 represent the base-emitter voltages of bipolar transistors, respectively. Based on the IV characteristics of bipolar transistors, we can obtain:

[0048]

[0049] Where VT is the thermal voltage of the transistor, and I C It is the collector current of the transistor, I. S Given the reverse saturation current of the transistor, we can obtain the following by combining formulas (4) and (5):

[0050]

[0051] By simplifying formula (6), we can obtain:

[0052] I Q1 ×I Q2 =I Q3 ×I Q4 (7)

[0053] And because:

[0054]

[0055]

[0056]

[0057]

[0058] Substituting the above current relationship into formula (7) yields:

[0059]

[0060] If the resistance values ​​of resistors R1 to R4 are equal, then formula (8) can be simplified to:

[0061] V ref ×(V t ―V ton ) = V ton ×V out

[0062]

[0063]

[0064]

[0065] Therefore, the output voltage Vout can be dynamically adjusted based on the pulse width of the square wave signal PWM. When the duty cycle D of the square wave signal PWM is less than 50%, the voltage regulation circuit 100 of this embodiment can obtain an output voltage Vout greater than the reference voltage Vref, that is, realize boost regulation. When the duty cycle of the square wave signal PWM is greater than 50%, the voltage regulation circuit 100 of this embodiment can obtain an output voltage Vout less than the reference voltage Vref, that is, realize buck regulation.

[0066] In addition, the current calculation circuit 140 of this embodiment also includes transistors Mn3, Mn6, and Mn7, current mirror circuits 104 to 107, and operational amplifier Amp4.

[0067] In this configuration, transistor Mn3 is connected between the power supply voltage Vdd and the base of bipolar transistor Qn1. Transistor Mn3 is, for example, an N-type MOSFET, with its gate connected to the collector of bipolar transistor Qn1, its drain connected to the power supply voltage Vdd, and its source connected to the base of bipolar transistor Qn1. Transistor Mn3 provides a voltage bias to bipolar transistor Qn1, enabling Qn1 to operate normally.

[0068] Transistor Mn6 is connected between the collector and base of bipolar transistor Qn2. Transistor Mn6 is, for example, an N-type MOSFET, with its gate connected to the collector of bipolar transistor Qn2 and its source connected to the base of bipolar transistor Qn2. Current mirror circuit 106 is connected to the drain of transistor Mn6 and is used to feedback the base current of bipolar transistor Qn2. Current mirror circuit 106 includes transistors Mp6 and Mp7, which are, for example, P-type MOSFETs. The sources of transistors Mp6 and Mp7 are connected to the power supply voltage Vdd. The gates of transistors Mp6 and Mp7 are connected to each other and to the drain of transistor Mp6. The drain of transistor Mp6 serves as the current input terminal of current mirror circuit 106 and is connected to the drain of transistor Mn6. The drain of transistor Mp7 serves as the current output terminal of current mirror circuit 106 and is used to output the base current of bipolar transistor Qn2. The current mirror circuit 104 is used to obtain the bias current supplied to the emitter of the bipolar transistor Qn2 based on the differential current It-Iton and the base current of the bipolar transistor Qn2. The current mirror circuit 104 includes transistors Mn4 and Mn5, which are, for example, N-type MOSFETs. The sources of transistors Mn4 and Mn5 are connected to ground, and their gates are connected to each other and to the drain of transistor Mn4. The drain of transistor Mn4 is also connected to the differential current It-Iton and the base current of the bipolar transistor Qn2. The drain of transistor Mn5 is connected to the emitter of the bipolar transistor Qn2 to provide the bias current to it.

[0069] Transistor Mn7 is connected between the collector and base of bipolar transistor Qn3. Transistor Mn7 is, for example, an N-type MOSFET, with its gate connected to the collector of bipolar transistor Qn3 and its source connected to the base of bipolar transistor Qn3. Current mirror circuit 107 is connected to the drain of transistor Mn7 and is used to feedback the base current of bipolar transistor Qn3. Current mirror circuit 107 includes transistors Mp8 and Mp9, which are, for example, P-type MOSFETs. The sources of transistors Mp8 and Mp9 are connected to the power supply voltage Vdd. The gates of transistors Mp8 and Mp9 are connected to each other and to the drain of transistor Mp9. The drain of transistor Mp9 serves as the current input terminal of current mirror circuit 107 and is connected to the drain of transistor Mn7. The drain of transistor Mp8 serves as the current output terminal of current mirror circuit 107 and is used to output the base current of bipolar transistor Qn3. The current mirror circuit 105 is used to obtain the bias current supplied to the emitter of the bipolar transistor Qn3 based on the second input current Iton and the base current of the bipolar transistor Qn3. The current mirror circuit 105 includes transistors Mn8 and Mn9, which are, for example, N-type MOSFETs. The sources of transistors Mn8 and Mn9 are connected to ground, and their gates are connected to each other and to the drain of transistor Mn9. The drain of transistor Mn9 is also connected to the second input current Iton and the base current of the bipolar transistor Qn3. The drain of transistor Mn8 is connected to the emitter of the bipolar transistor Qn3 to provide the bias current thereto.

[0070] The non-inverting input of operational amplifier Amp4 is connected to the emitter of bipolar transistor Qn3, while the inverting input and output of operational amplifier Amp4 are connected to the base of bipolar transistor Qn4. Operational amplifier Amp4 serves as a voltage follower between bipolar transistors Qn3 and Qn4 to achieve isolation between them.

[0071] Figure 6 A schematic circuit diagram of a current-to-voltage conversion circuit 150 in a voltage regulation circuit 100 according to a first embodiment of the present invention is shown. Figure 6As shown, the current-to-voltage conversion circuit 150 of this embodiment includes a current mirror circuit 108 and a resistor R4. The current mirror circuit 108 is used to mirror the output current Iout onto the resistor R4 to generate the output voltage Vout at their common node. The current mirror circuit 108 includes transistors Mp14 and Mp15, which are, for example, P-type MOSFETs. The sources of transistors Mp14 and Mp15 are connected to the power supply voltage Vdd. The gates of transistors Mp14 and Mp15 are connected to each other and to the drain of transistor Mp14. The drain of transistor Mp14 is used to connect to the output current Iout. The drain of transistor Mp15 is connected to the first terminal of the resistor R4, the second terminal of the resistor R4 is grounded, and the common node of the drain of transistor Mp15 and the resistor R4 is used to provide the output voltage Vout.

[0072] Figure 7 A schematic circuit diagram of a square wave to voltage converter 200 according to a second embodiment of the present invention is shown. Figure 7 As shown, the present invention also provides a square wave to voltage converter 200 for converting a square wave signal PWM into a first input voltage Vt and a second input voltage Vton. This square wave to voltage converter 200 can be integrated into the voltage regulation circuit 100 of the first embodiment, or it can be located independently outside the voltage regulation circuit 100; the present invention does not impose any limitations on this.

[0073] refer to Figure 7The square wave to voltage converter 200 of this embodiment includes a ramp voltage generation module 210, a first sample-and-hold module 220, a second sample-and-hold module 230, an output module 240, and a logic control module 250. The square wave signal PWM in this embodiment has adjacent sampling and holding periods. The ramp voltage generation module 210 generates a linearly rising ramp voltage signal RAMP during the sampling period of the square wave signal PWM and resets the ramp voltage signal RAMP to reference ground during the holding period of the square wave signal PWM. The first sample-and-hold module 220 samples the ramp voltage signal RAMP during the sampling period of the square wave signal PWM to obtain a first sampled voltage signal Vt_h, wherein the sampling duration of the first sample-and-hold module 220 is equal to the time of the sampling period. The second sample-and-hold module 230 samples the ramp voltage signal RAMP during the sampling period of the square wave signal PWM to obtain a second sampled voltage signal Vton_h, wherein the sampling duration of the second sample-and-hold module 230 is equal to the high-level time of the square wave signal PWM. Furthermore, the first sample-and-hold module 220 and the second sample-and-hold module 230 also hold the first sampled voltage signal Vt_h and the second sampled voltage signal Vton_h during the hold period of the square wave signal PWM. The output module 240 is used to obtain the first input voltage Vt based on the first sampled voltage signal Vt_h and the second input voltage Vton based on the second sampled voltage signal Vton_h after a preset time delay after the end of the sampling period of the square wave signal PWM.

[0074] The working principle of the square wave to voltage converter 200 in this embodiment is as follows: By charging the capacitor with current, the high and low level logic signal (i.e., the square wave signal PWM) representing the duty cycle information is converted into a voltage signal on the capacitor. Then, the voltage on the capacitor is sampled and held at the rising and falling edges of the square wave signal PWM. The ratio of the sampled and held voltage signals is the duty cycle of the square wave signal PWM. Furthermore, the square wave to voltage converter 200 in this embodiment divides the continuous period of the square wave signal PWM into adjacent sampling and holding periods. It samples the voltage on the capacitor during the sampling period of the square wave signal PWM and holds the sampled voltage during the subsequent holding period. This provides a stable and accurate signal sampling, solves timing problems, provides a stable input for subsequent signal processing, and improves the efficiency of signal processing.

[0075] Based on the above working principle, such as Figure 7As shown, the logic control module 250 is used to generate first to fourth control signals ST1 to ST4 based on the square wave signal PWM. The first control signal ST1 controls the operation of the ramp voltage generation module 210, and has an invalid control level (e.g., logic low) corresponding to the sampling period of the square wave signal PWM and an valid control level (e.g., logic high) corresponding to the hold period of the square wave signal PWM. The second control signal ST2 controls the operation of the first sample-and-hold module 220, and has a valid control level (e.g., logic high) corresponding to the sampling period of the square wave signal PWM and an invalid control level (e.g., logic low) corresponding to the hold period of the square wave signal PWM. The third control signal ST3 controls the operation of the second sample-and-hold module 230, and has a valid control level (e.g., logic high) corresponding to the high-level time of the sampling period of the square wave signal PWM and an invalid control level (e.g., logic low) corresponding to the low-level time and hold period of the sampling period of the square wave signal PWM. The fourth control signal ST4 is used to control the operation of the output module 240, and the fourth control signal ST4 is a narrow pulse signal.

[0076] Furthermore, the ramp voltage generation module 210 includes a current source IBP, a capacitor C1, a switch S1, and an operational amplifier Amp5. The current source IBP and capacitor C1 are connected in series between the power supply voltage Vdd and ground. The first terminal of switch S1 is connected to the first terminal of capacitor C1, and the second terminal of switch S1 is connected to the second terminal of capacitor C1 and ground. The control terminal of switch S1 is used to apply the first control signal ST1. The non-inverting input terminal of operational amplifier Amp5 is connected to the common node of current source IBP and capacitor C1, and the inverting input terminal and output terminal of operational amplifier Amp5 are connected. Operational amplifier Amp5 forms a voltage follower structure, and the ramp voltage signal RAMP is output through the output terminal of operational amplifier Amp5. In this embodiment, the ramp voltage generation module 210 is used to turn off switch S1 during the invalid control level phase of the first control signal ST1 to generate the linearly rising ramp voltage signal RAMP, and to turn on switch S1 during the valid control level phase of the first control signal ST1 to reset the ramp voltage signal RAMP to ground.

[0077] The first sample-and-hold module 220 includes a switch S2, a capacitor C2, and an operational amplifier Amp6. Switch S2 and capacitor C2 are connected in series between the ramp voltage signal RAMP and ground, and the control terminal of switch S2 is used to apply the second control signal ST2. The non-inverting input terminal of operational amplifier Amp6 is connected to the common node of switch S2 and capacitor C2, and the inverting input terminal and output terminal of operational amplifier Amp6 are connected. Operational amplifier Amp6 forms a voltage follower structure, and the first sampled voltage signal Vt_h is output through the output terminal of operational amplifier Amp6. In this embodiment, the first sample-and-hold module 220 is used to turn on switch S2 during the valid control level phase of the second control signal ST2 to sample the ramp voltage signal RAMP, and to turn off switch S2 during the invalid control level phase of the second control signal ST2 to hold the first sampled voltage signal Vt_h.

[0078] The second sample-and-hold module 230 includes a switch S3, a capacitor C3, and an operational amplifier Amp7. Switch S3 and capacitor C3 are connected in series between the ramp voltage signal RAMP and ground, and the control terminal of switch S3 is used to apply the third control signal ST3. The non-inverting input terminal of operational amplifier Amp7 is connected to the common node of switch S3 and capacitor C3, and the inverting input terminal and output terminal of operational amplifier Amp7 are connected. Operational amplifier Amp7 forms a voltage follower structure, and the second sampled voltage signal Vton_h is output through the output terminal of operational amplifier Amp7. In this embodiment, the second sample-and-hold module 230 is used to turn on switch S3 during the valid control level phase of the third control signal ST3 to sample the ramp voltage signal RAMP, and to turn off switch S3 during the invalid control level phase of the third control signal ST3 to hold the second sampled voltage signal Vton_h.

[0079] The output module 240 includes switches S4 and S5, capacitor C4 and capacitor C5. Switch S4 and capacitor C4 are connected in series between the first sampled voltage signal Vt_h and ground, and their common node is used to output the first input voltage Vt. Switch S5 and capacitor C5 are connected in series between the second sampled voltage signal Vton_h and ground, and their common node is used to output the second input voltage Vton. A fourth control signal ST4 is applied to the control terminals of switches S4 and S5, and during the active level phase of the fourth control signal ST4, switches S4 and S5 are turned on to output the first input voltage Vt and the second input voltage Vton, respectively.

[0080] Figure 8 A schematic circuit diagram of the logic control module 250 in the square wave to voltage converter circuit 200 according to a second embodiment of the present invention is shown. Figure 8 This is one implementation of the logic control module 250 in this embodiment, but the implementation of the logic control module 250 of the present invention is not limited to this. Figure 8 .like Figure 8 As shown, the logic control module 250 of this embodiment includes D flip-flops DFF1 to DFF3, inverters INV1 and INV2, buffers BUF1 and BUF2, AND gate circuits, narrow pulse module 201, and delay module 202.

[0081] Among them, D flip-flops DFF1 to DFF3 all include a data terminal D, a clock terminal Clk, a first output terminal Q, and a second output terminal Q-. In addition, D flip-flops DFF1 and DFF3 also include an enable / set terminal Set, and D flip-flop DFF2 also includes an enable / reset terminal Reset.

[0082] In this embodiment, the clock terminal Clk of the D flip-flop DFF1 is connected to the square wave signal PWM through the buffer BUF1, its data terminal D is connected to the second output terminal Q-, its enable and set terminal Set is used to receive an enable signal EN, and its first output terminal Q is used to output the first control signal ST1.

[0083] The clock terminal Clk of D flip-flop DFF2 is used to receive the square wave signal PWM. Its data terminal D is connected to the data terminal D and the second output terminal Q of D flip-flop DFF1. Its first output terminal Q is connected to the input of inverter INV1. The output of inverter INV1 is used to provide the second control signal ST2.

[0084] The clock input Clk of the D flip-flop DFF3 is connected to the square wave signal PWM through the inverter INV2 to receive the inverted signal of the square wave signal PWM. Its data input D is connected to the first output Q of the D flip-flop DFF1. Its enable input Set is used to receive the enable signal EN. Its first output Q is connected to one input of the AND gate circuit. The other input of the AND gate circuit is also connected to the second control signal ST2. The AND gate circuit is used to provide the third control signal ST3 according to the second control signal ST2 and the output of the D flip-flop DFF3.

[0085] The input terminal of buffer BUF2 is connected to the first output terminal Q of the D flip-flop DFF1, and the output of buffer BUF2 is connected to the output of narrow pulse module 201. The narrow pulse module 201 is used to generate the fourth control signal ST4 according to the output of buffer BUF2.

[0086] The delay module 202 is connected between the second output terminal Q- of the D flip-flop DFF2 and the enable / reset terminal Reset. The delay module 202 is used to reset the D flip-flop DFF2 according to the output of the second output terminal Q- of the D flip-flop DFF2.

[0087] Figure 9 A schematic waveform diagram of a square wave to voltage converter 200 according to a second embodiment of the present invention is shown below, in conjunction with... Figures 7 to 9 The working principle of the square wave to voltage converter 200 in this embodiment will be explained in detail.

[0088] like Figure 9 As shown, before time t1, D flip-flops DFF1 and DFF3 are set by the enable signal EN. At this time, the first output terminal Q of DFF1 is logic high, and the second output terminal Q- is logic low, meaning the first control signal ST1 is logic high. The first output terminal Q of DFF3 is also logic high. Since the data terminals D of both DFF1 and DFF2 are connected to the second output terminal Q- of DFF1, the signals at the data terminals D of both DFF1 and DFF2 are logic low. Furthermore, DFF2 is enabled and reset by the delay module 202. At this time, the first output terminal Q of DFF2 is logic low, so the second control signal ST2 is logic high, and the third control signal ST3 is logic high. Moreover, the logic high first control signal ST1 turns on the switch S1 in the ramp voltage generation module 210, pulling the ramp voltage signal RAMP low to the reference ground.

[0089] During the sampling period from time t1 to t3, when the rising edge of the square wave signal PWM arrives, as shown in time t1, D flip-flops DFF1 and DFF3 are triggered, transmitting their respective data terminal D signals to the first output terminal Q. Therefore, the first control signal ST1 flips to logic low, while the second control signal ST2 remains logic high. As a result, switch S1 in the ramp voltage generation module 210 is turned off, current source IBP charges capacitor C1, and the ramp voltage signal RAMP rises linearly. Simultaneously, since the second control signal ST2 and the third control signal ST3 are also logic high, switches S2 and S3 are turned on, and the first sampled voltage signal Vt_h and the second sampled voltage signal Vton_h also rise linearly.

[0090] At time t2, when the falling edge of the square wave signal PWM arrives, D flip-flop DFF3 is triggered, transmitting its data terminal D signal to the first output terminal Q. Since the data terminal D of DFF3 is connected to the first output terminal Q of D flip-flop DFF1, and the first output terminal Q of DFF1 is logic low, the first output terminal Q of DFF3 also flips to logic low. As a result, the third control signal ST3 flips to logic low, and switch S3 is turned off. At this time, the second sample-and-hold module 230 stops sampling the ramp voltage signal RAMP and stores the second sampled voltage signal Vton_h on capacitor C3. Since switch S2 is still on, the first sampled voltage signal Vt_h continues to rise linearly.

[0091] At time t3, the next rising edge of the square wave signal PWM arrives, and D flip-flops DFF1 and DFF2 are triggered again. At this time, the first output terminal Q of D flip-flops DFF1 and DFF2 flips to logic high, so the first control signal ST1 is logic high and the second control signal ST2 is logic low. As a result, switch S2 opens, the first sample-and-hold module 220 stops sampling the ramp voltage signal RAMP, and stores the first sampled voltage signal Vt_h on capacitor C2. In this way, the proportional time is converted into a proportional sampled voltage. At the same time, switch S1 is turned on, and switch S1 grounds the first terminal of capacitor C1, thereby pulling the ramp voltage signal RAMP to ground. Then, after a suitable delay, the fourth control signal ST4 generates a valid pulse, outputting the first sampled voltage signal Vt_h as the first input voltage Vt, and outputting the second sampled voltage signal Vton_h as the second input voltage Vton. Afterwards, between the hold period times t4 and t6, the first input voltage Vt and the second input voltage Vton are held, thus facilitating the use of subsequent circuits.

[0092] In summary, the voltage regulation circuit of this invention can dynamically adjust the output voltage based on the pulse width of a square wave signal, exhibiting a fast response speed. Furthermore, this voltage regulation circuit can simultaneously achieve boost, buck, and buck-boost adjustments based on the duty cycle of the square wave signal. Compared to traditional circuits that can only achieve single-direction adjustment, this voltage regulation circuit offers greater flexibility, adapting to different application scenarios without requiring additional hardware or circuit design. Moreover, compared to needing to design two separate boost or buck circuits, this voltage regulation circuit saves costs and occupies less circuit space, contributing to reduced cost and size of electronic devices.

[0093] Furthermore, the present invention also provides a square wave to voltage converter circuit, which can be used in the voltage regulation circuit of the present invention or used alone. The square wave to voltage converter circuit converts the high and low level logic signal (i.e., square wave signal) representing duty cycle information into a voltage signal on the capacitor by charging the capacitor with current. Then, the voltage on the capacitor is sampled and held by the rising and falling edges of the square wave signal. The ratio of the sampled and held voltage signals is the duty cycle of the square wave signal, thereby realizing the extraction of duty cycle information in the square wave signal.

[0094] Furthermore, the square wave to voltage converter of the present invention divides the continuous period of the square wave signal into adjacent sampling periods and holding periods, samples the voltage on the capacitor during the sampling period of the square wave signal, and holds the sampled voltage during the subsequent holding period. This can provide a stable and accurate signal sampling, solve timing problems, provide a stable input for subsequent signal processing, and improve the efficiency of signal processing.

[0095] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0096] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A voltage regulation circuit based on pulse width modulation, comprising: The first voltage-to-current conversion circuit is used to convert the reference voltage into a reference current that is linearly related to it. The second voltage-to-current conversion circuit is used to convert the first input voltage into a first input current that is linearly related to it, wherein the first input voltage has a voltage value corresponding to the period of a square wave signal; A third voltage-to-current conversion circuit is used to convert a second input voltage into a second input current that is linearly related to it. The second input voltage has a voltage value corresponding to the high-level time of the square wave signal, and the ratio of the second input voltage to the first input voltage is the duty cycle represented by the square wave signal. A current subtractor is used to obtain the difference current between the first input current and the second input current. A current calculation circuit is used to calculate the reference current, the difference current, and the second input current to obtain the output current; as well as A current-to-voltage conversion circuit is used to convert the output current into an output voltage.

2. The voltage regulation circuit of claim 1, wherein, The current calculation circuit is configured to obtain the output current according to the following formula: Iout = Iref × (It - Iton) ÷ Iton, where Iout represents the output current, Iref represents the reference current, It represents the first input current, and Iton represents the second input current.

3. The voltage regulation circuit according to claim 1, wherein, The first voltage-to-current conversion circuit includes: First transistor; A first resistor, the first end of which is connected to the first transistor, and the second end of which is connected to ground; A first operational amplifier has its non-inverting input connected to the reference voltage, its inverting input connected to the common node of the first transistor and the first resistor, and its output connected to the control terminal of the first transistor. The first operational amplifier is used to generate the reference current in the first transistor based on the reference voltage and the resistance value of the first resistor. A first current mirror circuit, connected to the first terminal of the first transistor, is used to output the reference current to the current calculation circuit. The second voltage-to-current conversion circuit includes: Second transistor; The second resistor has its first end connected to the second transistor and its second end connected to ground. A second operational amplifier has its non-inverting input connected to the first input voltage, its inverting input connected to the common node of the second transistor and the second resistor, and its output connected to the control terminal of the second transistor. This second operational amplifier is used to generate the first input current in the second transistor based on the first input voltage and the resistance value of the second resistor. The current subtractor is implemented through a second current mirror circuit. The current input terminal of the second current mirror circuit is used to receive the first input current and the second input current, and its current output terminal is used to output the difference current between the two to the current calculation circuit. The third voltage-to-current conversion circuit includes: Third transistor; The third resistor has its first end connected to the third transistor and its second end connected to ground. A third operational amplifier has its non-inverting input connected to the second input voltage, its inverting input connected to the common node of the third transistor and the third resistor, and its output connected to the control terminal of the third transistor. This third operational amplifier is used to generate the second input current in the third transistor based on the second input voltage and the resistance value of the third resistor. A third current mirror circuit, connected to the first terminal of the third transistor, is used to output the second input current to the current subtractor and the current calculation circuit. The current-to-voltage conversion circuit includes: The eighth current mirror circuit; and The fourth resistor has its first terminal connected to the eighth current mirror circuit and its second terminal connected to ground. The eighth current mirror circuit is used to mirror the output current onto the fourth resistor to generate the output voltage at their common node.

4. The voltage regulation circuit according to claim 1, wherein, The current calculation circuit includes: The first bipolar transistor has a first terminal connected to the reference current and a second terminal connected to ground; The second bipolar transistor has a first terminal connected to the differential current and a second terminal connected to the control terminal and the first bias current of the first bipolar transistor. The third bipolar transistor has its first terminal connected to the second input current, its second terminal connected to the second bias current, and its control terminal connected to the control terminal of the second bipolar transistor. The fourth bipolar transistor has a first terminal for providing the output current, a control terminal connected to the second terminal of the third bipolar transistor and the second bias current, and its second terminal connected to ground. A fourth transistor has a first terminal connected to the power supply voltage, a control terminal connected to the first terminal of the first bipolar transistor, and a second terminal connected to the control terminal of the first bipolar transistor. The fourth transistor is used to provide voltage bias to the first bipolar transistor. The fifth transistor has its control terminal connected to the first terminal of the second bipolar transistor, and its second terminal connected to the control terminal of the second bipolar transistor. The fourth current mirror circuit has its current input terminal connected to the first terminal of the fifth transistor, and its current output terminal is used to feed back the control terminal current of the second bipolar transistor. The fifth current mirror circuit is connected to the differential current, the current output terminal of the fourth current mirror circuit, and the second terminal of the second bipolar transistor, and is used to obtain the first bias current based on the sum of the differential current and the control terminal current of the second bipolar transistor. The sixth transistor has its control terminal connected to the first terminal of the third bipolar transistor, and its second terminal connected to the control terminal of the third bipolar transistor. A sixth current mirror circuit, whose current input terminal is connected to the first terminal of the sixth transistor, and whose current output terminal is used to feedback the control terminal current of the third bipolar transistor; and The seventh current mirror circuit is connected to the second input current, the current output terminal of the sixth current mirror circuit, and the second terminal of the third bipolar transistor, and is used to obtain the second bias current based on the sum of the second input current and the control terminal current of the third bipolar transistor.

5. The voltage regulation circuit of claim 4, wherein, The current calculation circuit also includes: The fourth operational amplifier has its non-inverting input terminal connected to the second terminal of the third bipolar transistor, and its inverting input terminal and output terminal connected to the control terminal of the fourth bipolar transistor. The fourth operational amplifier is used to form a first voltage follower between the third bipolar transistor and the fourth bipolar transistor.

6. The voltage regulation circuit according to claim 1 further includes: A square wave to voltage converter circuit is used to convert the square wave signal into a first input voltage and a second input voltage, wherein the square wave signal has adjacent sampling periods and hold periods. The square wave to voltage converter circuit includes: A ramp voltage generation module is used to generate a linearly rising ramp voltage signal during the sampling period of the square wave signal. A first sample-and-hold module is used to sample the ramp voltage signal during the sampling period of the square wave signal to obtain a first sampled voltage signal, wherein the sampling duration of the first sample-and-hold module is equal to the time of the sampling period. The second sample-and-hold module is used to sample the ramp voltage signal during the sampling period of the square wave signal to obtain a second sampled voltage signal, wherein the sampling duration of the second sample-and-hold module is equal to the high-level time of the square wave signal; and The output module is configured to obtain the first input voltage based on the first sampled voltage signal and the second input voltage based on the second sampled voltage signal, respectively, after a preset time delay following the end of the sampling period of the square wave signal.

7. The voltage regulation circuit according to claim 6, wherein, The ramp voltage generation module is also used to reset the ramp voltage signal to the reference ground during the hold period of the square wave signal. The first sample-and-hold module and the second sample-and-hold module are further configured to hold the first sampled voltage signal and the second sampled voltage signal during the holding period of the square wave signal.

8. The voltage regulation circuit according to claim 7, wherein, The square wave to voltage converter circuit also includes: The logic control module is used to generate first to fourth control signals based on the square wave signal. The first control signal is used to control the operation of the ramp voltage generation module, and the first control signal has an invalid control level corresponding to the sampling period of the square wave signal and an effective control level corresponding to the holding period of the square wave signal. The second control signal is used to control the operation of the first sample-and-hold module, and the second control signal has an effective control level corresponding to the sampling period of the square wave signal and an invalid control level corresponding to the holding period of the square wave signal. The third control signal is used to control the operation of the second sample-and-hold module, and the third control signal has an effective control level corresponding to the high level time of the sampling period of the square wave signal and an invalid control level corresponding to the low level time of the sampling period and the hold period of the square wave signal. The fourth control signal is used to control the operation of the output module, and the fourth control signal is a narrow pulse signal.

9. The voltage regulation circuit of claim 8, wherein, The ramp voltage generation module includes: A current source and a first capacitor are connected in series between the power supply voltage and ground; A first switch is connected in parallel between the two ends of the first capacitor, and the first control signal is applied to the control terminal of the first switch; and The second voltage follower has its input connected to the common node of the current source and the first capacitor, and its output is used to output the ramp voltage signal. The ramp voltage generating module is configured to turn off the first switch during the invalid control level phase of the first control signal to generate a linearly rising ramp voltage signal, and to turn on the first switch during the valid control level phase of the first control signal to reset the ramp voltage signal to ground. The first sample-and-hold module includes: A second switch and a second capacitor are connected in series between the ramp voltage signal and ground, and the second control signal is applied to the control terminal of the second switch; and A third voltage follower has its input connected to the common node of the second switch and the second capacitor, and its output is used to output the first sampled voltage signal. The first sample-and-hold module is configured to turn on the second switch during the valid control level phase of the second control signal to sample the ramp voltage signal, and to turn off the second switch during the invalid control level phase of the second control signal to hold the first sampled voltage signal. The second sample-and-hold module includes: A third switch and a third capacitor are connected in series between the ramp voltage signal and ground, and the third control signal is applied to the control terminal of the third switch; and A fourth voltage follower has its input connected to the common node of the third switch and the third capacitor, and its output is used to output the second sampled voltage signal. The second sample-and-hold module is configured to turn on the third switch during the valid control level phase of the third control signal to sample the ramp voltage signal, and to turn off the third switch during the invalid control level phase of the third control signal to hold the second sampled voltage. The output module includes: A fourth switch and a fourth capacitor are connected in series between the first sampled voltage signal and ground, and their common node is used to output the first input voltage; and A fifth switch and a fifth capacitor are connected in series between the second sampled voltage signal and ground, and their common node is used to output the second input voltage. The fourth control signal is applied to the control terminals of the fourth switch and the fifth switch. The logic control module includes: The first D flip-flop has a clock terminal for receiving the square wave signal, a data terminal connected to the second output terminal, and a first output terminal for outputting the first control signal. The second D flip-flop has a clock terminal for receiving the square wave signal and a data terminal connected to the data terminal and the second output terminal of the first D flip-flop. A first inverter is connected to the first output terminal of the second D flip-flop, and the first inverter is used to provide the second control signal according to the output of the second D flip-flop; The third D flip-flop has a clock terminal for receiving the inverted signal of the square wave signal, and its data terminal is connected to the first output terminal of the first D flip-flop. An AND gate circuit, the first input of which is connected to the second control signal, and the second input of which is connected to the first output of the third D flip-flop, the AND gate circuit being used to provide the third control signal according to the second control signal and the output of the third D flip-flop; A first buffer, the input of which is connected to the first output of the first D flip-flop; and A narrow pulse module, whose input is connected to the output of the first buffer, is used to generate the fourth control signal based on the output of the first buffer.

10. The voltage regulation circuit according to claim 9, wherein, The first D flip-flop and the third D flip-flop also include an enable set terminal for receiving an enable signal. The voltage regulation circuit further includes a second buffer connected between the square wave signal and the clock input of the first D flip-flop. The logic control module further includes a delay module connected to the second output terminal and the enable / reset terminal of the second D flip-flop, the delay module being used to reset the second D flip-flop according to the output of the second D flip-flop.

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