A rubidium clock FSK small modulation signal generation system and method

Abstract

A rubidium clock FSK small modulation signal generation system and method belong to the field of electronic information technology. This invention includes a 2-divider, an M-divider, an accumulator based on DDS principle, and an XOR gate: to generate a square wave signal containing a 5.3125MHz FSK small modulation signal spectral component under a 10MHz clock source input condition, where the center frequency of this spectral component (5.3125MHz) is finely adjustable. The application of this software realizes a fully digital process for FSK small modulation signal processing, reducing analog circuitry, lowering debugging difficulty, and significantly reducing FPGA resource consumption and clock speed.

Description

Technical Field

[0001] This invention relates to a rubidium clock FSK small modulation signal generation system and method, belonging to the field of electronic information technology. Background Technology

[0002] The 6.83468*GHz microwave FSK small-modulation signal within the rubidium clock frequency-locked loop is obtained by mixing a single-frequency 6.840GHz signal with a 5.3125*MHz FSK small-modulation signal whose center frequency can be finely adjusted. Therefore, the purpose of this method is to generate the 5.3125*MHz FSK small-modulation signal.

[0003] Generating the spectral components of the 5.3125*MHz FSK small modulation signal directly based on the DDS principle requires a clock rate of >10MHz and a matching frequency multiplier circuit. Due to various factors such as truncation error, the square wave signal generated based on the DDS principle contains a large number of harmonic noises and requires filtering processing. Summary of the Invention

[0004] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a rubidium clock FSK small modulation signal generation system and method, which reduces the requirements for clock rate, eliminates the need for frequency multiplication circuit, reduces debugging difficulty, and saves hardware resources.

[0005] The technical solution of the present invention is: a rubidium clock FSK small modulation signal generation system, including a frequency divider, an M-divider, an accumulator and a digital processing module;

[0006] A frequency divider is used to divide the input clock signal by two to generate a first frequency output signal and send it to the digital processing module.

[0007] A frequency divider and an accumulator are connected in series; the frequency divider is used to divide the input clock signal into several channels to generate several output signals to the accumulator; the accumulator is used to accumulate the output signals of the frequency divider to generate a second frequency modulated square wave signal with an adjustable center frequency and send it to the digital processing module.

[0008] The digital processing module is used to perform XOR digital mixing processing on the first frequency output signal and the second frequency modulated square wave signal to obtain a square wave signal with a preset frequency modulated spectral component.

[0009] Furthermore, the range of the number of divisions of the multi-divider is [1, 10].

[0010] Furthermore, the frequency of the input clock signal is 10MHz; the first frequency is 5MHz; the second frequency is 0.3125MHz; and the preset frequency is 5.3125MHz.

[0011] Furthermore, the accumulator is implemented based on the DDS method.

[0012] Furthermore, the frequency divider controls the switching of two N-bit frequency control words by receiving an externally input modulated square wave signal; the accumulator accumulates the switching result under the trigger of a reference clock, and takes the highest bit of the accumulated result as the 0.3125*MHz FSK modulated square wave signal.

[0013] Furthermore, the modulation depth of the FSK modulated square wave signal is Δω=(HL)×f clk / 2 N Where H and L are two N-bit frequency control words that convert binary to decimal; f clk The frequency of the reference clock.

[0014] Furthermore, the center frequency of the FSK modulated square wave signal is Here, H and L are two N-bit frequency control words that convert binary to decimal; f clk The frequency of the reference clock.

[0015] A method for generating a rubidium clock FSK small modulation signal includes:

[0016] The input clock signal is divided by two to generate a first frequency output signal;

[0017] The input clock signal is divided into several channels to generate several output signals, which are then accumulated to generate a second frequency modulated square wave signal with an adjustable center frequency.

[0018] The first frequency output signal and the second frequency modulated square wave signal are XORed digitally to obtain a square wave signal with a preset frequency modulated spectral component.

[0019] Furthermore, the switching of two N-bit frequency control words is controlled by receiving an externally input modulated square wave signal; the accumulator accumulates the switching result under the trigger of the reference clock, and takes the highest bit of the accumulation result as the 0.3125*MHz FSK modulated square wave signal.

[0020] The modulation depth of the FSK modulated square wave signal is Δω=(HL)×f clk / 2 N ;

[0021] The center frequency of the FSK modulated square wave signal is

[0022] Here, H and L are two N-bit frequency control words that convert binary to decimal; f clk The frequency of the reference clock.

[0023] Furthermore, the range of the plurality of paths is [1, 10];

[0024] The frequency of the input clock signal is 10MHz; the first frequency is 5MHz; the second frequency is 0.3125MHz; and the preset frequency is 5.3125MHz.

[0025] The accumulation is implemented based on the DDS method.

[0026] The advantages of this invention compared to the prior art are:

[0027] (1) Using 10MHz as the reference clock, without frequency multiplication, a 5.3125*MHz FSK small modulation signal is generated;

[0028] (2) It adopts a fully digital processing method, which can be implemented using only FPGA, saving hardware resources.

[0029] (3) By adjusting the center frequency of the 0.3125*MHz FSK small modulation signal, the accuracy of the rubidium clock output frequency of 10MHz can be adjusted, and the adjustment accuracy is 17 times higher than that of the existing methods. Attached Figure Description

[0030] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0031] Figure 1 Block diagram of the principle of generating small modulation signal of rubidium clock FSK;

[0032] Figure 2 Block diagram of the principle for generating a 0.3125*MHz FSK small-modulation square wave signal;

[0033] Figure 3 Spectral distribution diagram of FSK small-modulation square wave signal at 0.3125*MHz;

[0034] Figure 4 Waveform of FSK small-modulation square wave signal at LVTTL level (5.3125*MHz);

[0035] Figure 5 Spectral distribution diagram of FSK small-modulation square wave signal at 5.3125*MHz;

[0036] Figure 6 Changes in light intensity signal caused by frequency variations of microwave small modulation signals under the influence of transition spectral lines. Detailed Implementation

[0037] To better understand the above technical solutions, the technical solutions of this application will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of this application and the specific features in the embodiments are detailed descriptions of the technical solutions of this application, rather than limitations on the technical solutions of this application. In the absence of conflict, the embodiments of this application and the technical features in the embodiments can be combined with each other.

[0038] The following description, in conjunction with the accompanying drawings, provides a more detailed account of a rubidium clock FSK small modulation signal generation system and method provided in this application. Specific implementation methods may include (e.g.) Figure 1 As shown): The 10MHz signal output from the crystal oscillator is divided by two to obtain a 5MHz square wave signal; the other signal is generated using a frequency of 10MHz or a frequency divided by M based on 10MHz as a clock reference (M is an integer, 1≤M≤10) based on the DDS principle, resulting in a 0.3125MHz small-modulation square wave signal with a finely adjustable center frequency; the 5MHz signal and the 0.3125MHz FSK small-modulation signal are XORed digitally to obtain a square wave signal containing a spectral component of 5.3125*MHz small modulation.

[0039] This square wave signal contains a significant amount of spurious signals. After being mixed with a 6.840 GHz single-frequency microwave signal, it yields a 6.83468 MHz FSK small-modulation signal spectral component, which also shifts the spurious signals to the vicinity of this spectral component. The bandwidth of the transition spectrum of the rubidium clock's physical components at the 6.83468 GHz frequency is only a few hundred Hz (equivalent to a bandpass filter with a Q value of over ten million), significantly reducing the impact of these spurious signals on frequency stability.

[0040] The solution provided in the embodiments of this application includes:

[0041] 1) Generation of 0.3125MHz FSK small-modulation square wave signal and 5MHz single-frequency square wave signal based on DDS principle

[0042] like Figure 2 The generated 0.3125MHz FSK small-modulation square wave signal is shown: Reference clock f clk It can be a 10MHz crystal oscillator or a 10MHz frequency divided by a digital integer. The input modulating square wave signal controls the switching of two N-bit frequency control words (H or L). clkWhen triggered, the accumulator accumulates the switching result, and the overflow of the N-bit accumulated result does not need to be handled. The highest bit of the accumulated result is taken as a 0.3125*MHz FSK small modulation square wave signal.

[0043] The modulation frequency Ω of the FSK small-modulation square wave signal is equal to Figure 2 The frequency of the modulating square wave signal.

[0044] The modulation depth of the FSK small-modulation square wave signal depends on Figure 2 The difference between the two N-bit frequency control words and the reference clock f clk The result is obtained by calculation using formula (1):

[0045] Δω=(HL)×f clk / 2 N (Formula 1)

[0046] In the formula:

[0047] Δω is the modulation depth of the 0.3125MHz FSK small-modulation square wave signal;

[0048] H stands for Frequency control word H, which converts binary to decimal.

[0049] L stands for Frequency control word L, which converts binary to decimal.

[0050] f clk Reference clock frequency;

[0051] N represents the number of bits in the frequency control word.

[0052] The center frequency of the FSK small-modulation square wave signal is obtained by formula (2):

[0053]

[0054] In the formula:

[0055] f is the center frequency of the 0.3125MHz FSK small-modulation square wave signal;

[0056] H stands for Frequency control word H, which converts binary to decimal.

[0057] L stands for Frequency control word L, which converts binary to decimal.

[0058] f clk Reference clock frequency;

[0059] N represents the number of bits in the frequency control word.

[0060] By setting parameters, the center frequency, modulation frequency, and modulation depth of the FSK small modulation square wave signal can be adjusted within a certain range.

[0061] Depend on Figure 2 It is evident that, to conserve FPGA resources, a simplified design is adopted, omitting DDS lookup tables and scrambling measures. This results in a high truncation error and a significant amount of spurious signals. Taking a typical FSK small-modulation square wave signal with the following parameters—center frequency 0.3125MHz, modulation frequency 82Hz, modulation depth 220Hz, and LVTTL 3.3V level—as an example, simulations were performed using MATLAB. The simulation results are as follows: Figure 3 As shown.

[0062] Figure 3 The top image shows the far-end spectrum at 0.3125 MHz; the bottom image shows the near-end spectrum at 0.3125 MHz. The spectrum contains the critical signal frequency component at 0.3125 MHz. Near-end spurious signals exhibit a -5.046 dBm spurious signal at 0.4368 MHz (Δf≈125 kHz, ΔP≈5 dBc) and a -5.551 dBm spurious signal at 0.1884 MHz (Δf≈125 kHz, ΔP≈5 dBc). The near-end spurious signals are characterized by a symmetrical distribution.

[0063] A 5MHz square wave signal was obtained by dividing a 10MHz crystal oscillator by two using an FPGA.

[0064] 2) Digital XOR mixing to generate a 5.3125*MHz square wave FSK signal and spectrum simulation

[0065] The mixing method generally uses a multiplier. The 0.3125*MHz FSK small modulation square wave signal and the 5MHz square wave signal are multiplied by an XOR logic gate instead of multiplication. The principle is shown in Table 1.

[0066] Table 1 compares the results of multiplication with those of XOR logic processing.

[0067]

[0068] As shown in Table 1, if the value '-1' of the multiplication operation is defined as logic level '0' in the logic operation, and the value '1' of the multiplication operation is defined as logic level '1' in the logic operation, then the result of the multiplier operation is completely consistent with the result of the XOR logic processing. That is, the XOR logic gate circuit can replace the multiplier for digital signal mixing.

[0069] The LVTTL level waveform of the 5.3125*MHz square wave FSK signal after mixing is as follows: Figure 4As shown, the top image is the waveform of a 5MHz square wave signal, the middle image is the waveform of a 0.3125MHz signal generated based on the DDS principle, and the bottom image is the waveform after XORing the two signals.

[0070] right Figure 4 Spectral analysis was performed on the LVTTL level waveform of the 5.3125*MHz square wave FSK signal after XOR mixing, as follows: Figure 5 As shown. Figure 5 The upper and middle figures show the far-end spectrum distribution. Figure 3 The mixed signal waveform is a signal with abundant spurious signals, with 5.3125*MHz as the main peak. The figure below shows the spectrum analysis of the near end of the 5.3125*MHz square wave signal with the main peak. The nearest spurious signals are 5.437MHz (Δf≈125KHz, ΔP≈6dBc) and 5.188MHz (Δf≈125KHz, ΔP≈8dBc).

[0071] 3) Assessment of the magnitude of the impact of stray emissions on the frequency stability of the rubidium clock and test results of the short-term frequency stability of the entire clock.

[0072] The 6.8346875*GHz microwave signal fed into the rubidium clock's physical section is obtained by downmixing a 6.840GHz and a 5.3125*MHz square wave FSK signal. Therefore... Figure 5 Spurious signals present in the 5.3125*MHz square wave FSK signal are transported into the vicinity of the microwave signal via spectral shift. The transition spectral lines in the physical part are as follows: Figure 6 As shown.

[0073] In the principal coordinate system, the horizontal axis ω represents the frequency value, and the vertical axis I represents the light intensity. When... Figure 6 When the lower-middle modulation signal is near the center frequency ω0 of the transition spectral line, it produces a corresponding change in light intensity, as shown in the small coordinate graph It on the right side of the figure. If the frequency of the microwave spurious signal is far from the center frequency of the transition spectral line, its impact on the rubidium clock performance is very small, as evaluated below:

[0074] The relationship between the average transition probability of an atom and microwave frequency and power can be calculated using Equation 3.

[0075]

[0076] In the formula:

[0077] ω is the frequency of the microwave small modulation signal;

[0078] ω0 is the center frequency of the transition spectral line;

[0079] The value of b is directly proportional to the microwave power;

[0080] τ is the average lifetime of microwave-activated atoms.

[0081] Pe represents the average atomic transition probability.

[0082] As shown in Formula 3, the average transition probability is related to the frequency and power of microwave spurious emissions. When the normal small modulation frequency deviates from the center frequency of the transition spectrum by (100-200) Hz, it is within the bandwidth of the transition spectrum. Figure 5 The most recent spurious frequency deviates from the main peak by 100 kHz, which is 1 / 1000 of the main peak; the most recent spurious power is about 1 / 4 of the main peak; thus, Pe(spurious ±1) / Pe(main) ≤ 1E-7 is obtained. Similarly, Pe(spurious ±2) / Pe(main) ≤ 1E-8, and so on, decreasing sequentially, and their impact can be ignored in engineering. If the transition linewidth is 500 Hz, the signal-to-noise ratio degradation caused by spurs (≤ 3E-7) can be converted into a frequency stability of approximately 1E-14. Even without knowing the type of noise caused by spurs, a conservative estimate can be made that the resulting frequency stability flickfloor of the rubidium clock is better than 1E-14.

[0083] The frequency stability is 2.96E-12 / 1s, 6.3E-13 / 10s, and 2.4E-13 / 100s; no significant degradation was observed compared with test data using other modulation signal generation methods. This method meets the stability requirements of digital spaceborne rubidium clocks and miniaturized rubidium clocks.

[0084] In summary, the 0.3125*MHz signal generated based on the DDS principle does not require changes to hardware parameters; various parameters of FSK modulation can be achieved simply by adjusting the frequency control word in the software. After digitally XORing with the 5MHz signal, a spectral component containing a small 5.3125*MHz FSK modulation signal is generated, exhibiting abundant harmonics. This method identifies these spurious signals as having been spectrally shifted to the vicinity of 6.8346875GHz, but these are limited by the transition spectral bandwidth of the rubidium clock's physical components, thus having a limited impact on the overall frequency stability of the rubidium clock. Therefore, this method can be applied to rubidium clock products.

[0085] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0086] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

[0087] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A rubidium clock FSK small modulation signal generation system, characterized by, Includes a frequency divider (divider by two), a frequency divider (M-divider), an accumulator, and a digital processing module; A frequency divider is used to divide the input clock signal by two to generate a first frequency output signal and send it to the digital processing module. A frequency divider and an accumulator are connected in series; the frequency divider is used to divide the input clock signal into several channels to generate several output signals to the accumulator; the accumulator is used to accumulate the output signals of the frequency divider to generate a second frequency modulated square wave signal with an adjustable center frequency and send it to the digital processing module. The digital processing module is used to perform XOR digital mixing processing on the first frequency output signal and the second frequency modulated square wave signal to obtain a square wave signal with a preset frequency modulated spectral component. The input clock signal has a frequency of 10MHz; the first frequency is 5MHz; the second frequency is 0.3125MHz; and the preset frequency is 5.3125MHz. MHz; The accumulator is implemented based on the DDS method; The frequency divider controls the switching of two N-bit frequency control words by receiving an externally input modulated square wave signal; the accumulator accumulates the switching results under the trigger of a reference clock, and takes the highest bit of the accumulated result as 0.3125. A MHz FSK modulated square wave signal.

2. A rubidium clock FSK small modulation signal generation system according to claim 1, characterized in that, The range of the number of divisions of the multi-divider is [1, 10].

3. A rubidium clock FSK small modulation signal generation system according to claim 1, characterized in that, The modulation depth of the FSK modulated square wave signal is ; wherein and are two N-bit frequency control words, which convert binary to decimal; is the frequency of the clock signal.

4. A rubidium clock FSK small modulation signal generation system according to claim 1, characterized in that, The center frequency of the FSK modulated square wave signal is ; wherein and are two N-bit frequency control words, which convert binary to decimal; is the frequency of the clock signal.

5. A method for generating a rubidium clock FSK small modulation signal, characterized by, include: The input clock signal is divided by two to generate a first frequency output signal; The input clock signal is divided into several channels to generate several output signals, which are then accumulated to generate a second frequency modulated square wave signal with an adjustable center frequency. The first frequency output signal and the second frequency modulated square wave signal are subjected to XOR digital mixing to obtain a square wave signal with a preset frequency modulated spectral component. The switching of two N-bit frequency control words is controlled by receiving an externally input modulated square wave signal; the accumulator accumulates the switching result under the trigger of a reference clock, and the highest bit of the accumulated result is output as 0.3125. MHz FSK modulated square wave signal; The modulation depth of the FSK modulated square wave signal is ; The center frequency of the FSK modulated square wave signal is ; wherein, and are two N-bit frequency control words, converted from binary to decimal; is the frequency of the reference clock; The range of the aforementioned paths is [1, 10]; The frequency of the input clock signal is 10 MHz; the first frequency is 5 MHz; the second frequency is 0.3125 MHz; the preset frequency is 5.3125 MHz; The accumulation is implemented based on the DDS method.

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