Shift register, scan driving circuit and display device

Abstract

A shift register is provided. The shift register includes a first input circuit (110), a first output circuit (120), a second input circuit (130), a second output circuit (140), and at least one function circuit (150). The first input circuit (110) is configured to transmit an input signal to a first node (N1) under control of a first control signal (K1). The first output circuit (120) is configured to transmit a first output signal (S1) to a first scan signal terminal (Gout1) under control of a potential of the first node (N1). The second input circuit (130) is configured to transmit a first voltage signal (VGL) to a second node (N2) under control of a second control signal (K2). The second output circuit (140) is configured to transmit a second output signal (S2) to the first scan signal terminal (Gout1) under control of a potential of the second node (N2). And, the function circuit (150) is configured to block a path between a function input terminal and a function output terminal under control of a function control signal to maintain a potential of the function output terminal.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a shift register, a scan driving circuit and a display device. BACKGROUND

[0002] With the continuous development of electronic products, display panels with display functions are widely used in people's life and work, providing convenience for people. SUMMARY

[0003] In one aspect, a shift register is provided. The shift register includes a first input circuit, a first output circuit, a second input circuit, a second output circuit, and at least one function circuit. The first input circuit is coupled to an input signal terminal, a first control signal terminal, and a first node. The first input circuit is configured to transmit an input signal provided by the input signal terminal to the first node under the control of a first control signal provided by the first control signal terminal. The first output circuit is coupled to the first node, a first output signal terminal, and a first scan signal terminal. The first output circuit is configured to transmit a first output signal provided by the first output signal terminal to the first scan signal terminal under the control of a potential of the first node. The second input circuit is coupled to a first voltage signal terminal, a second control signal terminal, and a second node. The second input circuit is configured to transmit a first voltage signal provided by the first voltage signal terminal to the second node under the control of a second control signal provided by the second control signal terminal. The second output circuit is coupled to the first scan signal terminal, the second node, and a second output signal terminal. The second output circuit is configured to transmit a second output signal provided by the second output signal terminal to the first scan signal terminal under the control of a potential of the second node. The function circuit is coupled to a function input terminal, a function output terminal, and a function control terminal. The function circuit is configured to block a path between the function input terminal and the function output terminal under the control of a function control signal provided by the function control terminal to maintain a potential of the function output terminal. The function output terminal includes one of the circuit nodes.

[0004] In some embodiments, the function circuit includes an oxide transistor. A control electrode of the oxide transistor is coupled to the function control terminal, a first electrode of the oxide transistor is coupled to the function input terminal, and a second electrode of the oxide transistor is coupled to the function output terminal.

[0005] In some embodiments, the oxide transistor includes a first gate pattern, an active layer, and a second gate pattern sequentially stacked on one side of a substrate. The active layer includes an oxide semiconductor material. The first gate pattern and the second gate pattern constitute the control electrode of the oxide transistor.

[0006] In some embodiments, the oxide transistor further comprises a source-drain metal pattern. Wherein the same source-drain metal pattern is coupled with the first gate pattern and the second gate pattern respectively.

[0007] In some embodiments, the first control signal terminal comprises a first clock signal terminal. The first input circuit comprises a second transistor. A control electrode of the second transistor is coupled with the first clock signal terminal, a first electrode of the second transistor is coupled with the input signal terminal, and a second electrode of the second transistor is coupled with the first node.

[0008] In some embodiments, the first control signal terminal comprises a first auxiliary clock signal terminal. The first input circuit is multiplexed as a functional circuit. The first input circuit is further configured to, under control of a first auxiliary clock signal provided by the first auxiliary clock signal terminal, block a path between the input signal terminal and the first node to maintain the potential of the first node.

[0009] In some embodiments, the first input circuit comprises a second transistor, and the second transistor comprises an oxide transistor. The first auxiliary clock signal terminal serves as a functional control terminal. A control electrode of the second transistor is coupled with the first auxiliary clock signal terminal, a first electrode of the second transistor is coupled with the input signal terminal, and a second electrode of the second transistor is coupled with the first node.

[0010] In some embodiments, the first control signal terminal comprises a third control signal terminal and a fourth control signal terminal. The first input circuit is further configured to, under control of a third control signal provided by the third control signal terminal and a fourth control signal provided by the fourth control signal terminal, transmit the input signal to the first node. Wherein the first input circuit comprises a functional circuit, and the functional circuit is coupled in series between the input signal terminal and the first node.

[0011] The third control signal terminal serves as one of the functional control terminals. The functional circuit is configured to, under control of the third control signal provided by the third control signal terminal, block a path between the input signal terminal and the first node to maintain the potential of the first node. And / or, the fourth control signal terminal serves as one of the functional control terminals. The functional circuit is configured to, under control of the fourth control signal provided by the fourth control signal terminal, block a path between the input signal terminal and the first node to maintain the potential of the first node.

[0012] In some embodiments, the third control signal terminal comprises a second clock signal terminal, and the fourth control signal terminal comprises a first auxiliary clock signal terminal. The first input circuit comprises a second transistor and a third transistor, the functional circuit comprises the third transistor, and the third transistor comprises an oxide transistor. The first auxiliary clock signal terminal is one of the functional control terminals. The control electrode of the second transistor is coupled to the second clock signal terminal, the first electrode of the second transistor is coupled to the input signal terminal, the second electrode of the second transistor is coupled to the first electrode of the third transistor, the control electrode of the third transistor is coupled to the first auxiliary clock signal terminal, and the second electrode of the third transistor is coupled to the first node. Alternatively, the third control signal terminal comprises a second auxiliary clock signal terminal, and the fourth control signal terminal comprises a first clock signal terminal. The first input circuit comprises a second transistor and a third transistor, the functional circuit comprises the second transistor, and the second transistor comprises an oxide transistor. The second auxiliary clock signal terminal is one of the functional control terminals. The control electrode of the second transistor is coupled to the second auxiliary clock signal terminal, the first electrode of the second transistor is coupled to the input signal terminal, the second electrode of the second transistor is coupled to the first electrode of the third transistor, the control electrode of the third transistor is coupled to the first clock signal terminal, and the second electrode of the third transistor is coupled to the first node.

[0013] In some embodiments, the second control signal terminal comprises a first clock signal terminal. The second input circuit comprises a fourth transistor, the control electrode of the fourth transistor is coupled to the first clock signal terminal, the first electrode of the fourth transistor is coupled to the first voltage signal terminal, and the second electrode of the fourth transistor is coupled to the second node.

[0014] In some embodiments, the second control signal terminal comprises a first auxiliary clock signal terminal. The second input circuit is multiplexed as a functional circuit. The second input circuit is further configured to, under the control of a first auxiliary clock signal provided by the first auxiliary clock signal terminal, block the path between the first voltage signal terminal and the second node to maintain the potential of the second node.

[0015] In some embodiments, the second input circuit comprises a fourth transistor, and the fourth transistor comprises an oxide transistor. The first auxiliary clock signal terminal is one of the functional input terminals. The control electrode of the fourth transistor is coupled to the first auxiliary clock signal terminal, the first electrode of the fourth transistor is coupled to the first voltage signal terminal, and the second electrode of the fourth transistor is coupled to the second node.

[0016] In some embodiments, the shift register further includes a first control circuit. The first control circuit is coupled to the fifth control signal terminal, the second node and the third output signal terminal respectively. The first control circuit is configured to transmit a third output signal provided by the third output signal terminal to the second node under control of a fifth control signal provided by the fifth control signal terminal.

[0017] In some embodiments, the first control circuit includes a fifth transistor. The fifth control signal terminal includes a first node; the third output signal terminal includes a first clock signal terminal or a second voltage signal terminal. The control electrode of the fifth transistor is coupled to the first node, the first electrode of the fifth transistor is coupled to the third output signal terminal, and the second electrode of the fifth transistor is coupled to the second node.

[0018] In some embodiments, a functional circuit is coupled in series between the second node and the third output signal terminal. The functional circuit is further coupled to a third clock signal terminal; the third output signal terminal includes a first clock signal terminal. The functional circuit is configured to block a path between the second node and the first clock signal terminal under control of a third clock signal provided by the third clock signal terminal, so as to maintain the potential of the second node.

[0019] In some embodiments, the functional circuit includes a first transistor, and the first transistor includes an oxide transistor. The third clock signal terminal serves as a functional control terminal; the control electrode of the first transistor is coupled to the third clock signal terminal, the first electrode of the first transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the first transistor is coupled to the second node. The second electrode of the fifth transistor is coupled to the second node through the first transistor. Alternatively, the control electrode of the first transistor is coupled to the third clock signal terminal, the first electrode of the first transistor is coupled to the first clock signal terminal, and the second electrode of the first transistor is coupled to the first electrode of the fifth transistor. The first electrode of the fifth transistor is coupled to the first clock signal terminal through the first transistor.

[0020] In some embodiments, the second input circuit includes a fourth transistor, and the fourth transistor is configured to be coupled to a first voltage signal line. In the plane where the shift register is located, the first transistor is located on the side of the fourth transistor away from the first voltage signal line.

[0021] In some embodiments, the first transistor comprises a first gate pattern, an active layer, and a second gate pattern which are sequentially stacked on one side of a substrate. The active layer comprises an oxide semiconductor material. The first gate pattern and the second gate pattern constitute a control electrode of the first transistor. The first gate pattern and the second gate pattern of the first transistor are located on the side of the third clock signal terminal close to the substrate. The first gate pattern and the second gate pattern of the first transistor are respectively coupled to the third clock signal terminal.

[0022] In some embodiments, the first input circuit comprises a third transistor configured to be coupled to a first clock signal line. In the plane where the shift register is located, the first transistor is located on the side of the third transistor away from the first clock signal line.

[0023] In some embodiments, the shift register further comprises a third output circuit and a fourth output circuit. The third output circuit is coupled to the first voltage signal terminal, the first node, and a second scan signal terminal. The third output circuit is configured to transmit a first voltage signal provided by the first voltage signal terminal to the second scan signal terminal under the control of the potential of the first node. The fourth output circuit is coupled to a second voltage signal terminal, the first node, and the second scan signal terminal. The fourth output circuit is configured to transmit a second voltage signal provided by the second voltage signal terminal to the second scan signal terminal under the control of the potential of the first node.

[0024] In some embodiments, the third output circuit is multiplexed as a functional circuit. The third output circuit is further configured to block the path between the first voltage signal terminal and the second scan signal terminal under the control of the potential of the first node to maintain the potential of the second scan signal terminal.

[0025] In some embodiments, the third output circuit comprises a sixth transistor comprising an oxide transistor. The first node serves as one of the functional control terminals; the fourth output circuit comprises a seventh transistor. The control electrode of the sixth transistor is coupled to the first node, the first electrode of the sixth transistor is coupled to the first voltage signal terminal, and the second electrode of the sixth transistor is coupled to the second scan signal terminal. The control electrode of the seventh transistor is coupled to the first node, the first electrode of the seventh transistor is coupled to the second voltage signal terminal, and the second electrode of the seventh transistor is coupled to the second scan signal terminal.

[0026] In some embodiments, the shift register further comprises a first control circuit. The first control circuit is coupled to the fifth control signal terminal, the second node and the third output signal terminal, respectively. The first control circuit is configured to transmit a third output signal provided by the third output signal terminal to the second node under control of a fifth control signal provided by the fifth control signal terminal. The third output signal terminal comprises a first clock signal terminal; the fifth control signal terminal comprises the second scan signal terminal; and the first control circuit is multiplexed as a functional circuit. The first control circuit is configured to block a path between the first clock signal terminal and the second node under control of a second scan signal provided by the second scan signal terminal, so as to maintain the potential of the second node.

[0027] In some embodiments, the shift register is as described above. The first control circuit comprises a fifth transistor, and the fifth transistor comprises an oxide transistor. The second scan signal terminal serves as one of the functional control terminals; a control electrode of the fifth transistor is coupled to the second scan signal terminal; a first electrode of the fifth transistor is coupled to the first clock signal terminal; and a second electrode of the fifth transistor is coupled to the second node.

[0028] In some embodiments, the shift register further comprises a noise reduction circuit. The noise reduction circuit is coupled to a second voltage signal terminal, a sixth control signal terminal, the second node and a first node, respectively. The noise reduction circuit is configured to transmit a second voltage signal provided by the second voltage signal terminal to the first node under control of the potential of the second node and a sixth control signal provided by the sixth control signal terminal.

[0029] In some embodiments, the noise reduction circuit comprises an eighth transistor and a ninth transistor. A control electrode of the eighth transistor is coupled to the second node; a first electrode of the eighth transistor is coupled to the second voltage signal terminal; and a second electrode of the eighth transistor is coupled to a first electrode of the ninth transistor. A control electrode of the ninth transistor is coupled to the sixth control signal terminal; and a second electrode of the ninth transistor is coupled to the first node.

[0030] In some embodiments, the sixth control signal terminal comprises a fourth clock signal terminal. A functional circuit is coupled in series between the second voltage signal terminal and the first node, and the functional circuit is further coupled to the first node. The functional circuit is configured to block a path between the second voltage signal terminal and the first node under control of the potential of the first node, so as to maintain the potential of the first node.

[0031] In some embodiments, the functional circuit includes a first transistor, the first transistor includes an oxide transistor; the first node is as one of the functional control terminals. The control electrode of the first transistor is coupled with the first node, the first electrode of the first transistor is coupled with the second voltage signal terminal, the second electrode in the first transistor is coupled with the first electrode of the eighth transistor, and the first electrode of the eighth transistor is coupled with the second voltage signal terminal through the first transistor. Alternatively, the control electrode of the first transistor is coupled with the first node, the first electrode of the first transistor is coupled with the second electrode of the eighth transistor, and the second electrode in the first transistor is coupled with the first electrode of the ninth transistor; the second electrode of the eighth transistor is coupled with the first electrode of the ninth transistor through the first transistor. Alternatively, the control electrode of the first transistor is coupled with the first node, the first electrode of the first transistor is coupled with the second electrode of the ninth transistor, the second electrode in the first transistor is coupled with the first node, and the second electrode of the ninth transistor is coupled with the first node through the first transistor.

[0032] In some embodiments, the sixth control signal terminal includes a fourth auxiliary clock signal terminal. The first noise reduction circuit includes a functional circuit. The functional circuit is configured to block the path between the first node and the second voltage signal terminal under the control of the fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal, so as to maintain the potential of the first node.

[0033] In some embodiments, the noise reduction circuit includes an eighth transistor and a ninth transistor. The functional circuit includes a ninth transistor, and the ninth transistor includes an oxide transistor. The fourth auxiliary clock signal terminal is as one of the functional control terminals. The control electrode of the eighth transistor is coupled with the second node, the first electrode of the eighth transistor is coupled with the second voltage signal terminal, the second electrode of the eighth transistor is coupled with the first electrode of the ninth transistor, the control electrode of the ninth transistor is coupled with the fourth auxiliary clock signal terminal, and the second electrode of the ninth transistor is coupled with the first node.

[0034] In some embodiments, the shift register further includes a first control circuit, and the first control circuit includes a first transistor. The eighth transistor is configured to be coupled with a second voltage signal line. In the plane where the shift register is located, the first transistor is located on the side of the second voltage signal line away from the eighth transistor.

[0035] In some embodiments, in the plane where the shift register is located, the first transistor is located between the first voltage signal terminal and the second voltage signal terminal.

[0036] In some embodiments, the shift register further comprises a first voltage stabilizing circuit. The circuit nodes further comprise a third node. The first voltage stabilizing circuit is coupled with the first node, the third node and an eighth control signal terminal, respectively. The first output circuit is coupled with the third node and the first node through the first voltage stabilizing circuit. The first voltage stabilizing circuit is configured to turn on the first node and the third node under the control of the potential of the third node and an eighth control signal provided by the eighth control signal terminal. The first output circuit is configured to transmit a first output signal provided by the first output signal terminal to the first scan signal terminal under the control of the potential of the third node.

[0037] In some embodiments, the first voltage stabilizing circuit comprises a tenth transistor. The eighth control signal terminal comprises a first voltage signal terminal. The control electrode of the tenth transistor is coupled with the first voltage signal terminal, the first electrode of the tenth transistor is coupled with the first node, and the second electrode of the tenth transistor is coupled with the third node.

[0038] In some embodiments, the eighth control signal terminal comprises a second voltage signal terminal. The first voltage stabilizing circuit is multiplexed as a functional circuit. The first voltage stabilizing circuit is further configured to block the path between the first node and the third node to maintain the potential of the third node under the control of the potential of the third node and a second voltage signal provided by the second voltage signal terminal.

[0039] In some embodiments, the functional circuit comprises a tenth transistor. The tenth transistor comprises an oxide transistor. The second voltage signal terminal serves as a functional control terminal. The control electrode of the tenth transistor is coupled with the second voltage signal terminal, the first electrode of the tenth transistor is coupled with the first node, and the second electrode of the tenth transistor is coupled with the third node.

[0040] In some embodiments, the shift register further comprises a second control circuit. The circuit nodes further comprise a fourth node. The second control circuit is coupled with the second node, the fourth node, a fourth clock signal terminal and a ninth control signal terminal, respectively. The second output circuit is coupled with the fourth node and the second node through the second control circuit. The second control circuit is configured to transmit a fourth clock signal provided by the fourth clock signal terminal to the fourth node under the control of the potential of the second node and a ninth control signal provided by the ninth control signal terminal. The second output circuit is configured to transmit a second output signal provided by the second output signal terminal to the first scan signal terminal under the control of the fourth node.

[0041] In some embodiments, the second control circuit includes an eleventh transistor, a twelfth transistor, and a first capacitor. A control electrode of the eleventh transistor is coupled with the second node, a first electrode of the eleventh transistor is coupled with the fourth clock signal terminal, and a second electrode of the eleventh transistor is coupled with a first electrode of the twelfth transistor. A control electrode of the twelfth transistor is coupled with the ninth control signal terminal, and a second electrode of the twelfth transistor is coupled with the fourth node. A first plate of the first capacitor is coupled with the second node, and a second plate of the first capacitor is coupled with the first electrode of the twelfth transistor.

[0042] In some embodiments, the ninth control signal terminal includes a fourth auxiliary clock signal terminal. The second control circuit includes a functional circuit. The functional circuit is configured to, under control of a fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal, block a path between the fourth clock signal terminal and the fourth node to maintain the potential of the fourth node.

[0043] In some embodiments, the second control circuit includes an eleventh transistor, a twelfth transistor, and a first capacitor. The functional circuit includes the twelfth transistor, and the twelfth transistor includes an oxide transistor. The fourth auxiliary clock signal terminal is one of the functional control terminals. A control electrode of the eleventh transistor is coupled with the second node, a first electrode of the eleventh transistor is coupled with the fourth clock signal terminal, and a second electrode of the eleventh transistor is coupled with a first electrode of the twelfth transistor. A control electrode of the twelfth transistor is coupled with the fourth auxiliary clock signal terminal, and a second electrode of the twelfth transistor is coupled with the fourth node. A first plate of the first capacitor is coupled with the second node, and a second plate of the first capacitor is coupled with the first electrode of the twelfth transistor.

[0044] In some embodiments, the first input circuit includes a second transistor. The shift register further includes a first control circuit, and the first control circuit includes a first transistor. In a plane on which the shift register is located, the first transistor is located between the second transistor and the first capacitor.

[0045] In some embodiments, the shift register further comprises a second voltage stabilizing circuit; the circuit nodes further comprise a fifth node. The second voltage stabilizing circuit is coupled with a tenth control signal terminal, the second node and the fifth node. The second control circuit is coupled with the fifth node and coupled with the second node through the second voltage stabilizing circuit. The second voltage stabilizing circuit is configured to form a path between the second node and the fifth node under the control of the potential of the fifth node and a tenth control signal provided by the tenth control signal terminal. The second control circuit is configured to transmit a fourth clock signal provided by a fourth clock signal terminal to the fourth node under the control of the potential of the fifth node and a ninth control signal provided by a ninth control signal terminal.

[0046] In some embodiments, the second voltage stabilizing circuit comprises a thirteenth transistor. A control electrode of the thirteenth transistor is coupled with the tenth control signal terminal, a first electrode of the thirteenth transistor is coupled with the second node, and a second electrode of the thirteenth transistor is coupled with the fifth node.

[0047] In some embodiments, the tenth control signal terminal comprises a second voltage signal terminal. The second voltage stabilizing circuit is multiplexed as a functional circuit. The second voltage stabilizing circuit is further configured to block the path between the second node and the fifth node under the control of the potential of the fifth node and a second voltage signal provided by the second voltage signal terminal, so as to maintain the potential of the fifth node.

[0048] In some embodiments, the functional circuit comprises the thirteenth transistor, and the thirteenth transistor comprises an oxide transistor. The second voltage signal terminal serves as one of the functional control terminals. A control electrode of the thirteenth transistor is coupled with the second voltage signal terminal, a first electrode of the thirteenth transistor is coupled with the second node, and a second electrode of the thirteenth transistor is coupled with the fifth node.

[0049] In some embodiments, the shift register further comprises a first voltage stabilizing circuit. The circuit nodes comprise a third node, a sixth node and a seventh node. The first control signal terminal comprises a first clock signal terminal and an eleventh control signal terminal. The first input circuit is coupled with the input signal terminal, the first node, the sixth node and the eleventh control signal terminal. The first input circuit is configured to transmit an input signal provided by the input signal terminal to the first node under the control of a first clock signal provided by the first clock signal terminal. The first input circuit is further configured to transmit the input signal provided by the input signal terminal to the sixth node under the control of an eleventh control signal provided by the eleventh control signal terminal.

[0050] The eighth control signal terminal includes a first voltage signal terminal and a twelfth control signal terminal. The first voltage stabilizing circuit is coupled with the third node, the sixth node, the seventh node, the first voltage signal terminal and the twelfth control signal terminal. The first voltage stabilizing circuit is configured to form a path between the first node and the third node under the control of the potential of the third node and a first voltage signal provided by the first voltage signal terminal. The first voltage stabilizing circuit is further configured to form a path between the sixth node and the seventh node under the control of the potential of the seventh node and a twelfth control signal provided by the twelfth control signal terminal.

[0051] In some embodiments, the first input circuit includes a second transistor and a third transistor. The control electrode of the second transistor is coupled with the first clock signal terminal, the first electrode of the second transistor is coupled with the input signal terminal, and the second electrode of the second transistor is coupled with the first node. The control electrode of the third transistor is coupled with the eleventh control signal terminal, the first electrode of the third transistor is coupled with the input signal terminal, and the second electrode of the third transistor is coupled with the sixth node. The first voltage stabilizing circuit includes a tenth transistor and a fourteenth transistor. The control electrode of the tenth transistor is coupled with the first voltage signal terminal, the first electrode of the tenth transistor is coupled with the first node, and the second electrode of the tenth transistor is coupled with the third node. The control electrode of the fourteenth transistor is coupled with the twelfth control signal terminal, the first electrode of the fourteenth transistor is coupled with the sixth node, and the second electrode of the fourteenth transistor is coupled with the seventh node.

[0052] In some embodiments, the eleventh control signal terminal includes a first auxiliary clock signal terminal. The first input circuit includes a functional circuit. The functional circuit is configured to block the path between the input signal terminal and the sixth node under the control of a first auxiliary clock signal provided by the first auxiliary clock signal terminal to maintain the potential of the sixth node.

[0053] In some embodiments, the first input circuit includes a second transistor and a third transistor. The functional circuit includes a third transistor, and the third transistor includes an oxide transistor. The first auxiliary clock signal terminal is one of the functional control terminals. The control electrode of the second transistor is coupled with the first clock signal terminal, the first electrode of the second transistor is coupled with the input signal terminal, and the second electrode of the second transistor is coupled with the first node. The control electrode of the third transistor is coupled with the first auxiliary clock signal terminal, the first electrode of the third transistor is coupled with the input signal terminal, and the second electrode of the third transistor is coupled with the sixth node.

[0054] In some embodiments, the twelfth control signal terminal comprises a second voltage signal terminal. The first voltage regulating circuit comprises a functional circuit. The functional circuit is configured to, under control of a second voltage signal provided by the second voltage signal terminal, block a path between the sixth node and the seventh node to maintain the potential of the seventh node.

[0055] In some embodiments, the first voltage regulating circuit comprises a tenth transistor and a fourteenth transistor. The functional circuit comprises the fourteenth transistor, the fourteenth transistor comprising an oxide transistor; the second voltage signal terminal as one of the functional control terminals. The tenth transistor has a control electrode coupled to the first voltage signal terminal, a first electrode coupled to the first node, and a second electrode coupled to the third node. The fourteenth transistor has a control electrode coupled to the second voltage signal terminal, a first electrode coupled to the sixth node, and a second electrode coupled to the seventh node.

[0056] In some embodiments, the shift register further comprises a third voltage regulating circuit. The third voltage regulating circuit is coupled to the seventh node and the third node, respectively. The third voltage regulating circuit is configured to, under control of the potential of the seventh node, conduct between the seventh node and the third node.

[0057] In some embodiments, the third voltage regulating circuit comprises a fifteenth transistor. The fifteenth transistor has a control electrode coupled to the seventh node, a first electrode coupled to the seventh node, and a second electrode coupled to the third node.

[0058] In some embodiments, the first output signal terminal comprises a fourth clock signal terminal or a first voltage signal terminal. The first output circuit comprises a sixteenth transistor. The sixteenth transistor has a control electrode coupled to the first node, a first electrode coupled to the first output signal terminal, and a second electrode coupled to the first scan signal terminal. The second output signal terminal comprises a second clock signal terminal or a second voltage signal terminal. The second output circuit comprises a seventeenth transistor and a second capacitor. The seventeenth transistor has a control electrode coupled to the second node, a first electrode coupled to the second output signal terminal, and a second electrode coupled to the first scan signal terminal. The second capacitor has a first plate coupled to the second output signal terminal and a second plate coupled to the second node.

[0059] In some embodiments, the shift register further includes a first control circuit. The first control circuit includes a first transistor. The first transistor includes a first gate pattern, an active layer, and a second gate pattern which are sequentially stacked on one side of a substrate, and a material of the active layer includes an oxide semiconductor material. The second gate pattern in the first transistor is provided in the same layer as the control electrode of the seventeenth transistor.

[0060] In another aspect, a scan driving circuit is provided. The scan driving circuit includes a first voltage signal line, and N-stage cascaded shift registers which are sequentially arranged along an extension direction of the first voltage signal line. The shift register is the shift register described above.

[0061] In some embodiments, two adjacent shift registers are symmetrically provided along a direction perpendicular to the extension direction of the first voltage signal line. Two oxide semiconductor structures belonging to the two adjacent shift registers are integrally formed.

[0062] In another aspect, a display device is provided. The display device includes a display region, and a peripheral region provided on at least one side of the display region. The display region includes a plurality of sub-pixels, and the peripheral region includes the scan driving circuit described above, which is coupled to the plurality of sub-pixels. BRIEF DESCRIPTION OF DRAWINGS

[0063] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings described in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual flow, actual timing, etc. of the product, method, signal, etc. involved in the embodiments of the present disclosure.

[0064] Figure 1 A structural diagram of a display device according to some embodiments;

[0065] Figure 2 A structural diagram of a pixel circuit according to some embodiments;

[0066] Figure 3 A structural diagram of a shift register according to some embodiments;

[0067] Figure 4A A sectional view of an oxide transistor in a shift register according to some embodiments, from one angle;

[0068] Figure 4B A sectional view of an oxide transistor in a shift register according to some embodiments, from another angle;

[0069] Figure 5 Structure diagram of a shift register according to some embodiments;

[0070] Figure 6 Structure diagram of a shift register according to some embodiments;

[0071] Figure 7 Structure diagram of a shift register according to some embodiments;

[0072] Figure 8 Structure diagram of a shift register according to some embodiments;

[0073] Figure 9 Structure diagram of a shift register according to some embodiments;

[0074] Figure 10 Structure diagram of a shift register according to some embodiments;

[0075] Figure 11 Structure diagram of a shift register according to some embodiments;

[0076] Figure 12 Structure diagram of a shift register according to some embodiments;

[0077] Figure 13 Structure diagram of a shift register according to some embodiments;

[0078] Figure 14 Top view of a shift register on a display substrate according to some embodiments;

[0079] Figure 15 Top view of a shift register on a display substrate according to some embodiments;

[0080] Figure 16 Structure diagram of a shift register according to some embodiments;

[0081] Figure 17 Structure diagram of a shift register according to some embodiments;

[0082] Figure 18 Structure diagram of a shift register according to some embodiments;

[0083] Figure 19 Top view of a shift register on a display substrate according to some embodiments;

[0084] Figure 20 Structure diagram of a shift register according to some embodiments;

[0085] Figure 21 Structure diagram of a shift register according to some embodiments;

[0086] Figure 22 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ;

[0087] Figure 23 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ;

[0088] Figure 24 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ;

[0089] Figure 25 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ;

[0090] Figure 26 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ;

[0091] Figure 27 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ;

[0092] Figure 28 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ;

[0093] Figure 29 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ;

[0094] Figure 30 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ;

[0095] Figure 31 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ;

[0096] Figure 32 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ;

[0097] Figure 33 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ; Figure 32

[0098] A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ; Figure 34

[0099] A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ; Figure 35 Figure 34 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ;

[0100] Figure 36 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ;

[0101] Figure 37 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ;

[0102] Figure 38 ​A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ;

[0103] Figure 39 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ;

[0104] Figure 40 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ;

[0105] Figure 41 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ;

[0106] Figure 42 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ; Figure 41

[0107] A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ; Figure 43

[0108] A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ; Figure 44

[0109] A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ; Figure 45

[0110] A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ; Figure 46

[0111] A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ; Figure 47

[0112] A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ; Figure 48

[0113] A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ; Figure 49

[0114] A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ; Figure 50 Figure 49 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ;

[0115] Figure 51 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ;

[0116] Figure 52 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ;

[0117] Figure 53 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ;

[0118] Figure 54 A timing diagram of a plurality of signal terminals and a plurality of nodes in the shift register shown in FIG. 1 1 ; ​

[0119] Figure 55 A top view of two shift registers on a display substrate in a display device according to some embodiments. DETAILED DESCRIPTION

[0120] The technical solutions in the some embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure but not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0121] Unless otherwise required by context, the term "comprise" and its other forms such as "comprises" and "comprising" are to be construed as open, inclusive, meaning that "comprising" means "including but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to mean that the particular feature, structure, material or characteristic associated with that embodiment or example is included in at least one embodiment or example of the present disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics described can be included in any suitable manner in any one or more embodiments or examples.

[0122] Hereinafter, the terms "first", "second" are used only for the purpose of description and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0123] In describing some embodiments, "electrically connected" and "connected" and their derivatives can be used. For example, the term "point connection" can be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0124] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0125] The use of "configured to" herein is meant "open and inclusive," in that a device or pieces of equipment that are configured to perform additional tasks or steps are encompassed by the device.

[0126] Additionally, the use of "based on" is meant to be open and inclusive, in that a process, step, calculation, or other action that is "based on" one or more recited conditions or values can be based on additional conditions or values beyond those recited.

[0127] In describing some embodiments, the use of "coupled" and "connected," and variations thereof, is intended to indicate either a direct electrical connection between two or more components or an indirect electrical connection through one or more additional components. For example, any of the components described herein could be directly or indirectly coupled to or connected with any of the other components by way of one or more buses and buses could be shared between multiple components—returning to the example of a bus, the bus that is shared could provide signals to one component generalized to a bus shared between components or the bus that is shared could provide return signal information from one component generalized to a bus shared between components. In contrast, the use of "coupled" can also mean that two or more components do not contact each other, but are mutually coordinated—each component acting independently and not in physical contact with each other. Herein "coupled" includes the two aforementioned meanings, in terms of either a direct physical connection or an indirect connection through one or more additional components.

[0128] In describing some embodiments, the use of "active potential" and "inactive potential" is intended to indicate that the active potential is a potential that is applied to a control terminal of a transistor that enables a path between a first terminal of the transistor and a second terminal of the transistor, and the inactive potential is a potential that is applied to the control terminal of the transistor that does not enable the path between the first terminal of the transistor and the second terminal of the transistor.

[0129] The relationship between the "first clock signal" and the "first auxiliary clock signal" is that, in a working phase, the potential of the first auxiliary clock signal is opposite to the potential of the first clock signal; in a buffer phase between two adjacent working phases, the potential of the first auxiliary clock signal can be the same as or opposite to the potential of the first clock signal. For example, in a working phase, the potential of the first clock signal is a high potential, and the potential of the first auxiliary clock signal is a low potential. For another example, in a buffer phase, the potential of the first clock signal is a high potential, and the potential of the first auxiliary clock signal can be a high potential or a low potential.

[0130] Similarly, the relationship between the "second clock signal" and the "second auxiliary clock signal", the relationship between the "third clock signal" and the "third auxiliary clock signal", and the relationship between the "fourth clock signal" and the "fourth auxiliary clock signal" can be referred to the relationship between the "first clock signal" and the "first auxiliary clock signal", which will not be described herein.

[0131] As used herein, "approximately" or "about" includes the recited value and the average value within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0132] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0133] The shift register in the scan driving circuit is mainly composed of transistors, capacitors and the like. In the working process of the shift register, the potential of the internal control node is controlled by the transistors and capacitors, and then the output of the scan signal is realized.

[0134] In some embodiments, the scan driving circuit includes a plurality of low temperature poly-silicon thin film transistors (LTPS TFTs), and there are two poles of the LTPS TFTs respectively connected to signal ends providing signals with different potentials.

[0135] The present inventors have found that, due to the large electron mobility of the LTPS TFT, the leakage current thereof is also large. In the case that the two poles of the LTPS TFTs respectively receive signals with different potentials, even if the LTPS TFT is in an off state, leakage will occur between the two poles of the LTPS TFT, causing the internal circuit node potential to be unstable, and reducing the reliability of the display device.

[0136] Based on this, some embodiments of the present disclosure provide a shift register, a scan driving circuit and a display device, which are introduced below respectively.

[0137] Figure 1 A structural schematic diagram of a display device according to some embodiments. For example, as shown in FIG. 1, the display device includes a scan driving circuit 100, a data driving circuit 200 and a display panel 300. Figure 1As shown, the display substrate 10 in the display device 1 includes a display region (i.e. pixel array region) AA and a peripheral region SA located at least one side of the display region AA, the display region AA includes: a plurality of rows and columns of sub-pixels P arranged in an array, a plurality of enable signal lines (EL1, …, ELi, …, ELm (i is an integer greater than or equal to 1, and m is an integer greater than or equal to i)) connected to the enable sub-circuits of the plurality of rows of sub-pixels P respectively, a plurality of reset signal lines (RL1, …, RLi, …, RLm) connected to the reset sub-circuits of the plurality of rows of sub-pixels P respectively, a plurality of first gate lines (GN1, …, GNi, …, GNm) connected to the compensation sub-circuits of the plurality of rows of sub-pixels P respectively, and a plurality of second gate lines (GP1, …, GPi, …, GPm) connected to the data writing sub-circuits of the plurality of rows of sub-pixels P respectively. For example, each sub-pixel P can include a pixel circuit having a circuit structure of 7T1C, 7T2C, 8T2C or 4T1C and a light emitting element in the art.

[0138] The peripheral region SA can include a first scan driving circuit 21 and a second scan driving circuit 22.

[0139] In some examples, the first scan driving circuit 21 can be connected to the plurality of enable signal lines EL1, EL2, …, ELi, …, ELm through a plurality of first connection traces 30 respectively, to provide enable signals to the enable sub-circuits of the plurality of rows of sub-pixels P respectively. Since the first scan driving circuit 21 is used to drive the enable sub-circuits of the sub-pixels P, the first scan driving circuit 21 can also be referred to as an enable gate scan driving circuit (EM GOA). Each first connection trace 30 and the enable signal line ELi connected thereto can be integrally formed, and in actual application, the width of the first connection trace 30 and the enable signal line ELi can be the same or different, which is not limited in the present disclosure.

[0140] In some examples, the second scan driving circuit 22 is located at the side of the first scan driving circuit 21 close to the display region AA, and is connected to the plurality of reset signal lines RL1, RL2, …, RLi, …, RLm through a plurality of second connection traces 40 respectively, to provide first reset signals to the first reset sub-circuits of the plurality of rows of sub-pixels P respectively. Each second connection trace 40 and the reset signal line RLi connected thereto can be integrally formed, and in actual application, the width of the second connection trace 40 and the reset signal line RLi can be the same or different, which is not limited in the present disclosure.

[0141] In some examples, the second scan driving circuit 22 can also be connected to multiple first gate lines GN1, ..., GNi, ..., GNm via multiple third connection traces 50, respectively, to provide first gate signals to the compensation sub-circuits of multiple rows of sub-pixels P. For example, the second scan driving circuit 22 provides first gate signals to the N-type transistors in sub-pixels P, therefore the second scan driving circuit 22 can also be called GATE GOA N, or simply GN. Each third connection trace 50 and the third gate scan signal line GNi connected thereto can be integrally formed. In practical applications, the widths of the third connection traces 50 and the third gate scan signal lines GNi can be the same or different, and this disclosure does not limit this.

[0142] In some examples, the peripheral area SA may also include a third scan driving circuit 23. The third scan driving circuit 23 is connected to multiple second gate lines GP1, ..., GPi, ..., GPm via multiple fourth connection traces 60, respectively, to provide second gate signals to the data writing sub-circuits of multiple rows of sub-pixels P. The second scan driving circuit 22 is located between the first scan driving circuit 21 and the third scan driving circuit 23, that is, the third scan driving circuit 23 is located on the side of the second scan driving circuit 22 closer to the display area 10. For example, the third scan driving circuit 23 provides second gate signals for the P-type transistors in the sub-pixel P, so the third scan driving circuit 23 can also be called GATE GOA P, or simply GP. Each fourth connection trace 60 and the second gate line GPi connected thereto can be integrally formed. In practical applications, the widths of the fourth connection traces 60 and the second gate lines GPi can be the same or different, and this disclosure does not limit this.

[0143] like Figure 1 As shown, data lines DL1 to DLn (n being an integer greater than 1) vertically pass through the display area AA to provide data signals for the multiple columns of sub-pixels P arranged in the array. For example, the pixel circuit in sub-pixels P operates under the control of the data signals transmitted through the data lines and the gate scan drive signal and enable signal transmitted through the gate lines to drive the light-emitting element to emit light, thereby realizing operations such as display. The light-emitting element can be, for example, an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED), and the embodiments disclosed herein are not limited thereto.

[0144] Figure 2 This is a circuit structure diagram of a sub-pixel according to some embodiments. For example... Figure 2 As shown, sub-pixel P includes a light-emitting element E and a pixel circuit M that drives the light-emitting element E to emit light. The pixel circuit M includes a driving sub-circuit 71, a data writing sub-circuit 72, a compensation sub-circuit 73, a reset sub-circuit 74, an enable sub-circuit 75, and a storage capacitor Cst.

[0145] The reset sub-circuit 74 includes a first reset sub-circuit 741 including a first reset transistor BT1. The compensation sub-circuit 73 includes a compensation transistor BT2. The driving sub-circuit 71 includes a driving transistor BT3. The data writing sub-circuit 72 includes a data writing transistor BT4. The enable sub-circuit 75 includes a first enable sub-circuit 751 including a first enable transistor BT5 and a second enable sub-circuit 752 including a second enable transistor BT6. The reset sub-circuit 74 further includes a second reset sub-circuit 742 including a second reset transistor BT7. For example, the first reset transistor BT1 and the compensation transistor BT2 are N-type transistors, and the data writing transistor BT4 and the second reset transistor BT7 are P-type transistors. The connection relationship and working principle of the pixel unit in the embodiments of the present disclosure are merely examples, and the pixel unit can also adopt other structures according to needs, which are not limited in the present disclosure.

[0146] As shown in FIG. 1, in some embodiments, the pixel circuit M is described as a whole: Figure 2

[0147] The control electrode of the first reset transistor BT1 is coupled with the reset signal line RTi, and the first electrode of the first reset transistor BT1 is coupled with the first initial signal line Vinit1. The first reset transistor BT1 is configured to transmit the first initial signal provided by the first initial signal line Vinit1 to the first node S1 under the control of the first reset signal provided by the reset signal line RTi.

[0148] The control electrode of the compensation transistor BT2 is coupled with the first gate line GNi, the first electrode of the compensation transistor BT2 is coupled with the first node S1, and the second electrode of the compensation transistor BT2 is coupled with the third node S3. The compensation transistor BT2 is configured to form a path between the first node S1 and the third node S3 under the control of the first gate signal provided by the first gate line GNi.

[0149] The control electrode of the driving transistor BT3 is coupled with the first node S1, the first electrode of the driving transistor BT3 is coupled with the second node S2, and the second electrode of the driving transistor BT3 is coupled with the third node S3. The driving transistor BT3 is configured to form a path between the second node S2 and the third node S3 under the control of the potential of the first node S1.

[0150] ​A control electrode of the data write transistor BT4 is coupled with the second gate line GPi, a first electrode of the data write transistor BT4 is coupled with the data line Vdata, and a second electrode of the data write transistor BT4 is coupled with the second node S2. The data write transistor BT4 is configured to transmit a data signal provided by the data line Vdata to the second node S2 under control of a second gate signal provided by the second gate line GPi.

[0151] A control electrode of the first enable transistor BT5 is coupled with the enable signal line ELi, a first electrode of the first enable transistor BT5 is coupled with the first power supply end VDD, and a second electrode of the first enable transistor BT5 is coupled with the second node S2. The first enable transistor BT5 is configured to transmit a first power supply signal provided by the first power supply end to the second node S2 under control of an enable signal provided by the enable signal line ELi.

[0152] A control electrode of the second enable transistor BT6 is coupled with the enable signal line ELi, a first electrode of the second enable transistor BT6 is coupled with the third node, and a second electrode of the second enable transistor BT6 is coupled with the fourth node. The second enable transistor BT6 is configured to form a path between the third node and the fourth node under control of an enable signal provided by the enable signal line ELi.

[0153] A control electrode of the second reset transistor BT7 is coupled with the second gate line GPi, a first electrode of the second reset transistor BT7 is coupled with the second initial signal line Vinit2, and a second electrode of the second reset transistor BT7 is coupled with the fourth node. The second reset transistor BT7 is configured to transmit a second initial signal provided by the second initial signal line Vinit2 to the fourth node under control of a second gate signal provided by the second gate line GPi.

[0154] In some embodiments, any scan driving circuit includes a plurality of shift registers cascaded, and each shift register is configured to drive one or more rows of the sub-pixels P. Embodiments of the present disclosure are described by taking an example in which each shift register is configured to drive one row of the sub-pixels P, but embodiments of the present disclosure are not limited thereto.

[0155] For example, the peripheral region can further include a first voltage signal line (not shown) and a second voltage signal line (not shown). Figure 1 Figure 1 ​The first voltage signal line is configured to provide a first voltage signal, and the second voltage signal line is configured to provide a second voltage signal. A potential value of the first voltage signal is less than a potential value of the second voltage signal. The first scan driving circuit 21 is coupled with the first voltage signal line to output the first voltage signal as a first part of the enable signal. For example, the first voltage signal line is connected with each of the plurality of first shift registers in the first scan driving circuit 21. The first part of the enable signal is, for example, a low potential part of the enable signal, which can enable the first enable transistor BT5 and the second enable transistor BT6 to be in a conductive state in the light emitting stage. The first scan driving circuit 21 is also coupled with the second voltage signal line to output the second voltage as a second part of the enable signal. For example, the second voltage signal line is coupled with each of the plurality of first shift registers in the first scan driving circuit 21. The second part of the enable signal is, for example, a high potential part of the enable signal, which can disable the first enable transistor BT5 and the second enable transistor BT6 to be in a non-conductive state in the light emitting stage.

[0156] Please refer to Figure 3 , Figure 3 FIG. 1 is a structural diagram of a shift register according to some embodiments. The embodiments of the present disclosure provide a shift register 100. The shift register 100 includes a first input circuit 110, a first output circuit 120, a second input circuit 130, a second output circuit 140, and at least one function circuit 150.

[0157] The first input circuit 110 is coupled with an input signal terminal Input, a first control signal terminal K1, and a first node N1. The first input circuit 110 is configured to transmit an input signal provided by the input signal terminal Input to the first node N1 under the control of a first control signal provided by the first control signal terminal K1.

[0158] In some examples, the first control signal terminal K1 can be a first clock signal terminal CLK1. In other examples, the first control signal terminal K1 can be a first auxiliary clock signal terminal NCLK1. In yet other examples, the first control signal terminal K1 can include a first clock signal terminal CLK1 and a second clock signal terminal CLK2. In yet other examples, the first clock signal terminal CLK1 and a second auxiliary clock signal terminal NCLK2. In yet other examples, the first auxiliary clock signal terminal NCLK1 and a second clock signal terminal CLK2.

[0159] The first output circuit 120 is coupled with a first output signal terminal S1, the first node N1, and a first scan signal terminal Gout1. The first output circuit 120 is configured to transmit a first output signal provided by the first output signal terminal S1 to the first scan signal terminal Gout1 under the control of a potential of the first node N1.

[0160] The first output signal terminal S1 can include a fourth clock signal terminal CLK4 or a first voltage signal terminal VGL.

[0161] The second input circuit 130 is coupled with the first voltage signal terminal VGL, a second control signal terminal K2 and a second node N2. The second input circuit 130 is configured to transmit a first voltage signal provided by the first voltage signal terminal VGL to the second node N2 under the control of a second control signal provided by the second control signal terminal K2.

[0162] The second control signal terminal K2 can include a first clock signal terminal CLK1 or a first auxiliary clock signal terminal NCLK1.

[0163] The second output circuit 140 is coupled with a second output signal terminal S2, the second node N2 and a first scan signal terminal Gout1. The second output circuit 140 is configured to transmit a second output signal provided by the second output signal terminal S2 to the first scan signal terminal Gout1 under the control of the potential of the second node N2.

[0164] The second output signal terminal S2 can include a second voltage signal terminal VGH or a second clock signal terminal CLK2.

[0165] The input signal terminal to which the first input circuit 110 in the current shift register is coupled can be coupled with the first scan signal terminal in the previous stage shift register, or can be coupled with a frame start signal line STV.

[0166] The functional circuit 150 is coupled with a functional input terminal, a functional output terminal and a functional control terminal. The functional circuit 150 is configured to block the path between the functional input terminal and the functional output terminal under the control of a functional control signal provided by the functional control terminal, so as to maintain the potential of the functional output terminal.

[0167] The functional input terminal can include one of a plurality of clock signal terminals, such as the first clock signal terminal CLK1 or the fourth clock signal terminal CLK4. The functional input terminal can also include one of a plurality of voltage signal terminals, such as the first voltage signal terminal VGL or the second voltage signal terminal VGH. The functional input terminal can also include an input signal terminal Input, one of a plurality of circuit nodes, etc., which are not limited herein.

[0168] The function control terminal can include one of a plurality of circuit nodes, such as a first node N1. The function control terminal can also include one of a plurality of voltage signal terminals, such as a second voltage signal terminal VGH. The function control terminal can also include one of a plurality of clock signal terminals, such as a third clock signal terminal CLK3. The function control terminal can also include one of a plurality of auxiliary clock signal terminals, such as a first auxiliary clock signal terminal NCLK1, and such as a third auxiliary clock signal terminal NCLK3. Of course, the function control terminal can also be one of a plurality of scan signal terminals, and the like, without limitation.

[0169] The function output terminal can include one of a plurality of circuit nodes, including at least a first node N1 and a second node N2. That is, the function output terminal of the function circuit 150 is coupled to one circuit node.

[0170] The function circuit 150, under the control of the function control signal provided at the function control terminal, blocks the path between the function input terminal and the function output terminal, and has the effect of blocking the function input terminal and the function output terminal.

[0171] The shift register provided by the embodiments of the present disclosure, under the control of the function control signal provided at the function control terminal, the function circuit 150 can block the path between the function input terminal and the function output terminal, reduce or even eliminate the influence of the function input terminal potential on the function output terminal potential, improve the stability of the internal circuit node potential of the shift register, and further improve the reliability of the display device.

[0172] In some embodiments, the function circuit 150 can be a switch circuit. Under the control of the function control signal provided at the function control terminal, the path between the input terminal (i.e., the function input terminal) of the switch circuit and the output terminal (i.e., the function output terminal) of the switch circuit is blocked.

[0173] In some embodiments, the function circuit 150 can include a low temperature polycrystalline oxide thin film transistor (LTPO TFT). The control electrode of the oxide transistor is coupled to the function control terminal, the first electrode of the oxide transistor is coupled to the function input terminal, and the second electrode of the oxide transistor is coupled to the function output terminal.

[0174] The oxide transistor refers to a transistor having an oxide semiconductor channel. The material of the oxide semiconductor channel can include indium gallium zinc oxide (IGZO) and other suitable oxide materials, which are not limited herein. The oxide transistor has a smaller off-state leakage current than the LTPS TFT, which can reduce or even eliminate the influence of the potential of the first electrode (functional input terminal) of the oxide transistor on the potential of the second electrode (functional output terminal) of the oxide transistor, improve the stability of the internal control node potential of the shift register, and further improve the reliability of the display device.

[0175] As shown in FIG. 1, in some embodiments, the oxide transistor T0 in the display substrate 10 includes a first gate pattern 310, an active layer 320, and a second gate pattern 330 which are sequentially stacked on one side of a substrate 300. The material of the active layer 220 includes an oxide semiconductor material. Figure 4A

[0176] The substrate 300 can be an organic substrate or an inorganic substrate. The material of the substrate 300 can be polyethylene terephthalate (PET), polyimide (PI), cyclo olefin polymer (COP), a glass substrate, and the like, which are not limited herein.

[0177] At least one gate insulating layer can be further provided between the substrate 300 and the first gate pattern 310. As shown in FIG. 2, the substrate 300 sequentially includes a first gate insulating layer 341 and a second gate insulating layer 342 from the direction away from the substrate 300. Figure 4A

[0178] The material of the first gate insulating layer 341 and / or the material of the second gate insulating layer 342 can be one or a combination of oxide, nitride, or oxynitride, which are not limited herein. In some examples, the material of the first gate insulating layer 341 includes oxide, and the material of the second gate insulating layer 342 includes nitride.

[0179] In some embodiments, a buffer layer can be further included between the substrate 300 and the first gate insulating layer 341, which is not limited herein.

[0180] As shown in FIG. 3, the first gate pattern 310 is formed above the second gate insulating layer 342. The material of the first gate pattern 310 can be a conductive material, such as a metal material or an alloy material. The metal material can be aluminum (Al), silver (Ag), magnesium (Mg), ytterbium (Yb), lithium (Li), and the like. Figure 4A

[0181] ​​​A third gate insulating layer 343 may also be included between the first gate pattern 310 and the active layer 320. The third gate insulating layer 343 covers the first gate pattern 310. The material of the third gate insulating layer 343 may be the same as the material of the first gate insulating layer 341 and / or the material of the second gate insulating layer 342, which will not be described in detail here.

[0182] An active layer 320 is formed above the third gate insulating layer 343. A fourth gate insulating layer 344 may also be included between the active layer 320 and the second gate pattern 330. The fourth gate insulating layer 344 covers the active layer 320. The material of the fourth gate insulating layer 344 may be the same as the material of the first gate insulating layer 341 and / or the material of the second gate insulating layer 342, which will not be described in detail here.

[0183] The second gate pattern 330 is formed above the fourth gate layer 344. The dimension of the active layer 320 in the direction parallel to the substrate 300 can be smaller than the dimension of the second gate pattern 330 in the direction parallel to the substrate 300. Alternatively, the dimension of the active layer 320 in the direction parallel to the substrate 300 can be larger than the dimension of the second gate pattern 330 in the direction parallel to the substrate 300. For example, the orthographic projection of the second gate pattern 330 onto the substrate 300 can be located inside the orthographic projection of the active layer 320 onto the substrate 300.

[0184] The active layer 320 is located between the first gate pattern 310 and the second gate pattern 330. That is, the orthographic projection of the active layer 320 on the substrate 300 is located within the overlapping region of the orthographic projection of the second gate pattern 330 on the substrate 300 and the orthographic projection of the first gate pattern 310 on the substrate 300.

[0185] like Figure 4A As shown, an interlayer dielectric layer 350 and a source / drain metal pattern 360 may be included above the second gate pattern 330. The interlayer dielectric layer 350 covers the second gate pattern 330. The source / drain metal pattern 360 can make electrical contact with the active layer 320 by penetrating the interlayer dielectric layer 350 and the fourth gate insulating layer 344. The first gate pattern 310 and the second gate pattern 330 can make electrical contact with different conductive patterns, or they can make electrical contact with the same conductive pattern; this is not limited here.

[0186] like Figure 4B As shown, in some embodiments, the oxide transistor T0 includes source / drain metal patterns 360. The same source / drain metal pattern 360 is coupled to a first gate pattern 341 and a second gate pattern 342, respectively.

[0187] The active layer 320 can have a dimension in a direction parallel to the substrate 300 that is smaller than a dimension of the first gate pattern 310 in a direction parallel to the substrate 300. In some examples, a footprint of the active layer 320 on the substrate 300 can be located inside a footprint of the first gate pattern 310 on the substrate 300.

[0188] The source-drain metal pattern 360 can be in direct contact with the first gate pattern 341 and the second gate pattern 342 to achieve coupling with the first gate pattern 341 and the second gate pattern 342. The source-drain metal pattern 360 can also be coupled with the first gate pattern 341 and the second gate pattern 342 through vias.

[0189] In some examples, as shown in FIG. 3, one source-drain metal pattern 360 is located on a side of the first gate pattern 341 and the second gate pattern 342 away from the substrate 300. The source-drain metal pattern 360 is coupled with the first gate pattern 341 through a third via H3 and coupled with the second gate pattern 342 through a fourth via H4. Figure 4B

[0190] The first input circuit 110 can have various configurations, which will be described in detail below through multiple embodiments.

[0191] As shown in FIG. 4, in some embodiments, the first control signal terminal K1 includes a first clock signal terminal CLK1. The first input circuit 110 includes a second transistor T2. Figure 5 Exemplarily, a control electrode of the second transistor T2 is coupled with the first clock signal terminal CLK1, a first electrode of the second transistor T2 is coupled with the input signal terminal Input, and a second electrode of the second transistor T2 is coupled with the first node N1.

[0192] In some examples, the second transistor T2 is a P-type transistor. The second transistor T2 transmits an input signal provided by the input signal terminal to the first node N1 under the control of the first clock signal being a low potential signal.

[0193] As shown in FIG. 5, in another embodiment, the first control signal terminal K1 includes a first auxiliary clock signal terminal NCLK1, and the first input circuit 110 is multiplexed as a functional circuit 150. The first auxiliary clock signal terminal NCLK1 serves as a functional control terminal, the input signal terminal serves as a functional input terminal, and the first node N1 serves as a functional output terminal.

[0194] Figure 6 The first input circuit 110 is further configured to, under the control of a first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1, block a path between the input signal terminal and the first node N1 to maintain the potential of the first node N1.

[0195] The first input circuit 110 is further configured to, under the control of a first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1, block a path between the input signal terminal and the first node N1 to maintain the potential of the first node N1. ​​

[0196] In some examples, when the potential of the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is an effective potential (e.g., a high potential), a path is formed between the input terminal (the input signal terminal) of the first input circuit 110 and the output terminal (the first node N1) of the first input circuit 110, and the input signal provided by the input signal terminal is transmitted to the first node N1. When the potential of the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is an ineffective potential (e.g., a low potential), the path between the input terminal (the input signal terminal) of the first input circuit 110 and the output terminal (the first node N1) of the first input circuit 110 is blocked, so as to maintain the potential of the first node N1.

[0197] As shown in FIG. 1, in some examples, the first input circuit 110 includes a second transistor T2, and the second transistor T2 includes an oxide transistor. Figure 6 For example, the control electrode of the second transistor T2 is coupled with the first auxiliary clock signal terminal NCLK1, the first electrode of the second transistor T2 is coupled with the input signal terminal, and the second electrode of the second transistor T2 is coupled with the first node N1.

[0198] For example, when the potential of the first auxiliary clock signal is an effective potential (e.g., a high potential), a path is formed between the first electrode (the input signal terminal) of the second transistor T2 and the second electrode (the first node N1) of the second transistor T2, and the input signal provided by the input signal terminal is transmitted to the first node N1. When the potential of the first auxiliary clock signal is an ineffective potential (e.g., a low potential), the path between the first electrode (the input signal terminal) of the second transistor T2 and the second electrode (the first node N1) of the second transistor T2 is blocked, so as to maintain the potential of the first node N1.

[0199] As shown in FIG. 1, in some examples, the first input circuit 110 includes a second transistor T2, and the second transistor T2 includes an oxide transistor.

[0200] Figure 7-9 As shown in FIG. 1, in some examples, the first control signal terminal K1 includes a third control signal terminal K3 and a fourth control signal terminal K4. The third control signal terminal K3 can be one of the plurality of clock signal terminals, for example, the first clock signal terminal CLK1; or the third control signal terminal K3 can be one of the plurality of auxiliary clock signal terminals, for example, the first auxiliary clock signal terminal NCLK1. The fourth control signal terminal K4 can be one of the plurality of clock signal terminals, for example, the second clock signal terminal CLK2; or the fourth control signal terminal K4 can be one of the plurality of auxiliary clock signal terminals, for example, the second auxiliary clock signal terminal NCLK2.

[0201] As shown in FIG. 1, in some examples, the first input circuit 110 includes a second transistor T2, and the second transistor T2 includes an oxide transistor. Figure 7 ​As shown, the first input circuit 110 is coupled with the third control signal terminal K3 and the fourth control signal terminal K4 respectively. The first input circuit 110 is further configured to transmit the input signal provided by the input signal terminal to the first node N1 under the control of the third control signal provided by the third control signal terminal K3 and the fourth control signal provided by the fourth control signal terminal K4.

[0202] In some examples, the third control signal terminal K3 is the second clock signal terminal CLK2, and the fourth control signal terminal K4 is the first clock signal terminal CLK1. As shown in FIG. 1, the first input circuit 110 is coupled with the second clock signal terminal CLK2 and the first clock signal terminal CLK1. Figure 8 As shown, the first input circuit 110 includes a second transistor T2 and a third transistor T3. The control electrode of the second transistor T2 is coupled with the second clock signal terminal CLK2, the first electrode of the second transistor T2 is coupled with the input signal terminal, the second electrode of the second transistor T2 is coupled with the first electrode of the third transistor T3, the control electrode of the third transistor T3 is coupled with the first clock signal terminal CLK1, and the second electrode of the third transistor T3 is coupled with the first node N1.

[0203] Taking the second transistor T2 and the third transistor T3 as P-type transistors as an example, when the second clock signal provided by the second clock signal terminal CLK2 and the third clock signal provided by the third clock signal terminal CLK3 are both low potential signals, a path between the input signal terminal and the first node N1 is formed, and the input signal provided by the input signal terminal is transmitted to the first node N1.

[0204] As shown in FIG. 1, in some embodiments, the first input circuit 110 includes a functional circuit 150 coupled in series between the input signal terminal and the first node N1. Figure 9

[0205] In some embodiments, the third control signal terminal K3 serves as a functional control terminal. The functional circuit 150 is configured to block the path between the input signal terminal and the first node N1 under the control of the third control signal provided by the third control signal terminal K3, so as to maintain the potential of the first node N1.

[0206] ​In some examples, the first input circuit 110 includes a second transistor T2 and a third transistor T3, and the second transistor T2 includes an oxide transistor. A control electrode of the second transistor T2 is coupled to a third control signal terminal K3, a first electrode of the second transistor T2 is coupled to an input signal terminal, a second electrode of the second transistor T2 is coupled to a first electrode of the third transistor T3, a control electrode in the third transistor T3 is coupled to a fourth control signal terminal K4, and a second electrode of the third transistor T3 is coupled to the first node N1. In a case where a third control signal provided at the third control signal terminal K3 has an invalid potential, a path between the first electrode of the second transistor T2 and the second electrode of the second transistor T2 is blocked, a path between the input signal terminal and the first node N1 is blocked, and a potential of the first node N1 is maintained. The input signal terminal is a functional input terminal, and the first node N1 is a functional output terminal through the third transistor T3.

[0207] Exemplarily, the second transistor T2 is an N-type transistor, and the third transistor T3 is a P-type transistor. In a case where a third control signal provided at the third control signal terminal K3 is a high potential signal and a fourth control signal provided at the fourth control signal terminal K4 is a low potential signal, a path between the input signal terminal and the first node N1 is formed, and an input signal provided at the input signal terminal is transmitted to the first node N1. In a case where the third control signal provided at the third control signal terminal K3 is a low potential signal, a path between the first electrode of the second transistor T2 and the second electrode of the second transistor T2 is blocked, a path between the input signal terminal and the first node N1 is blocked, and a potential of the first node N1 is maintained.

[0208] As shown in FIG. 1, Figure 9 In some examples, the third control signal terminal K3 includes a second auxiliary clock signal terminal NCLK2, and the fourth control signal terminal K4 includes a first clock signal terminal CLK1. The first input circuit 110 includes a second transistor T2 and a third transistor T3, and the second transistor T2 includes an oxide transistor.

[0209] Exemplarily, the second transistor T2 is an N-type transistor, and the third transistor T3 is a P-type transistor. In a case where a second auxiliary clock signal provided at the second auxiliary clock signal terminal NCLK2 is a high potential signal and a first clock signal provided at the first clock signal terminal CLK1 is a low potential signal, a path between the input signal terminal and the first node N1 is formed, and an input signal provided at the input signal terminal is transmitted to the first node N1. In a case where the second auxiliary clock signal provided at the second auxiliary clock signal terminal NCLK2 is a low potential signal, a path between the first electrode of the second transistor T2 and the second electrode of the second transistor T2 is blocked, a path between the input signal terminal and the first node N1 is blocked, and a potential of the first node N1 is maintained.

[0210] As shown in FIG. 9, in some examples, the third control signal terminal K3 includes a first clock signal terminal CLK1, and the fourth control signal terminal K4 includes a second clock signal terminal CLK2. The first input circuit 110 includes a second transistor T2 and a third transistor T3. The third transistor T3 includes an oxide transistor. Figure 10 As shown in FIG. 9, in some examples, the third control signal terminal K3 includes a first clock signal terminal CLK1, and the fourth control signal terminal K4 includes a second clock signal terminal CLK2. The first input circuit 110 includes a second transistor T2 and a third transistor T3. The third transistor T3 includes an oxide transistor.

[0211] In some examples, the first input circuit 110 includes a second transistor T2 and a third transistor T3, and the third transistor T3 includes an oxide transistor. The control electrode of the second transistor T2 is coupled to the third control signal terminal K3, the first electrode of the second transistor T2 is coupled to the input signal terminal, the second electrode of the second transistor T2 is coupled to the first electrode of the third transistor T3, the control electrode of the third transistor T3 is coupled to the fourth control signal terminal K4, and the second electrode of the third transistor T3 is coupled to the first node N1. When the fourth control signal provided by the fourth control signal terminal K4 has an invalid potential, the path between the first electrode of the third transistor T3 and the second electrode of the third transistor T3 is blocked, thereby blocking the path between the input signal terminal and the first node N1 to maintain the potential of the first node N1. The input signal terminal serves as a functional input terminal through the second transistor T2, and the first node N1 serves as a functional output terminal.

[0212] For example, the second transistor T2 is a P-type transistor, and the third transistor T3 is an N-type transistor. When the third control signal provided by the third control signal terminal K3 is a low potential signal and the fourth control signal provided by the fourth control signal terminal K4 is a high potential signal, a path is formed between the input signal terminal and the first node N1, thereby transmitting the input signal provided by the input signal terminal to the first node N1. When the fourth control signal provided by the fourth control signal terminal K4 is a low potential signal, the path between the first electrode of the second transistor T2 and the second electrode of the second transistor T2 is blocked, thereby blocking the path between the input signal terminal and the first node N1 to maintain the potential of the first node N1.

[0213] As shown in FIG. 9, in some examples, the third control signal terminal K3 includes a first clock signal terminal CLK1, and the fourth control signal terminal K4 includes a second clock signal terminal CLK2. The first input circuit 110 includes a second transistor T2 and a third transistor T3. The third transistor T3 includes an oxide transistor. Figure 10

[0214] ​In some examples, the second transistor T2 is a P-type transistor, and the third transistor T3 is an N-type transistor. When the second clock signal provided by the second clock signal terminal CLK2 is a low potential signal and the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a high potential signal, a path is formed between the input signal terminal and the first node N1, so as to transmit the input signal provided by the input signal terminal to the first node N1. When the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is at a low potential, a path between the first electrode of the third transistor T3 and the second electrode of the third transistor T3 is blocked, so as to block the path between the input signal terminal and the first node N1, so as to maintain the potential of the first node N1.

[0215] The second input circuit 130 can have various configurations, which will be described in detail below through multiple embodiments.

[0216] As shown in FIG. 1, in some embodiments, the second control signal terminal K2 includes a first clock signal terminal CLK1. The second input circuit 130 includes a fourth transistor T4, a control electrode of the fourth transistor T4 is coupled to the first clock signal terminal CLK1, a first electrode of the fourth transistor T4 is coupled to the first voltage signal terminal VGL, and a second electrode of the fourth transistor T4 is coupled to a second node N2. Figure 5 In some examples, the fourth transistor T4 is a P-type transistor. The fourth transistor T4 is configured to form a path between the first electrode (the first voltage signal terminal VGL) of the fourth transistor T4 and the second electrode (the second node N2) of the fourth transistor T4 when the potential of the first clock signal provided by the first clock signal terminal CLK1 is at a low potential, so as to transmit the first voltage signal provided by the first voltage signal terminal VGL to the second node N2.

[0217] As shown in FIG. 1, in some embodiments, the second control signal terminal K2 includes a first clock signal terminal CLK1. The second input circuit 130 includes a fourth transistor T4, a control electrode of the fourth transistor T4 is coupled to the first clock signal terminal CLK1, a first electrode of the fourth transistor T4 is coupled to the first voltage signal terminal VGL, and a second electrode of the fourth transistor T4 is coupled to a second node N2.

[0218] Figure 11 As shown in FIG. 1, in some embodiments, the second control signal terminal K2 includes a first clock signal terminal CLK1. The second input circuit 130 includes a fourth transistor T4, a control electrode of the fourth transistor T4 is coupled to the first clock signal terminal CLK1, a first electrode of the fourth transistor T4 is coupled to the first voltage signal terminal VGL, and a second electrode of the fourth transistor T4 is coupled to a second node N2.

[0219] The second input circuit 130 is configured to form a path between the first voltage signal terminal VGL and the second node N2 when the potential of the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is at a valid potential, so as to transmit the first voltage signal provided by the first voltage signal terminal VGL to the second node N2.

[0220] ​The second input end is further configured to, in a case where the first auxiliary clock signal provided by the first auxiliary clock signal end NCLK1 has an invalid potential, block a path between the first voltage signal end VGL and the second node N2, so as to maintain the potential of the second node N2.

[0221] As shown in Figure 11 In some examples, the second input circuit 130 includes a fourth transistor T4, where the fourth transistor T4 includes an oxide transistor.

[0222] The control electrode of the fourth transistor T4 is coupled with the first auxiliary clock signal end NCLK1, the first electrode of the fourth transistor T4 is coupled with the first voltage signal end VGL, and the second electrode of the fourth transistor T4 is coupled with the second node N2.

[0223] In some examples, the fourth transistor T4 is an N-type transistor. In a case where the first auxiliary clock signal provided by the first auxiliary clock signal end NCLK1 is a high potential signal, a path between the first electrode (the first voltage signal end VGL) of the fourth transistor T4 and the second electrode (the second node N2) of the fourth transistor T4 is formed, so as to realize transmission of the first voltage signal provided by the first voltage signal end VGL to the second node N2. In a case where the first auxiliary clock signal provided by the first auxiliary clock signal end NCLK1 is a low potential signal, the path between the first electrode (the first voltage signal end VGL) of the fourth transistor T4 and the second electrode (the second node N2) of the fourth transistor T4 is blocked, so as to realize blocking of the path between the first voltage signal end VGL and the second node N2, so as to maintain the potential of the second node N2.

[0224] The first control circuit 160 can have various settings, which will be described in detail through multiple embodiments.

[0225] As shown in Figure 3 In some embodiments, the shift register further includes a first control circuit 160. The first control circuit 160 is coupled with the fifth control signal end K5, the second node N2, and the third output signal end S3, respectively. The first control circuit 160 is configured to, under the control of a fifth control signal provided by the fifth control signal end K5, transmit a third output signal provided by the third output signal end S3 to the second node N2.

[0226] The fifth control signal end K5 can be one of the plurality of clock signal ends, for example, the fourth clock signal end CLK4. The fifth control signal end K5 can also be one of the plurality of circuit nodes, for example, the first node N1. The fifth control signal end K5 can also be the first scan signal end. The fifth control signal end K5 can also be one of the plurality of auxiliary clock signal ends, for example, the first auxiliary clock signal end NCLK1, which is not limited here.

[0227] The third output signal terminal S3 can be one of the plurality of clock signal terminals, for example, the first clock signal terminal CLK1. The third output signal terminal S3 can also be one of the plurality of voltage signal terminals, for example, the second voltage signal terminal VGH.

[0228] As shown in FIG. 1, in some embodiments, the first control circuit 160 includes a fifth transistor T5. A control electrode of the fifth transistor T5 is coupled to a fifth control signal terminal K5. A first electrode of the fifth transistor T5 is coupled to the third output signal terminal S3. A second electrode of the fifth transistor T5 is coupled to the second node N2. Figure 5 As shown in FIG. 2, in some examples, the fifth control signal is the first node N1, and the third output signal terminal S3 is the first clock signal terminal CLK1. The control electrode of the fifth transistor T5 is coupled to the first node N1. The first electrode of the fifth transistor T5 is coupled to the first clock signal terminal CLK1. The second electrode of the fifth transistor T5 is coupled to the second node N2. The fifth transistor T5 is configured to transmit a first clock signal provided by the first clock signal terminal CLK1 to the second node N2 under control of the potential of the first node N1.

[0229] Figure 12 As shown in FIG. 3, in other examples, the fifth control signal is the first node N1, and the third output signal terminal S3 is the second voltage signal terminal VGH. The control electrode of the fifth transistor T5 is coupled to the first node N1. The first electrode of the fifth transistor T5 is coupled to the second voltage signal terminal VGH. The second electrode of the fifth transistor T5 is coupled to the second node N2. The fifth transistor T5 is configured to transmit a second voltage signal provided by the second voltage signal terminal VGH to the second node N2 under control of the potential of the first node N1.

[0230] As shown in FIG. 4, in other embodiments, a functional circuit 150 is coupled in series between the second node N2 and the third output signal terminal S3. The third output signal terminal S3 includes the first clock signal terminal CLK1, and the functional control terminal includes a third clock signal terminal CLK3. Figure 13 The functional circuit 150 is configured to block a path between the second node N2 and the first clock signal terminal CLK1 under control of a third clock signal provided by the third clock signal terminal CLK3, so as to maintain the potential of the second node N2.

[0231] Figure 3 The functional circuit 150 is configured to block a path between the second node N2 and the first clock signal terminal CLK1 under control of a third clock signal provided by the third clock signal terminal CLK3, so as to maintain the potential of the second node N2.

[0232] The functional circuit 150 is configured to block a path between the second node N2 and the first clock signal terminal CLK1 under control of a third clock signal provided by the third clock signal terminal CLK3, so as to maintain the potential of the second node N2.

[0233] ​​The functional circuit 150 can be located between the first clock signal terminal CLK1 and the first control circuit 160, or between the second node N2 and the first control circuit 160. The functional input terminal of the functional circuit 150 is the first clock signal terminal CLK1, the functional output terminal is the second clock signal terminal CLK2, and the path between the first clock signal terminal CLK1 and the second node N2 can be blocked to maintain the potential of the second node N2.

[0234] The third clock signal provided by the third clock signal terminal CLK3 can control the functional circuit 150. When the first control circuit 160 controls the path between the first clock signal terminal CLK1 and the second node N2, the potential of the third clock signal is a valid potential to control the path between the functional input terminal and the functional output terminal, i.e., does not affect the path between the first clock signal terminal CLK1 and the second node N2.

[0235] The third clock signal provided by the third clock signal terminal CLK3 can also control the functional circuit 150. When the first control circuit 160 controls the disconnection between the first clock signal terminal CLK1 and the second node N2, and the potential of the first clock signal provided by the first clock signal terminal CLK1 is different from the potential of the second node N2, the potential of the third clock signal is an invalid potential to control the blocking of the path between the functional input terminal and the functional output terminal, thereby ensuring that the second node N2 is not affected by the first clock signal provided by the first clock signal terminal CLK1, and maintaining the potential of the second node N2.

[0236] In some examples, the functional circuit 150 includes a first transistor T1, wherein the first transistor T1 includes an oxide transistor. The functional circuit 150 is coupled in series between the second node N2 and the first control circuit 160.

[0237] The control electrode of the first transistor T1 is coupled to the third clock signal terminal CLK3, the first electrode of the first transistor T1 is coupled to the second electrode of the fifth transistor T5, the second electrode of the first transistor T1 is coupled to the second node N2, the first electrode of the fifth transistor T5 is coupled to the first clock signal terminal CLK1, and the control electrode of the fifth transistor T5 is coupled to the first node N1.

[0238] In some examples, the first transistor T1 is an N-type transistor. In a case where the third clock signal provided by the third clock signal terminal CLK3 is a high potential signal, a path is formed between the first electrode of the first transistor T1 (coupled with the first clock signal terminal CLK1 through the fifth transistor T5) and the second electrode of the first transistor T1 (the second node N2), so as to transmit the first clock signal provided by the first clock signal terminal CLK1 to the second node N2. In a case where the third clock signal provided by the third clock signal terminal CLK3 is a low potential signal, the path between the first electrode of the first transistor T1 (coupled with the first clock signal terminal CLK1 through the fifth transistor T5) and the second electrode of the first transistor T1 (the second node N2) is blocked, so as to block the path between the first clock signal terminal CLK1 and the second node N2, so as to maintain the potential of the second node N2.

[0239] As shown in FIG. 1, in some examples, the functional circuit 150 includes a first transistor T1, where the first transistor T1 includes an oxide transistor. The functional circuit 150 is coupled in series between the first clock signal terminal CLK1 and the first control circuit 160. Figure 13 The control electrode of the first transistor T1 is coupled with the third clock signal terminal CLK3, the first electrode of the first transistor T1 is coupled with the first clock signal terminal CLK1, the second electrode of the first transistor T1 is coupled with the first electrode of the fifth transistor T5, the second electrode of the fifth transistor T5 is coupled with the second node N2, and the control electrode of the fifth transistor T5 is coupled with the first node N1.

[0240] In some examples, the first transistor T1 is an N-type transistor. In a case where the third clock signal provided by the third clock signal terminal CLK3 is a high potential signal, a path is formed between the first electrode of the first transistor T1 (coupled with the first clock signal terminal CLK1 through the fifth transistor T5) and the second electrode of the first transistor T1 (the second node N2), so as to transmit the first clock signal provided by the first clock signal terminal CLK1 to the second node N2. In a case where the third clock signal provided by the third clock signal terminal CLK3 is a low potential signal, the path between the first electrode of the first transistor T1 (coupled with the first clock signal terminal CLK1 through the fifth transistor T5) and the second electrode of the first transistor T1 (the second node N2) is blocked, so as to block the path between the first clock signal terminal CLK1 and the second node N2, so as to maintain the potential of the second node N2.

[0241] In some embodiments, as shown in FIG. 1, the shift register includes the first transistor T1 of the functional circuit 150, and the fourth transistor T4 of the second input circuit 130. Wherein, as shown in FIG. 1, the first transistor T1 of the functional circuit 150 is coupled in series between the first clock signal terminal CLK1 and the first control circuit 160.

[0242] Figure 13 In some examples, the functional circuit 150 includes a first transistor T1, where the first transistor T1 includes an oxide transistor. The functional circuit 150 is coupled in series between the first clock signal terminal CLK1 and the first control circuit 160. Figure 14 ​As shown, the fourth transistor T4 is configured to be coupled to the first voltage signal line VGL'.

[0243] like Figure 14 As shown, on the plane where the shift register is located, the first transistor T1 is located on the side of the fourth transistor T4 away from the first voltage signal line VGL'.

[0244] In other embodiments, such as Figure 13 As shown, the shift register includes the fifth transistor T5 of the first control circuit 160, the first transistor T1 of the functional circuit 150, the second transistor T2 of the first input circuit 110, and the fourth transistor T4 of the second input circuit 130.

[0245] like Figure 14 As shown, on the plane where the shift register is located, the first transistor T1 is situated within the region enclosed by the second transistor T2, the fourth transistor T4, and the fifth transistor T5. For example, the first transistor T1 is located at the center of the region enclosed by the second transistor T2, the fourth transistor T4, and the fifth transistor T5.

[0246] like Figure 14 As shown, the first clock signal terminal CLK1 is coupled to the first clock signal line CLK1' through the first trace L1, the third clock signal terminal CLK3 is coupled to the third clock signal line CLK3' through the third trace L3, the fourth clock signal terminal CLK4 is coupled to the fourth clock signal line CLK4' through the fourth trace L4, the first voltage signal terminal VGL is coupled to the first voltage signal line VGL' through the fifth trace L5, and the second voltage signal terminal VGH is coupled to the second voltage signal line VGH' through the sixth trace L6.

[0247] The first voltage signal line VGL', the first clock signal line CLK1', the third clock signal line CLK3', and the fourth clock signal line CLK4' all extend along the second direction Y and are spaced apart along the first direction X. The first voltage signal line VGL', the first clock signal line CLK1', the third clock signal line CLK3', and the fourth clock signal line CLK4' can be located on the same side of the shift register in the first direction X, and are arranged sequentially in a direction away from the shift register.

[0248] The second voltage signal line VGH' can be located on the other side of the shift register in the first direction X and extended along the second direction Y.

[0249] In some embodiments, the structure of the first transistor T1 is as follows: Figure 4B The oxide transistors shown have the same structure, so they will not be described in detail here.

[0250] The first gate pattern 341 and the second gate pattern 342 of the first transistor T1 are located on a side of the third clock signal terminal CLK3 close to the substrate 300. The first gate pattern 341 and the second gate pattern 342 of the first transistor T1 are coupled with the third clock signal terminal CLK3, respectively. For example, a source-drain metal pattern 360 is connected with the first gate pattern 341, the second gate pattern 342 and the third clock signal terminal CLK3, respectively, to realize the coupling of the first gate pattern 341 and the second gate pattern 342 of the first transistor T1 with the third clock signal terminal CLK3.

[0251] The first gate pattern 341 and the second gate pattern 342 of the first transistor T1 can be in direct contact with the third clock signal terminal CLK3 to realize the coupling with the third clock signal terminal CLK3. The first gate pattern 341 and the second gate pattern 342 of the first transistor T1 can also be coupled with the third clock signal terminal CLK3 through a via.

[0252] In some examples, as shown in FIG. 6, one source-drain metal pattern 360 is located on a side of the first gate pattern 341 and the second gate pattern 342 away from the substrate 300. The source-drain metal pattern 360 is coupled with the first gate pattern 341 through a third via H3 and coupled with the second gate pattern 342 through a fourth via H4. The third clock signal terminal CLK3 is coupled with the source-drain metal pattern through a third trace L3, thereby realizing the coupling with the first gate pattern and the second gate pattern. Figure 4B

[0253] In some embodiments, as shown in FIG. 7, the shift register includes the second transistor T2 and the third transistor T3 of the first input circuit 110. As shown in FIG. 7, the third transistor T3 is configured to be coupled with the first clock signal line CLK1’. The first transistor T1 is located on a side of the third transistor T3 away from the first clock signal line CLK1’. Figure 7-10 Figure 15

[0254] In other embodiments, as shown in FIG. 8, the shift register includes the third transistor T3 of the first input circuit 110, the fifth transistor T5 of the first control circuit 160, and the ninth transistor T9 of the second control circuit 170. Figure 7-10

[0255] As shown in FIG. 9, the first transistor T1 is located in an area surrounded by the third transistor T3, the fifth transistor T5 and the ninth transistor T9. For example, the first transistor T1 is located at a central position of the area surrounded by the third transistor T3, the fifth transistor T5 and the ninth transistor T9. Figure 15

[0256] As shown in FIG. 10, the first transistor T1 is located in an area surrounded by the third transistor T3, the fifth transistor T5 and the ninth transistor T9. For example, the first transistor T1 is located at a central position of the area surrounded by the third transistor T3, the fifth transistor T5 and the ninth transistor T9. Figure 15 ​​​​​As shown, the first clock signal terminal CLK1 is coupled to the first clock signal line CLK1' through the first trace L1, the fourth clock signal terminal CLK4 is coupled to the fourth clock signal line CLK4' through the fourth trace L4, the fourth auxiliary clock signal terminal is coupled to the fourth auxiliary clock signal line NCLK4' through the eighth trace L8, the first voltage signal terminal VGL is coupled to the first voltage signal line VGL' through the fifth trace L5, the second clock signal terminal CLK2 is coupled to the second clock signal line CLK2' through the second trace L2, and the second voltage signal terminal VGH is coupled to the second voltage signal line VGH' through the sixth trace L6.

[0257] The first clock signal line CLK1', the fourth clock signal line CLK4', the fourth auxiliary clock signal line NCLK4', and the first voltage signal line VGL' all extend along the second direction Y and are spaced apart along the first direction X. The first voltage signal line VGL', the first clock signal line CLK1', the fourth clock signal line CLK4', and the fourth auxiliary clock signal line NCLK4' can be located on the same side of the shift register in the first direction X, and are arranged sequentially in a direction away from the shift register.

[0258] The second clock signal line CLK2' and the second voltage signal line VGH' both extend along the second direction Y and are spaced apart along the first direction X. The second clock signal line CLK2' and the second voltage signal line VGH' can be located on the other side of the shift register in the first direction X, and are arranged sequentially in a direction away from the shift register.

[0259] like Figure 16 As shown, in some embodiments, the shift register further includes a third output circuit 190 and a fourth output circuit 200.

[0260] The third output circuit 190 is coupled to the first voltage signal terminal VGL, the first node N1, and the second scan signal terminal. The third output circuit 190 is configured to transmit the first voltage signal provided by the first voltage signal terminal VGL to the second scan signal terminal under the control of the potential of the first node N1.

[0261] The fourth output circuit 200 is coupled to the second voltage signal terminal VGH, the first node N1, and the second scan signal terminal. The fourth output circuit 200 is configured to transmit the second voltage signal provided by the second voltage signal terminal VGH to the second scan signal terminal under the control of the potential of the first node N1.

[0262] In the embodiment, the shift register is a double-output shift register. That is, the shift register provides the first gate signal for the N-type transistor in the sub-pixel and provides the second gate signal for the P-type transistor in the sub-pixel. Exemplarily, the first scan signal end provides the first gate signal for the N-type transistor in the sub-pixel; and the second scan signal end provides the second gate signal for the P-type transistor in the sub-pixel.

[0263] In some examples, when the potential of the first node N1 is at a low potential, the third output circuit 190 transmits the first voltage signal provided by the first voltage signal end VGL to the second scan signal end; and when the potential of the first node N1 is at a high potential, the fourth output circuit 200 transmits the second voltage signal provided by the second voltage signal end VGH to the second scan signal end.

[0264] In the embodiment, as shown in Figure 17 The first output signal end S1S1 coupled with the first output circuit 120 can be the fourth clock signal end CLK4. That is, the first output circuit 120 transmits the fourth clock signal provided by the fourth clock signal end CLK4 to the first scan signal end under the control of the potential of the first node N1.

[0265] As shown in Figure 17 In some embodiments, the third output circuit 190 includes a function circuit 150. The first node N1 serves as a function control end. The first output circuit 120 is further configured to, under the control of the potential of the first node N1, block the path between the first voltage signal end VGL and the second scan signal end to maintain the potential of the second scan signal end.

[0266] That is, the function control end includes the first node N1, the function input end includes the first voltage end, and the function output end includes the second scan signal end. The circuit nodes include the first node N1, the second node N2, and the second scan signal end.

[0267] In some examples, the first output circuit 120 is configured to, when the potential of the first node N1 is at a valid potential (for example, a high potential), control the path between the first voltage signal end VGL and the second scan signal end to realize the transmission of the first voltage signal provided by the first voltage signal end VGL to the second scan signal end. The first output circuit 120 is further configured to, when the potential of the first node N1 is at an invalid potential (for example, a high potential), block the path between the first voltage signal end VGL and the second scan signal end to maintain the potential of the second scan signal end.

[0268] As shown in Figure 17 In some examples, the third output circuit 190 includes a sixth transistor T6, and the sixth transistor T6 includes an oxide transistor. The fourth output circuit 200 includes a seventh transistor T7.

[0269] The control electrode of the sixth transistor T6 is coupled to the first node N1, the first electrode of the sixth transistor T6 is coupled to the first voltage signal terminal VGL, and the second electrode of the sixth transistor T6 is coupled to the second scan signal terminal.

[0270] The control electrode of the seventh transistor T7 is coupled to the first node N1, the first electrode of the seventh transistor T7 is coupled to the second voltage signal terminal VGH, and the second electrode of the seventh transistor T7 is coupled to the second scan signal terminal.

[0271] In some examples, the sixth transistor T6 is an N-type transistor, and the seventh transistor T7 is a P-type transistor. When the potential of the first node N1 is low, a path is formed between the first terminal (second voltage signal terminal VGH) and the second terminal (second scan signal terminal) of the seventh transistor T7, and the path between the first terminal (first voltage signal terminal VGL) and the second terminal (second scan signal terminal) of the sixth transistor T6 is interrupted. This allows the second voltage signal provided by the second voltage signal terminal VGH to be transmitted to the second scan signal terminal while preventing the first voltage signal provided by the first voltage signal terminal VGL from affecting the potential of the second scan signal terminal. When the potential of the first node N1 is high, a path is formed between the first terminal (first voltage signal terminal VGL) and the second terminal (second scan signal terminal) of the sixth transistor T6, allowing the first voltage signal provided by the first voltage signal terminal VGL to be transmitted to the second scan signal terminal.

[0272] like Figure 17 As shown, in some embodiments, the shift register includes a first control circuit 160, a third output circuit 190, and a fourth output circuit 200. The third output signal terminal S3 includes a first clock signal terminal CLK1, the fifth control signal terminal K5 includes a second scan signal terminal, and the first control circuit 160 is multiplexed into a functional circuit 150.

[0273] That is, the function control terminal includes a second scan signal terminal, the function input terminal includes a first clock signal terminal CLK1, and the function output terminal includes a second node N2.

[0274] The first control circuit 160 is configured to, when the potential of the second scan signal provided by the second scan signal terminal is an effective potential, control the formation of a path between the first clock signal terminal CLK1 and the second node N2, thereby transmitting the first clock signal provided by the first clock signal terminal CLK1 to the second node N2. The first control circuit 160 is also configured to, when the potential of the second scan signal provided by the second scan signal terminal is an invalid potential, disconnect the path between the first clock signal terminal CLK1 and the second node N2 to maintain the potential of the second node N2.

[0275] As shown in FIG. 1, in some embodiments, the fifth transistor T5 in the first control circuit 160 comprises an oxide transistor. Figure 17

[0276] The control electrode of the fifth transistor T5 is coupled with the second scan signal terminal, the first electrode of the fifth transistor T5 is coupled with the first clock signal terminal CLK1, and the second electrode of the fifth transistor T5 is coupled with the second node N2.

[0277] In some examples, the fifth transistor T5 is an N-type transistor. In the case that the second scan signal provided by the second scan signal terminal is at a high potential, a path is formed between the first electrode (the first clock signal terminal CLK1) of the fifth transistor T5 and the second electrode (the second node N2) of the fifth transistor T5, so as to realize transmission of the first clock signal provided by the first clock signal terminal CLK1 to the second node N2. In the case that the second scan signal provided by the second scan signal terminal is at a low potential, the path between the first electrode (the first clock signal terminal CLK1) of the fifth transistor T5 and the second electrode (the second node N2) of the fifth transistor T5 is blocked, so as to realize maintenance of the potential of the second node N2.

[0278] The above-mentioned shift register can further comprise a noise reduction circuit 170, which has multiple setting modes, which will be described in detail through multiple embodiments.

[0279] As shown in FIG. 1, in some embodiments, the noise reduction circuit 170 is respectively coupled with the second voltage signal terminal VGH, the sixth control signal terminal K6, the second node N2 and the first node N1. The noise reduction circuit 170 is configured to form a path between the second voltage signal terminal VGH and the first node N1 under the control of the potential of the second node N2 and the sixth control signal provided by the sixth control signal terminal K6. Figure 3 The sixth control signal terminal K6 can be one of the multiple clock signal terminals, for example, the fourth clock signal terminal CLK4. The sixth control signal terminal K6 can also be one of the multiple auxiliary clock signal terminals, for example, the fourth auxiliary clock signal terminal NCLK4. The sixth control signal terminal K6 can also be one of the multiple circuit nodes, for example, the first node N1, which is not limited here.

[0280] As shown in FIG. 1, in some examples, the sixth control signal terminal K6 comprises the fourth clock signal terminal CLK4. The noise reduction circuit 170 is configured to control the formation of a path between the second voltage signal terminal VGH and the first node N1 under the control of the potential of the second node N2 and the fourth clock signal provided by the fourth clock signal terminal CLK4, so as to realize transmission of the second voltage signal provided by the second voltage signal terminal VGH to the first node N1.

[0281] Figure 18 As shown in FIG. 1, in some examples, the sixth control signal terminal K6 comprises the fourth clock signal terminal CLK4. The noise reduction circuit 170 is configured to control the formation of a path between the second voltage signal terminal VGH and the first node N1 under the control of the potential of the second node N2 and the fourth clock signal provided by the fourth clock signal terminal CLK4, so as to realize transmission of the second voltage signal provided by the second voltage signal terminal VGH to the first node N1.​​

[0282] As shown in FIG. 8, in some embodiments, the noise reduction circuit 170 includes an eighth transistor T8 and a ninth transistor T9. The control electrode of the eighth transistor T8 is coupled with the second node N2, the first electrode of the eighth transistor T8 is coupled with the second voltage signal terminal VGH, the second electrode of the eighth transistor T8 is coupled with the first electrode of the ninth transistor T9, the control electrode of the ninth transistor T9 is coupled with the sixth control signal terminal K6, and the second electrode of the ninth transistor T9 is coupled with the first node N1. Figure 18 As shown in FIG. 8, in some embodiments, the noise reduction circuit 170 includes an eighth transistor T8 and a ninth transistor T9. The control electrode of the eighth transistor T8 is coupled with the second node N2, the first electrode of the eighth transistor T8 is coupled with the second voltage signal terminal VGH, the second electrode of the eighth transistor T8 is coupled with the first electrode of the ninth transistor T9, the control electrode of the ninth transistor T9 is coupled with the sixth control signal terminal K6, and the second electrode of the ninth transistor T9 is coupled with the first node N1.

[0283] Figure 18 As shown in FIG. 8, in some embodiments, the noise reduction circuit 170 includes an eighth transistor T8 and a ninth transistor T9. The control electrode of the eighth transistor T8 is coupled with the second node N2, the first electrode of the eighth transistor T8 is coupled with the second voltage signal terminal VGH, the second electrode of the eighth transistor T8 is coupled with the first electrode of the ninth transistor T9, the control electrode of the ninth transistor T9 is coupled with the sixth control signal terminal K6, and the second electrode of the ninth transistor T9 is coupled with the first node N1.

[0284] Taking the eighth transistor T8 and the ninth transistor T9 as P-type transistors as an example: in the case that the potential of the second node N2 is at a low potential and the potential of the fourth clock signal provided by the fourth clock signal terminal CLK4 is at a low potential, a path is formed between the first electrode (the second voltage signal terminal VGH) of the eighth transistor T8 and the second electrode of the eighth transistor T8, and a path is formed between the first electrode of the ninth transistor T9 and the second electrode (the first node N1) of the ninth transistor T9, that is, a path is formed between the second voltage signal terminal VGH and the first node N1, thereby realizing transmission of the second voltage signal provided by the second voltage signal terminal VGH to the first node N1.

[0285] As shown in FIG. 8, in some embodiments, the noise reduction circuit 170 includes an eighth transistor T8 and a ninth transistor T9. The control electrode of the eighth transistor T8 is coupled with the second node N2, the first electrode of the eighth transistor T8 is coupled with the second voltage signal terminal VGH, the second electrode of the eighth transistor T8 is coupled with the first electrode of the ninth transistor T9, the control electrode of the ninth transistor T9 is coupled with the sixth control signal terminal K6, and the second electrode of the ninth transistor T9 is coupled with the first node N1. Figure 18 Figure 19 As shown in FIG. 8, in some embodiments, the noise reduction circuit 170 includes an eighth transistor T8 and a ninth transistor T9. The control electrode of the eighth transistor T8 is coupled with the second node N2, the first electrode of the eighth transistor T8 is coupled with the second voltage signal terminal VGH, the second electrode of the eighth transistor T8 is coupled with the first electrode of the ninth transistor T9, the control electrode of the ninth transistor T9 is coupled with the sixth control signal terminal K6, and the second electrode of the ninth transistor T9 is coupled with the first node N1.

[0286] As shown in FIG. 8, in some embodiments, the noise reduction circuit 170 includes an eighth transistor T8 and a ninth transistor T9. The control electrode of the eighth transistor T8 is coupled with the second node N2, the first electrode of the eighth transistor T8 is coupled with the second voltage signal terminal VGH, the second electrode of the eighth transistor T8 is coupled with the first electrode of the ninth transistor T9, the control electrode of the ninth transistor T9 is coupled with the sixth control signal terminal K6, and the second electrode of the ninth transistor T9 is coupled with the first node N1. Figure 19 As shown in FIG. 8, in some embodiments, the noise reduction circuit 170 includes an eighth transistor T8 and a ninth transistor T9. The control electrode of the eighth transistor T8 is coupled with the second node N2, the first electrode of the eighth transistor T8 is coupled with the second voltage signal terminal VGH, the second electrode of the eighth transistor T8 is coupled with the first electrode of the ninth transistor T9, the control electrode of the ninth transistor T9 is coupled with the sixth control signal terminal K6, and the second electrode of the ninth transistor T9 is coupled with the first node N1.

[0287] As shown in FIG. 8, in some embodiments, the noise reduction circuit 170 includes an eighth transistor T8 and a ninth transistor T9. The control electrode of the eighth transistor T8 is coupled with the second node N2, the first electrode of the eighth transistor T8 is coupled with the second voltage signal terminal VGH, the second electrode of the eighth transistor T8 is coupled with the first electrode of the ninth transistor T9, the control electrode of the ninth transistor T9 is coupled with the sixth control signal terminal K6, and the second electrode of the ninth transistor T9 is coupled with the first node N1. Figure 18 As shown in FIG. 8, in some embodiments, the noise reduction circuit 170 includes an eighth transistor T8 and a ninth transistor T9. The control electrode of the eighth transistor T8 is coupled with the second node N2, the first electrode of the eighth transistor T8 is coupled with the second voltage signal terminal VGH, the second electrode of the eighth transistor T8 is coupled with the first electrode of the ninth transistor T9, the control electrode of the ninth transistor T9 is coupled with the sixth control signal terminal K6, and the second electrode of the ninth transistor T9 is coupled with the first node N1.​​

[0288] As shown in FIG. 7, in the plane where the shift register is located, the first transistor T1 is located on the side of the fourth transistor T4 and the fifth transistor T5 away from the first voltage signal line VGL'. Meanwhile, the first transistor T1 is located on the side of the second transistor T2 and the eighth transistor T8 close to the first voltage signal line VGL'. Figure 19

[0289] As shown in FIG. 7, the first clock signal end CLK1 is coupled with the first clock signal line CLK1' through the first wire L1, the fourth clock signal end CLK4 is coupled with the fourth clock signal line CLK4' through the fourth wire L4, the first voltage signal end VGL is coupled with the first voltage signal line VGL' through the fifth wire L5, and the second voltage signal end VGH is coupled with the second voltage signal line VGH' through the sixth wire L6. Figure 19

[0290] The first voltage signal line VGL', the fourth clock signal line CLK4' and the first clock signal line CLK1' all extend along the second direction Y and are arranged at intervals along the first direction X. The first voltage signal line VGL', the fourth clock signal line CLK4' and the first clock signal line CLK1' can be located on the same side of the shift register in the first direction X and are arranged in turn in the direction away from the shift register.

[0291] The second voltage signal line VGH' extends along the second direction Y, wherein the second voltage signal line VGH' can be located on the side of the shift register away from the substrate. That is, the orthogonal projection of the second voltage signal line VGH' on the substrate overlaps with the orthogonal projection of the shift register on the substrate.

[0292] In some embodiments, in the plane where the shift register is located, the first transistor T1 is located between the first voltage signal end VGL and the second voltage signal end VGH. For example, in the first direction X, the first transistor T1 is located between the connection position of the first voltage signal line VGL' and the fourth transistor T4 and the connection position of the second voltage signal line VGH' and the fifth transistor T5. For another example, the orthogonal projection of the first transistor T1 on the substrate is located between the orthogonal projection of the connection position of the first voltage signal line VGL' and the fourth transistor T4 on the substrate and the orthogonal projection of the connection position of the second voltage signal line VGH' and the fifth transistor T5 on the substrate.

[0293] In some examples, in the first direction X, the first transistor T1 is located between the first voltage signal line VGL' and the second voltage signal line VGH'.

[0294] In some embodiments, as shown in FIG. 7, the first clock signal end CLK1 is coupled with the first clock signal line CLK1' through the first wire L1, the fourth clock signal end CLK4 is coupled with the fourth clock signal line CLK4' through the fourth wire L4, the first voltage signal end VGL is coupled with the first voltage signal line VGL' through the fifth wire L5, and the second voltage signal end VGH is coupled with the second voltage signal line VGH' through the sixth wire L6. Figure 19 ​​As shown, there can be multiple first voltage signal lines VGL', and similarly, there can also be multiple second voltage signal lines VGH'. Some of the first voltage signal lines VGL' can be located on the side of the shift register away from the substrate; some of the second voltage signal lines VGH' can also be located on the side of the shift register away from the substrate.

[0295] In some embodiments, Figure 19 The structure of the first transistor T1 in the image can be similar to that of... Figure 4B The oxide transistors shown have the same structure, so they will not be described in detail here.

[0296] like Figure 20 As shown, in some embodiments, the sixth control signal terminal K6 includes the fourth clock signal terminal CLK4. A functional circuit 150 is connected in series between the second voltage signal terminal VGH and the first node N1. The functional control terminal includes the first node N1, the functional input terminal includes the second voltage signal terminal VGH, and the functional output terminal includes the first node N1.

[0297] The functional circuit 150 is configured to form a path between the second voltage signal terminal VGH and the first node N1 when the potential of the first node N1 is an effective potential, thereby transmitting the second voltage signal provided by the second voltage signal terminal VGH to the first node N1.

[0298] The functional circuit 150 is also configured to disconnect the path between the second voltage signal terminal VGH and the first node N1 when the potential of the first node N1 is an invalid potential, so as to maintain the potential of the first node N1.

[0299] Specifically, the functional circuit 150 can be connected in series between the eighth transistor T8 and the second voltage signal terminal VGH; it can also be connected in series between the eighth transistor T8 and the ninth transistor T9; or it can be connected in series between the ninth transistor T9 and the first node N1. In any of these three locations, the functional circuit 150 can, while isolating the functional input terminal and the functional output terminal, disconnect the path between the second voltage signal terminal VGH and the first node N1, thereby maintaining the potential of the first node N1.

[0300] In some embodiments, the functional circuit 150 is connected in series between the eighth transistor T8 and the second voltage signal terminal VGH. The functional circuit 150 includes a first transistor T1, which is an oxide transistor.

[0301] The control electrode of the first transistor T1 is coupled to the first node N1, the first electrode of the first transistor T1 is coupled to the second voltage signal terminal VGH, and the second electrode of the first transistor T1 is coupled to the first electrode of the eighth transistor T8.

[0302] In some examples, the first transistor T1 is an N-type transistor, and the eighth transistor T8 and the ninth transistor T9 are P-type transistors. When the potential of the first node N1 is high, the potential of the second node N2 is low, and the fourth clock signal provided by the fourth clock signal terminal CLK4 is low, the first terminal of the first transistor T1 (the second voltage signal terminal VGH) forms a path with the second terminal of the first transistor T1, the first terminal of the eighth transistor T8, the second terminal of the eighth transistor T8, the first terminal of the ninth transistor T9, and the second terminal of the ninth transistor T9 (the first node N1), thereby transmitting the second voltage signal provided by the second voltage signal terminal VGH to the first node N1.

[0303] When the potential of the first node N1 is low, the path between the first terminal and the second terminal of the first transistor T1 is cut off, thereby cutting off the path between the second voltage signal and the first node N1 to maintain the potential of the first node N1.

[0304] like Figure 20 As shown, in some embodiments, functional circuit 150 is connected in series between the eighth transistor T8 and the ninth transistor T9. Functional circuit 150 includes a first transistor T1, which is an oxide transistor.

[0305] The control electrode of the first transistor T1 is coupled to the first node N1, the first electrode of the first transistor T1 is coupled to the second electrode of the eighth transistor T8, and the second electrode of the first transistor T1 is coupled to the first electrode of the ninth transistor T9.

[0306] In some examples, the first transistor T1 is an N-type transistor, and the eighth transistor T8 and the ninth transistor T9 are P-type transistors. When the potential of the first node N1 is high, the potential of the second node N2 is low, and the fourth clock signal provided by the fourth clock signal terminal CLK4 is low, the first terminal of the eighth transistor T8 (the second voltage signal terminal VGH) forms a path with the second terminal of the eighth transistor T8, the first terminal of the first transistor T1, the second terminal of the first transistor T1, the first terminal of the ninth transistor T9, and the second terminal of the ninth transistor T9 (the first node N1), thereby transmitting the second voltage signal provided by the second voltage signal terminal VGH to the first node N1.

[0307] When the potential of the first node N1 is low, the path between the first terminal and the second terminal of the first transistor T1 is cut off, thereby cutting off the path between the second voltage signal and the first node N1 to maintain the potential of the first node N1.

[0308] In some embodiments, the functional circuit 150 is coupled in series between the ninth transistor T9 and the first node N1. The functional circuit 150 includes a first transistor T1, and the first transistor T1 includes an oxide transistor.

[0309] The control electrode of the first transistor T1 is coupled to the first node N1, the first electrode of the first transistor T1 is coupled to the second electrode of the ninth transistor T9, and the second electrode in the first transistor T1 is coupled to the first node N1.

[0310] In some examples, the first transistor T1 is an N-type transistor, and the eighth transistor T8 and the ninth transistor T9 are P-type transistors. When the potential of the first node N1 is at a high potential, the potential of the second node N2 is at a low potential, and the fourth clock signal provided by the fourth clock signal terminal CLK4 is at a low potential, the first electrode (the second voltage signal terminal VGH) of the eighth transistor T8 forms a path between the second electrode of the eighth transistor T8, the first electrode of the ninth transistor T9, the second electrode of the ninth transistor T9, the first electrode of the first transistor T1, and the second electrode (the first node N1) of the first transistor T1 in sequence, so as to realize transmission of the second voltage signal provided by the second voltage signal terminal VGH to the first node N1.

[0311] When the potential of the first node N1 is at a low potential, the path between the first electrode of the first transistor T1 and the second electrode of the first transistor T1 is blocked, so as to block the path between the second voltage signal and the first node N1, and maintain the potential of the first node N1.

[0312] As shown in FIG. 1, in some embodiments, the functional circuit 150 includes a ninth transistor T9. The ninth transistor T9 includes an oxide transistor. The control electrode of the ninth transistor T9 is coupled to the fourth auxiliary clock signal terminal NCLK4. Figure 21

[0313] The noise reduction circuit 170 includes a functional circuit 150. The functional circuit 150 is coupled in series between the second voltage signal terminal VGH and the first node N1. The functional control terminal includes the fourth auxiliary clock signal terminal NCLK4, the input terminal of the functional circuit 150 includes the second voltage signal terminal VGH, and the output terminal of the functional circuit 150 includes the first node N1.

[0314] The functional circuit 150 is configured to block the path between the first node N1 and the second voltage signal terminal VGH under the control of the fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4, so as to maintain the potential of the first node N1.

[0315] As shown in FIG. 1, in some embodiments, the functional circuit 150 includes a ninth transistor T9. The ninth transistor T9 includes an oxide transistor. The control electrode of the ninth transistor T9 is coupled to the fourth auxiliary clock signal terminal NCLK4. Figure 21 The ninth transistor T9 is coupled in series between the eighth transistor T8 and the first node N1. The control electrode of the ninth transistor T9 is coupled to the fourth auxiliary clock signal terminal NCLK4.​

[0316] In some examples, the eighth transistor T8 is a P-type transistor, and the ninth transistor T9 is an N-type transistor. When the potential of the fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is high and the potential of the second node N2 is low, a path is formed between the second voltage signal terminal VGH and the first node N1, so that the second voltage signal provided by the second voltage signal terminal VGH is transmitted to the first node N1 sequentially through the first terminal of the eighth transistor T8 (second voltage signal terminal VGH), the second terminal of the eighth transistor T8, the first terminal of the ninth transistor T9, and the second terminal of the ninth transistor T9 (first node N1).

[0317] When the potential of the fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is low, the path between the first terminal and the second terminal of the ninth transistor T9 is cut off, thereby cutting off the path between the second voltage signal terminal VGH and the first node N1, so as to maintain the potential of the first node N1.

[0318] The aforementioned shift register also includes a first voltage regulator circuit 180, which has various configuration methods, and will be described in detail below through several embodiments.

[0319] like Figure 3-13 As shown, in some embodiments, the circuit node further includes a third node N3. The first voltage regulator circuit 180 is coupled to the first node N1, the third node N3 and the eighth control signal terminal K8, respectively. The first output circuit 120 is coupled to the third node N3 and is coupled to the first node N1 through the first voltage regulator circuit 180.

[0320] The eighth control signal terminal K8 mentioned above can be one of multiple voltage signal terminals, such as the first voltage signal terminal VGL, or the second voltage signal terminal VGH.

[0321] The first voltage regulator circuit 180 is configured to connect the first node N1 and the third node N3 under the control of the potential of the third node N3 and the eighth control signal provided by the eighth control signal terminal K8.

[0322] like Figure 6-13 As shown, in some embodiments, the first voltage regulator circuit 180 includes a tenth transistor T10.

[0323] The control terminal of the tenth transistor T10 is coupled to the eighth control signal terminal K8, the first terminal of the tenth transistor T10 is coupled to the first node N1, and the second terminal of the tenth transistor T10 is coupled to the third node N3.

[0324] In some examples, the tenth transistor T10 is a P-type transistor, and the eighth control signal end K8 includes a first voltage signal end VGL. In a case where a potential of the eighth control signal provided by the eighth control signal end K8 is lower than a potential of the third node N3, a path between the first pole (the first node N1) of the tenth transistor T10 and the second pole (the third node N3) of the tenth transistor T10 is formed, and the potential of the first node N1 is transmitted to the third node N3.

[0325] As shown in FIG. 8, in some embodiments, the eighth control signal end K8 includes a second voltage signal end VGH. Figure 22

[0326] The first voltage stabilizing circuit 180 is multiplexed as a functional circuit 150. The functional control end includes the second voltage signal end VGH, the functional input end includes the first node N1, and the functional output end includes the third node N3.

[0327] The first voltage stabilizing circuit 180 is further configured to, under control of the potential of the third node N3 and the potential of the second voltage signal provided by the second voltage signal end VGH, cut off the path between the first node N1 and the third node N3, so as to maintain the potential of the third node N3.

[0328] As shown in FIG. 8, in some embodiments, the tenth transistor T10 is an oxide transistor. The control pole of the tenth transistor T10 is coupled with the second voltage signal end VGH. Figure 22

[0329] In some examples, the tenth transistor T10 is an N-type transistor. In a case where the potential of the second voltage signal provided by the second voltage signal end VGH is lower than the potential of the third node N3, a path between the first pole (the first node N1) of the tenth transistor T10 and the second pole (the third node N3) of the tenth transistor T10 is formed, and the potential of the first node N1 is transmitted to the third node N3. In a case where the potential of the second voltage signal provided by the second voltage signal end VGH is higher than the potential of the third node N3, the path between the first pole (the first node N1) of the tenth transistor T10 and the second pole (the third node N3) of the tenth transistor T10 is cut off, so as to maintain the potential of the third node N3.

[0330] The shift register described above further includes a second control circuit 210, which has multiple setting modes, which will be described in detail through multiple embodiments below.

[0331] As shown in FIG. 8, in some embodiments, the eighth control signal end K8 includes a second voltage signal end VGH. Figure 23 ​​As shown, in some embodiments, the circuit node further includes a fourth node N4. The second control circuit 210 is coupled to the second node N2, the fourth node N4, the fourth clock signal terminal CLK4, and the ninth control signal terminal K9, respectively. The second output circuit 140 is coupled to the fourth node N4 and is coupled to the second node N2 through the second control circuit 210.

[0332] The ninth control signal terminal K9 may include one of multiple clock signal terminals, such as the first clock signal terminal CLK1, or the fourth clock signal terminal CLK4. The ninth control signal terminal K9 may also include one of multiple auxiliary clock signal terminals, such as the fourth auxiliary clock signal terminal NCLK4.

[0333] The second control circuit 210 is configured to transmit the fourth clock signal provided by the fourth clock signal terminal CLK4 to the fourth node N4 under the control of the potential of the second node N2 and the ninth control signal provided by the ninth control signal terminal K9.

[0334] The second control circuit 210 can control the operating state of the second output circuit 140 by controlling the potential of the fourth node N4. For example, the second output circuit 140 is configured to transmit the second output signal provided by the second output signal terminal S2 to the first scan signal terminal when the potential of the fourth node N4 is an effective potential.

[0335] like Figure 24 As shown, in some examples, the second control circuit 210 includes an eleventh transistor T11, a twelfth transistor T12, and a first capacitor. The control terminal of the eleventh transistor T11 is coupled to the second node N2, the first terminal of the eleventh transistor T11 is coupled to the fourth clock signal terminal CLK4, the second terminal of the eleventh transistor T11 is coupled to the first terminal of the twelfth transistor T12, the control terminal of the twelfth transistor T12 is coupled to the ninth control signal terminal K9, the second terminal of the twelfth transistor T12 is coupled to the fourth node N4, the first plate of the first capacitor is coupled to the second node N2, and the second plate of the first capacitor is coupled to the first terminal of the twelfth transistor T12.

[0336] like Figure 24As shown, in some examples, the ninth control signal terminal K9 includes the fourth clock signal terminal CLK4, and the eleventh transistor T11 and the twelfth transistor T12 include P-type transistors. When the potential of the second node N2 is low and the fourth clock signal provided by the fourth clock signal terminal CLK4 is low, a path is formed sequentially through the first terminal of the eleventh transistor T11 (fourth clock signal terminal CLK4), the second terminal of the eleventh transistor T11, the first terminal of the twelfth transistor T12, and the second terminal of the twelfth transistor T12 (fourth node N4), thereby transmitting the fourth clock signal provided by the fourth clock signal terminal CLK4 to the fourth node N4.

[0337] Among them, the first capacitor maintains the potential of the second node N2 stable when the potential of the first terminal of the twelfth transistor T12 is stable.

[0338] like Figure 25 As shown, in some embodiments, the ninth control signal terminal K9 includes the fourth auxiliary clock signal terminal NCLK4.

[0339] The second control circuit 210 includes a functional circuit 150. The functional control terminal includes a fourth auxiliary clock signal terminal NCLK4, the functional input terminal includes a fourth clock signal terminal CLK4, and the functional output terminal includes a fourth node N4.

[0340] The functional circuit 150 is configured to form a path between the fourth clock signal terminal CLK4 and the fourth node N4 when the potential of the fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is an effective potential, thereby realizing the transmission of the fourth clock signal provided by the fourth clock signal terminal CLK4 to the fourth node N4.

[0341] The functional circuit 150 is also configured to disconnect the path between the second clock signal terminal CLK2 and the fourth node N4 when the potential of the fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is an invalid potential, so as to maintain the potential of the fourth node N4.

[0342] In some embodiments, the functional circuit 150 includes a twelfth transistor T12, which is an oxide transistor. The control electrode of the twelfth transistor T12 is coupled to a fourth auxiliary clock signal terminal NCLK4.

[0343] In some examples, the eleventh transistor T11 is a P-type transistor, and the twelfth transistor T12 is an N-type transistor. When the potential of the fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is at a high potential and the potential of the first node N1 is at a low potential, a path is formed through the first electrode (the fourth clock signal terminal CLK4) of the eleventh transistor T11, the second electrode of the eleventh transistor T11, the first electrode of the twelfth transistor T12, and the second electrode (the fourth node N4) of the twelfth transistor T12 in sequence, so as to realize transmission of the fourth clock signal provided by the fourth clock signal terminal CLK4 to the fourth node N4. When the potential of the fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is at a low potential, the path between the first electrode of the twelfth transistor T12 and the second electrode of the twelfth transistor T12 is blocked, so as to block the path between the second clock signal terminal CLK2 and the fourth node N4, so as to maintain the potential of the fourth node N4.

[0344] As shown in FIG. 2, in some embodiments, the shift register further includes a second voltage stabilizing circuit 220 on the basis of the second control circuit 210. The circuit nodes further include a fifth node N5. Figure 26

[0345] The second voltage stabilizing circuit 220 is coupled with the tenth control signal terminal K10, the second node N2, and the fifth node N5. The second control circuit 210 is coupled with the fifth node N5 and coupled with the second node N2 through the second voltage stabilizing circuit 220. The second output circuit 140 is coupled with the second node N2 through the second control circuit 210 and the second voltage stabilizing circuit 220.

[0346] For example, the tenth control signal terminal K10 can include one of the plurality of voltage signal terminals, such as the first voltage signal terminal VGL, or the second voltage signal terminal VGH.

[0347] The second voltage stabilizing circuit 220 is configured to form a path between the second node N2 and the fifth node N5 when the potential of the fifth node N5 and the potential of the ninth control signal provided by the tenth control signal terminal K10 are effective potentials.

[0348] In some examples, the tenth control signal terminal K10 includes the first voltage signal terminal VGL. The second voltage stabilizing circuit 220 is configured to form a path between the second node N2 and the fifth node N5 under the control of the potential of the fifth node N5 and the potential of the first voltage terminal signal.

[0349] ​In some examples, the second voltage stabilizing circuit 220 includes a thirteenth transistor T13. A control electrode of the thirteenth transistor T13 is coupled to the tenth control signal terminal K10, a first electrode of the thirteenth transistor T13 is coupled to the second node N2, and a second electrode of the thirteenth transistor T13 is coupled to the fifth node N5.

[0350] As shown in FIG. 13, in some examples, the tenth control signal terminal K10 includes a first voltage signal terminal VGL, and the thirteenth transistor T13 is a P-type transistor. Figure 27 In a case where a first voltage signal provided by the first voltage signal terminal VGL is lower than a potential of the fifth node N5, a path between the first electrode (the second node N2) of the thirteenth transistor T13 and the second electrode (the fifth node N5) of the thirteenth transistor T13 is formed, and the potential of the second node N2 is transmitted to the fifth node N5.

[0351] As shown in FIG. 14, in some examples, the tenth control signal terminal K10 includes a second voltage signal terminal VGH. Figure 28

[0352] The second voltage stabilizing circuit 220 is multiplexed as a functional circuit 150. The functional control terminal includes the second voltage signal terminal VGH, the functional input terminal includes the second node N2, and the functional output terminal includes the fifth node N5.

[0353] The second voltage stabilizing circuit 220 is configured to form a path between the second node N2 and the fifth node N5 under the control of the potential of the fifth node N5 and the second voltage signal provided by the second voltage signal terminal VGH, and transmit the potential of the second node N2 to the fifth node N5.

[0354] The second voltage stabilizing circuit 220 is further configured to block the path between the second node N2 and the fifth node N5 under the control of the potential of the fifth node N5 and the second voltage signal provided by the second voltage signal terminal VGH, so as to maintain the potential of the fifth node N5.

[0355] As shown in FIG. 15, in some examples, the thirteenth transistor T13 is an N-type transistor. Figure 28 In a case where the potential of the fifth node N5 is lower than the potential of the second voltage signal provided by the second voltage signal terminal VGH, a path between the first electrode (the second node N2) of the thirteenth transistor T13 and the second electrode (the fifth node N5) of the thirteenth transistor T13 is formed, and the potential of the second node N2 is transmitted to the fifth node N5. In a case where the potential of the fifth node N5 is higher than the potential of the second voltage signal provided by the second voltage signal terminal VGH, the path between the first electrode (the second node N2) of the thirteenth transistor T13 and the second electrode (the fifth node N5) of the thirteenth transistor T13 is blocked, so as to maintain the potential of the fifth node N5.

[0356] ​like Figure 29 As shown, in some embodiments, a combined structure of a first voltage regulator circuit 180 and a first input circuit 110 in a shift register is provided. The circuit nodes include a sixth node N6 and a seventh node N7.

[0357] The first control signal terminal K1 includes a first clock signal terminal CLK1 and an eleventh control signal terminal K11. The first input circuit 110 is coupled to the input signal terminal, the first clock signal terminal CLK1, the first node N1, the sixth node N6 and the eleventh control signal terminal K11.

[0358] The eleventh control signal terminal K11 may include one of multiple clock signal terminals, such as the first clock signal terminal CLK1. The eleventh control signal terminal K11 may also include one of multiple auxiliary clock signal terminals, such as the first auxiliary clock signal terminal NCLK1.

[0359] The first input circuit 110 is configured to transmit the input signal provided by the input signal terminal to the first node N1 under the control of the first clock signal provided by the first clock signal terminal CLK1. The first input circuit 110 is also configured to transmit the input signal provided by the input signal terminal to the sixth node N6 under the control of the eleventh control signal provided by the eleventh control signal terminal K11.

[0360] The first voltage regulator circuit 180 is coupled to the first node N1, the sixth node N6, the third node N3, the seventh node N7, the first voltage signal terminal VGL, and the twelfth control signal terminal K12, respectively.

[0361] The twelfth control signal terminal K12 may include one of multiple voltage signal terminals, such as the first voltage signal terminal VGL, or the second voltage signal terminal VGH.

[0362] The first voltage regulator circuit 180 is configured to form a path between the first node N1 and the third node N3 under the control of the potential of the third node N3 and the first voltage signal provided by the first voltage signal terminal VGL. The first voltage regulator circuit 180 is also configured to form a path between the sixth node N6 and the seventh node N7 when the potential of the seventh node N7 and the potential of the twelfth control signal provided by the twelfth control signal terminal K12 are valid potentials.

[0363] In this embodiment, the first output circuit 120 is coupled to the third node N3 and to the first node N1 through the first voltage regulator circuit 180. The first output circuit 120 is also coupled to the seventh node N7 and to the sixth node N6 through the seventh node N7 and the first voltage regulator circuit 180.

[0364] like Figure 30As shown in the figure, in some embodiments, the first input circuit 110 includes a second transistor T2 and a third transistor T3. The first voltage stabilizing circuit 180 includes a tenth transistor T10 and a fourteenth transistor T14.

[0365] The control electrode of the second transistor T2 is coupled with the first clock signal end CLK1, the first electrode of the second transistor T2 is coupled with the input signal end, the second electrode of the second transistor T2 is coupled with the first node N1, the control electrode of the third transistor T3 is coupled with the eleventh control signal end K11, the first electrode of the third transistor T3 is coupled with the input signal end, and the second electrode of the third transistor T3 is coupled with the sixth node N6.

[0366] The control electrode of the tenth transistor T10 is coupled with the first voltage signal end VGL, the first electrode of the tenth transistor T10 is coupled with the first node N1, the second electrode of the tenth transistor T10 is coupled with the third node N3, the control electrode of the fourteenth transistor T14 is coupled with the twelfth control signal end K12, the first electrode of the fourteenth transistor T14 is coupled with the sixth node N6, and the second electrode of the fourteenth transistor T14 is coupled with the seventh node N7.

[0367] As shown in the figure, in some examples, the eleventh control signal end K11 includes the first clock signal end CLK1, the twelfth control signal end K12 includes the first voltage signal end VGL, and the second transistor T2 and the third transistor T3 are both P-type transistors. Figure 30 In the case that the first clock signal provided by the first clock signal end CLK1 is at a low potential and the first voltage signal provided by the first voltage signal end VGL is at a low potential, a path is formed between the first electrode (the input signal end) of the second transistor T2, the second electrode of the second transistor T2, the first electrode of the tenth transistor T10, and the second electrode (the third node N3) of the tenth transistor T10 in sequence, so as to realize transmission of the input signal provided by the input signal end to the third node N3.

[0368] In the case that the first clock signal provided by the first clock signal end CLK1 is at a low potential and the first voltage signal provided by the first voltage signal end VGL is at a low potential, a path is also formed between the first electrode (the input signal end) of the third transistor T3, the second electrode of the third transistor T3, the first electrode of the fourteenth transistor T14, and the second electrode (the seventh node N7) of the fourteenth transistor T14 in sequence, so as to realize transmission of the input signal provided by the input signal end to the seventh node N7.

[0369] As shown in the figure, in some embodiments, the eleventh control signal end K11 includes the first auxiliary clock signal end NCLK1. Figure 31

[0370] ​The first input circuit 110 includes a function circuit 150. The function control terminal includes a first auxiliary clock signal terminal NCLK1, the function input terminal includes an input signal terminal, and the function output terminal includes a sixth node N6.

[0371] The function circuit 150 is configured to form a path between the input signal terminal and the sixth node N6 when the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 has an effective potential, so as to realize transmission of the input signal provided by the input signal terminal to the sixth node N6.

[0372] The function circuit 150 is further configured to cut off the path between the input signal terminal and the sixth node N6 when the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 has an ineffective potential, so as to maintain the potential of the sixth node N6.

[0373] As shown in FIG. 1, Figure 31 In some embodiments, the function circuit 150 includes a third transistor T3, and the third transistor T3 includes an oxide transistor.

[0374] In some examples, the third transistor T3 is an N-type transistor. When the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is at a high potential, a path is formed between the first electrode (the input signal terminal) of the third transistor T3 and the second electrode (the sixth node N6) of the third transistor T3, so as to realize transmission of the input signal provided by the input signal terminal to the seventh node N7. When the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is at a low potential, the path between the first electrode (the input signal terminal) of the third transistor T3 and the second electrode (the sixth node N6) of the third transistor T3 is cut off, so as to maintain the potential of the sixth node N6.

[0375] As shown in FIG. 1, Figure 31 In some embodiments, the twelfth control signal terminal K12 includes a second voltage signal terminal VGH.

[0376] The first voltage stabilizing circuit 180 includes a function circuit 150. The function control terminal includes the second voltage signal terminal VGH, the function input terminal includes the sixth node N6, and the function output terminal includes a seventh node N7.

[0377] The function circuit 150 is configured to form a path between the sixth node N6 and the seventh node N7 when the potential of the second voltage signal provided by the second voltage signal terminal VGH is lower than the potential of the seventh node N7, so as to realize transmission of the potential of the sixth node N6 to the seventh node N7.

[0378] The functional circuit 150 is also configured to disconnect the path between the sixth node N6 and the seventh node N7 when the potential of the second voltage signal provided by the second voltage signal terminal VGH is higher than the potential of the seventh node N7, so as to maintain the potential of the seventh node N7.

[0379] like Figure 31 As shown, in some embodiments, the functional circuit 150 includes a fourteenth transistor T14, which is an oxide transistor.

[0380] In some examples, the fourteenth transistor T14 is an N-type transistor. When the potential of the second voltage signal provided by the second voltage signal terminal VGH is lower than that of the seventh node N7, a path is formed between the first terminal (sixth node N6) and the second terminal (seventh node N7) of the fourteenth transistor T14, thereby transferring the potential of the sixth node N6 to the seventh node N7. When the potential of the second voltage signal provided by the second voltage signal terminal VGH is higher than that of the seventh node N7, the path between the first terminal (sixth node N6) and the second terminal (seventh node N7) of the fourteenth transistor T14 is broken to maintain the potential of the seventh node N7.

[0381] like Figure 29 As shown, in some embodiments, the shift register may also include a third voltage regulator circuit.

[0382] The third voltage regulator circuit is coupled to both the seventh node N7 and the third node N3. The third voltage regulator circuit is configured to conduct between the seventh node N7 and the third node N3 under the control of the potential of the seventh node N7.

[0383] In this embodiment, the third voltage regulator circuit is connected in series between the fourteenth transistor T14 and the first output circuit 120. The first output circuit 120 is coupled to the third node N3 and is coupled to the seventh node N7 through the third voltage regulator circuit.

[0384] like Figure 30 and Figure 31 As shown, in some embodiments, the third voltage regulator circuit includes a fifteenth transistor T15.

[0385] The control electrode of the fifteenth transistor T15 is coupled to the seventh node N7, the first electrode of the fifteenth transistor T15 is coupled to the seventh node N7, and the second electrode of the fifteenth transistor T15 is coupled to the third node N3.

[0386] In some examples, the fifteenth transistor T15 is a P-type transistor. In a case where the potential at the seventh node N7 is at a low potential, a path is formed between the first pole (the seventh node N7) of the fifteenth transistor T15 and the second pole (the third node N3) of the fifteenth transistor T15, and the potential at the seventh node N7 is transmitted to the third node N3.

[0387] As shown in FIG. 1, Figure 5-13 , Figure 24-31 In some embodiments, the first output signal terminal S1 includes the fourth clock signal terminal CLK4 or the first voltage signal terminal VGL.

[0388] The first output circuit 120 includes a sixteenth transistor T16. The control pole of the sixteenth transistor T16 is coupled with the first node N1, the first pole of the sixteenth transistor T16 is coupled with the first output signal terminal S1, and the second pole of the sixteenth transistor T16 is coupled with the first scan signal terminal.

[0389] As shown in FIG. 1, Figure 5-13 In some examples, the first output signal terminal S1 includes the fourth clock signal terminal CLK4, and the sixteenth transistor T16 is a P-type transistor. In a case where the potential at the first node N1 is at a low potential, a path is formed between the first pole (the fourth clock signal terminal CLK4) of the sixteenth transistor T16 and the second pole (the first scan signal terminal) of the sixteenth transistor T16, and the fourth clock signal provided by the fourth clock signal terminal CLK4 is transmitted to the first scan signal terminal.

[0390] As shown in FIG. 1, Figure 5-13 In some embodiments, the first output circuit 120 can further include a fourth capacitor. The first pole plate of the fourth capacitor is coupled with the first scan signal terminal, and the second pole plate of the fourth capacitor is coupled with the first node N1,

[0391] The fourth capacitor cannot have a sudden change in potential difference between the two pole plates, so when the potential at one pole plate changes, the fourth capacitor can adjust the potential at the other pole plate through its bootstrap function.

[0392] As shown in FIG. 1, Figure 5-13 In some embodiments, the second output signal terminal S2 includes the second clock signal terminal CLK2 or the second voltage signal terminal VGH.

[0393] The second output circuit 140 includes a seventeenth transistor T17 and a second capacitor.

[0394] The control electrode of the seventeenth transistor T17 is coupled with the second node N2, the first electrode of the seventeenth transistor T17 is coupled with the second output signal terminal S2, and the second electrode of the seventeenth transistor T17 is coupled with the first scan signal terminal; the first plate of the second capacitor is coupled with the second output signal terminal S2, and the second plate of the second capacitor is coupled with the second node N2.

[0395] As Figure 5 , Figure 6 , Figure 10-13 As Figure 5-13 In some examples, the second output signal terminal S2 includes a second voltage signal terminal VGH, and the seventeenth transistor T17 is a P-type transistor. In the case that the potential of the second node N2 is at a low potential, a path is formed between the first electrode (the second voltage signal terminal VGH) of the seventeenth transistor T17 and the second electrode (the first scan signal terminal) of the seventeenth transistor T17, and the second voltage signal provided by the second voltage signal terminal VGH is transmitted to the first scan signal terminal.

[0396] In some embodiments, the shift register includes a first transistor T1 in the first control circuit 160, which has the same structure as the oxide transistor in Figure 4B . The second gate pattern in the first transistor T1 is arranged in the same layer as the control electrode of the seventeenth transistor T17.

[0397] It should be noted that "in the same layer" means that the film layer for forming a specific pattern is formed by the same film forming process, and then the layer structure is formed by one patterning process using the same mask plate. According to different specific patterns, the one patterning process can include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous, and these specific patterns can also be at different heights or have different thicknesses.

[0398] As Figure 32 shown, in some embodiments, the shift register can be a GATE GOA N. The shift register includes a second transistor T2, a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a sixteenth transistor T16, a seventeenth transistor T17, a second capacitor, and a fourth capacitor.

[0399] The control electrode of the second transistor T2 is coupled with the first clock signal terminal CLK1, the first electrode of the second transistor T2 is coupled with the input signal terminal, and the second electrode of the second transistor T2 is coupled with the first node N1.

[0400] The control terminal of the fourth transistor T4 is coupled to the first clock signal terminal CLK1, the first terminal of the fourth transistor T4 is coupled to the first voltage signal terminal VGL, and the second terminal of the fourth transistor T4 is coupled to the second node N2.

[0401] The control electrode of the fifth transistor T5 is coupled to the first node N1, the first electrode of the fifth transistor T5 is coupled to the first clock signal terminal CLK1, and the second electrode of the fifth transistor T5 is coupled to the second node N2.

[0402] The control electrode of the eighth transistor T8 is coupled to the second node N2, the first electrode of the eighth transistor T8 is coupled to the second voltage signal terminal VGH, and the second electrode of the eighth transistor T8 is coupled to the first electrode of the ninth transistor T9.

[0403] The control terminal of the ninth transistor T9 is coupled to the fourth clock signal terminal CLK4, and the second terminal of the ninth transistor T9 is coupled to the first node N1.

[0404] The control electrode of the tenth transistor T10 is coupled to the first voltage signal terminal VGL, the first electrode of the tenth transistor T10 is coupled to the first node N1, and the second electrode of the tenth transistor T10 is coupled to the third node N3.

[0405] The control electrode of the sixteenth transistor T16 is coupled to the third node N3, the first electrode of the sixteenth transistor T16 is coupled to the fourth clock signal terminal CLK4, and the second electrode of the sixteenth transistor T16 is coupled to the first scan signal terminal.

[0406] The control electrode of the seventeenth transistor T17 is coupled to the second node N2, the first electrode of the seventeenth transistor T17 is coupled to the second voltage signal terminal VGH, and the second electrode of the seventeenth transistor T17 is coupled to the first scan signal terminal.

[0407] The first plate of the second capacitor is coupled to the second voltage signal terminal VGH, and the second plate of the second capacitor is coupled to the second node N2.

[0408] The first plate of the fourth capacitor is coupled to the first scan signal terminal, and the second plate of the fourth capacitor is coupled to the third node N3.

[0409] like Figure 33 As shown, Figure 33 This includes the timing of the input signal provided by the input signal terminal, the timing of the first clock signal provided by the first clock signal terminal CLK1, the timing of the fourth clock signal provided by the fourth clock signal terminal CLK4, the timing of the first scan signal provided by the first scan signal terminal, and the timing of the first node N1 and the second node N2. Additionally, the first voltage signal terminal VGL continuously provides a low-level first voltage signal, and the second voltage signal terminal VGH continuously provides a high-level second voltage signal. Figure 33The working stage in the first stage t1, the second stage t2, the third stage t3 and the fourth stage t4. Among them, the fourth stage t4 includes the first sub-stage t41, the second sub-stage t42 and the third sub-stage t43.

[0410] The following is described with the second transistor T2, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the sixteenth transistor T16, the seventeenth transistor T17 are all P-type transistors:

[0411] In the first stage t1, the first clock signal provided by the first clock signal end CLK1 is a low potential signal, the fourth clock signal provided by the fourth clock signal end CLK4 is a high potential signal, and the input signal provided by the input signal end is a low potential signal, for example, the potential of the input signal is equal to the potential of the first voltage signal. Since the first clock signal is a low potential signal, the second transistor T2 is in the on state, and the input signal is transmitted to the first node N1 via the second transistor T2. Since the second transistor T2 transmits a low potential signal with threshold loss, the potential of the first node N1 is Vin (the potential of the input signal)-Vth2 (the threshold voltage of the second transistor T2), that is, VGL (the potential of the first voltage signal)-Vth2. Since the tenth transistor T10 receives the first voltage signal at the control electrode, the tenth transistor T10 is in the on state, and thus the voltage VGL-Vth2 is transmitted to the third node N3 via the tenth transistor T10. For example, the threshold voltage of the tenth transistor T10 is represented as Vth10, and for the same reason, since the tenth transistor T10 transmits a low potential signal with threshold loss, the potential of the third node N3 is VGL-VthN3, wherein VthN3 is the smaller one of Vth2 and Vth10 (the threshold voltage of the tenth transistor T10). The potential of the third node N3 can control the sixteenth transistor T16 to be in the on state, and the fourth clock signal is written into the first scan signal end as the first scan signal via the sixteenth transistor T16, that is, in the input stage t1, the output signal is a high potential fourth clock signal, for example, the high potential of the fourth clock signal is equal to the potential of the second voltage signal, that is, VGH (the potential of the second voltage signal).

[0412] In the first stage t1, since the first clock signal is a low potential signal, the fourth transistor T4 is in the on state, and the first voltage signal VGL is transmitted to the second node N2 via the fourth transistor T4. Since the potential of the first node N1 is VGL-Vth2, the fifth transistor T5 is in the on state, and the first clock signal at a low potential is transmitted to the second node N2 via the fifth transistor T5. For example, the threshold voltage of the fifth transistor T5 is represented as Vth5, and the threshold voltage of the fourth transistor T4 is represented as Vth4. When Vth4 < Vth5+Vth2, the potential of the second node N2 is VGL-Vth5-Vth2; and when Vth4 > Vth5+Vth2, the potential of the second node N2 is VGL-Vth4. At this time, the seventeenth transistor T17 and the eighth transistor T8 are both in the on state. Since the fourth clock signal is a high potential signal, the ninth transistor T9 is in the off state.

[0413] In the second stage t2, the first clock signal provided by the first clock signal terminal CLK1 is a high potential signal, the fourth clock signal provided by the fourth clock signal terminal CLK4 is a low potential signal, and the input signal provided by the input signal terminal is a high potential signal. The second transistor T2 and the fourth transistor T4 are both in the off state. The potential of the first node N1 is still VGL-Vth2, the fifth transistor T5 is in the on state, and the high potential first clock signal is transmitted to the second node N2 via the fifth transistor T5, i.e. the potential of the second node N2 is equal to the potential of the second voltage signal, so that the seventeenth transistor T17 and the eighth transistor T8 are both in the off state. Since the fourth clock signal is a low potential signal, the ninth transistor T9 is in the on state.

[0414] In the second stage t2, the sixteenth transistor T16 is in the on state, and the fourth clock signal is written into the first scan signal terminal as an output signal via the sixteenth transistor T16. In the first stage t1, the potential of one end of the first scan signal terminal connected to the first plate of the fourth capacitor C4 is equal to the potential of the second voltage signal, and the potential of one end of the third node N3 connected to the second plate of the fourth capacitor C4 is VGL-VthN3. In the second stage t2, the potential of one end of the first scan signal terminal connected to the first plate of the fourth capacitor C4 becomes VGL, and due to the bootstrap effect of the fourth capacitor C4, the potential of one end of the third node N3 connected to the second plate of the fourth capacitor C4 becomes 2VGL-VthN3-VGH, i.e. the potential of the third node N3 becomes 2VGL-VthN3-VGH. At this time, the tenth transistor T10 is in the off state, and the sixteenth transistor T16 can be better opened, and the potential of the first scan signal is equal to the potential of the first voltage signal.

[0415] In the third stage t3, the first clock signal provided by the first clock signal terminal CLK1 and the fourth clock signal provided by the fourth clock signal terminal CLK4 are both high potential signals, and the input signal provided by the input signal terminal is a high potential signal. The second transistor T2 and the fourth transistor T4 are both in the off state. The potential of the third node N3 becomes VGL-VthN3, at this time, the tenth transistor T10 is in the on state, and the potential of the first node N1 is also VGL-VthN3, the fifth transistor T5 is in the on state, and the first clock signal with a high potential is transmitted to the second node N2 through the fifth transistor T5, that is, the potential of the second node N2 is equal to the potential of the second voltage signal, thereby the seventeenth transistor T17 and the eighth transistor T8 are both in the off state. Since the fourth clock signal is a high potential signal, the ninth transistor T9 is in the off state.

[0416] In the third stage t3, the sixteenth transistor T16 is in the on state, and the fourth clock signal is written into the first scan signal terminal as the first scan signal through the sixteenth transistor T16, at this time, the first scan signal is a high potential fourth clock signal, that is, the second voltage signal VGH. Due to the bootstrap effect of the fourth capacitor C4, the potential of the third node N3 becomes VGL-VthN3.

[0417] In the first sub-stage t41 of the fourth stage t4, the first clock signal provided by the first clock signal terminal CLK1 is a low potential signal, the fourth clock signal provided by the fourth clock signal terminal CLK4 is a high potential signal, and the input signal provided by the input signal terminal is a high potential signal, for example, the input signal is equal to the second voltage signal VGH. Since the first clock signal is a low potential signal, the second transistor T2 is in the on state, and the input signal is transmitted to the first node N1 through the second transistor T2, and since the second transistor T2 transmits a high potential signal without threshold loss, the potential of the first node N1 is Vin (equal to the potential of the second voltage signal), and the fifth transistor T5 is in the off state. Since the tenth transistor T10 is in the on state, the potential of the third node N3 is the same as that of the first node N1, that is, the potential of the third node N3 is equal to the potential of the second voltage signal, and the sixteenth transistor T16 is in the off state. Since the first clock signal is a low potential signal, the fourth transistor T4 is in the on state, the potential of the second node N2 is VGL-Vth4, the seventeenth transistor T17 and the eighth transistor T8 are both in the on state, and the second voltage signal VGH is transmitted to the first scan signal terminal through the seventeenth transistor T17, that is, the first scan signal is the second voltage signal VGH.

[0418] In the second sub-stage t42 of the fourth stage t4, the first clock signal provided by the first clock signal terminal CLK1 is a high-level signal, the fourth clock signal provided by the fourth clock signal terminal CLK4 is a low-level signal, and the input signal provided by the input signal terminal is a high-level signal. The potentials of the third node N3 and the first node N1 are Vin (equal to the potential of the second voltage signal), and the sixteenth transistor T16 and the fifth transistor T5 are both in the off state. The first clock signal is a high-level signal, so the second transistor T2 and the fourth transistor T4 are both in the off state. Due to the holding effect of the second capacitor C2, the potential of the second node N2 is still VGL-Vth4, and the seventeenth transistor T17 and the eighth transistor T8 are both in the on state. The second voltage signal VGH is transmitted to the first scan signal terminal through the seventeenth transistor T17, and the first scan signal is the second voltage signal VGH.

[0419] In the second sub-stage t42 of the fourth stage t4, since the fourth clock signal is a low-level signal, the ninth transistor T9 is in the conducting state, so the second voltage signal VGH is transmitted to the first node N1 and the third node N3 via the eighth transistor T8 and the ninth transistor T9, so that the potential of the third node N3 and the potential of the first node N1 are kept at a high level.

[0420] In the third sub-stage t43 of the fourth stage t4, the first clock signal provided by the first clock signal terminal CLK1 and the second clock signal provided by the second clock signal terminal CLK2 are both high-level signals, and the input signal provided by the input signal terminal is also high-level. The potentials of the first node N1 and the third node N3 are equal to the potential of the second voltage signal, and the sixteenth transistor T16 and the fifth transistor T5 are both in the off state. The first clock signal is a high-level signal, so the second transistor T2 and the fourth transistor T4 are both in the off state, the potential of the second node N2 is still VGL-Vth4, and the seventeenth transistor T17 and the eighth transistor T8 are both in the on state. The second voltage signal VGH is transmitted to the first scan signal terminal via the seventeenth transistor T17, and the first scan signal is the second voltage signal VGH.

[0421] like Figure 5 As shown, in some embodiments, the shift register is compared to Figure 32 The difference in the shift register shown includes the addition of a first transistor T1, which is an oxide transistor. The first transistor T1 is connected in series between the second node N2 and the first clock signal terminal CLK1. For example, the first transistor T1 is connected in series between the second node N2 and the fifth transistor T5, or, for another example, the first transistor T1 is connected in series between the fifth transistor T5 and the first clock signal terminal CLK1. The control electrode of the first transistor T1 is coupled to the third clock signal terminal CLK3.

[0422] The following describes the first transistor T1 as an N-type transistor:

[0423] In combination Figure 5 and Figure 33 As shown in the above first stage t1, the third clock signal provided by the third clock signal terminal CLK3 is a high potential signal, the potential of the first node N1 is at a low potential (the voltage value is VGL-Vth2), the first transistor T1 and the fifth transistor T5 are both in the on state, the first clock signal provided by the first clock signal terminal CLK1 is a low potential signal, and is transmitted to the second node N2 via the first transistor T1 and the fifth transistor T5.

[0424] In the above second stage t2, the third clock signal provided by the third clock signal terminal CLK3 is a high potential signal, the potential of the first node N1 is at a low potential (the voltage value is VGL-Vth2), the first transistor T1 and the fifth transistor T5 are both in the on state, the first clock signal provided by the first clock signal terminal CLK1 is a high potential signal, and is transmitted to the second node N2 via the first transistor T1 and the fifth transistor T5.

[0425] In the above third stage t3, the third clock signal provided by the third clock signal terminal CLK3 is a high potential signal, the potential of the first node N1 is at a low potential (the voltage value is VGL-VthN3), the first transistor T1 and the fifth transistor T5 are both in the on state, the first clock signal provided by the first clock signal terminal CLK1 is a high potential signal, and is transmitted to the second node N2 via the first transistor T1 and the fifth transistor T5.

[0426] In the first sub-stage t41 of the above fourth stage t4, the third clock signal provided by the third clock signal terminal CLK3 is a low potential signal, the potential of the first node N1 is at a high potential (the voltage value is VGH), the first transistor T1 and the fifth transistor T5 are both in the off state, and the first transistor T1 can block the path between the third clock signal terminal CLK3 and the second node N2 to maintain the potential of the second node N2.

[0427] In the second sub-stage t42 of the above fourth stage t4, the third clock signal provided by the third clock signal terminal CLK3 is a low potential signal, the potential of the first node N1 is at a high potential (the voltage value is VGH), the first transistor T1 and the fifth transistor T5 are both in the off state, and the first transistor T1 can block the path between the third clock signal terminal CLK3 and the second node N2 to prevent the high potential first clock signal provided by the first clock signal terminal CLK1 from raising the potential of the second node N2, thereby maintaining the potential of the second node N2.

[0428] In the third sub-stage t43 of the fourth stage t4, the third clock signal provided by the third clock signal terminal CLK3 is a low potential signal, the potential of the first node N1 is at a high potential (the voltage value is VGH), the first transistor T1 and the fifth transistor T5 are both in the off state, and the first transistor T1 can block the path between the third clock signal terminal CLK3 and the second node N2, thereby preventing the high potential first clock signal provided by the first clock signal terminal CLK1 from raising the potential of the second node N2, so as to maintain the potential of the second node N2.

[0429] As can be seen from the above, the first transistor T1 is coupled in series between the second node N2 and the first clock signal terminal CLK1, and on the basis of the normal operation of the first control circuit 160, the first clock signal provided by the first clock signal terminal CLK1 can effectively avoid affecting the potential of the second node N2, improve the stability of the potential of the second node N2, and further improve the reliability of the shift register.

[0430] The working processes of other transistors can refer to the above example description, which will not be described here.

[0431] As shown in Figure 6 , in some embodiments, the shift register is different from the shift register shown in Figure 32 , and the difference includes that the second transistor T2 is an oxide transistor. In the embodiment, the control electrode of the second transistor T2 is coupled with the first auxiliary clock signal terminal NCLK1.

[0432] Taking the second transistor T2 as an N-type transistor for description:

[0433] In combination with Figure 6 and Figure 33 , in the above first stage t1, the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a high potential signal, the second transistor T2 is in the on state, the input signal provided by the input signal terminal is a low potential, and the input signal is transmitted to the first node N1 through the second transistor T2.

[0434] In the above second stage t2, the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a low potential signal, the second transistor T2 is in the off state, and the path between the input signal terminal and the first node N1 is blocked, thereby preventing the high potential input signal provided by the input signal terminal from raising the potential of the first node N1, so as to maintain the low potential of the first node N1.

[0435] In the third stage t3 mentioned above, the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a low-level signal, and the second transistor T2 is in the off state, cutting off the path between the input signal terminal and the first node N1, thereby preventing the high-level input signal provided by the input signal terminal from raising the potential of the first node N1, so as to maintain the low potential of the first node N1.

[0436] In the first sub-stage t41 of the fourth stage t4 mentioned above, the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a high-level signal, the second transistor T2 is in the on state, the input signal provided by the input signal terminal is a high-level signal, and the input signal is transmitted to the first node N1 via the second transistor T2.

[0437] In the second sub-stage t42 of the fourth stage t4 mentioned above, the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a low-level signal, and the second transistor T2 is in the off state, cutting off the path between the input signal terminal and the first node N1, so as to maintain the low potential of the first node N1.

[0438] In the third sub-stage t43 of the fourth stage t4 mentioned above, the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a low-potential signal, and the second transistor T2 is in the off state, cutting off the path between the input signal terminal and the first node N1, so as to maintain the low potential of the first node N1.

[0439] As described above, it can be seen that by using the second transistor T2 as an oxide transistor and coupling the control electrode of the second transistor T2 to the first auxiliary clock signal terminal NCLK1, the input signal provided by the input signal terminal can be prevented from affecting the potential of the first node N1 when the second transistor T2 is in the off state, while the first input circuit 110 is working normally. This improves the stability of the potential of the first node N1 and thus improves the reliability of the shift register.

[0440] The operation of other transistors can be referred to the example above, and will not be repeated here.

[0441] like Figure 11 As shown, in some embodiments, the shift register is compared to Figure 32 The difference in the shift register shown includes that the fourth transistor T4 is an oxide transistor. In this embodiment, the control electrode of the fourth transistor T4 is coupled to the first auxiliary clock signal terminal NCLK1.

[0442] The explanation will focus on the fourth transistor, T4, as an N-type transistor:

[0443] Combination Figure 11 and Figure 33As shown, in the first stage t1, the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a high potential signal, the fourth transistor T4 is in a conductive state, and the first voltage signal provided by the first voltage signal terminal VGL is transmitted to the second node N2 via the fourth transistor T4.

[0444] In the second stage t2, the potential of the first node N1 is at a low potential, the fifth transistor T5 is in a conductive state, and the first clock signal terminal CLK1 at a high potential is transmitted to the second node N2. The first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a low potential signal, the fourth transistor T4 is in a cut-off state, and the path between the first voltage signal terminal VGL and the second node N2 is blocked, preventing the low potential signal of the first voltage signal from affecting the high potential of the second node N2, thereby improving the stability of the potential of the second node N2.

[0445] In the third stage t3, the potential of the first node N1 is at a low potential, the fifth transistor T5 is in a conductive state, and the first clock signal terminal CLK1 at a high potential is transmitted to the second node N2. The first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a low potential signal, the fourth transistor T4 is in a cut-off state, and the path between the first voltage signal terminal VGL and the second node N2 is blocked to maintain the high potential of the second node N2.

[0446] In the first sub-stage t41 of the fourth stage t4, the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a high potential signal, the fourth transistor T4 is in a conductive state, and the first voltage signal provided by the first voltage signal terminal VGL is transmitted to the second node N2 via the fourth transistor T4.

[0447] In the second sub-stage t42 of the fourth stage t4, the potential of the first node N1 is at a high potential, and the fifth transistor T5 is in a cut-off state. The first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a low potential signal, the second transistor T2 is in a cut-off state, and the path between the input signal terminal and the first node N1 is blocked to maintain the low potential of the second node N2.

[0448] In the third sub-stage t43 of the fourth stage t4, the potential of the first node N1 is at a high potential, and the fifth transistor T5 is in a cut-off state. The first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a low potential signal, the second transistor T2 is in a cut-off state, and the path between the input signal terminal and the first node N1 is blocked to maintain the low potential of the second node N2.

[0449] As can be seen from the above, the fourth transistor T4 is taken as an oxide transistor, and the control electrode of the fourth transistor T4 is coupled with the first auxiliary clock signal terminal NCLK1, so that the input signal provided by the first voltage signal terminal VGL can be prevented from affecting the potential of the second node N2 in the case that the fourth transistor T4 is in the off state on the basis of the normal operation of the second input circuit 130, the stability of the potential of the second node N2 is improved, and the reliability of the shift register is further improved.

[0450] The working processes of other transistors can refer to the above description, which will not be repeated here.

[0451] As shown in FIG. 1, Figure 22 In some embodiments, the shift register is different from the shift register shown in FIG. 1 in that the tenth transistor T10 is an oxide transistor. Figure 32 In the embodiment, the control electrode of the tenth transistor T10 is coupled with the second voltage signal terminal VGH.

[0452] Taking the tenth transistor T10 as an N-type transistor for description:

[0453] As shown in FIG. 1, Figure 22 and Figure 33 In the above first stage t1, the potential of the first node N1 is at a low potential (the voltage value is VGL-Vth2). The second voltage signal provided by the second voltage signal terminal VGH is a high potential signal, and the tenth transistor T10 is in the on state, so that the potential of the first node N1 is transmitted to the third node N3 through the tenth transistor T10.

[0454] In the above second stage t2, the potential of the third node N3 is at a low potential (2VGL-VthN3-VGH). The second voltage signal provided by the second voltage signal terminal VGH is a high potential signal, and the tenth transistor T10 is in the off state, so as to cut off the path between the first node N1 and the third node N3, thereby maintaining the low potential of the third node N3.

[0455] In the above third stage t3, the potential of the first node N1 is at a low potential (the voltage value is VGL-VthN3). The second voltage signal provided by the second voltage signal terminal VGH is a high potential signal, and the tenth transistor T10 is in the on state, so that the potential of the first node N1 is transmitted to the third node N3 through the tenth transistor T10.

[0456] In the first, second and third sub-stages t41, t42 and t43 of the above fourth stage t4, the potential of the first node N1 is at a high potential. The second voltage signal provided by the second voltage signal terminal VGH is a high potential signal, and the tenth transistor T10 is in the on state, so that the potential of the first node N1 is transmitted to the third node N3 through the tenth transistor T10.

[0457] As can be seen from the above, by using the tenth transistor T10 as an oxide transistor and coupling the control terminal of the tenth transistor T10 to the second voltage signal terminal VGH, it is possible to prevent the potential of the first node N1 from affecting the potential of the third node N3 when the tenth transistor T10 is in the off state, based on the normal operation of the first voltage regulator circuit 180. This improves the stability of the potential of the third node N3 and thus improves the reliability of the shift register.

[0458] The operation of other transistors can be referred to the example above, and will not be repeated here.

[0459] like Figure 20 As shown, in some embodiments, the shift register is compared to Figure 32 The difference in the shift register shown includes the addition of a first transistor T1, which is an oxide transistor. The first transistor T1 is connected in series between the second voltage signal terminal VGH and the first node N1, and the control electrode of the first transistor T1 is also connected to the first node N1. The series connection of the first transistor T1 between the second voltage signal terminal VGH and the first node N1 can have various configurations, as previously described in detail and will not be repeated here.

[0460] The following explanation assumes that the first transistor T1 is an N-type transistor and is located between the eighth transistor T8 and the ninth transistor T9:

[0461] Combination Figure 20 and Figure 33 As shown, in the first stage t1, the potential of the second node N2 is low, and the eighth transistor T8 is in the on state. The fourth clock signal provided by the fourth clock signal terminal CLK4 is a high-potential signal, and the ninth transistor T9 is in the off state. The potential of the first node N1 is low, and the first transistor T1 is in the off state, cutting off the path between the second voltage signal terminal VGH and the first node N1 to prevent the high-potential second voltage signal from affecting the low potential of the first node N1 and maintaining the stability of the first node N1.

[0462] In the second stage t2 described above, the potential of the second node N2 is high, and the eighth transistor T8 is in the off state. The fourth clock signal provided by the fourth clock signal terminal CLK4 is a low-potential signal, and the ninth transistor T9 is in the on state. The potential of the first node N1 remains low, and the first transistor T1 is in the off state, cutting off the path between the second voltage signal terminal VGH and the first node N1 to prevent the high-potential second voltage signal from affecting the low potential of the first node N1 and maintaining the stability of the first node N1.

[0463] In the third stage t3, the second node N2 is at low potential, and the eighth transistor T8 is in the on state. The fourth clock signal provided by the fourth clock signal terminal CLK4 is a high potential signal, and the ninth transistor T9 is in the off state. The first node N1 is still at low potential, and the first transistor T1 is in the off state, cutting off the path between the second voltage signal terminal VGH and the first node N1, so as to prevent the high potential second voltage signal from affecting the low potential of the first node N1, and maintaining the stability of the first node N1.

[0464] In the first sub-stage t41 of the fourth stage t4, the second node N2 is at high potential, and the eighth transistor T8 is in the off state. The fourth clock signal provided by the fourth clock signal terminal CLK4 is a high potential signal, and the ninth transistor T9 is in the off state. The first node N1 is at high potential, and the first transistor T1 is in the on state. Since the first node N1 and the second voltage signal are both at high potential, the second voltage signal will not affect the potential of the first node N1.

[0465] In the second sub-stage t42 of the fourth stage t4, the second node N2 is at low potential, and the eighth transistor T8 is in the on state. The fourth clock signal provided by the fourth clock signal terminal CLK4 is a low potential signal, and the ninth transistor T9 is in the on state. The first node N1 is at high potential, and the first transistor T1 is in the on state, forming a path between the second voltage signal terminal VGH and the first node N1, and realizing the transmission of the second voltage signal terminal VGH to the first node N1.

[0466] In the second sub-stage t43 of the fourth stage t4, the second node N2 is at low potential, and the eighth transistor T8 is in the on state. The fourth clock signal provided by the fourth clock signal terminal CLK4 is a high potential signal, and the ninth transistor T9 is in the off state. The first node N1 is at high potential, and the first transistor T1 is in the on state. Since the first node N1 and the second voltage signal are both at high potential, the second voltage signal will not affect the potential of the first node N1.

[0467] As described above, it can be seen that the first transistor T1 is coupled in series between the second voltage signal terminal VGH and the first node N1, and on the basis of the normal operation of the noise reduction circuit 170, the second voltage signal can effectively avoid affecting the potential of the first node N1 in the case that at least one of the eighth transistor T8 and the ninth transistor T9 is in the off state and the first node N1 is different from the potential of the second voltage signal, improving the stability of the potential of the first node N1, and further improving the reliability of the shift register.

[0468] The working processes of other transistors can refer to the above example description, which will not be described here.

[0469] As shown in FIG. 1, in some embodiments, the shift register is different from the shift register shown in FIG. 1 in that the ninth transistor T9 is an oxide transistor. Figure 21 As shown in FIG. 1, in some embodiments, the shift register is different from the shift register shown in FIG. 1 in that the ninth transistor T9 is an oxide transistor. Figure 32 As shown in FIG. 1, in some embodiments, the shift register is different from the shift register shown in FIG. 1 in that the ninth transistor T9 is an oxide transistor.

[0470] As shown in FIG. 1, in some embodiments, the shift register is different from the shift register shown in FIG. 1 in that the ninth transistor T9 is an oxide transistor.

[0471] As shown in FIG. 1, in some embodiments, the shift register is different from the shift register shown in FIG. 1 in that the ninth transistor T9 is an oxide transistor. Figure 21 As shown in FIG. 1, in some embodiments, the shift register is different from the shift register shown in FIG. 1 in that the ninth transistor T9 is an oxide transistor. Figure 33 In the first stage t1, the potential of the first node N1 and the potential of the second node N2 are both at a low potential, and the eighth transistor T8 is in a conductive state. The fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is a low potential signal, and the ninth transistor T9 is in a cut-off state. The ninth transistor T9 blocks the path between the first node N1 and the second voltage signal terminal VGH, preventing the second voltage signal as a high potential from affecting the potential of the first node N1, improving the stability of the potential of the first node N1, and further improving the reliability of the shift register.

[0472] In the second stage t2, the potential of the first node N1 is at a low potential, and the potential of the second node N2 is at a high potential, and the eighth transistor T8 is in a cut-off state. The fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is a high potential signal, and the ninth transistor T9 is in a conductive state.

[0473] In the third stage t3, the potential of the first node N1 is at a low potential, and the potential of the second node N2 is at a high potential, and the eighth transistor T8 is in a cut-off state. The fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is a low potential signal, and the ninth transistor T9 is in a cut-off state. The ninth transistor T9 blocks the path between the second voltage signal terminal VGH and the first node N1, preventing the second voltage signal as a high potential from affecting the low potential of the first node N1, improving the stability of the potential of the first node N1, and further improving the reliability of the shift register.

[0474] In the first sub-stage t41 of the fourth stage t4, the potential of the first node N1 is at a high potential, and the potential of the second node N2 is at a low potential, and the eighth transistor T8 is in a conductive state. The fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is at a low potential, and the ninth transistor T9 is in a cut-off state, blocking the path between the second voltage signal terminal VGH and the first node N1.

[0475] In the second sub-stage t42 of the fourth stage t4, the potential of the second node N2 is at a low potential, and the eighth transistor T8 is in a conductive state. The fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is a high potential signal, and the ninth transistor T9 is in a conductive state, forming a path between the second voltage signal terminal VGH and the first node N1, and the second voltage signal is transmitted to the first node N1, controlling the potential of the first node N1 to be at a high potential.

[0476] In the third sub-stage t43 of the fourth stage t4, the potential of the first node N1 is at a high potential, and the potential of the second node N2 is at a low potential, and the eighth transistor T8 is in a conductive state. The fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is at a low potential, and the ninth transistor T9 is in a cut-off state, blocking the path between the second voltage signal terminal VGH and the first node N1.

[0477] As described above, it can be seen that the ninth transistor T9 can effectively avoid the influence of the second voltage signal provided by the second voltage signal terminal VGH on the potential of the first node N1 on the basis of normal operation, improve the stability of the potential of the first node N1, and further improve the reliability of the shift register.

[0478] The working processes of other transistors can refer to the above example description, which will not be described here.

[0479] As shown in FIG. 1, in some embodiments, the shift register is different from the shift register shown in FIG. 1 in that the sixth transistor T6 and the seventh transistor T7 are added, and the sixth transistor T6 is an oxide transistor. In this embodiment, the shift register GATE GOA P and GATE GOA N, that is, the shift register includes both the first scan signal terminal for controlling the P-type transistor in the pixel circuit and the second scan signal terminal for controlling the N-type transistor in the pixel circuit. Figure 17 Figure 32 The control electrode of the sixth transistor T6 is coupled with the first node N1, the first electrode of the sixth transistor T6 is coupled with the first voltage signal terminal VGL, and the second electrode of the sixth transistor T6 is coupled with the second scan signal terminal.

[0480] The control electrode of the seventh transistor T7 is coupled with the first node N1, the first electrode of the seventh transistor T7 is coupled with the second voltage signal terminal VGH, and the second electrode of the seventh transistor T7 is coupled with the second scan signal terminal.

[0481] Taking the sixth transistor T6 as an N-type transistor and the seventh transistor T7 as a P-type transistor for description:

[0482] In combination with and

[0483] Figure 17 Figure 33 ​​As shown, in the first stage t1, the second stage t2, and the third stage t3, the potential of the first node N1 is low, the sixth transistor T6 is in the off state, and the seventh transistor T7 is in the on state. The second voltage signal provided by the second voltage signal terminal VGH is transmitted to the second scan signal terminal, making the second scan signal output by the second scan signal terminal a high-potential signal. The sixth transistor T6 isolates the path between the second scan signal terminal and the first voltage signal terminal VGL, preventing the low potential (VGL) signal of the first voltage signal terminal VGL from affecting the high potential of the second scan signal terminal, thereby maintaining the potential of the second scan signal terminal.

[0484] In the first sub-stage t41, the second sub-stage t42, and the third sub-stage t43 of the fourth stage t4 mentioned above, the potential of the first node N1 is high, the sixth transistor T6 is in the on state, the seventh transistor T7 is in the off state, and the first voltage signal provided by the first voltage signal terminal VGL is transmitted to the second scan signal terminal, so that the second scan signal output by the second scan signal terminal is a low potential signal.

[0485] As described above, the sixth transistor T6 and the seventh transistor T7 can effectively control the potential of the second scan signal provided by the second scan signal terminal. Simultaneously, when the sixth transistor T6 is in the off state, it can effectively prevent the low potential (VGL) signal of the first voltage signal terminal VGL from affecting the high potential of the second scan signal terminal, improving the stability of the potential of the second scan signal terminal and thus improving the reliability of the shift register.

[0486] The operation of other transistors can be referred to the example above, and will not be repeated here.

[0487] like Figure 17 As shown, in some embodiments, the shift register is compared to Figure 32 The difference in the shift register shown includes that the fifth transistor T5 is an oxide transistor. In this embodiment, the control electrode of the fifth transistor T5 is coupled to the second scan signal terminal.

[0488] The fifth transistor, T5, is an N-type transistor, as explained below:

[0489] Combination Figure 17 and Figure 33 As shown, in the first stage t1, the second stage t2 and the third stage t3, the second scan signal provided by the second scan signal terminal is a high potential signal, the fifth transistor T5 is in the conducting state, forming a path between the first clock signal terminal CLK1 and the second node N2, and transmitting the first clock signal provided by the first clock signal terminal CLK1 to the second node N2.

[0490] In the first sub-stage t41, the second sub-stage t42, and the third sub-stage t43 of the fourth stage t4 mentioned above, the second scan signal provided by the second scan signal terminal is a low-potential signal, and the fifth transistor T5 is in the off state, cutting off the path between the first clock signal terminal CLK1 and the second node N2, so as to prevent the first clock signal provided by the first clock signal terminal CLK1 from affecting the potential of the second node N2.

[0491] As described above, while the fifth transistor T5 can perform the aforementioned functions normally, it can also effectively prevent the first clock signal provided by the first clock signal terminal CLK1 from affecting the potential of the second node N2 when the fifth transistor T5 is in the off state, thereby improving the stability of the potential of the second node N2 and thus improving the reliability of the shift register. In addition, it can also reduce the coupling of additional control signals with the control electrode of the fifth transistor T5, reducing the manufacturing cost of the shift register.

[0492] The operation of other transistors can be referred to the example above, and will not be repeated here.

[0493] like Figure 34 As shown, in some embodiments, the shift register can be a light-emitting scan bit register. The shift register may include a second transistor T2, a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, a ninth transistor T9, an eleventh transistor T11, a twelfth transistor T12, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a second capacitor, a first capacitor, and a fourth capacitor.

[0494] The control electrode of the second transistor T2 is coupled to the first clock signal terminal CLK1, the first electrode of the second transistor T2 is coupled to the input signal terminal, and the second electrode of the second transistor T2 is coupled to the first node N1.

[0495] The control terminal of the fourth transistor T4 is coupled to the first clock signal terminal CLK1, the first terminal of the fourth transistor T4 is coupled to the first voltage signal terminal VGL, and the second terminal of the fourth transistor T4 is coupled to the second node N2.

[0496] The control electrode of the fifth transistor T5 is coupled to the first node N1, the first electrode of the fifth transistor T5 is coupled to the first clock signal terminal CLK1, and the second electrode of the fifth transistor T5 is coupled to the second node N2.

[0497] The control electrode of the eighth transistor T8 is coupled to the second node N2, the first electrode of the eighth transistor T8 is coupled to the second voltage signal terminal VGH, and the second electrode of the eighth transistor T8 is coupled to the first electrode of the ninth transistor T9.

[0498] The control terminal of the ninth transistor T9 is coupled to the fourth clock signal terminal CLK4, and the second terminal of the ninth transistor T9 is coupled to the first node N1.

[0499] The control electrode of the eleventh transistor T11 is coupled to the second node N2, the first electrode of the eleventh transistor T11 is coupled to the fourth clock signal terminal CLK4, and the second electrode of the eleventh transistor T11 is coupled to the first electrode of the twelfth transistor T12.

[0500] The control terminal of the twelfth transistor T12 is coupled to the fourth clock signal terminal CLK4, and the second terminal of the twelfth transistor T12 is coupled to the fourth node N4.

[0501] The control electrode of the sixteenth transistor T16 is coupled to the third node N3, the first electrode of the sixteenth transistor T16 is coupled to the first voltage signal terminal VGL, and the second electrode of the sixteenth transistor T16 is coupled to the first scan signal terminal.

[0502] The control electrode of the seventeenth transistor T17 is coupled to the fourth node N4, the first electrode of the seventeenth transistor T17 is coupled to the second voltage signal terminal VGH, and the second electrode of the seventeenth transistor T17 is coupled to the first scan signal terminal.

[0503] The control electrode of the eighteenth transistor T18 is coupled to the first node N1, the first electrode of the eighteenth transistor T18 is coupled to the second voltage signal terminal VGH, and the second electrode of the eighteenth transistor T18 is coupled to the fourth node N4.

[0504] The first plate of the first capacitor C1 is coupled to the second node N2, and the second plate of the first capacitor C1 is coupled to the first terminal of the twelfth transistor T12.

[0505] The first plate of the second capacitor C2 is coupled to the second voltage signal terminal VGH, and the second plate of the second capacitor C2 is coupled to the fourth node N4.

[0506] The first plate of the fifth capacitor C5 is coupled to the first node N1, and the second plate of the fifth capacitor C5 is coupled to the fourth clock signal terminal CLK4.

[0507] like Figure 35 As shown, Figure 35 This includes the timing changes of the input signal provided by the input signal terminal, the timing changes of the first clock signal provided by the first clock signal terminal CLK1, the timing changes of the fourth clock signal provided by the fourth clock signal terminal CLK4, and the timing changes of the first scan signal provided by the first scan signal terminal. Additionally, the first voltage signal terminal VGL continuously provides a low-level first voltage signal, and the second voltage signal terminal VGH continuously provides a high-level second voltage signal. Figure 35The working stages in the first stage t1, the second stage t2, the third stage t3, the fourth stage t4 and the fifth stage t5. Among them, the adjacent two working stages also include a buffer stage.

[0508] The second transistor T2, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, the sixteenth transistor T16, the seventeenth transistor T17 and the eighteenth transistor T18 are all P-type transistors.

[0509] In the first stage t1, the first clock signal provided by the first clock signal end CLK1 is a low potential signal, the fourth clock signal provided by the fourth clock signal end CLK4 is a high potential signal, and the input signal provided by the input signal end is a high potential signal, for example, the input signal is equal to the second voltage signal. Because the first clock signal is a low potential signal, the second transistor T2 is in a conductive state, and the input signal is transmitted to the first node N1 through the second transistor T2, so that the potential of the first node N1 is equal to the potential of the second voltage signal. The potential of the first node N1 is at a high potential, which causes the fifth transistor T5, the eighteenth transistor T18 and the sixteenth transistor T16 to be in a cut-off state. The fourth transistor T4 is in a conductive state, and the first voltage signal provided by the first voltage signal end VGL is transmitted to the second node N2 through the fourth transistor T4, and the second node N2 is at a low potential (VGL). Because the fourth clock signal is a high potential signal, the ninth transistor T9 and the twelfth transistor T12 are both in a cut-off state, the fourth node N4 maintains the high potential of the last stage, the seventeenth transistor T17 is in a cut-off state, and the first scan signal end maintains the low potential of the last stage.

[0510] In the second stage t2, the first clock signal provided by the first clock signal terminal CLK1 is a high potential signal, the fourth clock signal provided by the fourth clock signal terminal CLK4 is a low potential signal, and the input signal provided by the input signal terminal is a high potential signal. Since the first clock signal is a high potential signal, the second transistor T2 and the fourth transistor T4 are both in the off state. The first node N1 keeps the high potential in the first stage t1, causing the fifth transistor T5, the eighteenth transistor T18 and the sixteenth transistor T16 to be in the off state. The second node N2 keeps the low potential in the first stage t1, and the fourth clock signal is a low potential signal, causing the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11 and the twelfth transistor T12 to be in the on state. In this way, the second voltage signal provided by the second voltage signal terminal VGH is transmitted to the first node N1 via the eighth transistor T8 and the ninth transistor T9, and the first node N1 is kept at a high potential; the fourth clock signal is transmitted to the fourth node N4 via the eleventh transistor T11 and the twelfth transistor T12, and the fourth node N4 is at a low potential (VGL), causing the seventeenth transistor T17 to be in the on state, and the second voltage signal provided by the second voltage signal terminal VGH is transmitted to the first scan signal terminal, and the first scan signal provided by the first scan signal terminal is a high potential signal.

[0511] In the third stage t3, the first clock signal provided by the first clock signal terminal CLK1 is a low potential signal, the fourth clock signal provided by the fourth clock signal terminal CLK4 is a high potential signal, and the input signal provided by the input signal terminal is a high potential signal. Since the first clock signal is a low potential signal, the second transistor T2 is in the on state, and the input signal is transmitted to the first node N1 via the second transistor T2, so that the potential of the first node N1 is equal to the potential of the second voltage signal. The potential of the first node N1 is at a high potential, causing the fifth transistor T5, the eighteenth transistor T18 and the sixteenth transistor T16 to be in the off state. The fourth transistor T4 is in the on state, and the first voltage signal is transmitted to the second node N2 via the fourth transistor T4, and the potential of the second node N2 is equal to the potential of the first voltage signal. Since the fourth clock signal is a high potential signal, the ninth transistor T9 and the twelfth transistor T12 are both in the off state, the fourth node N4 keeps the low potential in the second stage t2, the seventeenth transistor T17 is in the on state, the second voltage signal provided by the second voltage signal terminal VGH is transmitted to the first scan signal terminal, and the first scan signal provided by the first scan signal terminal is a high potential signal.

[0512] In the fourth stage t4, the first clock signal provided by the first clock signal terminal CLK1 is a high potential signal, the fourth clock signal provided by the fourth clock signal terminal CLK4 is a low potential signal, and the input signal provided by the input signal terminal is a low potential signal. Since the first clock signal is a high potential signal, the second transistor T2 and the fourth transistor T4 are both in the off state. The first node N1 keeps the high potential in the third stage t3, causing the fifth transistor T5, the eighteenth transistor T18 and the sixteenth transistor T16 to be in the off state. The second node N2 keeps the low potential in the third stage t3, and the fourth clock signal is a low potential signal, causing the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11 and the twelfth transistor T12 to be in the on state. In this way, the second voltage signal provided by the second voltage signal terminal VGH is transmitted to the first node N1 via the eighth transistor T8 and the ninth transistor T9, and the first node N1 is kept at a high potential; the fourth clock signal is transmitted to the fourth node N4 via the eleventh transistor T11 and the twelfth transistor T12, and the fourth node N4 is at a low potential (VGL), causing the seventeenth transistor T17 to be in the on state, and the second voltage signal provided by the second voltage signal terminal VGH is transmitted to the first scan signal terminal, and the first scan signal provided by the first scan signal terminal is a high potential signal.

[0513] In the fifth stage t5, the first clock signal provided by the first clock signal terminal CLK1 is a low potential signal, the fourth clock signal provided by the fourth clock signal terminal CLK4 is a high potential signal, and the input signal provided by the input signal terminal is a low potential signal. Since the first clock signal is a low potential signal, the second transistor T2 and the fourth transistor T4 are both in the on state. The input signal is transmitted to the first node N1 via the second transistor T2, so that the potential of the first node N1 is equal to the potential of the first voltage signal. The potential of the first node N1 is at a low potential, and the fifth transistor T5, the eighteenth transistor T18 and the sixteenth transistor T16 are all in the on state. The second voltage signal is transmitted to the fourth node N4 via the eighteenth transistor T18, and the potential of the fourth node N4 is equal to the potential of the second voltage signal. The potential of the fourth node N4 is at a high potential, causing the seventeenth transistor T17 to be in the off state. The first voltage signal terminal VGL transmits the first voltage signal to the first scan signal terminal via the sixteenth transistor T16, and the first scan signal provided by the first scan signal terminal is a low potential signal.

[0514] As shown in FIG. 1, in some embodiments, the shift register is compared to a conventional shift register. Figure 24 Figure 34 ​The difference between the shift register shown in the figure and the shift register shown in the figure includes that a first transistor T1 is added, and the first transistor T1 includes an oxide transistor. The first transistor T1 is coupled in series between the second node N2 and the first clock signal end CLK1, for example, the first transistor T1 is coupled in series between the second node N2 and the fifth transistor T5, and for example, the first transistor T1 is coupled in series between the fifth transistor T5 and the first clock signal end CLK1. In addition, the control electrode of the first transistor T1 is coupled with the fourth node N4.

[0515] The first transistor T1 is taken as an N-type transistor for description:

[0516] Combined with the figure shown in the figure, Figure 24 and Figure 35 In the above-mentioned first stage t1, the potential of the first node N1 is at a high potential, the potential of the second node N2 is at a low potential, and the fifth transistor T5 is in a cut-off state. The potential of the fourth node N4 is at a high potential, the first transistor T1 is in a conductive state, and the first clock signal as a low potential signal will not affect the low potential of the second node N2.

[0517] In the above-mentioned second stage t2, the potential of the first node N1 is at a high potential, the potential of the second node N2 is at a low potential, and the fifth transistor T5 is in a cut-off state. The potential of the fourth node N4 is at a low potential, the first transistor T1 is in a cut-off state, and the path between the first clock signal end CLK1 and the second node N2 is blocked, avoiding the first clock signal end CLK1 as a high potential signal affecting the low potential of the second node N2, and maintaining the stability of the potential of the second node N2.

[0518] In the above-mentioned third stage t3, the potential of the first node N1 is at a high potential, the potential of the second node N2 is at a low potential, and the fifth transistor T5 is in a cut-off state. The potential of the fourth node N4 is at a low potential, the first transistor T1 is in a cut-off state, and the path between the first clock signal end CLK1 and the second node N2 is blocked, maintaining the stability of the potential of the second node N2.

[0519] In the above-mentioned fourth stage t4, the potential of the first node N1 is at a high potential, the potential of the second node N2 is at a low potential, and the fifth transistor T5 is in a cut-off state. The potential of the fourth node N4 is at a low potential, the first transistor T1 is in a cut-off state, and the path between the first clock signal end CLK1 and the second node N2 is blocked, avoiding the first clock signal end CLK1 as a high potential signal affecting the low potential of the second node N2, and maintaining the stability of the potential of the second node N2.

[0520] In the fifth stage t5 mentioned above, the potential of the first node N1 is low, the potential of the second node N2 is low, and the fifth transistor T5 is in the on state. The potential of the fourth node N4 is high, and the first transistor T1 is in the on state, forming a path between the first clock signal terminal CLK1 and the second node N2. This allows the first clock signal, which is a low-potential signal, to be transmitted to the second node N2 via the first transistor T1 and the fifth transistor T5, controlling the potential of the second node N2 to be low.

[0521] As described above, it can be seen that the first transistor T1 is connected in series between the second node N2 and the first clock signal terminal CLK1. On the basis of the normal operation of the first control circuit 160, it can also effectively prevent the first clock signal provided by the first clock signal terminal CLK1 from affecting the potential of the second node N2, improve the stability of the potential of the second node N2, and thus improve the reliability of the shift register.

[0522] The operation of other transistors can be referred to the example above, and will not be repeated here.

[0523] like Figure 36 As shown, in some embodiments, the shift register is compared to Figure 34 The difference in the shift register shown includes that the second transistor T2 is an oxide transistor. In this embodiment, the control electrode of the second transistor T2 is coupled to the first auxiliary clock signal terminal NCLK1.

[0524] The explanation will focus on the second transistor, T2, as an N-type transistor:

[0525] Combination Figure 36 and Figure 35 As shown, in the first stage t1 and the third stage t3, the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a high-level signal, the second transistor T2 is in the on state, the input signal provided by the input signal terminal is a high-level signal, and the input signal is transmitted to the first node N1 via the second transistor T2.

[0526] In the second stage t2 and the fourth stage t4, the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a low-level signal, and the second transistor T2 is in the off state, isolating the input signal terminal from the first node N1. Specifically, in the fourth stage t4, the input signal is a low-level signal, and the first node N1 is at a high level. The second transistor T2's isolation of the input signal terminal from the first node N1 prevents the low-level input signal from affecting the high level of the first node N1, improving the stability of the first node N1's potential and thus enhancing the reliability of the shift register.

[0527] In the fifth stage t5, the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a high potential signal, the second transistor T2 is in a conductive state, and the input signal provided by the input signal terminal is a low potential, forming a path between the input signal terminal and the first node N1, and the input signal is transmitted to the first node N1 via the second transistor T2.

[0528] As can be seen from the above, as an oxide transistor, the second transistor T2 can effectively avoid the influence of the input signal provided by the input signal terminal on the potential of the first node N1 on the basis of the normal operation of the first input circuit 110, improve the stability of the potential of the first node N1, and further improve the reliability of the shift register.

[0529] The working processes of other transistors can refer to the above example description, which will not be described here.

[0530] As shown in Figure 37 , in some embodiments, the shift register adds a first transistor T1 compared with the shift register shown in Figure 34 , and the first transistor T1 includes an oxide transistor. The first transistor T1 is coupled in series between the second voltage signal terminal VGH and the first node N1, and the control electrode of the first transistor T1 is coupled with the first node N1. The first transistor T1 can have multiple series positions when coupled in series between the second voltage signal terminal VGH and the first node N1, which has been described in detail before and will not be described here.

[0531] Taking the case that the first transistor T1 is an N-type transistor and the first transistor T1 is located between the eighth transistor T8 and the ninth transistor T9 as an example:

[0532] In combination with Figure 37 and Figure 35 , in the above first stage t1 and third stage t3, the potential of the first node N1 is at a high potential, and the first transistor T1 is in a conductive state; the fourth clock signal provided by the fourth clock signal terminal CLK4 is a high potential signal, and the ninth transistor T9 is in a cut-off state; the potential of the second node N2 is at a low potential, and the eighth transistor T8 is in a conductive state. The second voltage signal as a high potential signal will not affect the high potential of the first node N1.

[0533] In the first stage t1 and the fourth stage t4, the potential of the first node N1 is at a high potential, and the first transistor T1 is in a conducting state; the fourth clock signal provided by the fourth clock signal terminal CLK4 is a low potential signal, and the ninth transistor T9 is in a conducting state; the potential of the second node N2 is at a low potential, and the eighth transistor T8 is in a conducting state. The second voltage signal as a high potential signal does not affect the high potential of the first node N1. The second voltage signal as a high potential signal is transmitted to the first node N1 via the eighth transistor T8, the first transistor T1 and the ninth transistor T9, and controls the potential of the first node N1 to be at a high potential.

[0534] In the fifth stage t5, the potential of the first node N1 is at a low potential, and the first transistor T1 is in a cut-off state; the fourth clock signal provided by the fourth clock signal terminal CLK4 is a high potential signal, and the ninth transistor T9 is in a cut-off state; the potential of the second node N2 is at a low potential, and the eighth transistor T8 is in a conducting state. The first transistor T1 blocks the path between the second voltage terminal and the first node N1, prevents the first voltage signal terminal VGL as a high potential from affecting the low potential of the first node N1, improves the stability of the potential of the first node N1, and further improves the reliability of the shift register.

[0535] As described above, it can be seen that the first transistor T1 is coupled in series between the first node N1 and the second voltage signal terminal VGH. On the basis of normal operation of the noise reduction circuit 170, the second voltage signal provided by the second voltage signal terminal VGH can be effectively prevented from affecting the potential of the first node N1, the stability of the potential of the first node N1 is improved, and the reliability of the shift register is further improved.

[0536] The working processes of other transistors can refer to the above example description, which will not be described here.

[0537] As shown in Figure 38 In some embodiments, the ninth transistor T9 can be an oxide transistor. Wherein, the ninth transistor T9 is different from the ninth transistor T9 in Figure 34 The control electrode of the ninth transistor T9 is coupled with the fourth auxiliary clock signal terminal NCLK4.

[0538] Taking the ninth transistor T9 as an N-type transistor for description:

[0539] In combination with Figure 38 and Figure 35As shown, in the first stage t1 and the third stage t3, the potential of the first node N1 is high, the potential of the second node N2 is low, and the eighth transistor T8 is in the on state. The fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is a low-level signal, and the ninth transistor T9 is in the off state, cutting off the path between the second voltage signal terminal VGH and the first node N1.

[0540] In the second stage t2 and the fourth stage t4, the potential of the second node N2 is low, and the eighth transistor T8 is in the on state. The fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is a high-potential signal, and the ninth transistor T9 is in the on state, forming a path between the second voltage signal terminal VGH and the first node N1. The second voltage signal is transmitted to the first node via the eighth transistor T8 and the ninth transistor T9, controlling the potential of the first node N1 to be high.

[0541] In the fifth stage t5, the potential of the first node N1 is low, the potential of the second node N2 is low, and the eighth transistor T8 is in the on state. The fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is a low-level signal, and the ninth transistor T9 is in the off state. The ninth transistor T9 isolates the path between the second voltage signal terminal VGH and the first node N1, which can prevent the second voltage signal, which is a high-level signal, from affecting the low potential of the first node N1, thereby improving the stability of the potential of the first node N1 and thus improving the reliability of the shift register.

[0542] As can be seen from the above, the ninth transistor T9, as an oxide transistor, can effectively prevent the second voltage signal provided by the second voltage signal terminal VGH from affecting the potential of the first node N1, improve the stability of the potential of the first node N1, and thus improve the reliability of the shift register, on the basis of the normal operation of the noise reduction circuit 170.

[0543] The operation of other transistors can be referred to the example above, and will not be repeated here.

[0544] like Figure 25 As shown, in some embodiments, the shift register is compared to... Figure 34 The difference in the shift register shown is that the twelfth transistor T12 is an oxide transistor. The control terminal of the twelfth transistor T12 is coupled to the fourth auxiliary clock signal terminal NCLK4.

[0545] The following explanation uses the twelfth transistor, T12, as an N-type transistor:

[0546] Combination Figure 25 and Figure 35As shown in the first stage t1, the third stage t3 and the fifth stage t5, the potential of the second node N2 is at a low potential, and the eleventh transistor T11 is in a conductive state. The fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is a low potential signal, and the twelfth transistor T12 is in a cut-off state, thereby cutting off the path between the fourth clock signal terminal CLK4 and the fourth node N4. In the first stage t1 and the third stage t3, the path between the fourth clock signal terminal CLK4 and the fourth node N4 is cut off, thereby preventing the second voltage signal as a high potential signal from affecting the low potential of the fourth node N4.

[0547] In the second stage t2 and the fourth stage t4, the potential of the second node N2 is at a low potential, and the eleventh transistor T11 is in a conductive state. The fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is a high potential signal, and the twelfth transistor T12 is in a conductive state, thereby forming a path between the fourth clock signal terminal CLK4 and the fourth node N4, and the fourth clock signal as a low potential signal is transmitted to the fourth node N4 to control the fourth node N4 to be at a low potential.

[0548] As described above, it can be seen that the twelfth transistor T12 includes an oxide transistor, and on the basis of the normal operation of the second control circuit 210, the fourth clock signal provided by the fourth clock signal terminal CLK4 can effectively avoid affecting the potential of the fourth node N4, thereby improving the stability of the potential of the fourth node N4, and further improving the reliability of the shift register.

[0549] The working processes of other transistors can refer to the above example description, which will not be described here.

[0550] As shown in the first stage t1, the third stage t3 and the fifth stage t5, the potential of the second node N2 is at a low potential, and the eleventh transistor T11 is in a conductive state. The fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is a low potential signal, and the twelfth transistor T12 is in a cut-off state, thereby cutting off the path between the fourth clock signal terminal CLK4 and the fourth node N4. In the first stage t1 and the third stage t3, the path between the fourth clock signal terminal CLK4 and the fourth node N4 is cut off, thereby preventing the second voltage signal as a high potential signal from affecting the low potential of the fourth node N4. Figure 39 Figure 34 As shown in the first stage t1, the third stage t3 and the fifth stage t5, the potential of the second node N2 is at a low potential, and the eleventh transistor T11 is in a conductive state. The fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is a low potential signal, and the twelfth transistor T12 is in a cut-off state, thereby cutting off the path between the fourth clock signal terminal CLK4 and the fourth node N4. In the first stage t1 and the third stage t3, the path between the fourth clock signal terminal CLK4 and the fourth node N4 is cut off, thereby preventing the second voltage signal as a high potential signal from affecting the low potential of the fourth node N4.

[0551] The following describes the tenth transistor T10 as a P-type transistor:

[0552] As shown in the first stage t1, the third stage t3 and the fifth stage t5, the potential of the second node N2 is at a low potential, and the eleventh transistor T11 is in a conductive state. The fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is a low potential signal, and the twelfth transistor T12 is in a cut-off state, thereby cutting off the path between the fourth clock signal terminal CLK4 and the fourth node N4. In the first stage t1 and the third stage t3, the path between the fourth clock signal terminal CLK4 and the fourth node N4 is cut off, thereby preventing the second voltage signal as a high potential signal from affecting the low potential of the fourth node N4. Figure 39 Figure 35 As shown in the first stage t1, the third stage t3 and the fifth stage t5, the potential of the second node N2 is at a low potential, and the eleventh transistor T11 is in a conductive state. The fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is a low potential signal, and the twelfth transistor T12 is in a cut-off state, thereby cutting off the path between the fourth clock signal terminal CLK4 and the fourth node N4. In the first stage t1 and the third stage t3, the path between the fourth clock signal terminal CLK4 and the fourth node N4 is cut off, thereby preventing the second voltage signal as a high potential signal from affecting the low potential of the fourth node N4.

[0553] As shown in the first stage t1, the third stage t3 and the fifth stage t5, the potential of the second node N2 is at a low potential, and the eleventh transistor T11 is in a conductive state. The fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is a low potential signal, and the twelfth transistor T12 is in a cut-off state, thereby cutting off the path between the fourth clock signal terminal CLK4 and the fourth node N4. In the first stage t1 and the third stage t3, the path between the fourth clock signal terminal CLK4 and the fourth node N4 is cut off, thereby preventing the second voltage signal as a high potential signal from affecting the low potential of the fourth node N4. Figure 40 ​​As shown in some embodiments, the tenth transistor T10 is an oxide transistor. Wherein, the tenth transistor T10 is different from that shown in Figure 39 the tenth transistor T10 in that the control electrode of the tenth transistor T10 is coupled with the second voltage signal terminal VGH.

[0554] Figure 40 the tenth transistor T10 in Figure 39 the tenth transistor T10 in the above embodiment, which will not be repeated here.

[0555] the tenth transistor T10 in the above embodiment, which will not be repeated here.

[0556] As shown in some embodiments, the shift register is different from that shown in Figure 27 some embodiments, the shift register is different from that shown in Figure 34 the shift register shown in the above embodiment, which includes the thirteenth transistor T13. Wherein, the thirteenth transistor T13 is coupled in series between the second node N2 and the fifth node N5. Taking the thirteenth transistor T13 as a P-type transistor for example, the control electrode of the thirteenth transistor T13 is coupled with the first voltage signal terminal VGL.

[0557] Taking the thirteenth transistor T13 as a P-type transistor for example:

[0558] In combination with Figure 27 and Figure 35 the above first stage t1, the third stage t3 and the fifth stage t5, the potential of the second node N2 is at a low potential, the thirteenth transistor T13 is in a conductive state, forming a path between the second node N2 and the fifth node N5, so that the potential of the fifth node N5 is at a low potential. The eleventh transistor T11 is in a conductive state, forming a path between the fourth clock signal terminal CLK4 and the first plate of the first capacitor, the potential of the first plate of the first capacitor is at a high potential, and the potential of the second plate (i.e. the fifth node N5) of the first capacitor is at a low potential.

[0559] In the above second stage t2 and fourth stage t4, the potential of the second node N2 is at a low potential, and the eleventh transistor T11 is in a conductive state. The fourth clock signal provided by the fourth clock signal is changed from a high potential signal to a low potential signal, so that the potential of the first plate of the first capacitor is at a low potential. Due to the bootstrap effect of the first capacitor, the potential of the second plate (i.e. the fifth node N5) of the first capacitor is further lowered, and the thirteenth transistor T13 is in a cut-off state and makes the eleventh transistor T11 better conductive.

[0560] As shown in some embodiments, the shift register is different from that shown in Figure 28 some embodiments, the shift register is different from that shown in Figure 27The difference between the shift register shown in the thirteenth transistor T13 includes an oxide transistor. In the thirteenth transistor T13 as an example of an N-type transistor, the control electrode of the thirteenth transistor T13 is coupled to the second voltage signal terminal VGH. In this embodiment, the working process of the thirteenth transistor T13 is substantially the same as that of the thirteenth transistor T13 in the shift register described in the thirteenth embodiment. Figure 27 The working process of the thirteenth transistor T13 in the shift register described in the thirteenth embodiment is substantially the same as that of the thirteenth transistor T13 in the shift register described in the thirteenth embodiment. In addition, when the thirteenth transistor T13 is in the off state in the second stage t2 and the fourth stage t4, the path between the second node N2 and the fifth node N5 can be blocked, preventing the higher second node N2 from affecting the potential of the lower fifth node N5, and maintaining the stability of the potential of the fifth node N5.

[0561] The working processes of other transistors can refer to the above example description, which will not be described here.

[0562] As shown in FIG. 13A, in some embodiments, the shift register can be a light-emitting scanning bit register or a GATE GOAN. The shift register can include a second transistor T2, a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a first capacitor, a second capacitor, and a third capacitor. Figure 41 The control electrode of the second transistor T2 is coupled to the first clock signal terminal CLK1, the first electrode of the second transistor T2 is coupled to the input signal terminal, and the second electrode of the second transistor T2 is coupled to the first node N1.

[0563] The control electrode of the fourth transistor T4 is coupled to the first clock signal terminal CLK1, the first electrode of the fourth transistor T4 is coupled to the first voltage signal terminal VGL, and the second electrode of the fourth transistor T4 is coupled to the second node N2.

[0564] The control electrode of the fifth transistor T5 is coupled to the first node N1, the first electrode of the fifth transistor T5 is coupled to the first clock signal terminal CLK1, and the second electrode of the fifth transistor T5 is coupled to the second node N2.

[0565] The control electrode of the eighth transistor T8 is coupled to the second node N2, the first electrode of the eighth transistor T8 is coupled to the second voltage signal terminal VGH, and the second electrode of the eighth transistor T8 is coupled to the first plate of the third capacitor.

[0566] The control electrode of the ninth transistor T9 is coupled to the third node N3, the first electrode of the ninth transistor T9 is coupled to the fourth clock signal terminal CLK4, and the second electrode of the ninth transistor T9 is coupled to the first plate of the third capacitor.

[0567] The control electrode of the ninth transistor T9 is coupled to the third node N3, the first electrode of the ninth transistor T9 is coupled to the fourth clock signal terminal CLK4, and the second electrode of the ninth transistor T9 is coupled to the first plate of the third capacitor.

[0568] The control electrode of the tenth transistor T10 is coupled to the first voltage signal terminal VGL, the first electrode of the tenth transistor T10 is coupled to the first node N1, and the second electrode of the tenth transistor T10 is coupled to the third node N3.

[0569] The control electrode of the eleventh transistor T11 is coupled to the second node N2, the first electrode of the eleventh transistor T11 is coupled to the fourth clock signal terminal CLK4, and the second electrode of the eleventh transistor T11 is coupled to the first electrode of the twelfth transistor T12.

[0570] The control terminal of the twelfth transistor T12 is coupled to the fourth clock signal terminal CLK4, and the second terminal of the twelfth transistor T12 is coupled to the fourth node N4.

[0571] The control electrode of the sixteenth transistor T16 is coupled to the third node N3, the first electrode of the sixteenth transistor T16 is coupled to the first voltage signal terminal VGL, and the second electrode of the sixteenth transistor T16 is coupled to the first scan signal terminal.

[0572] The control electrode of the seventeenth transistor T17 is coupled to the fourth node N4, the first electrode of the seventeenth transistor T17 is coupled to the second voltage signal terminal VGH, and the second electrode of the seventeenth transistor T17 is coupled to the first scan signal terminal.

[0573] The control electrode of the eighteenth transistor T18 is coupled to the first node N1, the first electrode of the eighteenth transistor T18 is coupled to the second voltage signal terminal VGH, and the second electrode of the eighteenth transistor T18 is coupled to the fourth node N4.

[0574] The first plate of the first capacitor is coupled to the second node N2, and the second plate of the first capacitor is coupled to the first terminal of the twelfth transistor T12.

[0575] The first plate of the second capacitor is coupled to the second voltage signal terminal VGH, and the second plate of the second capacitor is coupled to the fourth node N4.

[0576] The second plate of the third capacitor is coupled to the third node N3.

[0577] like Figure 42 As shown, Figure 42 This includes the timing of the input signal provided by the input signal terminal, the timing of the first clock signal provided by the first clock signal terminal CLK1, the timing of the fourth clock signal provided by the fourth clock signal terminal CLK4, and the timing of the first scan signal provided by the first scan signal terminal. Additionally, the first voltage signal terminal VGL continuously provides a low-level first voltage signal, and the second voltage signal terminal VGH continuously provides a high-level second voltage signal. Figure 42The working stages in the shift register include a first stage t1, a second stage t2, a third stage t3, a fourth stage t4 and a fifth stage t5. Between two adjacent working stages, a buffer stage is further included.

[0578] The working process of the plurality of transistors and the plurality of circuit nodes in the shift register in this embodiment is substantially similar to that of the shift register shown in Figure 34 The difference between the shift register in this embodiment and the shift register shown in

[0579] In the first stage t1, the second stage t2, the third stage t3 and the fourth stage t4, the potential of the second node N2 is at a low potential, and the potential of the third node N3 is at a high potential. The ninth transistor T9 is in a cut-off state, and the eighth transistor T8 is in a conductive state. A path is formed between the second voltage signal end VGH and the first plate of the third capacitor, and the second voltage signal as a high potential signal is transmitted to the first plate of the third capacitor. The potential of the first plate of the third capacitor and the potential of the second plate of the third capacitor are both at a high potential.

[0580] In the fifth stage t5, the potential of the second node N2 is at a low potential, and the potential of the third node N3 is at a low potential. The fifth transistor T5 is in a conductive state. The eighth transistor T8 is in a conductive state, and a path is formed between the second voltage signal end VGH and the first plate of the third capacitor. The second voltage signal as a high potential signal is transmitted to the first plate of the third capacitor. The ninth transistor T9 is in a conductive state, and a path is formed between the fourth clock signal end CLK4 and the first plate of the third capacitor. The fourth clock signal as a high potential signal is transmitted to the first plate of the third capacitor, and the stability of the low potential of the second plate is maintained.

[0581] As shown in Figure 43 In some embodiments, the shift register is different from the shift register shown in Figure 41 The difference between the shift register in this embodiment and the shift register shown in Figure 36 The connection relationship of the second transistor T2 in this embodiment is the same as that of the second transistor T2 in the shift register shown in

[0582] As shown in Figure 44 In some embodiments, the shift register is different from the shift register shown in Figure 41The difference between the shift register shown in FIG. 9 and the shift register shown in FIG. 1 includes that the first transistor T1 is added, and the first transistor T1 includes an oxide transistor. The first transistor T1 is coupled in series between the second node N2 and the first clock signal terminal CLK1, for example, the first transistor T1 is coupled in series between the second node N2 and the fifth transistor T5, for another example, the first transistor T1 is coupled in series between the fifth transistor T5 and the first clock signal terminal CLK1. The connection relationship of the first transistor T1 is the same as that in FIG. 1, and the working state of each stage is also approximately the same, which can play the same role, and will not be described here. Figure 36 The connection relationship of the first transistor T1 in FIG. 9 is the same as that in FIG. 1, and the working state of each stage is also approximately the same, which can play the same role, and will not be described here.

[0583] As shown in FIG. 10, in some embodiments, the shift register is different from the shift register shown in FIG. 1 in that the fourth transistor T4 is an oxide transistor. Figure 45 The connection relationship of the fourth transistor T4 in FIG. 10 is the same as that in FIG. 1, and the working state of each stage is also approximately the same, which can play the same role, and will not be described here. Figure 41 As shown in FIG. 11, in some embodiments, the shift register is different from the shift register shown in FIG. 1 in that the tenth transistor T10 is an oxide transistor. Figure 25 The connection relationship of the tenth transistor T10 in FIG. 11 is the same as that in FIG. 1, and the working state of each stage is also approximately the same, which can play the same role, and will not be described here.

[0584] As shown in FIG. 12, in some embodiments, the shift register is different from the shift register shown in FIG. 1 in that the twelfth transistor T12 is an oxide transistor. Figure 46 The connection relationship of the twelfth transistor T12 in FIG. 12 is the same as that in FIG. 1, and the working state of each stage is also approximately the same, which can play the same role, and will not be described here. Figure 41 As shown in FIG. 13, in some embodiments, the shift register is different from the shift register shown in FIG. 1 in that the thirteenth transistor T13 is added. Figure 40 The connection relationship of the thirteenth transistor T13 in FIG. 13 is the same as that in FIG. 1, and the working state of each stage is also approximately the same, which can play the same role, and will not be described here.

[0585] As shown in FIG. 14, in some embodiments, the shift register is different from the shift register shown in FIG. 1 in that the thirteenth transistor T13 is added. Figure 47 The connection relationship of the thirteenth transistor T13 in FIG. 14 is the same as that in FIG. 1, and the working state of each stage is also approximately the same, which can play the same role, and will not be described here. Figure 41 As shown in FIG. 15, in some embodiments, the shift register is different from the shift register shown in FIG. 1 in that the thirteenth transistor T13 is added. Figure 25 The connection relationship of the thirteenth transistor T13 in FIG. 15 is the same as that in FIG. 1, and the working state of each stage is also approximately the same, which can play the same role, and will not be described here.

[0586] As shown in FIG. 16, in some embodiments, the shift register is different from the shift register shown in FIG. 1 in that the thirteenth transistor T13 is added. Figure 48 The connection relationship of the thirteenth transistor T13 in FIG. 16 is the same as that in FIG. 1, and the working state of each stage is also approximately the same, which can play the same role, and will not be described here. Figure 41 As shown in FIG. 17, in some embodiments, the shift register is different from the shift register shown in FIG. 1 in that the thirteenth transistor T13 is added. Figure 28 The connection relationship of the thirteenth transistor T13 in FIG. 17 is the same as that in FIG. 1, and the working state of each stage is also approximately the same, which can play the same role, and will not be described here.

[0587] As shown in FIG. 18, in some embodiments, the shift register is different from the shift register shown in FIG. 1 in that the thirteenth transistor T13 is added. Figure 49As shown, in some embodiments, the shift register can be a light emitting scan bit register or GATE GOAN. The shift register can include a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, a ninth transistor T9, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a first capacitor, a second capacitor, and a third capacitor.

[0588] The control electrode of the second transistor T2 is coupled with a second clock signal terminal CLK2, the first electrode of the second transistor T2 is coupled with an input signal terminal, and the second electrode of the second transistor T2 is coupled with the first electrode of the third transistor T3.

[0589] The control electrode of the third transistor T3 is coupled with a first clock signal terminal CLK1, and the second electrode of the third transistor T3 is coupled with a first node N1.

[0590] The control electrode of the fourth transistor T4 is coupled with the first clock signal terminal CLK1, the first electrode of the fourth transistor T4 is coupled with a first voltage signal terminal VGL, and the second electrode of the fourth transistor T4 is coupled with a second node N2.

[0591] The control electrode of the fifth transistor T5 is coupled with the first node N1, the first electrode of the fifth transistor T5 is coupled with the first clock signal terminal CLK1, and the second electrode of the fifth transistor T5 is coupled with the second node N2.

[0592] The control electrode of the eighth transistor T8 is coupled with the second node N2, the first electrode of the eighth transistor T8 is coupled with a second voltage signal terminal VGH, and the second electrode of the eighth transistor T8 is coupled with an eighth node.

[0593] The control electrode of the ninth transistor T9 is coupled with a third node N3, the first electrode of the ninth transistor T9 is coupled with a fourth clock signal terminal CLK4, and the second electrode of the ninth transistor T9 is coupled with the eighth node.

[0594] The control electrode of the eleventh transistor T11 is coupled with a fifth node N5, the first electrode of the eleventh transistor T11 is coupled with the fourth clock signal terminal CLK4, and the second electrode of the eleventh transistor T11 is coupled with the first electrode of the twelfth transistor T12.

[0595] The control electrode of the twelfth transistor T12 is coupled with the fourth clock signal terminal CLK4, and the second electrode of the twelfth transistor T12 is coupled with a fourth node N4.

[0596] The control terminal of the thirteenth transistor T13 is coupled to the first voltage signal terminal VGL, the first terminal of the thirteenth transistor T13 is coupled to the second node N2, and the second terminal of the thirteenth transistor T13 is coupled to the fifth node N5.

[0597] The control electrode of the sixteenth transistor T16 is coupled to the third node N3, the first electrode of the sixteenth transistor T16 is coupled to the first voltage signal terminal VGL, and the second electrode of the sixteenth transistor T16 is coupled to the first scan signal terminal.

[0598] The control electrode of the seventeenth transistor T17 is coupled to the fourth node N4, the first electrode of the seventeenth transistor T17 is coupled to the second voltage signal terminal VGH, and the second electrode of the seventeenth transistor T17 is coupled to the first scan signal terminal.

[0599] The control electrode of the eighteenth transistor T18 is coupled to the first node N1, the first electrode of the eighteenth transistor T18 is coupled to the second voltage signal terminal VGH, and the second electrode of the eighteenth transistor T18 is coupled to the fourth node N4.

[0600] The first plate of the first capacitor is coupled to the fifth node N5, and the second plate of the first capacitor is coupled to the second terminal of the eleventh transistor T11.

[0601] The first plate of the second capacitor is coupled to the second voltage signal terminal VGH, and the second plate of the second capacitor is coupled to the fourth node N4.

[0602] The first plate of the third capacitor is coupled to the second plate of the eighth transistor T8, and the second plate of the third capacitor is coupled to the third node N3.

[0603] like Figure 50 As shown, Figure 50 This includes the timing changes of the input signal provided by the input signal terminal, the timing changes of the first clock signal provided by the first clock signal terminal CLK1, the timing changes of the second clock signal provided by the second clock signal terminal CLK2, the timing changes of the fourth clock signal provided by the fourth clock signal terminal CLK4, and the timing changes of the first scan signal provided by the first scan signal terminal. Additionally, the first voltage signal terminal VGL continuously provides a low-level first voltage signal, and the second voltage signal terminal VGH continuously provides a high-level second voltage signal. Figure 50 The working stages include stage t1, stage t2, stage t3, and stage t4. A buffer stage is also included between adjacent working stages.

[0604] The following describes the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 as P-type transistors:

[0605] In combination Figure 49 and Figure 50 As shown in FIG. 1, in the first stage t1, the input signal provided by the input signal terminal is a low potential signal, the second clock signal provided by the second clock signal terminal CLK2 is a low potential signal, the first clock signal provided by the first clock signal terminal CLK1 is a low potential signal, and the fourth clock signal provided by the fourth clock signal terminal CLK4 is a high potential signal. Both the first clock signal and the second clock signal are low potential signals, and the second transistor T2, the third transistor T3, and the tenth transistor T10 are in the on state. The input signal is transmitted to the first node N1 via the second transistor T2 and the third transistor T3, and the potential of the first node N1 is low. The potential of the first node N1 is transmitted to the third node N3 via the tenth transistor T10, and the potential of the third node N3 is low. The fifth transistor T5, the ninth transistor T9, the sixteenth transistor T16, and the eighteenth transistor T18 are all in the on state. The eighteenth transistor T18 is in the on state, forming a path between the second clock signal terminal CLK2 and the fourth node N4, and the second clock signal as a low potential signal is transmitted to the fourth node N4, and the potential of the fourth node N4 is low. The seventeenth transistor T17 is in the on state, forming a path between the second clock signal terminal CLK2 and the first scan signal terminal, and the second clock signal as a low potential signal is transmitted to the first scan signal terminal. In addition, the sixteenth transistor T16 forms a path between the first voltage signal terminal VGL and the first scan signal terminal, and the first voltage signal is transmitted to the first scan signal terminal, and the first scan signal provided by the first scan signal terminal is a low potential signal.

[0606] In the second stage t2, the input signal provided by the input signal terminal is a low potential signal, the second clock signal provided by the second clock signal terminal CLK2 is a high potential signal, the first clock signal provided by the first clock signal terminal CLK1 is a high potential signal, and the fourth clock signal provided by the fourth clock signal terminal CLK4 changes from a low potential signal to a high potential signal.

[0607] In the stage that the fourth clock signal is a low potential signal, the first clock signal is a high potential signal, the third transistor T3 is in an off state, and the potential of the first node N1 maintains the low potential of the first stage t1; the fourth transistor T4 is in an off state. The fifth transistor T5 is in a conductive state, a path between the first clock signal end CLK1 and the second node N2 is formed, the first clock signal as a high potential signal is transmitted to the second node N2, so that the potential of the second node N2 is at a high potential. The ninth transistor T9 is in an off state, the potential of the third node N3 is at a low potential, the eighteenth transistor T18 is in a conductive state, a path between the second clock signal end CLK2 and the fourth node N4 is formed, the second clock signal as a high potential signal is transmitted to the fourth node N4, the potential of the fourth node N4 is at a high potential, the seventeenth transistor T17 is in an off state, and the sixteenth transistor T16 is in a conductive state, a path between the first voltage signal end VGL and the first scan signal end is formed, and the first voltage signal is transmitted to the first scan signal end. The first scan signal provided by the first scan signal end is a low potential signal.

[0608] In the third stage t3, the input signal provided by the input signal end is a high potential signal, the potential of the second clock signal provided by the second clock signal end CLK2 is a low potential signal, the first clock signal provided by the first clock signal end CLK1 is a low potential signal, and the fourth clock signal provided by the fourth clock signal end CLK4 is a high potential signal. The second transistor T2 and the third transistor T3 are both in a conductive state, a path between the input signal end and the first node N1 is formed, the input signal as a high potential signal is transmitted to the first node N1 via the second transistor T2 and the third transistor T3, and the potential of the first node N1 is at a high potential. The fourth transistor T4 is in a conductive state, a path between the first voltage signal end VGL and the second node N2 is formed, and the first voltage signal is transmitted to the second node N2 via the fourth transistor T4, so that the potential of the second node N2 is a low voltage. The tenth transistor T10 is in a conductive state, the high potential signal of the first node N1 is transmitted to the third node N3, and the sixteenth transistor T16 and the eighteenth transistor T18 are both in an off state. The fourth clock signal is a high potential signal, the twelfth transistor T12 is in an off state, the fourth node N4 maintains the high potential in the second stage t2, the seventeenth transistor T17 is in an off state, and the first scan signal end maintains the low potential signal in the second stage t2.

[0609] In the fourth stage t4, the input signal provided by the input signal end is a low potential signal, the second clock signal provided by the second clock signal end CLK2 is a high potential signal, the first clock signal provided by the first clock signal end CLK1 is a high potential signal, and the fourth clock signal provided by the fourth clock signal end CLK4 changes from a low potential signal to a high potential signal.

[0610] In the stage that the fourth clock signal is a low potential signal, the second transistor T2 and the third transistor T3 are both in the off state, the potential of the first node N1 maintains the high potential of the third stage t3, and the potential of the third node N3 maintains the high potential of the third stage t3. The eighteenth transistor T18, the fifth transistor T5 and the fourth transistor T4 are all in the off state, the potential of the second node N2 maintains the low potential of the third stage t3, the potential of the fifth node N5 maintains the low potential of the third stage t3, the eleventh transistor T11 and the twelfth transistor T12 are both in the on state, a path between the fourth clock signal end CLK4 and the fourth node N4 is formed, the fourth clock signal as a low potential signal is transmitted to the fourth node N4, so that the fourth node N4 is at a low potential, and the seventeenth transistor T17 is in the on state, a path between the first clock signal end CLK1 and the first scan signal end is formed, the first clock signal as a high potential signal is transmitted to the first scan signal end, and the first scan signal provided by the first scan signal end is a high potential signal.

[0611] As shown in Figure 7 , in some embodiments, the shift register is distinguished from the shift register shown in Figure 49 , including adding a first transistor T1, the first transistor T1 including an oxide transistor. The first transistor T1 is coupled in series between the second node N2 and the first clock signal end CLK1, for example, the first transistor T1 is coupled in series between the second node N2 and the fifth transistor T5, and for another example, the first transistor T1 is coupled in series between the fifth transistor T5 and the first clock signal end CLK1. In addition, the control electrode of the first transistor T1 is coupled to the fourth auxiliary clock signal end NCLK4.

[0612] The following describes the first transistor T1 as an N-type transistor:

[0613] In combination with Figure 7 and Figure 50 , in the above first stage t1, the potential of the first node N1 is at a low potential, the potential of the second node N2 is at a low potential, and the fifth transistor T5 is in the on state. The fourth auxiliary clock signal is a low potential signal, the first transistor T1 is in the off state, and the path between the second node N2 and the first clock signal end CLK1 is blocked, without affecting the first node N1 to maintain a low potential.

[0614] In the second stage t2 described above, the fourth auxiliary clock signal changes from a high-level signal to a low-level signal. During the stage when the fourth auxiliary clock signal is a high-level signal, the potential of the first node N1 is low, and the fifth transistor T5 is in the conducting state. The first transistor T1 is in the conducting state, forming a path between the first clock signal terminal CLK1 and the second node N2. The first clock signal, as a high-level signal, is transmitted to the second node N2, controlling the potential of the second node N2 to be high.

[0615] In the third stage t3 mentioned above, the potential of the first node N1 is high, the potential of the second node N2 is low, and the fifth transistor T5 is in the off state. The fourth auxiliary clock signal is a low-potential signal, the first transistor T1 is in the off state, cutting off the path between the first clock signal terminal CLK1 and the second node N2, without affecting the first node N1 maintaining a low potential.

[0616] In the fourth stage t4 described above, the fourth auxiliary clock signal changes from a high-level signal to a low-level signal. During this stage, when the fourth auxiliary clock signal is low, the potential of the first node N1 is high, the potential of the second node N2 is low, and the fifth transistor T5 is in the off state. The first transistor T1 is in the off state, cutting off the path between the first clock signal terminal CLK1 and the second node N2, preventing the high-level first clock signal terminal CLK1 from affecting the low potential of the second node N2, and maintaining the stability of the potential of the second node N2.

[0617] As described above, it can be seen that the first transistor T1 includes an oxide transistor. On the basis of the normal operation of the first control circuit 160, it can also effectively prevent the first clock signal provided by the first clock signal terminal CLK1 from affecting the potential of the second node N2, improve the stability of the potential of the second node N2, and thus improve the reliability of the shift register.

[0618] The operation of other transistors can be referred to the example above, and will not be repeated here.

[0619] like Figure 10 As shown, in some embodiments, the shift register is compared to Figure 7 The difference in the shift register shown includes that the third transistor T3 can be an oxide transistor. In this embodiment, the control electrode of the third transistor T3 is coupled to the first auxiliary clock signal terminal NCLK1.

[0620] The explanation will be based on the third transistor, T3, being an N-type transistor:

[0621] Combination Figure 10 and Figure 50As shown, in the first stage t1, the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a high-level signal, and the third transistor T3 is in the on state. The second clock signal provided by the second clock signal terminal CLK2 is a low-level signal, the second transistor T2 is on, the input signal provided by the input signal terminal is a low-level signal, and the input signal is transmitted to the first node N1 via the second transistor T2 and the third transistor T3.

[0622] In the second stage t2 mentioned above, the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a low-level signal, and the third transistor T3 is in the off state, cutting off the path between the input signal terminal and the first node N1, without affecting the maintenance of the low potential of the first node N1.

[0623] In the third stage t3 mentioned above, the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a high-level signal, and the third transistor T3 is in the on state. The second clock signal provided by the second clock signal terminal CLK2 is a low-level signal, the second transistor T2 is on, and the input signal provided by the input signal terminal is a high-level signal. The input signal is transmitted to the first node N1 via the second transistor T2 and the third transistor T3.

[0624] In the fourth stage t4 mentioned above, the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a low-level signal, and the third transistor T3 is in the off state, cutting off the path between the input signal terminal and the first node N1, preventing the input signal provided by the input signal terminal as a low-level signal from affecting the high potential of the first node N1, and maintaining the stability of the potential of the first node N1.

[0625] As described above, it can be seen that the third transistor T3 includes an oxide transistor. On the basis of the normal operation of the first input circuit 110, it can also effectively prevent the input signal provided by the input signal terminal from affecting the potential of the first node N1, improve the stability of the potential of the first node N1, and thus improve the reliability of the shift register.

[0626] The operation of other transistors can be referred to the example above, and will not be repeated here.

[0627] like Figure 9 As shown, in some embodiments, the shift register is compared to Figure 7 The difference in the shift register shown includes that the second transistor T2 can be an oxide transistor. In this embodiment, the control electrode of the second transistor T2 is coupled to the second auxiliary clock signal terminal NCLK2.

[0628] The explanation will focus on the second transistor, T2, as an N-type transistor:

[0629] like Figure 9and Figure 50 As shown, in the first stage t1, the second auxiliary clock signal provided by the second auxiliary clock signal terminal NCLK2 is a high-level signal, and the second transistor T2 is in the on state. The first clock signal provided by the first clock signal terminal CLK1 is a low-level signal, the third transistor T3 is on, the input signal provided by the input signal terminal is a low-level signal, and the input signal is transmitted to the first node N1 via the second transistor T2 and the third transistor T3.

[0630] In the second stage t2 mentioned above, the second auxiliary clock signal provided by the second auxiliary clock signal terminal NCLK2 is a low-level signal, and the second transistor T2 is in the off state, cutting off the path between the input signal terminal and the first node N1, without affecting the maintenance of the low potential of the first node N1.

[0631] In the third stage t3 mentioned above, the second auxiliary clock signal provided by the second auxiliary clock signal terminal NCLK2 is a high-level signal, and the second transistor T3 is in the on state. The first clock signal provided by the first clock signal terminal CLK1 is a low-level signal, the third transistor T3 is on, and the input signal provided by the input signal terminal is a high-level signal. The input signal is transmitted to the first node N1 via the second transistor T2 and the third transistor T3.

[0632] In the fourth stage t4 mentioned above, the second auxiliary clock signal provided by the second auxiliary clock signal terminal NCLK2 is a low-level signal, and the second transistor T2 is in the off state, cutting off the path between the input signal terminal and the first node N1, preventing the input signal provided by the input signal terminal as a low-level signal from affecting the high potential of the first node N1, and maintaining the stability of the potential of the first node N1.

[0633] As described above, it can be seen that the second transistor T2 includes an oxide transistor. On the basis of the normal operation of the first input circuit 110, it can also effectively prevent the input signal provided by the input signal terminal from affecting the potential of the first node N1, improve the stability of the potential of the first node N1, and thus improve the reliability of the shift register.

[0634] The operation of other transistors can be referred to the example above, and will not be repeated here.

[0635] like Figure 51 As shown, in some embodiments, the shift register is compared to Figure 7 The difference in the shift register shown includes that the fourth transistor T4 is an oxide transistor. In this embodiment, the control electrode of the fourth transistor T4 is coupled to the first auxiliary clock signal terminal NCLK1.

[0636] The explanation will focus on the fourth transistor, T4, as an N-type transistor:

[0637] CombinationFigure 51 and Figure 50 As shown in the above first stage t1, the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a high potential signal, the fourth transistor T4 is in a conductive state, and the first voltage signal provided by the first voltage signal terminal VGL is transmitted to the second node N2 via the fourth transistor T4.

[0638] In the above second stage t2, the potential of the first node N1 is at a low potential, the fifth transistor T5 is in a conductive state, and the first clock signal terminal CLK1 at a high potential is transmitted to the second node N2. The first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a low potential signal, the fourth transistor T4 is in a cut-off state, and the path between the first voltage signal terminal VGL and the second node N2 is blocked, preventing the low potential signal of the first voltage signal from affecting the high potential of the second node N2, thereby improving the stability of the potential of the second node N2.

[0639] In the above third stage t3, the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a high potential signal, the fourth transistor T4 is in a conductive state, and the first voltage signal provided by the first voltage signal terminal VGL is transmitted to the second node N2 via the fourth transistor T4.

[0640] In the above fourth stage t4, the second node N2 is at a low potential, the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a low potential signal, and the fourth transistor T4 is in a cut-off state, blocking the path between the first voltage signal terminal VGL and the second node N2, without affecting the second node N2 to maintain a low potential.

[0641] As described above, it can be seen that the fourth transistor T4 includes an oxide transistor, which can effectively avoid the influence of the first voltage signal provided by the first voltage signal terminal VGL on the potential of the second node N2 based on the normal operation of the second input circuit 130, thereby improving the stability of the potential of the second node N2 and further improving the reliability of the shift register.

[0642] The working processes of other transistors can be referred to the above example description, which will not be described here.

[0643] As shown in the above first stage t1, the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a high potential signal, the fourth transistor T4 is in a conductive state, and the first voltage signal provided by the first voltage signal terminal VGL is transmitted to the second node N2 via the fourth transistor T4. Figure 52 As shown in the above first stage t1, the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a high potential signal, the fourth transistor T4 is in a conductive state, and the first voltage signal provided by the first voltage signal terminal VGL is transmitted to the second node N2 via the fourth transistor T4. Figure 7 As shown in the above first stage t1, the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a high potential signal, the fourth transistor T4 is in a conductive state, and the first voltage signal provided by the first voltage signal terminal VGL is transmitted to the second node N2 via the fourth transistor T4.

[0644] The tenth transistor T10 is an N-type transistor, and the control electrode of the tenth transistor T10 is coupled to the second voltage signal terminal VGH.

[0645] As shown in the above first stage t1, the first auxiliary clock signal provided by the first auxiliary clock signal terminal NCLK1 is a high potential signal, the fourth transistor T4 is in a conductive state, and the first voltage signal provided by the first voltage signal terminal VGL is transmitted to the second node N2 via the fourth transistor T4. Figure 52and Figure 50 As shown, in the first stage t1, the potential of the first node N1 is low. The second voltage signal provided by the second voltage signal terminal VGH is a high potential signal, the tenth transistor T10 is in the on state, and the potential of the first node N1 is transmitted to the third node N3 through the tenth transistor T10.

[0646] In the second stage t2 described above, the potential of the first node N1 is low. Due to the bootstrap effect of the third capacitor, the potential of the third node N3 is low (2VGL-VthN3-VGH). The second voltage signal provided by the second voltage signal terminal VGH is a high potential signal, and the tenth transistor T10 is in the off state, cutting off the path between the first node N1 and the third node N3 to maintain the low potential of the third node N3.

[0647] In the third stage t3 mentioned above, the potential of the first node N1 is at a high potential. The second voltage signal provided by the second voltage signal terminal VGH is a high potential signal, the tenth transistor T10 is in the on state, and the potential of the first node N1 is transmitted to the third node N3 through the tenth transistor T10.

[0648] In the fourth stage t4 mentioned above, the potential of the first node N1 is high. The second voltage signal provided by the second voltage signal terminal VGH is also high, and the tenth transistor T10 is in the on state. The potential of the first node N1 is transmitted to the third node N3 through the tenth transistor T10.

[0649] As can be seen from the above, by using the tenth transistor T10 as an oxide transistor and coupling the control terminal of the tenth transistor T10 to the second voltage signal terminal VGH, it is possible to prevent the potential of the first node N1 from affecting the potential of the third node N3 when the tenth transistor T10 is in the off state, based on the normal operation of the first voltage regulator circuit 180. This improves the stability of the potential of the third node N3 and thus improves the reliability of the shift register.

[0650] The operation of other transistors can be referred to the example above, and will not be repeated here.

[0651] like Figure 53 As shown, in some embodiments, the shift register is compared to Figure 7 The difference in the shift register shown includes that the twelfth transistor T12 is an oxide transistor. In this embodiment, the control terminal of the twelfth transistor T12 is coupled to the fourth auxiliary clock signal terminal NCLK4.

[0652] The following explanation uses the twelfth transistor, T12, as an N-type transistor:

[0653] like Figure 53 and Figure 50As shown, in the first stage t1, the potential of the second node N2 is at low potential, the thirteenth transistor T13 is turned on, the potential of the fifth node N5 is at low potential, and the eleventh transistor T11 is in the on state. The fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal NCLK4 is a low potential signal, and the twelfth transistor T12 is in t...

Claims

1. A shift register, comprising: The first input circuit is coupled to the input signal terminal, the first control signal terminal, and the first node; The first input circuit is configured to transmit the input signal provided by the input signal terminal to the first node under the control of the first control signal terminal; A first output circuit is coupled to a first output signal terminal, the first node, and a first scan signal terminal; the first output circuit is configured to transmit a first output signal provided by the first output signal terminal to the first scan signal terminal under the control of the potential of the first node. The second input circuit is coupled to the first voltage signal terminal, the second control signal terminal, and the second node; the second input circuit is configured to transmit the first voltage signal provided by the first voltage signal terminal to the second node under the control of the second control signal provided by the second control signal terminal. The second output circuit is coupled to the second output signal terminal, the second node, and the first scan signal terminal; the second output circuit is configured to transmit the second output signal provided by the second output signal terminal to the first scan signal terminal under the control of the potential of the second node. as well as, At least one functional circuit is coupled to a functional input terminal, a functional output terminal, and a functional control terminal; the functional circuit is configured to, under the control of a functional control signal provided by the functional control terminal, disconnect the path between the functional input terminal and the functional output terminal to maintain the potential of the functional output terminal; The second control signal terminal includes a first auxiliary clock signal terminal, the second input circuit is multiplexed into a functional circuit, and the second input circuit is further configured to, under the control of the first auxiliary clock signal provided by the first auxiliary clock signal terminal, disconnect the path between the first voltage signal terminal and the second node in order to maintain the potential of the second node; The functional output terminal includes one of the circuit nodes.

2. The shift register according to claim 1, wherein, The functional circuit includes an oxide transistor; The control electrode of the oxide transistor is coupled to the functional control terminal, the first electrode of the oxide transistor is coupled to the functional input terminal, and the second electrode of the oxide transistor is coupled to the functional output terminal.

3. The shift register according to claim 2, wherein, The oxide transistor includes: a first gate pattern, an active layer, and a second gate pattern sequentially stacked on one side of a substrate, wherein the active layer is made of an oxide semiconductor material; The first gate pattern and the second gate pattern constitute the control electrode of the oxide transistor.

4. The shift register according to claim 3, wherein, The oxide transistor further includes source and drain metal patterns; wherein the same source and drain metal pattern is coupled to the first gate pattern and the second gate pattern, respectively.

5. The shift register according to claim 1, wherein, The first control signal terminal includes a first clock signal terminal; The first input circuit includes a second transistor; the control electrode of the second transistor is coupled to the first clock signal terminal, the first electrode of the second transistor is coupled to the input signal terminal, and the second electrode of the second transistor is coupled to the first node.

6. The shift register according to claim 1, wherein, The first control signal terminal includes a first auxiliary clock signal terminal; The first input circuit is multiplexed into a single functional circuit. The first input circuit is further configured to, under the control of a first auxiliary clock signal provided by the first auxiliary clock signal terminal, disconnect the path between the input signal terminal and the first node in order to maintain the potential of the first node.

7. The shift register according to claim 6, wherein, The first input circuit includes a second transistor, which is an oxide transistor; the first auxiliary clock signal terminal serves as a functional control terminal. The control electrode of the second transistor is coupled to the first auxiliary clock signal terminal, the first electrode of the second transistor is coupled to the input signal terminal, and the second electrode of the second transistor is coupled to the first node.

8. The shift register according to claim 1, wherein, The first control signal terminal includes a third control signal terminal and a fourth control signal terminal; The first input circuit is further configured to transmit the input signal to the first node under the control of the third control signal provided at the third control signal terminal and the fourth control signal provided at the fourth control signal terminal; The first input circuit includes a functional circuit, which is connected in series between the input signal terminal and the first node. The third control signal terminal serves as a functional control terminal; the functional circuit is configured to, under the control of the third control signal provided by the third control signal terminal, disconnect the path between the input signal terminal and the first node to maintain the potential of the first node; and / or, The fourth control signal terminal serves as a functional control terminal; the functional circuit is configured to, under the control of the fourth control signal provided by the fourth control signal terminal, disconnect the path between the input signal terminal and the first node in order to maintain the potential of the first node.

9. The shift register according to claim 8, wherein, The third control signal terminal includes a second clock signal terminal, and the fourth control signal terminal includes a first auxiliary clock signal terminal; The first input circuit includes a second transistor and a third transistor, the functional circuit includes the third transistor, and the third transistor includes an oxide transistor; the first auxiliary clock signal terminal serves as a functional control terminal. The control electrode of the second transistor is coupled to the second clock signal terminal, the first electrode of the second transistor is coupled to the input signal terminal, the second electrode of the second transistor is coupled to the first electrode of the third transistor, the control electrode of the third transistor is coupled to the first auxiliary clock signal terminal, and the second electrode of the third transistor is coupled to the first node; or, The third control signal terminal includes a second auxiliary clock signal terminal, and the fourth control signal terminal includes a first clock signal terminal; The first input circuit includes a second transistor and a third transistor, the functional circuit includes the second transistor, and the second transistor includes an oxide transistor; the second auxiliary clock signal terminal serves as a functional control terminal; The control electrode of the second transistor is coupled to the second auxiliary clock signal terminal, the first electrode of the second transistor is coupled to the input signal terminal, the second electrode of the second transistor is coupled to the first electrode of the third transistor, the control electrode of the third transistor is coupled to the first clock signal terminal, and the second electrode of the third transistor is coupled to the first node.

10. The shift register according to claim 1, wherein, The second control signal terminal includes a first clock signal terminal; The second input circuit includes a fourth transistor, the control terminal of which is coupled to the first clock signal terminal, the first terminal of which is coupled to the first voltage signal terminal, and the second terminal of which is coupled to the second node.

11. The shift register according to claim 1, wherein, The second input circuit includes a fourth transistor, which is an oxide transistor; the first auxiliary clock signal terminal serves as a functional input terminal. The control electrode of the fourth transistor is coupled to the first auxiliary clock signal terminal, the first electrode of the fourth transistor is coupled to the first voltage signal terminal, and the second electrode of the fourth transistor is coupled to the second node.

12. The shift register according to claim 1, further comprising: First control circuit; The first control circuit is coupled to the fifth control signal terminal, the second node, and the third output signal terminal respectively; the first control circuit is configured to transmit the third output signal provided by the third output signal terminal to the second node under the control of the fifth control signal provided by the fifth control signal terminal.

13. The shift register according to claim 12, wherein, The first control circuit includes a fifth transistor; the fifth control signal terminal includes a first node; the third output signal terminal includes a first clock signal terminal or a second voltage signal terminal. The control electrode of the fifth transistor is coupled to the first node, the first electrode of the fifth transistor is coupled to the third output signal terminal, and the second electrode of the fifth transistor is coupled to the second node.

14. The shift register according to claim 13, wherein, A functional circuit is connected in series between the second node and the third output signal terminal; the functional circuit is also coupled to a third clock signal terminal; the third output signal terminal includes a first clock signal terminal; The functional circuit is configured to, under the control of the third clock signal provided by the third clock signal terminal, disconnect the path between the second node and the first clock signal terminal in order to maintain the potential of the second node.

15. The shift register according to claim 14, wherein, The functional circuit includes a first transistor, which is an oxide transistor; the third clock signal terminal serves as a functional control terminal. The control terminal of the first transistor is coupled to the third clock signal terminal, the first terminal of the first transistor is coupled to the second terminal of the fifth transistor, the second terminal of the first transistor is coupled to the second node, and the second terminal of the fifth transistor is coupled to the second node through the first transistor; or, The control electrode of the first transistor is coupled to the third clock signal terminal, the first electrode of the first transistor is coupled to the first clock signal terminal, the second electrode of the first transistor is coupled to the first electrode of the fifth transistor, and the first electrode of the fifth transistor is coupled to the first clock signal terminal through the first transistor.

16. The shift register according to claim 15, wherein, The second input circuit includes a fourth transistor configured to be coupled to a first voltage signal line; On the plane where the shift register is located, the first transistor is located on the side of the fourth transistor away from the first voltage signal line.

17. The shift register according to claim 16, wherein, The first transistor includes: a first gate pattern, an active layer, and a second gate pattern sequentially stacked on one side of a substrate, wherein the active layer is made of an oxide semiconductor material; the first gate pattern and the second gate pattern constitute the control electrode of the first transistor; The first gate pattern and the second gate pattern of the first transistor are located on the side of the third clock signal terminal closer to the substrate; The first gate pattern and the second gate pattern of the first transistor are respectively coupled to the third clock signal terminal.

18. The shift register according to claim 15, wherein, The first input circuit includes a third transistor configured to be coupled to a first clock signal line; On the plane where the shift register is located, the first transistor is located on the side of the third transistor away from the first clock signal line.

19. The shift register according to claim 1, further comprising: Third output circuit and fourth output circuit; The third output circuit is coupled to the first voltage signal terminal, the first node, and the second scan signal terminal. The third output circuit is configured to transmit the first voltage signal provided by the first voltage signal terminal to the second scan signal terminal under the control of the potential of the first node. The fourth output circuit is coupled to the second voltage signal terminal, the first node, and the second scan signal terminal; the fourth output circuit is configured to transmit the second voltage signal provided by the second voltage signal terminal to the second scan signal terminal under the control of the potential of the first node.

20. The shift register according to claim 19, wherein, The third output circuit is multiplexed as a functional circuit; the third output circuit is also configured to, under the control of the potential of the first node, disconnect the path between the first voltage signal terminal and the second scan signal terminal in order to maintain the potential of the second scan signal terminal.

21. The shift register according to claim 20, wherein, The third output circuit includes a sixth transistor, which is an oxide transistor, and the first node serves as a function control terminal; the fourth output circuit includes a seventh transistor. The control electrode of the sixth transistor is coupled to the first node, the first electrode of the sixth transistor is coupled to the first voltage signal terminal, and the second electrode of the sixth transistor is coupled to the second scan signal terminal. The control electrode of the seventh transistor is coupled to the first node, the first electrode of the seventh transistor is coupled to the second voltage signal terminal, and the second electrode of the seventh transistor is coupled to the second scan signal terminal.

22. The shift register according to claim 20 or 21 further includes a first control circuit, the first control circuit being coupled to a fifth control signal terminal, the second node and the third output signal terminal respectively; the first control circuit is configured to transmit a third output signal provided by the third output signal terminal to the second node under the control of a fifth control signal provided by the fifth control signal terminal. The third output signal terminal includes a first clock signal terminal; the fifth control signal terminal includes a second scan signal terminal; the first control circuit is multiplexed into a single functional circuit. The first control circuit is configured to, under the control of the second scan signal provided by the second scan signal terminal, disconnect the path between the first clock signal terminal and the second node in order to maintain the potential of the second node.

23. The shift register according to claim 22, wherein, The shift register is the shift register as described in claim 13; the first control circuit includes a fifth transistor, the fifth transistor including an oxide transistor; the second scan signal terminal serves as a function control terminal; The control electrode of the fifth transistor is coupled to the second scan signal terminal, the first electrode of the fifth transistor is coupled to the first clock signal terminal, and the second electrode of the fifth transistor is coupled to the second node.

24. The shift register according to claim 1, further comprising: Noise reduction circuit; The noise reduction circuit is coupled to the second voltage signal terminal, the sixth control signal terminal, the second node, and the first node, respectively. The noise reduction circuit is configured to transmit the second voltage signal provided by the second voltage signal terminal to the first node under the control of the potential of the second node and the sixth control signal provided by the sixth control signal terminal.

25. The shift register according to claim 24, wherein, The noise reduction circuit includes an eighth transistor and a ninth transistor; the control electrode of the eighth transistor is coupled to the second node, the first electrode of the eighth transistor is coupled to the second voltage signal terminal, the second electrode of the eighth transistor is coupled to the first electrode of the ninth transistor, the control electrode of the ninth transistor is coupled to the sixth control signal terminal, and the second electrode of the ninth transistor is coupled to the first node.

26. The shift register according to claim 25, wherein, The sixth control signal terminal includes a fourth clock signal terminal; A functional circuit is connected in series between the second voltage signal terminal and the first node, and the functional circuit is also coupled to the first node; The functional circuit is configured to, under the control of the potential of the first node, disconnect the path between the second voltage signal terminal and the first node in order to maintain the potential of the first node.

27. The shift register according to claim 26, wherein, The functional circuit includes a first transistor, which is an oxide transistor; the first node serves as a control terminal for the function. The control electrode of the first transistor is coupled to the first node, the first electrode of the first transistor is coupled to the second voltage signal terminal, the second electrode within the first transistor is coupled to the first electrode of the eighth transistor, and the first electrode of the eighth transistor is coupled to the second voltage signal terminal through the first transistor. or, The control electrode of the first transistor is coupled to the first node; the first electrode of the first transistor is coupled to the second electrode of the eighth transistor; the second electrode within the first transistor is coupled to the first electrode of the ninth transistor; the second electrode of the eighth transistor is coupled to the first electrode of the ninth transistor through the first transistor; or... The control electrode of the first transistor is coupled to the first node, the first electrode of the first transistor is coupled to the second electrode of the ninth transistor, the second electrode of the first transistor is coupled to the first node, and the second electrode of the ninth transistor is coupled to the first node through the first transistor.

28. The shift register according to claim 24, wherein, The sixth control signal terminal includes a fourth auxiliary clock signal terminal; The noise reduction circuit includes a functional circuit; the functional circuit is configured to, under the control of the fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal, disconnect the path between the first node and the second voltage signal terminal in order to maintain the potential of the first node.

29. The shift register according to claim 28, wherein, The noise reduction circuit includes an eighth transistor and a ninth transistor; the functional circuit includes a ninth transistor, which is an oxide transistor; the fourth auxiliary clock signal terminal serves as a functional control terminal. The control electrode of the eighth transistor is coupled to the second node, the first electrode of the eighth transistor is coupled to the second voltage signal terminal, the second electrode of the eighth transistor is coupled to the first electrode of the ninth transistor, the control electrode of the ninth transistor is coupled to the fourth auxiliary clock signal terminal, and the second electrode of the ninth transistor is coupled to the first node.

30. The shift register of claim 25 or 29, further comprising a first control circuit including a first transistor; the eighth transistor being configured to be coupled to a second voltage signal line; On the plane where the shift register is located, the first transistor is located on the side of the second voltage signal line away from the eighth transistor.

31. The shift register according to claim 30, wherein, On the plane where the shift register is located, the first transistor is located between the first voltage signal terminal and the second voltage signal terminal.

32. The shift register according to claim 1, further comprising: First voltage regulator circuit; The circuit node also includes a third node; The first voltage regulator circuit is coupled to the first node, the third node, and the eighth control signal terminal respectively. The first output circuit is coupled to the third node and is coupled to the first node through the first voltage regulator circuit. The first voltage regulator circuit is configured to turn on the first node and the third node under the control of the potential of the third node and the eighth control signal provided by the eighth control signal terminal. The first output circuit is configured to transmit the first output signal provided by the first output signal terminal to the first scan signal terminal under the control of the potential of the third node.

33. The shift register according to claim 32, wherein, The first voltage regulator circuit includes a tenth transistor; the eighth control signal terminal includes a first voltage signal terminal; The control electrode of the tenth transistor is coupled to the first voltage signal terminal, the first electrode of the tenth transistor is coupled to the first node, and the second electrode of the tenth transistor is coupled to the third node.

34. The shift register according to claim 32, wherein, The eighth control signal terminal includes a second voltage signal terminal; The first voltage regulator circuit is multiplexed as a functional circuit; the first voltage regulator circuit is also configured to, under the control of the potential of the third node and the potential of the second voltage signal provided by the second voltage signal terminal, disconnect the path between the first node and the third node in order to maintain the potential of the third node.

35. The shift register according to claim 34, wherein, The functional circuit includes a tenth transistor, which is an oxide transistor; the second voltage signal terminal serves as a functional control terminal. The control electrode of the tenth transistor is coupled to the second voltage signal terminal, the first electrode of the tenth transistor is coupled to the first node, and the second electrode of the tenth transistor is coupled to the third node.

36. The shift register according to claim 1, further comprising: The second control circuit; the circuit node also includes a fourth node; The second control circuit is coupled to the second node, the fourth node, the fourth clock signal terminal, and the ninth control signal terminal respectively. The second output circuit is coupled to the fourth node and is coupled to the second node through the second control circuit. The second control circuit is configured to transmit the fourth clock signal provided by the fourth clock signal terminal to the fourth node under the control of the potential of the second node and the ninth control signal provided by the ninth control signal terminal. The second output circuit is configured to, under the control of the fourth node, transmit the second output signal provided by the second output signal terminal to the first scan signal terminal.

37. The shift register according to claim 36, wherein, The second control circuit includes an eleventh transistor, a twelfth transistor, and a first capacitor; The control electrode of the eleventh transistor is coupled to the second node, the first electrode of the eleventh transistor is coupled to the fourth clock signal terminal, the second electrode of the eleventh transistor is coupled to the first electrode of the twelfth transistor, the control electrode of the twelfth transistor is coupled to the ninth control signal terminal, the second electrode of the twelfth transistor is coupled to the fourth node, the first plate of the first capacitor is coupled to the second node, and the second plate of the first capacitor is coupled to the first electrode of the twelfth transistor.

38. The shift register according to claim 36, wherein, The ninth control signal terminal includes a fourth auxiliary clock signal terminal; The second control circuit includes a functional circuit; the functional circuit is configured to, under the control of the fourth auxiliary clock signal provided by the fourth auxiliary clock signal terminal, disconnect the path between the fourth clock signal terminal and the fourth node in order to maintain the potential of the fourth node.

39. The shift register according to claim 38, wherein, The second control circuit includes an eleventh transistor, a twelfth transistor, and a first capacitor; the functional circuit includes the twelfth transistor, which is an oxide transistor; the fourth auxiliary clock signal terminal serves as a functional control terminal. The control electrode of the eleventh transistor is coupled to the second node, the first electrode of the eleventh transistor is coupled to the fourth clock signal terminal, the second electrode of the eleventh transistor is coupled to the first electrode of the twelfth transistor, the control electrode of the twelfth transistor is coupled to the fourth auxiliary clock signal terminal, the second electrode of the twelfth transistor is coupled to the fourth node, the first plate of the first capacitor is coupled to the second node, and the second plate of the first capacitor is coupled to the first electrode of the twelfth transistor.

40. The shift register according to claim 37, wherein, The first input circuit includes a second transistor; the shift register further includes a first control circuit, which includes a first transistor. On the plane where the shift register is located, the first transistor is situated between the second transistor and the first capacitor.

41. The shift register according to any one of claims 36 to 40, further comprising: The second voltage regulator circuit; the circuit node also includes a fifth node; The second voltage regulator circuit is coupled to the tenth control signal terminal, the second node, and the fifth node. The second control circuit is coupled to the fifth node and is also coupled to the second node through the second voltage regulator circuit. The second voltage regulator circuit is configured to form a path between the second node and the fifth node under the control of the potential of the fifth node and the tenth control signal provided by the tenth control signal terminal. The second control circuit is configured to transmit the fourth clock signal provided by the fourth clock signal terminal to the fourth node under the control of the potential of the fifth node and the ninth control signal provided by the ninth control signal terminal.

42. The shift register according to claim 41, wherein, The second voltage regulator circuit includes a thirteenth transistor; The control electrode of the thirteenth transistor is coupled to the tenth control signal terminal, the first electrode of the thirteenth transistor is coupled to the second node, and the second electrode of the thirteenth transistor is coupled to the fifth node.

43. The shift register according to claim 41, wherein, The tenth control signal terminal includes a second voltage signal terminal; The second voltage regulator circuit is multiplexed as a functional circuit; the second voltage regulator circuit is also configured to, under the control of the potential of the fifth node and the second voltage signal provided by the second voltage signal terminal, disconnect the path between the second node and the fifth node in order to maintain the potential of the fifth node.

44. The shift register according to claim 43, wherein, The functional circuit includes a thirteenth transistor, which is an oxide transistor; the second voltage signal terminal serves as a control terminal for the function. The control electrode of the thirteenth transistor is coupled to the second voltage signal terminal, the first electrode of the thirteenth transistor is coupled to the second node, and the second electrode of the thirteenth transistor is coupled to the fifth node.

45. The shift register according to claim 1, further comprising: First voltage regulator circuit; The circuit nodes include the third node, the sixth node, and the seventh node; The first control signal terminal includes a first clock signal terminal and an eleventh control signal terminal; the first input circuit is coupled to the input signal terminal, the first node, the sixth node, and the eleventh control signal terminal; the first input circuit is configured to transmit the input signal provided by the input signal terminal to the first node under the control of the first clock signal provided by the first clock signal terminal; the first input circuit is further configured to transmit the input signal provided by the input signal terminal to the sixth node under the control of the eleventh control signal provided by the eleventh control signal terminal. The first voltage regulator circuit is coupled to the third node, the sixth node, the seventh node, the first voltage signal terminal, and the twelfth control signal terminal; the first voltage regulator circuit is configured to form a path between the first node and the third node under the control of the potential of the third node and the first voltage signal provided by the first voltage signal terminal; the first voltage regulator circuit is further configured to form a path between the sixth node and the seventh node under the control of the potential of the seventh node and the twelfth control signal provided by the twelfth control signal terminal.

46. ​​The shift register according to claim 45, wherein, The first input circuit includes a second transistor and a third transistor; the control electrode of the second transistor is coupled to the first clock signal terminal, the first electrode of the second transistor is coupled to the input signal terminal, the second electrode of the second transistor is coupled to the first node, the control electrode of the third transistor is coupled to the eleventh control signal terminal, the first electrode of the third transistor is coupled to the input signal terminal, and the second electrode of the third transistor is coupled to the sixth node. The first voltage regulator circuit includes a tenth transistor and a fourteenth transistor; the control electrode of the tenth transistor is coupled to the first voltage signal terminal, the first electrode of the tenth transistor is coupled to the first node, the second electrode of the tenth transistor is coupled to the third node, the control electrode of the fourteenth transistor is coupled to the twelfth control signal terminal, the first electrode of the fourteenth transistor is coupled to the sixth node, and the second electrode of the fourteenth transistor is coupled to the seventh node.

47. The shift register according to claim 45, wherein, The eleventh control signal terminal includes a first auxiliary clock signal terminal; The first input circuit includes a functional circuit; the functional circuit is configured to, under the control of a first auxiliary clock signal provided by the first auxiliary clock signal terminal, disconnect the path between the input signal terminal and the sixth node in order to maintain the potential of the sixth node.

48. The shift register according to claim 47, wherein, The first input circuit includes a second transistor and a third transistor; the functional circuit includes a third transistor, which is an oxide transistor; the first auxiliary clock signal terminal serves as a functional control terminal. The control electrode of the second transistor is coupled to the first clock signal terminal, the first electrode of the second transistor is coupled to the input signal terminal, the second electrode of the second transistor is coupled to the first node, the control electrode of the third transistor is coupled to the first auxiliary clock signal terminal, the first electrode of the third transistor is coupled to the input signal terminal, and the second electrode of the third transistor is coupled to the sixth node.

49. The shift register according to claim 45, wherein, The twelfth control signal terminal includes a second voltage signal terminal; The first voltage regulator circuit includes a functional circuit; the functional circuit is configured to, under the control of a second voltage signal provided by the second voltage signal terminal, disconnect the path between the sixth node and the seventh node in order to maintain the potential of the seventh node.

50. The shift register according to claim 49, wherein, The first voltage regulator circuit includes a tenth transistor and a fourteenth transistor; the functional circuit includes a fourteenth transistor, which is an oxide transistor; the second voltage signal terminal serves as a control terminal for the function. The control electrode of the tenth transistor is coupled to the first voltage signal terminal, the first electrode of the tenth transistor is coupled to the first node, the second electrode of the tenth transistor is coupled to the third node, the control electrode of the fourteenth transistor is coupled to the second voltage signal terminal, the first electrode of the fourteenth transistor is coupled to the sixth node, and the second electrode of the fourteenth transistor is coupled to the seventh node.

51. The shift register according to any one of claims 45 to 50, further comprising: Third voltage regulator circuit; The third voltage regulator circuit is coupled to the seventh node and the third node respectively; The third voltage regulator circuit is configured to connect the seventh node and the third node under the control of the potential of the seventh node.

52. The shift register according to claim 51, wherein, The third voltage regulator circuit includes a fifteenth transistor; The control electrode of the fifteenth transistor is coupled to the seventh node, the first electrode of the fifteenth transistor is coupled to the seventh node, and the second electrode of the fifteenth transistor is coupled to the third node.

53. The shift register according to claim 1, wherein, The first output signal terminal includes a fourth clock signal terminal or a first voltage signal terminal; The first output circuit includes a sixteenth transistor; The control electrode of the sixteenth transistor is coupled to the first node, the first electrode of the sixteenth transistor is coupled to the first output signal terminal, and the second electrode of the sixteenth transistor is coupled to the first scan signal terminal. The second output signal terminal includes a second clock signal terminal or a second voltage signal terminal; The second output circuit includes a seventeenth transistor and a second capacitor; The control electrode of the seventeenth transistor is coupled to the second node, the first electrode of the seventeenth transistor is coupled to the second output signal terminal, and the second electrode of the seventeenth transistor is coupled to the first scan signal terminal; The first plate of the second capacitor is coupled to the second output signal terminal, and the second plate of the second capacitor is coupled to the second node.

54. The shift register according to claim 53 further includes a first control circuit, the first control circuit including a first transistor; the first transistor includes a first gate pattern, an active layer and a second gate pattern sequentially stacked on one side of a substrate, the active layer being made of an oxide semiconductor material; The second gate pattern in the first transistor is disposed on the same layer as the control electrode of the seventeenth transistor.

55. A scanning drive circuit, comprising: First voltage signal line; An N-stage cascaded shift register arranged sequentially along the extension direction of the first voltage signal line; the shift register is any one of claims 1 to 54.

56. The scanning drive circuit according to claim 55, wherein, Two adjacent shift registers are symmetrically arranged along the extension direction perpendicular to the first voltage signal line; The two oxide semiconductor structures belonging to the two adjacent shift registers are integrally formed structures.

57. A display device, comprising a display area and a peripheral area located on at least one side of the display area; Multiple sub-pixels located within the display area; The scan driving circuit as described in claim 55 or 56 is located within the peripheral area, and the scan driving circuit is coupled to the plurality of sub-pixels.

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