Display substrate, preparation method thereof and display device

Abstract

A display substrate, a manufacturing method thereof and a display device, the display substrate comprising: a plurality of sub-pixels, a first sub-pixel comprising a first pixel circuit and a first effective light-emitting area; a second sub-pixel comprising a second pixel circuit and a second effective light-emitting area; a first light-shielding layer between the first pixel circuit and a first substrate, a first light-shielding layer and the first pixel circuit being at least partially overlapped in orthographic projection on the first substrate; a second light-shielding layer between the second pixel circuit and the first substrate, a second light-shielding layer and the second pixel circuit being at least partially overlapped in orthographic projection on the first substrate; the area of the first effective light-emitting area being greater than the area of the second effective light-emitting area, the area of the first light-shielding layer being greater than the area of the second light-shielding layer, adjusting the aperture ratio of the first sub-pixel and the second sub-pixel can make the whole process simple.

Description

[0001] This application is a divisional application of application number 202210823111.7, filed on July 14, 2022. Technical Field

[0002] Embodiments of this disclosure relate to a display substrate, a method for fabricating the same, and a display device. Background Technology

[0003] Display devices include thin-film transistor liquid crystal displays (TFT-LCDs) and active-matrix organic light-emitting diode (AMOLED) displays. AMOLED displays offer advantages such as long lifespan, high brightness, high contrast, and wide color gamut. Besides being thinner and lighter than conventional liquid crystal displays, AMOLED displays, which use AMOLEDs as their light-emitting elements, also feature fast response times, wide viewing angles, and low-voltage operation. Therefore, AMOLED displays are widely used in cellular phones, portable information terminals, televisions, and monitors.

[0004] Organic light-emitting diode (OLED) display devices mainly consist of a cathode, an emissive layer, and an anode. In an active matrix OLED display device, each sub-pixel has a switching transistor and a driving transistor. By adjusting the switching transistor and the driving transistor, the emissive layer in the OLED display device emits light. Summary of the Invention

[0005] This disclosure provides at least one embodiment of a display substrate, a method for manufacturing the same, and a display device. The display substrate can adjust its aperture ratio by making the area of ​​a first effective light-emitting region larger than the area of ​​a second effective light-emitting region and the area of ​​a first light-shielding layer larger than the area of ​​a second light-shielding layer.

[0006] At least one embodiment of this disclosure provides a display substrate, the display substrate comprising: a first substrate; a plurality of sub-pixels disposed on the first substrate, the plurality of sub-pixels including a first sub-pixel and a second sub-pixel; wherein, the first sub-pixel includes a first pixel circuit and a first effective light-emitting region; the second sub-pixel includes a second pixel circuit and a second effective light-emitting region; a first light-shielding layer is disposed between the first pixel circuit and the first substrate, and the orthographic projection of the first light-shielding layer on the first substrate and the orthographic projection of the first pixel circuit on the first substrate at least partially overlap; a second light-shielding layer is disposed between the second pixel circuit and the first substrate, and the orthographic projection of the second light-shielding layer on the first substrate and the orthographic projection of the second pixel circuit on the first substrate at least partially overlap; the area of ​​the first effective light-emitting region is larger than the area of ​​the second effective light-emitting region, and the area of ​​the first light-shielding layer is larger than the area of ​​the second light-shielding layer.

[0007] For example, in the display substrate provided in at least one embodiment of this disclosure, the wavelength of the light emitted from the first effective light-emitting region is greater than the wavelength of the light emitted from the second effective light-emitting region, the ratio of the area of ​​the first light-shielding layer to the area of ​​the first sub-pixel is a, the ratio of the area of ​​the second light-shielding layer to the area of ​​the second sub-pixel is b, and the range of the ratio M1 of a and b is 1.020 to 1.120.

[0008] For example, in the display substrate provided in at least one embodiment of this disclosure, the aperture ratio of the first sub-pixel is n1(1-a), and the aperture ratio of the second sub-pixel is n2(1-b); (1-a) / (1-b)=(n2 / n1)M2*K1*K2, where K1 is the ratio of the initial brightness of the second sub-pixel to the initial brightness of the first sub-pixel, K2 is the ratio of the lifetime of the second sub-pixel to the lifetime of the first sub-pixel, n1 is the ratio of the area of ​​the aperture region in the first sub-pixel to the area of ​​the portion of the first sub-pixel excluding the area blocked by the first light-shielding layer, n2 is the ratio of the area of ​​the aperture region in the second sub-pixel to the area of ​​the portion of the second sub-pixel excluding the area blocked by the second light-shielding layer, the value range of (n2 / n1)M2 is 1.000~1.130, and the value range of (1-a) / (1-b) is 0.877~0.997.

[0009] For example, in at least one embodiment of the display substrate provided in this disclosure, the plurality of sub-pixels further includes a third sub-pixel; the third sub-pixel includes a third pixel circuit and a third effective light-emitting area; a third light-shielding layer is disposed between the third pixel circuit and the first substrate, and the orthographic projection of the third light-shielding layer on the first substrate and the orthographic projection of the third pixel circuit on the first substrate at least partially overlap; the wavelength of the light emitted from the third effective light-emitting area is less than the wavelength of the light emitted from the second effective light-emitting area, and on a plane parallel to the main surface of the first substrate, the area ratio c of the third light-shielding layer is equal to the area of ​​the third light-shielding layer and the third effective light-emitting area. The ratio of the area of ​​the third sub-pixel, wherein the aperture ratio of the third sub-pixel is n3(1-c); (1-c) / (1-b)=(n2 / n3)M3*K3*K4, where K3 is the ratio of the initial brightness of the second sub-pixel to the initial brightness of the third sub-pixel, K4 is the ratio of the lifetime of the second sub-pixel to the lifetime of the third sub-pixel, n3 is the ratio of the area of ​​the aperture region in the third sub-pixel to the area of ​​the part of the third sub-pixel excluding the area blocked by the third light-shielding layer, the value range of (n2 / n3)M3 is 0.190~0.260, and the value range of (1-c) / (1-b) is 1.002~1.350.

[0010] For example, in a display substrate provided in at least one embodiment of this disclosure, the plurality of sub-pixels further includes a fourth sub-pixel; the fourth sub-pixel includes a fourth pixel circuit and a fourth effective light-emitting region; a fourth light-shielding layer is disposed between the fourth pixel circuit and the first substrate, and the orthographic projection of the fourth light-shielding layer on the first substrate and the orthographic projection of the fourth pixel circuit on the first substrate at least partially overlap; the wavelength of the light emitted from the fourth effective light-emitting region is greater than the wavelength of the light emitted from the second effective light-emitting region, and on a plane parallel to the main surface of the first substrate, the area ratio d of the fourth light-shielding layer is equal to the ratio of the area of ​​the fourth light-shielding layer to the area of ​​the fourth sub-pixel, and the aperture ratio n4(1-d) of the fourth sub-pixel ranges from 0.230 to 0.950, where n4 is the ratio of the area of ​​the open region in the fourth sub-pixel to the area of ​​the portion of the fourth sub-pixel excluding the area blocked by the fourth light-shielding layer.

[0011] For example, in a display substrate provided in at least one embodiment of this disclosure, the first sub-pixel further includes a first light-emitting element, the first pixel circuit controls the first light-emitting element to emit light, and the color of the light emitted by the first light-emitting element is the same as the color of the light emitted from the first effective light-emitting area; the second sub-pixel further includes a second light-emitting element, the second pixel circuit controls the second light-emitting element to emit light, and the color of the light emitted by the second light-emitting element is the same as the color of the light emitted from the second effective light-emitting area; the third sub-pixel further includes a third light-emitting element, the third pixel circuit controls the third light-emitting element to emit light, and the color of the light emitted by the third light-emitting element is the same as the color of the light emitted from the third effective light-emitting area.

[0012] For example, in a display substrate provided in at least one embodiment of this disclosure, the first sub-pixel further includes a first light-emitting element, and the first pixel circuit controls the first light-emitting element to emit light; the second sub-pixel further includes a second light-emitting element, and the second pixel circuit controls the second light-emitting element to emit light; the third sub-pixel further includes a third light-emitting element, and the third pixel circuit controls the third light-emitting element to emit light; the fourth sub-pixel further includes a fourth light-emitting element, and the fourth pixel circuit controls the fourth light-emitting element to emit light; the first light-emitting element, the second light-emitting element, the third light-emitting element, and the fourth light-emitting element are all white light-emitting elements, and in the first light-emitting... A first filter layer, a second filter layer, a third filter layer, and a light-transmitting layer are respectively disposed on the side of the optical element, the second light-emitting element, the third light-emitting element, and the fourth light-emitting element away from the first substrate. The color of the light emitted from the first filter layer is the same as the color of the light emitted from the first effective light-emitting region, the color of the light emitted from the second filter layer is the same as the color of the light emitted from the second effective light-emitting region, the color of the light emitted from the third filter layer is the same as the color of the light emitted from the third effective light-emitting region, and the color of the light emitted from the light-transmitting layer is the same as the color of the light emitted from the fourth effective light-emitting region.

[0013] For example, in the display substrate provided in at least one embodiment of this disclosure, the transmittance of the material of the first filter layer is λ1, the transmittance of the material of the second filter layer is λ2, the transmittance of the material of the third filter layer is λ3, and the transmittance of the material of the light-transmitting layer is λ4; the total transmittance T(λ) of the first filter layer, the second filter layer, the third filter layer and the light-transmitting layer is T(λ) = n1(1-a)λ1 + n2(1-b)λ2 + n3(1-c)λ3 + n4(1-d)λ4, and the value of λ4 is in the range of 0.260 to 0.950; the sum of the transmittances of the first filter layer, the second filter layer and the third filter layer and the transmittance of the light-transmitting layer satisfy: [n1(1-a)λ1 + n2(1-b)λ2 + n3(1-c)λ3] : [n4(1-d)λ4] = 1:1, and the value of n4(1-d) is in the range of 0.260 to 0.860.

[0014] For example, in the display substrate provided in at least one embodiment of this disclosure, the ratio of the sum of the areas of the first light-filtering layer, the second light-filtering layer, the third light-filtering layer, and the light-transmitting layer to the sum of the areas of the first light-shielding layer, the second light-shielding layer, the third light-shielding layer, and the fourth light-shielding layer on a plane parallel to the main surface of the first substrate is in the range of 1.050 to 6.800.

[0015] For example, in a display substrate provided in at least one embodiment of this disclosure, the ratio of the area of ​​the first filter layer to the area of ​​the first light-shielding layer on a plane parallel to the main surface of the first substrate is in the range of 2.000 to 3.000.

[0016] For example, in the display substrate provided in at least one embodiment of this disclosure, the ratio of the area of ​​the second filter layer to the area of ​​the second light-shielding layer on a plane parallel to the main surface of the first substrate ranges from 1.1074 to 1.6938.

[0017] For example, at least one embodiment of the present disclosure provides a display substrate that further includes: a data line and a first sensing line extending along a first direction and a second sensing line extending along a second direction, wherein the data line and the second sensing line intersect to define a plurality of pixel regions, each pixel region having a sub-pixel; a first power supply voltage line parallel to the data line is disposed between adjacent sub-pixels, and a second power supply voltage line parallel to the second direction is disposed on the side of the first effective light-emitting region near the first light-shielding layer, the second power supply voltage line intersects with the first power supply voltage line and is connected to the first drain of the first driving transistor in the first pixel circuit, and the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the first light-shielding layer on the first substrate overlap.

[0018] For example, in a display substrate provided in at least one embodiment of this disclosure, the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the fourth light-shielding layer on the first substrate overlap.

[0019] For example, in a display substrate provided in at least one embodiment of this disclosure, the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the third light-shielding layer on the first substrate overlap, and also overlap with the orthographic projection of the second light-shielding layer on the first substrate.

[0020] For example, in the display substrate provided in at least one embodiment of this disclosure, the overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the first light-shielding layer on the first substrate is greater than the overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the second light-shielding layer on the first substrate.

[0021] For example, in a display substrate provided in at least one embodiment of this disclosure, the overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the first light-shielding layer on the first substrate is greater than the overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the third light-shielding layer on the first substrate.

[0022] For example, in the display substrate provided in at least one embodiment of this disclosure, the overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the first light-shielding layer on the first substrate is greater than the overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the fourth light-shielding layer on the first substrate; the overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the fourth light-shielding layer on the first substrate is greater than the overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the third light-shielding layer on the first substrate is greater than the overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the second light-shielding layer on the first substrate.

[0023] For example, in a display substrate provided in at least one embodiment of this disclosure, in a first sub-pixel, the overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the first light-shielding layer on the first substrate is 0.03 to 0.30 square micrometers; in a second sub-pixel, the overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the fourth light-shielding layer on the first substrate is 0.02 to 0.20 square micrometers; in a third sub-pixel, the overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the third light-shielding layer on the first substrate is 0 to 0.05 square micrometers; and in a fourth sub-pixel, the overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the second light-shielding layer on the first substrate is 0 to 0.08 square micrometers.

[0024] For example, in a display substrate provided in at least one embodiment of this disclosure, the second power supply voltage line includes a first part and a second part that are separated from each other, and the first part and the second part are connected to the first power supply voltage line through different via structures.

[0025] For example, in a display substrate provided in at least one embodiment of this disclosure, the first portion and the first drain of the first driving transistor in the first pixel circuit and the second drain of the second driving transistor in the second pixel circuit are connected; the second portion and the third drain of the third driving transistor in the third pixel circuit and the fourth drain of the fourth driving transistor in the fourth pixel circuit are connected.

[0026] For example, in a display substrate provided in at least one embodiment of this disclosure, the extension direction of the first portion is parallel to the extension direction of the second portion, both the first portion and the second portion extend along a straight line, and the first portion is on the side of the second portion closer to the second sensing line.

[0027] For example, in a display substrate provided in at least one embodiment of this disclosure, the first portion is connected to the middle region of the first drain and the second drain, and the second portion is connected to the edge of the third drain away from the second sensing line and the edge of the fourth drain away from the second sensing line.

[0028] For example, in a display substrate provided in at least one embodiment of this disclosure, both the first portion and the second portion extend along a fold line. The first portion is connected to the edge of the first drain electrode away from the second sensing line and to the central region of the second drain electrode. The second portion is connected to the edge of the third drain electrode away from the second sensing line and to the central region of the fourth drain electrode.

[0029] For example, in a display substrate provided in at least one embodiment of this disclosure, the first drain and the first light-shielding layer are connected by a first via that sequentially penetrates the interlayer insulating layer, the gate insulating layer and the buffer layer.

[0030] For example, at least one embodiment of the present disclosure provides a display substrate that further includes a first gate line extending along the second direction and a first gate extending from the first gate line and toward a side close to the second power supply voltage line, wherein the planar shape of the first light-shielding layer includes a first sub-part and a second sub-part extending along the first direction, and a first distance between the first side of the first sub-part near the first gate line and the first gate line is greater than a second distance between the second side of the second sub-part near the first gate and the first gate.

[0031] For example, in a display substrate provided in at least one embodiment of this disclosure, a second gate line parallel to the first gate line is further included, wherein the first gate line is configured as the gate of a first switching transistor, the second gate line is configured as the gate of a first sensing transistor included in the first pixel circuit, the gate of a second sensing transistor included in the second pixel circuit, the gate of a third sensing transistor included in the third pixel circuit, and the gate of a fourth sensing transistor included in the fourth pixel circuit.

[0032] At least one embodiment of this disclosure also provides a display device, which includes a display substrate as described in any of the above embodiments and a cover plate disposed opposite to the display substrate. The cover plate includes a second substrate, and a quantum dot layer is disposed on the side of the second substrate close to the display substrate. The quantum dot layer includes a plurality of quantum dot units, and the plurality of quantum dot units correspond one-to-one with a plurality of sub-pixels. The color of each of the plurality of quantum dot units is the same as the color of the corresponding sub-pixel.

[0033] The display device provided in at least one embodiment of this disclosure further includes: a black matrix disposed on the side of the second substrate near the display substrate, the black matrix having a plurality of openings, each of the quantum dot units being located in one of the openings.

[0034] At least one embodiment of this disclosure also provides a method for fabricating a display substrate, the method comprising: providing a first substrate; forming a plurality of sub-pixels on the first substrate, wherein forming the plurality of sub-pixels includes forming a first sub-pixel and a second sub-pixel; forming the first sub-pixel includes forming a first pixel circuit and a first effective light-emitting region; forming the second sub-pixel includes forming a second pixel circuit and a second effective light-emitting region; forming a first light-shielding layer between the first pixel circuit and the first substrate, wherein the orthographic projection of the first light-shielding layer on the first substrate and the orthographic projection of the first pixel circuit on the first substrate at least partially overlap; forming a second light-shielding layer between the second pixel circuit and the first substrate, wherein the orthographic projection of the second light-shielding layer on the first substrate and the orthographic projection of the second pixel circuit on the first substrate at least partially overlap; the area of ​​the first effective light-emitting region is larger than the area of ​​the second effective light-emitting region, and the area of ​​the first light-shielding layer is larger than the area of ​​the second light-shielding layer.

[0035] For example, in the preparation method provided in at least one embodiment of this disclosure, the wavelength of the light emitted from the first effective light-emitting region is greater than the wavelength of the light emitted from the second effective light-emitting region; the ratio of the area of ​​the first light-shielding layer to the area of ​​the first sub-pixel is a; the ratio of the area of ​​the second light-shielding layer to the area of ​​the second sub-pixel is b; and the range of the ratio M1 of a and b is 1.020 to 1.120; the aperture ratio of the first sub-pixel is n1(1-a); and the aperture ratio of the second sub-pixel is n2(1-b); (1-a) / (1-b)=(n2 / n1)M2*K1*K2, where K1 is the aperture ratio of the first sub-pixel. The initial brightness of the second sub-pixel is the ratio of the initial brightness of the first sub-pixel to the initial brightness of the second sub-pixel. K2 is the ratio of the lifetime of the second sub-pixel to the lifetime of the first sub-pixel. n1 is the ratio of the area of ​​the opening region in the first sub-pixel to the area of ​​the portion of the first sub-pixel excluding the area blocked by the first light-shielding layer. n2 is the ratio of the area of ​​the opening region in the second sub-pixel to the area of ​​the portion of the second sub-pixel excluding the area blocked by the second light-shielding layer. The value range of (n2 / n1)M2 is 1.000 to 1.130, and the value range of (1-a) / (1-b) is 0.877 to 0.997. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0037] Figure 1A schematic diagram of a planar structure of a display substrate provided in at least one embodiment of this disclosure;

[0038] Figure 2 This is a schematic diagram of a planar structure of another display substrate provided in at least one embodiment of the present disclosure;

[0039] Figure 3 This is a schematic diagram of a planar structure of another display substrate provided in at least one embodiment of the present disclosure;

[0040] Figure 4 This is a schematic diagram of a planar structure of another display substrate provided in at least one embodiment of the present disclosure;

[0041] Figure 5 This is a schematic diagram of a planar structure of another display substrate provided in at least one embodiment of the present disclosure;

[0042] Figure 6 This is a schematic diagram of a planar structure of another display substrate provided in at least one embodiment of the present disclosure;

[0043] Figure 7 This is a schematic diagram of a planar structure of another display substrate provided in at least one embodiment of the present disclosure;

[0044] Figure 8A for Figures 1-3 A schematic diagram of the cross-sectional structure of the display substrate along line A-A'.

[0045] Figure 8B for Figure 4 A schematic diagram of the cross-sectional structure of the display substrate along lines B-B' and C-C'.

[0046] Figure 9 This is a schematic diagram of a planar structure of another display substrate provided in at least one embodiment of the present disclosure;

[0047] Figure 10 This is a schematic diagram of a planar structure of another display substrate provided in at least one embodiment of the present disclosure;

[0048] Figure 11 This is a schematic diagram of a planar structure of another display substrate provided in at least one embodiment of the present disclosure;

[0049] Figure 12 A schematic diagram of a 3T1C pixel circuit for a display substrate provided in at least one embodiment of this disclosure;

[0050] Figure 13 for Figure 12 The diagram shows the signal timing of the pixel circuit during the display process.

[0051] Figure 14 for Figure 12The diagram shown is a timing diagram of the first signal of the pixel circuit during the detection process;

[0052] Figure 15 for Figure 12 The diagram shows the second signal timing of the pixel circuit during the detection process;

[0053] Figure 16 This is a cross-sectional structural schematic diagram of a display device provided in at least one embodiment of the present disclosure;

[0054] Figure 17 A flowchart illustrating a method for fabricating a display substrate, provided for at least one embodiment of this disclosure; and

[0055] Figures 18A-18H This diagram illustrates the formation process of a first sub-pixel, provided for at least one embodiment of this disclosure. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0057] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0058] As the resolution of LED displays increases, the pixel size of LED displays is continuously decreasing. The luminous intensity of red, green, and blue sub-pixels in LED displays is inconsistent, and the wavelengths of light emitted by red, green, and blue sub-pixels are different. Therefore, it is necessary to adjust the aperture ratios corresponding to different colored sub-pixels to achieve better light mixing. For light-emitting elements emitting white or blue light, filter layers need to be placed in the areas corresponding to red, green, and blue sub-pixels. As the pixel size in LED displays decreases, the spacing between the filter layers corresponding to different colored sub-pixels decreases, easily leading to color crosstalk. This makes it more difficult to adjust the aperture ratios of red, green, and blue sub-pixels by adjusting the size of the filter layers. The inventors of this disclosure have noticed that the aperture ratios of different sub-pixels can be adjusted by designing the size of the light-shielding layers corresponding to different sub-pixels, thus simplifying the entire process of fabricating the display substrate.

[0059] At least one embodiment of this disclosure provides a display substrate, comprising: a first substrate and a plurality of sub-pixels disposed on the first substrate, the plurality of sub-pixels including a first sub-pixel and a second sub-pixel, the first sub-pixel including a first pixel circuit and a first effective light-emitting region; the second sub-pixel including a second pixel circuit and a second effective light-emitting region; a first light-shielding layer disposed between the first pixel circuit and the first substrate, wherein the orthographic projection of the first light-shielding layer on the first substrate and the orthographic projection of the first pixel circuit on the first substrate at least partially overlap; a second light-shielding layer disposed between the second pixel circuit and the first substrate, wherein the orthographic projection of the second light-shielding layer on the first substrate and the orthographic projection of the second pixel circuit on the first substrate at least partially overlap; the area of ​​the first effective light-emitting region is larger than the area of ​​the second effective light-emitting region, and the area of ​​the first light-shielding layer is larger than the area of ​​the second light-shielding layer. The embodiments of this disclosure adjust the aperture ratio corresponding to different sub-pixels by designing the size of the light-shielding layer corresponding to different sub-pixels, thereby simplifying the entire process of fabricating the display substrate.

[0060] For example, Figure 1 This is a schematic diagram of a planar structure of a display substrate provided in at least one embodiment of the present disclosure, such as... Figure 1As shown, the display substrate 100 includes a first substrate 101 and a plurality of sub-pixels 102 disposed on the first substrate 101. The plurality of sub-pixels 102 are arranged in a second direction Y, that is, the plurality of sub-pixels 102 are arranged side by side in the second direction Y. The plurality of sub-pixels 102 includes a first sub-pixel 1021 and a second sub-pixel 1022 arranged side by side in the second direction Y. The direction intersecting or perpendicular to the second direction Y is a first direction X. The first sub-pixel 1021 includes a first pixel circuit 1021a and a first effective light-emitting area 1021b in the first direction X; the second sub-pixel 1022 includes a second pixel circuit 1022a and a second effective light-emitting area 1022b in the first direction X. A first light-shielding layer 103 is disposed between the first pixel circuit 1021a and the first substrate 101 in a direction perpendicular to the main surface of the first substrate 101, and the orthographic projection of the first light-shielding layer 103 on the first substrate 101 and the orthographic projection of the first pixel circuit 1021a on the first substrate 101 at least partially overlap. A second light-shielding layer 104 is disposed between the second pixel circuit 1022a and the first substrate 101, and the orthographic projection of the second light-shielding layer 104 on the first substrate 101 and the orthographic projection of the second pixel circuit 1022a on the first substrate 101 at least partially overlap. The area of ​​the first effective light-emitting region 1021b is larger than the area of ​​the second effective light-emitting region 1022b, and the area of ​​the first light-shielding layer 103 is larger than the area of ​​the second light-shielding layer 104. That is, by adjusting the aperture ratios corresponding to the first and second sub-pixels, the entire process can be simplified.

[0061] For example, the wavelength of the light emitted from the first effective light-emitting region 1021b is greater than the wavelength of the light emitted from the second effective light-emitting region 1022b. The ratio of the area of ​​the first light-shielding layer 103 to the area of ​​the first sub-pixel 1021 is a, and the ratio of the area of ​​the second light-shielding layer 104 to the area of ​​the second sub-pixel 1022 is b. The range of the ratio M1 of a and b is 1.020 to 1.120. When the ratio of a to b, M1, is less than 1.020, the ratio a of the area of ​​the first light-blocking layer 103 to the area of ​​the first sub-pixel 1021 is relatively small, resulting in a large aperture ratio of the first sub-pixel 1021 and a small aperture ratio of the second sub-pixel 1022, leading to poor final color mixing. When the ratio of a to b, M1, is greater than 1.120, the ratio a of the area of ​​the first light-blocking layer 103 to the area of ​​the first sub-pixel 1021 is relatively large, resulting in a small aperture ratio of the first sub-pixel 1021 and a large aperture ratio of the second sub-pixel 1022, leading to poor final color mixing. Furthermore, when the ratio M1 of a to b is less than 1.020, the ratio a of the area of ​​the first light-shielding layer 103 to the area of ​​the first sub-pixel 1021 is relatively small, resulting in a relatively small first light-shielding layer 103 corresponding to the first sub-pixel 1021, and a weaker shielding and protection effect on the first pixel circuit 1021a (for example, the first light-shielding layer 103 overlaps with the active layer of the driving transistor of the first pixel circuit 1021a at least, playing a shielding and protection role and preventing leakage current from external light irradiation); when the ratio M1 of a to b is greater than 1.120, the second light-shielding layer 104 corresponding to the second sub-pixel 1022 is relatively small, resulting in a weaker shielding and protection effect on the second pixel circuit 1022a (for example, the first light-shielding layer 103 overlaps with the active layer of the driving transistor of the second pixel circuit 1022a at least, playing a shielding and protection role and preventing leakage current from external light irradiation).

[0062] For example, the first sub-pixel and the second sub-pixel included in the plurality of sub-pixels may be two adjacent sub-pixels arranged side by side along the second direction in a pixel unit, or two mutually spaced sub-pixels arranged side by side along the second direction in a pixel unit. The embodiments of this disclosure do not limit this, as long as the first sub-pixel and the second sub-pixel are in the same pixel unit.

[0063] For example, in one example, the first sub-pixel 1021 and the second sub-pixel 1022 are a red sub-pixel and a green sub-pixel, respectively. Correspondingly, the first effective light-emitting area 1021b is a red light-emitting area, and the second effective light-emitting area 1022b is a green light-emitting area. Typically, the light-emitting area of ​​the red sub-pixel is larger than that of the green sub-pixel, that is, the area of ​​the first effective light-emitting area 1021b is larger than the area of ​​the second effective light-emitting area 1022b. By setting the area of ​​the first light-shielding layer 103 to be larger than the area of ​​the second light-shielding layer 104, the aperture ratio of the first sub-pixel 1021 and the second sub-pixel 1022 can be adjusted to achieve a better final light mixing effect. Moreover, the process of fabricating the display substrate is simpler, and the display substrate has higher luminous efficiency. Furthermore, since the wavelength of light emitted from the red sub-pixel is greater than that of light emitted from the green sub-pixel, the red sub-pixel is more prone to diffraction, which in turn affects the pixel circuit of the same sub-pixel or other sub-pixels. Therefore, the area of ​​the first light-shielding layer 103 is set to be larger than the area of ​​the second light-shielding layer 104 to reduce the diffraction effect of light emitted from the red sub-pixel.

[0064] For example, the first light-shielding layer 103 and the second light-shielding layer 104 can be formed using the same material in the same process step. The material of the first light-shielding layer 103 and the second light-shielding layer 104 can be a metal material with light-shielding properties, or other materials with light-shielding properties. The embodiments disclosed herein do not limit this.

[0065] For example, such as Figure 1 As shown, the orthographic projections of the first effective light-emitting region 1021b on the first substrate 101 and the first light-shielding layer 103 on the first substrate 101 do not overlap. Similarly, the orthographic projections of the second effective light-emitting region 1022b on the first substrate 101 and the second light-shielding layer 104 on the first substrate 101 do not overlap. When this display substrate is used in a display panel, it can achieve top emission, bottom emission, or bidirectional emission. The embodiments disclosed herein do not limit this.

[0066] For example, such as Figure 1 As shown, in one example, a equals the area of ​​the first light-shielding layer divided by the area of ​​the first sub-pixel, b equals the area of ​​the second light-shielding layer divided by the area of ​​the second sub-pixel, and M1 = a / b. In another example, the area of ​​the first sub-pixel 1021 is equal to the area of ​​the second sub-pixel 1022. Therefore, on a plane parallel to the main surface of the first substrate 101, the ratio of the area of ​​the first light-shielding layer 103 to the area of ​​the second light-shielding layer 104 is equal to M1.

[0067] For example, such as Figure 1As shown, the area blocked by the first light-blocking layer 103 is not an opening area. Besides the area blocked by the first light-blocking layer 103 and the opening area, the first sub-pixel 1021 also includes other areas. The area blocked by the second light-blocking layer 104 is not an opening area. Besides the area blocked by the second light-blocking layer 104 and the opening area, the second sub-pixel 1022 also includes other areas. The aperture ratio of the first sub-pixel 1021 is n1(1-a), where n1 is the ratio of the area of ​​the opening area in the first sub-pixel 1021 to the area of ​​the portion of the first sub-pixel 1021 excluding the area blocked by the first light-blocking layer 103. The aperture ratio of the second sub-pixel is n2(1-b), where n2 is the ratio of the area of ​​the opening area in the second sub-pixel 1022 to the area of ​​the portion of the second sub-pixel 1022 excluding the area blocked by the second light-blocking layer 104. (n1 / n2)(1-a) / (1-b)=M2*K1*K2, which leads to: (1-a) / (1-b)=(n2 / n1)M2*K1*K2, where K1 is the ratio of the initial brightness of the second sub-pixel to the initial brightness of the first sub-pixel, K2 is the ratio of the lifetime of the second sub-pixel to the lifetime of the first sub-pixel, and the value range of (n2 / n1)M2 is 1.000~1.130, and (1-a) / (1-b) The value of M2 ranges from 0.877 to 0.997. M2 is a coefficient without a unit. It is only used to satisfy the equation (1-a) / (1-b)=(n2 / n1)M2*K1*K2 so that both sides are equal. Moreover, (1-a) / (1-b) on the left side of the equation is a ratio without a unit. (n2 / n1), K1 and K2 on the right side of the equation are also ratios without a unit. Therefore, M2 on the right side of the equation is also without a unit and is just a coefficient.

[0068] For example, the above formula (n1 / n2)(1-a) / (1-b)=M2*K1*K2 can be adapted to the following formula: (initial brightness of sub-pixel * aperture ratio of pixel / initial brightness of pixel unit) * luminous lifetime of sub-pixel = C 常数 It is deduced.

[0069] (Initial brightness of the first sub-pixel * aperture ratio of the first sub-pixel) / initial brightness of the pixel unit) * luminous lifetime of the first sub-pixel = M2 * (Initial brightness of the second sub-pixel * aperture ratio of the second sub-pixel) / initial brightness of the pixel unit) * luminous lifetime of the second sub-pixel.

[0070] Further derivation yields: (Aperture ratio of the first sub-pixel) / (Aperture ratio of the second sub-pixel) = M2 * ((Initial brightness of the second sub-pixel / Initial brightness of the pixel unit) * Lamp lifetime of the second sub-pixel) / ((Initial brightness of the first sub-pixel / Initial brightness of the pixel unit) * Lamp lifetime of the first sub-pixel). Since the first and second sub-pixels correspond to the same pixel unit, the initial brightness of the pixel unit corresponding to the first sub-pixel is equal to the initial brightness of the pixel unit corresponding to the second sub-pixel. Therefore, the above formula can be simplified to formula (I):

[0071] (Aperture ratio of the first sub-pixel) / (Aperture ratio of the second sub-pixel) = M2*((Initial brightness of the second sub-pixel * Lamp life of the second sub-pixel) / (Initial brightness of the first sub-pixel * Lamp life of the first sub-pixel)).

[0072] Substituting the aperture ratio of the first sub-pixel = n1(1-a) and the aperture ratio of the second sub-pixel = n2(1-b) into formula (I), we obtain the following formula (II):

[0073] (Aperture ratio of the first sub-pixel) / (Aperture ratio of the second sub-pixel)=(n1 / n2)(1-a) / (1-b)=M2*((Initial brightness of the second sub-pixel * Light-emitting lifetime of the second sub-pixel) / (Initial brightness of the first sub-pixel * Light-emitting lifetime of the first sub-pixel)).

[0074] The following formula is derived from formula (II): (1-a) / (1-b)=(n2 / n1)M2*((initial brightness of the second sub-pixel * luminous lifetime of the second sub-pixel) / (initial brightness of the first sub-pixel * luminous lifetime of the first sub-pixel))=(n2 / n1)M2*K1*K2, where K1=initial brightness of the second sub-pixel / initial brightness of the first sub-pixel, and K2=luminous lifetime of the second sub-pixel / luminous lifetime of the first sub-pixel. For example, in one example, (n2 / n1)M2=1.000~1.130. For example, when n2=n1, M2=1.000~1.130.

[0075] For example, in one example, the initial brightness of the first sub-pixel is 26.1 cd / m². 2 The initial brightness of the second sub-pixel is 86.1 cd / m². 2 The first sub-pixel has a light-emitting lifetime of 150,000 hours, the second sub-pixel has a light-emitting lifetime of 40,000 hours, n2 = n1, M2 = 1.130, then we can calculate: (1-a) / (1-b) = 1.13 * (86.1 cd / m 2 *40000h) / (26.1cd / m 2*150000h))=0.994. The initial brightness can be obtained by testing the brightness of each sub-pixel under a certain grayscale condition. For example, under 255 grayscale levels of the display device, the brightness of each sub-pixel is tested. For example, the second sub-pixel emits light with a shorter wavelength, so the initial brightness of the second sub-pixel is higher and its lifespan is shorter; the first sub-pixel emits light with a longer wavelength, so the initial brightness of the first sub-pixel is lower and its lifespan is longer. Therefore, K1 is less than K2.

[0076] For example, in one example, the first sub-pixel is a red sub-pixel and the second sub-pixel is a green sub-pixel. Under normal circumstances, the green sub-pixel has a higher initial brightness and a shorter lifetime, while the red sub-pixel has a lower initial brightness and a longer lifetime. Therefore, K1 is less than K2.

[0077] For example, in Figure 1 In the structure shown, the plurality of sub-pixels 102 also includes a third sub-pixel 1023, that is, a third sub-pixel 1023 is also provided on the first substrate 101, which is arranged side by side with the first sub-pixel 1021 and the second sub-pixel 1022. The third sub-pixel 1023 may include a third pixel circuit 1023a and a third effective light-emitting area 1023b.

[0078] For example, a third light-shielding layer 105 is disposed between the third pixel circuit 1023a and the first substrate 101, and the orthographic projection of the third light-shielding layer 105 on the first substrate 101 and the orthographic projection of the third pixel circuit 1023a on the first substrate 101 at least partially overlap. The wavelength of the light emitted from the third effective light-emitting region 1023b is less than the wavelength of the light emitted from the second effective light-emitting region 1022b, and on a plane parallel to the main surface of the first substrate 101, the area ratio c of the third light-shielding layer 105 is equal to the ratio of the area of ​​the third light-shielding layer 105 to the area of ​​the third sub-pixel 1023, and the aperture ratio of the third sub-pixel 1023 is n3(1-c).

[0079] Similarly, following the derivation process of (1-a) / (1-b)=(n2 / n1)M2*K1*K2 above, we can derive: (1-c) / (1-b)=(n2 / n3)M3*K3*K4, where K3 is the ratio of the initial brightness of the second sub-pixel to the initial brightness of the third sub-pixel, K4 is the ratio of the lifetime of the second sub-pixel to the lifetime of the third sub-pixel, n3 is the ratio of the area of ​​the opening region in the third sub-pixel to the area of ​​the part of the third sub-pixel excluding the area blocked by the third light-shielding layer, and (n2 / n3)M The value of 3 ranges from 0.190 to 0.260, and the value of (1-c) / (1-b) ranges from 1.002 to 1.350. M3 is a coefficient without a unit, used only to satisfy the equation (1-c) / (1-b)=(n2 / n3)M3*K3*K4, where both sides are equal. Furthermore, (1-c) / (1-b) on the left side of the equation is a ratio without a unit, and (n2 / n3), K3, and K4 on the right side of the equation are also ratios without a unit. Therefore, M3 on the right side of the remaining equation is also without a unit, serving only as a coefficient.

[0080] For example, the first effective light-emitting area 1021b, the second effective light-emitting area 1022b, and the third effective light-emitting area 1023b correspond to the red light-emitting area, the green light-emitting area, and the blue light-emitting area, respectively, and the corresponding first sub-pixel 1021, second sub-pixel 1022, and third sub-pixel 1023 are the red sub-pixel, the green sub-pixel, and the blue sub-pixel, respectively.

[0081] For example, in one example, the initial brightness of the second sub-pixel 1022 is 86.1 cd / m². 2 The second sub-pixel 1022 has a luminous lifetime of 40,000 hours, and the third sub-pixel 1023 has an initial brightness of 11.3 cd / m². 2 The luminous lifetime of the third sub-pixel 1023 is 60,000 hours. Given n2 = n3 and M3 = 0.260, we can calculate: (1-c) / (1-b) = 0.260 * (86.1 cd / m 2 *40000h) / (11.3cd / m 2 *60000h))=1.32.

[0082] For example, such as Figure 1As shown, the first sub-pixel 1021 further includes a first light-emitting element 1021c. The first pixel circuit 1021a controls the first light-emitting element 1021c to emit light, and the color of the light emitted by the first light-emitting element 1021c is the same as the color of the light emitted from the first effective light-emitting area 1021b. The second sub-pixel 1022 further includes a second light-emitting element 1022c. The second pixel circuit 1022a controls the second light-emitting element 1022c to emit light, and the color of the light emitted by the second light-emitting element 1022c is the same as the color of the light emitted from the second effective light-emitting area 1022b. The third sub-pixel 1023 further includes a third light-emitting element 1023c. The third pixel circuit 1023a controls the third light-emitting element 1023c to emit light, and the color of the light emitted by the third light-emitting element 1023c is the same as the color of the light emitted from the third effective light-emitting area 1023b. For example, the first light-emitting element 1021c, the second light-emitting element 1022c, and the third light-emitting element 1023c emit first color light, second color light, and third color light, respectively. The first color light, the second color light, and the third color light can be mixed to form white light.

[0083] For example, in one instance, the first, second, and third light-emitting elements emit red, green, and blue light, respectively.

[0084] For example, in one example, the area of ​​the first light-shielding layer 103 corresponding to the red sub-pixel is greater than the area of ​​the second light-shielding layer 104 corresponding to the green sub-pixel, which is greater than the area of ​​the third light-shielding layer 105 corresponding to the blue sub-pixel. For example, the ratio of the area of ​​the first light-shielding layer 103 to the area of ​​the second light-shielding layer 104 to the area of ​​the third light-shielding layer 105 is 20:19:18. Since the wavelength of the light emitted from the red pixel is greater than that from the green sub-pixel, which is greater than that from the blue sub-pixel, longer wavelengths are more prone to diffraction, thus affecting the pixel circuitry of the same sub-pixel or other sub-pixels. Therefore, the area of ​​the light-shielding layer corresponding to the sub-pixel with the longer wavelength is larger to reduce the diffraction effect of its emitted light. For example, in one example, the area of ​​the first light-shielding layer 103 corresponding to the red sub-pixel is greater than the area of ​​the second light-shielding layer 104 corresponding to the green sub-pixel, which is greater than the area of ​​the third light-shielding layer 105 corresponding to the blue sub-pixel. For example, the ratio of a:b:c is 20:19:18.

[0085] For example, Figure 2 This is a schematic diagram of a planar structure of another display substrate provided in at least one embodiment of the present disclosure, as shown below. Figure 2 As shown, compared to Figure 1 The structure of the display substrate shown is in Figure 2In the structure shown, the plurality of sub-pixels 102 also includes a fourth sub-pixel 1024, that is, the first substrate 101 also has a fourth sub-pixel 1024 arranged side by side with the first sub-pixel 1021, the second sub-pixel 1022 and the third sub-pixel 1023.

[0086] It should be noted that, although in Figure 2 In the first sub-pixel 1021, the second sub-pixel 1022, the fourth sub-pixel 1024 and the third sub-pixel 1023 are arranged side by side in sequence. However, the embodiments of this disclosure are not limited to this. The third sub-pixel 1023 may also be arranged between the second sub-pixel 1022 and the fourth sub-pixel 1024 or in other orders. The embodiments of this disclosure do not limit this.

[0087] For example, the relevant features of the first sub-pixel 1021, the second sub-pixel 1022, and the third sub-pixel 1023 can be found in the above description of... Figure 1 Related descriptions.

[0088] For example, such as Figure 2 As shown, the fourth sub-pixel 1024 includes a fourth pixel circuit 1024a and a fourth effective light-emitting region 1024b. A fourth light-shielding layer 106 is disposed between the fourth pixel circuit 1024a and the first substrate 101, and the orthographic projection of the fourth light-shielding layer 106 on the first substrate 101 and the orthographic projection of the fourth pixel circuit 1024a on the first substrate 101 at least partially overlap. The wavelength of the light emitted from the fourth effective light-emitting region 1024b is greater than the wavelength of the light emitted from the second effective light-emitting region 1022b. On a plane parallel to the main surface of the first substrate 101, the area ratio d of the fourth light-shielding layer 106 is equal to the ratio of the area of ​​the fourth light-shielding layer 106 to the area of ​​the fourth sub-pixel 1024. The aperture ratio n4(1-d) of the fourth sub-pixel 1024 ranges from 0.230 to 0.950, where n4 is the ratio of the area of ​​the open region in the fourth sub-pixel to the area of ​​the part of the fourth sub-pixel excluding the area blocked by the fourth light-shielding layer.

[0089] For example, in one example, the light emitted from the fourth sub-pixel 1024 is white light, that is, the fourth sub-pixel 1024 is a white sub-pixel, and correspondingly, the fourth effective light-emitting area 1024b is a white light-emitting area.

[0090] For example, Figure 3 This is a schematic diagram of the planar structure of another display substrate provided in at least one embodiment of the present disclosure, as shown below. Figure 3As shown, the first sub-pixel 1021 includes a first light-emitting element 1021c, and the first pixel circuit 1021a controls the first light-emitting element 1021c to emit light. The second sub-pixel 1022 also includes a second light-emitting element 1022c, and the second pixel circuit 1022a controls the second light-emitting element 1022c to emit light. The third sub-pixel 1023 also includes a third light-emitting element 1023c, and the third pixel circuit 1023a controls the third light-emitting element 1023c to emit light. The fourth sub-pixel 1024 also includes a fourth light-emitting element 1024c, and the fourth pixel circuit 1024a controls the fourth light-emitting element 1024c to emit light. The first light-emitting element 1021c, the second light-emitting element 1022c, the third light-emitting element 1023c and the fourth light-emitting element 1024c are all white light-emitting elements, and a first filter layer 1021d, a second filter layer 1022d, a third filter layer 1023d and a light-transmitting layer 1024d are respectively provided on the side of the first light-emitting element 1021c, the second light-emitting element 1022c, the third light-emitting element 1023c and the fourth light-emitting element 1024c away from the first substrate 101. The color of the light emitted from the first filter layer 1021d is the same as the color of the light emitted from the first effective light-emitting region 1021b. The color of the light emitted from the second filter layer 1022d is the same as the color of the light emitted from the second effective light-emitting region 1022b. The color of the light emitted from the third filter layer 1023d is the same as the color of the light emitted from the third effective light-emitting region 1023b. The color of the light emitted from the light-transmitting layer 1024d is the same as the color of the light emitted from the fourth effective light-emitting region 1024b, which is still white light.

[0091] It should be noted that, for the sake of simplicity, in Figure 3 The first substrate 101 is omitted in the text.

[0092] For example, such as Figure 3As shown, the transmittance of the material of the first filter layer 1021d is λ1, the transmittance of the material of the second filter layer 1022d is λ2, the transmittance of the material of the third filter layer 1023d is λ3, and the transmittance of the material of the light-transmitting layer 1024d is λ4. The total transmittance of the first filter layer 1021d, the second filter layer 1022d, the third filter layer 1023d and the light-transmitting layer 1024d is T(λ)=n1(1-a)λ1+n2(1-b)λ2+n3(1-c)λ3+n4(1-d)λ4, and the value of λ4 is in the range of 0.260~0.950. The sum of the transmittance of the first filter layer 1021d, the second filter layer 1022d, and the third filter layer 1023d, and the transmittance of the light-transmitting layer 1024d satisfy the following proportional relationship: [n1(1-a)λ1+n2(1-b)λ2+n3(1-c)λ3]:[n4(1-d)λ4]=1:1, and the value of n4(1-d) ranges from 0.260 to 0.860, where n4 is the ratio of the area of ​​the opening region in the fourth sub-pixel 1024 to the area of ​​the part of the fourth sub-pixel 1024 excluding the area blocked by the fourth light-blocking layer 106.

[0093] For example, the first light-emitting element 1021c, the second light-emitting element 1022c, the third light-emitting element 1023c and the fourth light-emitting element 1024c are all light-emitting elements that emit white light. This design can make the uniformity of the emitted light better, and the width of the white light spectrum can be adjusted, and optical compensation can also be performed.

[0094] For example, in one example, on a plane parallel to the main surface of the first substrate 101, the ratio of the sum of the areas of the first filter layer 1021d, the second filter layer 1022d, the third filter layer 1023d, and the light-transmitting layer 1024d to the sum of the areas of the first light-shielding layer 103, the second light-shielding layer 104, the third light-shielding layer 105, and the fourth light-shielding layer 106 ranges from 1.050 to 6.800. For example, the ratio can be 1.100, 1.200, 2.000, 2.500, 3.000, 3.500, 4.000, 4.500, 5.000, 5.500, 6.000, or 6.500. The embodiments of this disclosure do not limit this.

[0095] For example, in another example, on a plane parallel to the main surface of the first substrate 101, the ratio of the sum of the areas of the first filter layer 1021d, the second filter layer 1022d, the third filter layer 1023d, and the light-transmitting layer 1024d to the sum of the areas of the first light-shielding layer 103, the second light-shielding layer 104, the third light-shielding layer 105, and the fourth light-shielding layer 106 ranges from 1.100 to 3.300. For example, this ratio can be 1.200, 1.300, 1.400, 1.600, 1.800, 2.000, 2.400, 2.700, 2.900, 3.100, 3.200, or 3.300, and the embodiments of this disclosure are not limited thereto.

[0096] For example, in one example, on a plane parallel to the main surface of the first substrate 101, the ratio of the area of ​​the first filter layer 1021d to the area of ​​the first light-shielding layer 103 is in the range of 2.000 to 3.000, for example, the ratio is 2.000, 2.200, 2.400, 2.600, 2.800 or 3.000.

[0097] For example, in one example, on a plane parallel to the main surface of the first substrate 101, the ratio of the area of ​​the second filter layer 1022d to the area of ​​the second light-shielding layer 104 ranges from 1.1074 to 1.6938. For example, the ratio of the area of ​​the second filter layer 1022d to the area of ​​the second light-shielding layer 104 is 1.1074, 1.200, 1.300, 1.400, 1.500, or 1.600. The embodiments of this disclosure do not limit this.

[0098] For example, in one example, on a plane parallel to the main surface of the first substrate 101, the ratio of the area of ​​the third filter layer 1023d to the area of ​​the third light-shielding layer 105 ranges from 1.4650 to 2.02268. For example, the ratio of the area of ​​the third filter layer 1023d to the area of ​​the third light-shielding layer 105 is 1.510, 1.600, 1.700, 1.800, 1.900 or 2.100. The embodiments of this disclosure do not limit this.

[0099] For example, in one example, on a plane parallel to the main surface of the first substrate 101, the ratio of the area of ​​the light-transmitting layer 1024d to the area of ​​the fourth light-shielding layer 106 ranges from 2.1760 to 3.2850. For example, the ratio of the area of ​​the light-transmitting layer 1024d to the area of ​​the fourth light-shielding layer 106 is 2.210, 2.600, 2.700, 2.800, 2.900, or 3.100. The embodiments of this disclosure do not limit this.

[0100] For example, combining Figures 1-3The display substrate 100 further includes a data line 107 and a first sensing line 108 extending along a first direction X, and a second sensing line 109 extending along a second direction Y. The data line 107 and the second sensing line 109 intersect to define a plurality of pixel regions, each pixel region having one sub-pixel 102. A first power supply voltage line 110 parallel to the data line 107 is provided between adjacent sub-pixels 102. A second power supply voltage line 111 parallel to the second direction Y is provided on the side of the first effective light-emitting region 1021b near the first light-shielding layer 103. The second power supply voltage line 111 intersects with the first power supply voltage line 110 and is connected to the first drain of the first driving transistor in the first pixel circuit 1021a. The orthographic projection of the second power supply voltage line 111 on the first substrate 101 overlaps with the orthographic projection of the first light-shielding layer 103 on the first substrate 101.

[0101] For example, such as Figure 2 As shown, in one example, the orthographic projection of the second power supply voltage line 111 on the first substrate 101 and the orthographic projection of the first light-shielding layer 103 on the first substrate 101 have an overlapping portion. The orthographic projections of the second power supply voltage line 111, the second light-shielding layer 104, the third light-shielding layer 105, and the fourth light-shielding layer 106 on the first substrate 101 do not have overlapping portions. However, the orthographic projections of the second power supply voltage line 111 and the fourth light-shielding layer 106 on the first substrate 101 have an adjacent portion. This design can enhance the stability of the first light-shielding layer 103. A capacitor can be formed between the first light-shielding layer 103 and the second power supply voltage line 111, thereby preventing the first light-shielding layer 103 from drifting when the gate signal is not turned on.

[0102] For example, such as Figure 1 As shown, in another example, the orthographic projection of the second power supply voltage line 111 on the first substrate 101 and the orthographic projection of the first light-shielding layer 103 on the first substrate 101 have overlapping portions, while the orthographic projections of the second power supply voltage line 111 on the first substrate 101, the second light-shielding layer 104 on the first substrate 101, and the third light-shielding layer 105 on the first substrate 101 do not have overlapping portions.

[0103] For example, in another example, the orthographic projections of the second power supply voltage line 111 on the first substrate 101, the orthographic projections of the first light-shielding layer 103, the second light-shielding layer 104, the third light-shielding layer 105, and the fourth light-shielding layer 106 on the first substrate 101 do not have overlapping portions.

[0104] For example, the second sensing line 109 extending along the second direction Y can be a curved extension, a broken line extension, or a straight line extension, as long as the overall extension direction of the second sensing line 109 is along the second direction Y. Figures 1-3 In the structure shown, the second sensing lines 109 all extend in a straight line.

[0105] For example, such as Figure 3 As shown, the second power supply voltage line 111 is connected to the source S11 of the driving transistor T11 in the first sub-pixel 1021, the second power supply voltage line 111 is connected to the source S12 of the driving transistor T12 in the second sub-pixel 1022, the second power supply voltage line 111 is connected to the source S13 of the driving transistor T13 in the third sub-pixel 1023, and the second power supply voltage line 111 is connected to the source S14 of the driving transistor T14 in the fourth sub-pixel 1024.

[0106] For example, such as Figure 3 As shown, the orthographic projection of the second power supply voltage line 111 on the first substrate 101 overlaps with the orthographic projection of the first light-shielding layer 103 on the first substrate 101, and also overlaps with the orthographic projection of the fourth light-shielding layer 106 on the first substrate 101. The orthographic projections of the second power supply voltage line 111, the second light-shielding layer 104, and the third light-shielding layer 105 on the first substrate 101 do not overlap. This design can enhance the stability of the first light-shielding layer 103 and the fourth light-shielding layer 106. Capacitors can be formed between the first light-shielding layer 103 and the second power supply voltage line 111, and between the fourth light-shielding layer 106 and the second power supply voltage line 111, thereby preventing the first light-shielding layer 103 and the fourth light-shielding layer 106 from drifting when the gate signal is not turned on.

[0107] For example, Figure 4 This is a schematic diagram of the planar structure of another display substrate provided in at least one embodiment of the present disclosure, as shown below. Figure 4As shown, the orthographic projections of the second power supply voltage line 111 on the first substrate 101, the orthographic projections of the first light-shielding layer 103, the second light-shielding layer 104, the third light-shielding layer 105, and the fourth light-shielding layer 106 on the first substrate 101 all have overlapping portions.

[0108] For example, such as Figure 4 As shown, the overlapping area of ​​the orthographic projection of the second power supply voltage line 111 on the first substrate 101 and the orthographic projection of the first light-shielding layer 103 on the first substrate 101 is greater than the overlapping area of ​​the orthographic projection of the second power supply voltage line 111 on the first substrate 101 and the orthographic projection of the second light-shielding layer 104 on the first substrate 101, and balances the capacitance between the first light-shielding layer 103 and the second power supply voltage line 111, and between the fourth light-shielding layer 106 and the second power supply voltage line 111.

[0109] For example, such as Figure 4 As shown, the overlapping area of ​​the orthographic projection of the second power supply voltage line 111 on the first substrate 101 and the orthographic projection of the first light-shielding layer 103 on the first substrate 101 is greater than the overlapping area of ​​the orthographic projection of the second power supply voltage line 111 on the first substrate 101 and the orthographic projection of the third light-shielding layer 105 on the first substrate 101. This design can enhance the stability of the first light-shielding layer 103 and the third light-shielding layer 105, and balance the capacitance between the first light-shielding layer 103 and the second power supply voltage line 111, and between the third light-shielding layer 105 and the second power supply voltage line 111.

[0110] For example, such as Figure 4As shown, the overlapping area of ​​the orthographic projection of the second power supply voltage line 111 on the first substrate 101 and the orthographic projection of the first light-shielding layer 103 on the first substrate 101 is greater than the overlapping area of ​​the orthographic projection of the second power supply voltage line 111 on the first substrate 101 and the orthographic projection of the fourth light-shielding layer 106 on the first substrate 101. Similarly, the overlapping area of ​​the orthographic projection of the second power supply voltage line 111 on the first substrate 101 and the orthographic projection of the fourth light-shielding layer 106 on the first substrate 101 is greater than the overlapping area of ​​the orthographic projection of the second power supply voltage line 111 on the first substrate 101 and the orthographic projection of the third light-shielding layer 105 on the first substrate 101. The overlapping area of ​​the orthographic projection of the second power supply voltage line 111 on the first substrate 101 and the orthographic projection of the third light-shielding layer 105 on the first substrate 101 is greater than the overlapping area of ​​the orthographic projection of the second power supply voltage line 111 on the first substrate 101 and the orthographic projection of the second light-shielding layer 104 on the first substrate 101. This design can enhance the stability of the first light-shielding layer 103, the second light-shielding layer 104, the third light-shielding layer 105 and the fourth light-shielding layer 106, and balance the capacitance between the first light-shielding layer 103 and the second power supply voltage line 111, between the second light-shielding layer 104 and the second power supply voltage line 111, between the third light-shielding layer 105 and the second power supply voltage line 111, and between the fourth light-shielding layer 106 and the second power supply voltage line 111.

[0111] For example, in one example, in a first sub-pixel 1021, the overlapping area of ​​the orthographic projection of the second power supply voltage line 111 onto the first substrate 101 and the orthographic projection of the first light-shielding layer 103 onto the first substrate 101 is 0.03 to 0.30 square micrometers. In a second sub-pixel 1022, the overlapping area of ​​the orthographic projection of the second power supply voltage line 111 onto the first substrate 101 and the orthographic projection of the fourth light-shielding layer 106 onto the first substrate 101 is 0.02 to 0.20 square micrometers. In a third sub-pixel 1023, the overlapping area of ​​the orthographic projection of the second power supply voltage line 111 onto the first substrate 101 and the orthographic projection of the third light-shielding layer 105 onto the first substrate 101 is 0 to 0.05 square micrometers, and in a fourth sub-pixel 1024, the overlapping area of ​​the orthographic projection of the second power supply voltage line 111 onto the first substrate 101 and the orthographic projection of the second light-shielding layer 104 onto the first substrate 101 is 0 to 0.08 square micrometers.

[0112] For example, the second power supply voltage line 111 extending along the second direction Y can be a curved extension, a broken line extension, or a straight line extension, as long as the overall extension direction of the second power supply voltage line 111 is along the second direction Y. Figures 1-4 In the structure shown, the second power supply voltage lines 111 all extend along a straight line.

[0113] For example, Figure 5 This is a schematic diagram of the planar structure of another display substrate provided in at least one embodiment of the present disclosure, as shown below. Figure 5 As shown, the second power supply voltage line 111 includes a first part 111a and a second part 111b that are separated from each other. The first part 111a and the second part 111b are connected to the first power supply voltage line 110 through different via structures. For example, by configuring the second power supply voltage line 111 to include multiple parts that are separated from each other and are not directly connected, it is possible to avoid the second power supply voltage line 111 being too long, which would result in too much charge accumulating on the second power supply voltage line 111.

[0114] For example, in Figure 5 In the structure shown, both the first part 111a and the second part 111b extend along a curve, but the embodiments of this disclosure are not limited to this, and the first part 111a and the second part 111b may also extend along a straight line.

[0115] For example, such as Figure 5 As shown, the first source S11 of the first driving transistor T11 in the first part 111a and the first pixel circuit 1021a, and the second source S12 of the second driving transistor T12 in the second pixel circuit 1022a are connected. The third source S13 of the third driving transistor T13 in the second part 111b and the third source S14 of the fourth driving transistor T14 in the fourth pixel circuit 1024a are connected. This can balance the charge accumulated in the first part 111a and the second part 111b, making the charge more dispersed.

[0116] For example, Figure 6 This is a schematic diagram of the planar structure of another display substrate provided in at least one embodiment of the present disclosure, as shown below. Figure 6 As shown, the extension direction of the first part 111a is parallel to the extension direction of the second part 111b. Both the first part 111a and the second part 111b extend along a straight line. The first part 111a is connected to the first source S11 of the first driving transistor T11 in the first pixel circuit 1021a and the second source S12 of the second driving transistor T12 in the second pixel circuit 1022a. The second part 111b is connected to the third source S13 of the third driving transistor T13 in the third pixel circuit 1023a and the fourth source S14 of the fourth driving transistor T14 in the fourth pixel circuit 1024a. The first part 111a is located on the side of the second part 111b closer to the second sensing line 109, which makes the wiring process easier.

[0117] For example, such as Figure 6As shown, the first part 111a is connected to the middle region of the first source S11 and the second source S12, and the second part 111b is connected to the edge of the third source S13 away from the second sensing line 109 and the edge of the fourth source S14 away from the second sensing line 109. This allows for a more precise size design of the display substrate.

[0118] For example, Figure 7 This is a schematic diagram of the planar structure of another display substrate provided in at least one embodiment of the present disclosure, as shown below. Figure 7 As shown, both the first portion 111a and the second portion 111b extend along a zigzag line. The first portion 111a connects to the edge of the first source S11 away from the second induction line 109 and to the central region of the third source S13. The second portion 111b connects to the edge of the second source S12 away from the second induction line 109 and to the central region of the fourth source S14. The first portion 111a and the second portion 111b are electrically connected to the first power supply voltage line 110 through the same via structure. The fact that both the first portion 111a and the second portion 111b extend along a zigzag line allows for flexible adjustment of the connection positions between the second power supply voltage line 111 and the first source S11, the second source S12, the third source S13, and the fourth source S14, depending on the circuit design.

[0119] For example, Figure 8A for Figures 1-3 A schematic diagram of the cross-sectional structure of the display substrate along line A-A' is shown in the figure. Figure 8A As shown, the first drain D11 and the first light-shielding layer 103 are connected through a first via V11, which sequentially penetrates the interlayer insulating layer 112, the gate insulating layer 113, and the buffer layer 114. Figure 8A As shown, the first drain D11 and the active layer 115 are connected through a second via V12, and the first source S11 and the active layer 115 are connected through a second via V12, which sequentially penetrates the interlayer insulating layer 112 and the gate insulating layer 113. Figure 8A In the structure shown, the gate G11 is disposed on the side of the active layer 115 away from the first substrate 101. Of course, the embodiments disclosed herein are not limited to this, and the gate G11 may also be disposed on the side of the active layer 115 close to the first substrate 101.

[0120] For example, Figure 8B for Figure 4 A schematic diagram of the cross-sectional structure of the display substrate along lines B-B' and C-C' is shown in the figure. Figure 8BAs shown, a passivation layer 121 and a planarization layer 122 are provided on the side of the first drain D11 and the first source S11 away from the first substrate 101. A first electrode 123 is provided on the side of the planarization layer 122 away from the first substrate 101. The first electrode 123 can be an anode, and the first electrode 123 is connected to the first drain D11. A first color light-emitting unit 1021e, a second color light-emitting unit 1022e, a third color light-emitting unit 1023e, and a fourth color light-emitting unit 1024e are arranged side by side on the side of the first electrode 123 away from the first substrate 101.

[0121] For example, in one example, the first color light-emitting unit 1021e, the second color light-emitting unit 1022e, the third color light-emitting unit 1023e, and the fourth color light-emitting unit 1024e can be a red light-emitting unit, a green light-emitting unit, a blue light-emitting unit, and a white light-emitting unit, respectively. The first color light-emitting unit 1021e, the second color light-emitting unit 1022e, and the third color light-emitting unit 1023e can be a first color light-emitting layer that emits a first color light, a second color light-emitting layer that emits a second color light, and a third color light-emitting layer that emits a third color light, respectively.

[0122] For example, in another example, the first color light-emitting unit 1021e, the second color light-emitting unit 1022e, the third color light-emitting unit 1023e and the fourth color light-emitting unit 1024e can be a combination of a white light-emitting element and a first filter layer, a second filter layer, a third filter layer and a light-transmitting layer, wherein the first filter layer, the second filter layer and the third filter layer can be a red filter layer, a green filter layer and a blue filter layer, respectively.

[0123] For example, a second electrode is also provided on the side of the first color light-emitting unit 1021e, the second color light-emitting unit 1022e, the third color light-emitting unit 1023e, and the fourth color light-emitting unit 1024e away from the first substrate 101. This second electrode can be a cathode. Other structures of the display substrate 100 can refer to conventional designs, and the embodiments disclosed herein are not limited thereto.

[0124] It should be noted that the thin-film transistor in the embodiments of this disclosure can be a bottom-gate thin-film transistor or a top-gate thin-film transistor. Figure 8A and Figure 8B This explanation uses a top-gate thin-film transistor as an example.

[0125] For example, Figure 9 This is a schematic diagram of the planar structure of another display substrate provided in at least one embodiment of the present disclosure, as shown below. Figure 9As shown, the display substrate 100 also includes a first gate line 116 extending along the second direction Y, and a first gate 117 extending from the first gate line 116 and extending toward the side near the second power supply voltage line 111. The planar shape of the first light-shielding layer 103 includes a first sub-part 103a and a second sub-part 103b extending along the first direction X. There is a gap between the first light-shielding layer 103 and the first gate line 116 and the first gate 117, such that there is a first capacitance between the first light-shielding layer 103 and the first gate line 116, and a second capacitance between the first light-shielding layer 103 and the first gate 117. The first distance W1 between the first side 103a' of the first sub-part 103a near the first gate line 116 and the first gate line 116 is greater than the second distance W2 between the second side 103b' of the second sub-part 103b near the first gate 117 and the first gate 117. Since the area of ​​the first sub-part 103a is larger than the area of ​​the second sub-part 103b on a plane parallel to the main surface of the first substrate 101, by setting the first distance W1 between the first side 103a' of the first sub-part 103a near the first gate line 116 and the first gate line 116 to be greater than the second distance W2 between the second side 103b' of the second sub-part 103b near the first gate 117 and the first gate 117, it can be ensured that the first capacitance between the first light-shielding layer 103 and the first gate line 116 is equal to or approximately equal to the second capacitance between the first light-shielding layer 103 and the first gate 117.

[0126] For example, such as Figure 9 As shown, on a plane parallel to the main surface of the first substrate 101, the overall shape of the first sub-part 103a and the second sub-part 103b of the first light-shielding layer 103 includes a stepped shape, which is located at the edge of the first light-shielding layer 103 near the first gate line 116.

[0127] For example, the first sub-part 103a and the second sub-part 103b of the first light-shielding layer 103 can be a single unit or connected by a bridging structure, and the embodiments disclosed herein do not limit this.

[0128] It should be noted that, although Figure 9 The design shown is in the first sub-pixel 1021. The above structural design can also be found in the second, third, and fourth sub-pixels. That is, the second light-shielding layer 104, the third light-shielding layer 105, and the fourth light-shielding layer 106 can all have a structure similar to the first light-shielding layer 103, consisting of two parts.

[0129] For example, Figure 10 This is a schematic diagram of the planar structure of another display substrate provided in at least one embodiment of the present disclosure, as shown below. Figure 10As shown, the second sensing line 109 comprises two separate parts, which are connected to the first sensing line 108 via different via structures. The first sensing line 108 and the first power supply voltage line 110 are arranged adjacent to each other. Both the first sensing line 108 and the first power supply voltage line 110 are disposed between the second sub-pixel 1022 and the fourth sub-pixel 1024. For example, by configuring the second sensing line 109 to comprise two separate parts that are not directly connected, excessive charge accumulation on the second sensing line 109 due to its excessive length can be avoided. Other structural designs on the display substrate 100 can be found in the relevant descriptions above and will not be repeated here.

[0130] For example, Figure 11 This is a schematic diagram of the planar structure of another display substrate provided in at least one embodiment of the present disclosure, as shown below. Figure 11 As shown, the display substrate 100 also includes a second gate line 118 parallel to the first gate line 116. The first gate line 117 is configured as the gate of the first switching transistor N11, and the second gate line 118 is configured as the gate of the first sensing transistor M11 included in the first pixel circuit 1021a, the gate of the second sensing transistor M12 included in the second pixel circuit 1022a, the gate of the third sensing transistor M13 included in the third pixel circuit 1023a, and the gate of the fourth sensing transistor M14 included in the fourth pixel circuit 1024a. The display substrate 100 includes both the first gate line 116 and the second gate line 118, such that in a sub-pixel, the switching transistor (e.g., the first switching transistor) and the corresponding sensing transistor (e.g., the first sensing transistor) are controlled by different control lines, thereby making the adjustment of the switching transistor and sensing transistor in the same sub-pixel more flexible.

[0131] For example, the above Figures 1-11 The display substrates in all examples are organic light-emitting diode (OLED) display substrates, and the first, second, third, and fourth light-emitting elements are all OLEDs. The display substrate includes multiple gate lines and multiple data lines to provide scan signals (control signals) and data signals to the multiple sub-pixels, thereby driving the multiple sub-pixels. The pixel circuit includes a driving sub-circuit for driving the light-emitting elements to emit light and a detection sub-circuit for detecting the electrical characteristics of the sub-pixel to achieve external compensation. This disclosure does not limit the specific structure of the pixel circuit.

[0132] For example, Figure 12 This is a schematic diagram of a 3T1C pixel circuit for a display substrate provided in at least one embodiment of the present disclosure. As needed, the pixel circuit may further include a compensation circuit and a reset circuit, etc., and the embodiments of the present disclosure do not limit this.

[0133] For example, such as Figure 12 As shown, the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst. For example, the first transistor T1 can be a driving transistor, the second transistor T2 can be a switching transistor, and the third transistor T3 can be a sensing transistor. The first electrode of the second transistor T2 is electrically connected to the first capacitor electrode of the storage capacitor Cst and the gate of the first transistor T1. The second electrode of the second transistor T2 is configured to receive a data signal GT. The second transistor T2 is configured to write the data signal DT into the gate of the first transistor T1 and the storage capacitor Cst in response to a first control signal G1. The first electrode of the first transistor T1 is electrically connected to the second electrode of the storage capacitor Cst and configured to be electrically connected to the first electrode of the light-emitting element. The second electrode of the first transistor T1 is configured to receive a first power supply voltage V1 (e.g., a high power supply voltage VDD). The first transistor T1 is configured to control the current used to drive the light-emitting element under the control of the voltage at its gate. The first electrode of the third transistor T3 is electrically connected to the first electrode of the first transistor T1 and the second electrode of the storage capacitor Cst. The second electrode of the third transistor T3 is configured to be connected to a first detection line to connect to an external detection circuit. The third transistor T3 is configured to detect the electrical characteristics of its sub-pixel in response to a second control signal G2 to achieve external compensation. These electrical characteristics include, for example, the threshold voltage and / or carrier mobility of the first transistor T1, or the threshold voltage and driving current of the light-emitting element. The external detection circuit is, for example, a conventional circuit including a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC), etc., which will not be described in detail in the embodiments of this disclosure.

[0134] For example, the transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The embodiments of this disclosure will use thin-film transistors as an example for explanation. The source and drain of the transistors used here can be structurally symmetrical, so their source and drain structures can be indistinguishable. Furthermore, transistors can be classified into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage). It should be noted that in the following description, the transistors will be described as... Figure 13 The example described uses an N-type transistor, but the embodiments of this disclosure are not limited to this and may also use other types of transistors.

[0135] The following is combined Figures 13-15 The signal timing diagram shown is for Figure 12 The working principle of the pixel circuit shown will be explained, in which... Figure 13 for Figure 12 The diagram shown illustrates the signal timing of the pixel circuit during the display process. Figure 14 for Figure 12 The diagram shown is a timing diagram of the first signal of the pixel circuit during the detection process. Figure 15 for Figure 12 The second signal timing diagram of the pixel circuit during the detection process is shown.

[0136] For example, such as Figure 13 As shown, the display process of each frame of the image includes a data writing and reset phase 1 and a light emission phase 2. Figure 13 The timing waveforms of each signal in each stage are shown. One working process of the 3T1C pixel circuit includes: In the data writing and reset stage 1, the first control signal G1 and the second control signal G2 are both on signals, the second transistor T2 and the third transistor T3 are turned on, the data signal DT is transmitted to the gate of the first transistor T1 through the second transistor T2, the analog-to-digital converter writes a reset signal to the first electrode of the light-emitting element (e.g., the anode of the OLED) through the third transistor T3, the first transistor T1 is turned on and generates a driving current to charge the first electrode of the light-emitting element to the working voltage; In the light-emitting stage 2, the first control signal G1 and the second control signal G2 are both off signals. Due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged, the first transistor T1 operates in saturation and the current remains unchanged, and drives the light-emitting element to emit light.

[0137] For example, Figure 14 The diagram shows the signal timing of the pixel circuit during threshold voltage detection. One operating process of the 3T1C pixel circuit includes: both the first control signal G1 and the second control signal G2 are on signals; the second transistor T2 and the third transistor T3 are turned on; the data signal DT is transmitted to the gate of the first transistor T1 via the second transistor T2; the analog-to-digital converter writes a reset signal to the first electrode (node ​​S) of the light-emitting element through the detection line connected to the third transistor T3 and the third transistor T3; the first transistor T1 is turned on and charges node S until it is turned off; then, the threshold voltage of the first transistor T1 can be obtained by sampling the voltage on the detection line through the digital-to-analog converter. This process can, for example, be performed when the display device formed on the display substrate is in a power-off state.

[0138] For example, Figure 15The diagram shows the signal timing of the pixel circuit during threshold voltage detection. One operation of the 3T1C pixel circuit includes: In the first stage, both the first control signal G1 and the second control signal G2 are on, the second transistor T2 and the third transistor T3 are turned on, and the data signal DT is transmitted to the gate of the first transistor T1 via the second transistor T2; the analog-to-digital converter writes a reset signal to the first electrode (node ​​S) of the light-emitting element through the detection line connected to the third transistor T3 and the third transistor T3; In the second stage, the first control signal G1 is off, the second control signal G2 is on, the second transistor T2 is off, the third transistor T3 is on, and the detection line connected to the third transistor T3 is floated. Due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains constant, the first transistor T1 operates in saturation with a constant current, and drives the light-emitting element to emit light. Then, the digital-to-analog converter samples the voltage on the detection line and, combined with the magnitude of the emitting current, calculates the carrier mobility in the first transistor T1. For example, this process can be performed during the blanking phase between display phases.

[0139] The electrical characteristics of the first transistor T1 can be obtained through the above detection, and the corresponding compensation algorithm can be implemented.

[0140] It is understandable that the first control signal G1 and the second control signal G2 may not be activated simultaneously. For example, one operating process of the 3T1C pixel circuit includes: in the first stage, the first control signal G1 is activated before the second control signal G2.

[0141] For example, the display substrate 100 may further include a data driving circuit and a scan driving circuit. The data driving circuit is configured to output a data signal, such as the aforementioned data signal DT, as needed (e.g., an image signal from a display device including the display substrate is input). The pixel circuit of each sub-pixel is further configured to receive the data signal and apply it to the gate of the first transistor. The scan driving circuit is configured to output various scan signals, such as the aforementioned first control signal G1 and second control signal G2, which may be, for example, an integrated circuit chip (IC) or a gate drive circuit (GOA) directly fabricated on the display substrate.

[0142] For example, the display substrate 100 also includes a control circuit. For example, the control circuit is configured to control the data driving circuit to apply a data signal and to control the gate driving circuit to apply a scan signal. An example of this control circuit is a timing control circuit (T-con). The control circuit can take various forms, for example, including a processor and a memory, the memory including executable code, which the processor runs to perform the detection method described above.

[0143] For example, the processor can be a central processing unit (CPU) or other form of processing device with data processing capabilities and / or instruction execution capabilities, such as a microprocessor, a programmable logic controller (PLC), etc.

[0144] For example, the storage device may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and a processor may execute the functions expected by the program instructions. Various application programs and various data, such as electrical characteristic parameters obtained in the above-described detection method, may also be stored in the computer-readable storage medium.

[0145] For example, Figure 16 This is a cross-sectional structural schematic diagram of a display device provided in at least one embodiment of the present disclosure, such as... Figure 16 As shown, the display device 20 includes a display substrate 100 as described in any of the above embodiments and a cover plate 300 disposed opposite to the display substrate 100. The cover plate 300 includes a second substrate 301. A quantum dot layer 302 is disposed on the side of the second substrate 301 near the display substrate 100. The quantum dot layer 302 includes a plurality of quantum dot units 3021. The plurality of quantum dot units 3021 correspond one-to-one with a plurality of sub-pixels. The color of each of the plurality of quantum dot units 3021 is the same as the color of the corresponding sub-pixel. The plurality of quantum dot units 3021 can improve the color gamut of the display device 20.

[0146] For example, in one example, the plurality of quantum dot units 3021 includes a first quantum dot unit, a second quantum dot unit, and a third quantum dot unit, wherein the color of the first quantum dot unit is the same as the color of the first sub-pixel, the color of the second quantum dot unit is the same as the color of the second sub-pixel, and the color of the third quantum dot unit is the same as the color of the third sub-pixel.

[0147] For example, in one example, the first sub-pixel, the second sub-pixel, and the third sub-pixel are red sub-pixels, green sub-pixels, and blue sub-pixels, respectively. Correspondingly, the first quantum dot unit, the second quantum dot unit, and the third quantum dot unit are red quantum dot units, green quantum dot units, and blue quantum dot units, respectively.

[0148] For example, in one example, the plurality of quantum dot units 3021 includes a first quantum dot unit, a second quantum dot unit, a third quantum dot unit, and a fourth quantum dot unit, wherein the color of the first quantum dot unit is the same as the color of the first sub-pixel, the color of the second quantum dot unit is the same as the color of the second sub-pixel, the color of the third quantum dot unit is the same as the color of the third sub-pixel, and the color of the fourth quantum dot unit is the same as the color of the fourth sub-pixel.

[0149] For example, in one example, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, respectively. Correspondingly, the first quantum dot unit, the second quantum dot unit, the third quantum dot unit, and the fourth quantum dot unit are red quantum dot units, green quantum dot units, blue quantum dot units, and white quantum dot units, respectively.

[0150] For example, Figure 16 Taking the first sub-pixel and the first quantum dot unit as an example, a passivation layer 121 and a planarization layer 122 are provided on the side of the first drain D11 and the first source S11 away from the first substrate 101. A first electrode 123 is provided on the side of the planarization layer 122 away from the first substrate 101. The first electrode 123 can be an anode, and it is connected to the first drain D11. A pixel defining layer 124 is provided on the side of the first electrode 123 away from the first substrate 101, and a first color light-emitting unit 1021e is provided on the side of the pixel defining layer 124 away from the first substrate 101. In one example, the first color light-emitting unit 1021e is a first color light-emitting layer, and a second electrode 126 is provided on the side of the first color light-emitting unit 1021e away from the first substrate 101. The second electrode 126 can be a cathode.

[0151] For example, in another example, the first color light-emitting unit 1021e, the second color light-emitting unit 1022e, and the third color light-emitting unit 1023e may be a combination of a white light-emitting element and a first filter layer, a second filter layer, and a third filter layer. The first filter layer, the second filter layer, and the third filter layer may be a red filter layer, a green filter layer, and a blue filter layer, respectively. The embodiments disclosed herein do not limit this.

[0152] For example, in another example, the first color light-emitting unit 1021e, the second color light-emitting unit 1022e, the third color light-emitting unit 1023e and the fourth color light-emitting unit 1024e can be a combination of a white light-emitting element and a first filter layer, a second filter layer, a third filter layer and a light-transmitting layer. The first filter layer, the second filter layer and the third filter layer can be a red filter layer, a green filter layer and a blue filter layer, respectively. The embodiments of this disclosure are not limited in this respect.

[0153] For example, such as Figure 16 As shown, the first drain D11 and the first light-shielding layer 103 are connected through a first via V11, which sequentially penetrates the interlayer insulating layer 112 and the buffer layer 114. The first drain D11 and the active layer 115 are connected through a second via V12, and the first source S11 and the active layer 115 are connected through the second via V12, which penetrates the interlayer insulating layer 112. For example, the gate G11 is disposed on the side of the active layer 115 away from the first substrate 101.

[0154] It should be noted that the thin-film transistor in the embodiments of this disclosure can be a bottom-gate thin-film transistor or a top-gate thin-film transistor. The accompanying drawings of the embodiments of this disclosure are illustrated using a top-gate thin-film transistor as an example.

[0155] For example, the pixel defining layer 124 has multiple openings, and each opening of the pixel defining layer 124 corresponds one-to-one with the opening area of ​​each sub-pixel of the display device 20.

[0156] For example, the first color light-emitting unit 1021e covers the pixel defining layer 124 and multiple openings in the pixel defining layer 124. Figure 16 As shown, the portion of the first color light-emitting unit 1021e located within the plurality of openings in the pixel defining layer 124 is in contact with the first electrode 123 (anode), while the portion of the first color light-emitting unit 1021e covering the pixel defining layer 124 is not in contact with the first electrode 123 (anode). Thus, when the first color light-emitting unit 1021e performs its light-emitting function, the portion of the first color light-emitting unit 1021e that is not in contact with the pixel defining layer 124 emits light, while the portion of the first color light-emitting unit 1021e covering the pixel defining layer 124 does not emit light.

[0157] For example, the first color light-emitting unit 1021e is a first color light-emitting layer. In other embodiments, in addition to the first color light-emitting layer, the first color light-emitting unit 1021e also includes one or more of the following: an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL), and a hole injection layer (HIL).

[0158] For example, the display substrate 100 further includes a first thin-film encapsulation layer 129 and a second thin-film encapsulation layer 127. The second thin-film encapsulation layer 127 covers the side of the second electrode 126 (cathode) away from the first substrate 101, serving an encapsulation function. The first thin-film encapsulation layer 129 can be used to encapsulate the quantum dot layer mentioned later. The first thin-film encapsulation layer 129 is disposed on the side of the support layer 132 away from the second substrate 302. After the display substrate 100 and the cover plate 300 are assembled to form the display device 20, the first thin-film encapsulation layer 129 and the second thin-film encapsulation layer 127 are disposed opposite to each other.

[0159] For example, the second thin-film encapsulation layer 127 can be a highly water-resistant film layer, which can be used to prevent external water and oxygen from affecting the display substrate 100. For example, the second thin-film encapsulation layer 127 can be made of materials such as silicon nitride or silicon oxide.

[0160] For example, such as Figure 16 As shown, the display device 20 also includes a filler material 128 disposed between the cover plate 300 and the display substrate 100. The filler material 128 can fill the gap formed after the cover plate 300 and the display substrate 100 of the display device 20 are assembled. Specifically, the filler material 128 is disposed between the first thin-film encapsulation layer 129 and the second thin-film encapsulation layer 127. The first thin-film encapsulation layer 129, the second thin-film encapsulation layer 127, and the filler material 128 disposed between them constitute an encapsulation structure, serving to encapsulate the display device 100. The filler material 128 can both support the cover plate 300 of the display device 20 and encapsulate the cover plate 300 and the display substrate 100 of the display device 20. When the filler material 128 is a curable transparent liquid, the display device 100 also includes a filler material barrier structure disposed on the side of the second thin film encapsulation layer 127 of the display substrate 100 away from the first substrate 101. The filler material barrier structure is arranged in a ring around the periphery of the second thin film encapsulation layer 127, and the filler material 128 is filled in the area surrounded by the filler material barrier structure.

[0161] For example, such as Figure 16 As shown, each opening in the pixel defining layer 124 of the display substrate 100 corresponds one-to-one with the opening area of ​​each sub-pixel of the display device 20, and each opening area S of the cover plate 300 of the display device 20 corresponds one-to-one with each opening in the pixel defining layer 124 of the display substrate 100. When the display device 20 performs its display function, the light emitted from the portion of the first color light-emitting unit 1021e that is not in contact with the pixel defining layer 124 enters the human eye after passing through each opening area S of the cover plate 300 of the display device 20, thereby realizing the display of the image.

[0162] For example, such as Figure 16As shown, the cover plate 300 includes a second substrate 301, and a black matrix 303 and a support layer 304 stacked on the side of the second substrate 301 near the display substrate 100. Both the black matrix 303 and the support layer 304 have multiple openings, and the multiple openings of the black matrix 303 at least partially overlap with the multiple openings of the support layer 304, for example, largely overlap or substantially overlap, to form the aforementioned multiple opening regions S. The black matrix 303 is used to prevent lateral light emitted by the first color light-emitting unit 1021e of the display substrate 100 from illuminating adjacent sub-pixels, thereby preventing color mixing problems in the display device 20. The support layer 304 has a specific height and can be used as a spacer. After the display substrate 100 and the cover plate 300 are assembled, the support layer 304 can be used to support the cover plate 300 of the display device 20.

[0163] For example, in one example, the black matrix 303 may be located away from the second substrate 301 relative to the support layer 304. In another example, the black matrix 303 may be located close to the second substrate 301 relative to the support layer 304.

[0164] For example, the embodiments of this disclosure do not limit the material of the black matrix 303, and the material can be selected based on the criterion of preventing pixel light leakage. For example, the material of the black matrix 303 can be a metallic material, such as chromium, aluminum, silver, or an aluminum-silver alloy.

[0165] For example, such as Figure 16 As shown, the cover plate 300 of the display device 20 also includes a quantum dot layer 302 disposed on the second substrate 301. The quantum dot layer 302 includes a plurality of quantum dot units 3021, each quantum dot unit 3021 being located in an opening region S.

[0166] For example, since each opening region S corresponds one-to-one with each opening of the pixel defining layer 124 of the display substrate 100, each quantum dot unit 3021 located in each opening region S also corresponds one-to-one with each opening of the pixel defining layer 124. The light emitted from the portion of the first color light-emitting unit 1021e of the display substrate 100 that is not in contact with the pixel defining layer 124 passes through each quantum dot unit 3021 as it passes through each opening region S.

[0167] For example, the quantum dots in the quantum dot unit 3021 are spherical semiconductor nanoparticles composed of group II-VI or III-V elements, with particle sizes ranging from a few nanometers to tens of nanometers. Due to the quantum confinement effect, the originally continuous energy bands of the quantum dot material become discrete energy level structures, and the quantum dots can emit visible light when excited by external light. The frequency of the emitted visible light changes with the particle size of the quantum dots, and the color of the emitted light can be controlled by adjusting the particle size of the quantum dots. In the embodiments of this disclosure, each quantum dot unit 3021 can emit light of a corresponding color when excited by the light emitted by the first color light-emitting unit 1021e of the display substrate 100, thereby enhancing the color gamut.

[0168] For example, due to the limitations of quantum dot material properties, quantum dot units may not be able to completely absorb the excitation light illuminating them. Increasing the thickness of the quantum dot units can improve their luminescence efficiency by maximizing their absorption of excitation light. Alternatively, a black matrix can be used as a barrier structure to isolate the individual quantum dot units, preventing color mixing between units of different colors. However, due to limitations in the material and manufacturing process of the black matrix, its thickness cannot be achieved at 2 μm or more, thus limiting the thickness of individual quantum dot units. Therefore, relying solely on a black matrix as a barrier structure to isolate the individual quantum dot units makes it difficult to manufacture very thick quantum dot units, thereby restricting their thickness.

[0169] For example, each quantum dot unit 3021 is located within the opening region S formed by the black matrix 303 and the support layer 304. The black matrix 303 and the support layer 304 constitute a barrier structure for each quantum dot unit 3021. The material of the support layer 304 can be a material that can be made relatively thick. Thus, since the support layer 304 can be made relatively thick, the barrier structure formed by the black matrix 303 and the support layer 304 can also be made relatively thick. This allows the thickness of each first color light-emitting unit 1021e to be made relatively thick, thereby enabling the first color light-emitting unit 1021e to absorb as much excitation light as possible, thereby improving the luminous efficiency of the first color light-emitting unit 1021e and thus improving the luminous efficiency of the display device 100.

[0170] For example, such as Figure 16 As shown, the display device 100 can be a top-emitting display device. The light emitted by the first color light-emitting unit 1021e of the display substrate 100 passes through the second electrode 126, the second thin film encapsulation layer 127 and the first thin film encapsulation layer 129 in sequence and irradiates the quantum dot layer 302.

[0171] For example, such as Figure 16As shown, the cover plate 300 of the display device 20 provided in the embodiments of this disclosure further includes a color filter layer 305 disposed between the first color light-emitting unit 1021e and the second substrate 301. The color filter layer 305 includes a plurality of filter units 3051, each filter unit 3051 being located within an opening region S. For example, the filter unit 3051 located within an opening region S corresponds to the same color as the quantum dot unit 3021. For example, in Figure 16 In the structure shown, the filter unit 3051 is a red filter unit.

[0172] For example, in one example, filter unit 3051 may include multiple red filter units, multiple green filter units and multiple blue filter units, and in the case where multiple quantum dot units 3021 include multiple red quantum dot units and multiple green quantum dot units, the multiple red filter units and multiple red quantum dot units are located in an opening region S, and the multiple green filter units and multiple green quantum dot units are located in an opening region S.

[0173] Embodiments of this disclosure also provide a method for fabricating a display substrate, the method comprising: providing a first substrate; forming a plurality of sub-pixels on the first substrate, wherein forming the plurality of sub-pixels includes forming a first sub-pixel and a second sub-pixel; forming the first sub-pixel includes forming a first pixel circuit and a first effective light-emitting region; forming the second sub-pixel includes forming a second pixel circuit and a second effective light-emitting region; forming a first light-shielding layer between the first pixel circuit and the first substrate, wherein the orthographic projection of the first light-shielding layer on the first substrate and the orthographic projection of the first pixel circuit on the first substrate at least partially overlap; and forming a second light-shielding layer between the second pixel circuit and the first substrate. The second light-shielding layer has its orthographic projection on the first substrate and the orthographic projection of the second pixel circuit on the first substrate at least partially overlap; the wavelength of the light emitted from the first effective light-emitting area is greater than the wavelength of the light emitted from the second effective light-emitting area; the ratio of the area of ​​the first light-shielding layer to the area of ​​the first sub-pixel is a, and the ratio of the area of ​​the second light-shielding layer to the area of ​​the second sub-pixel is b; the ratio M1 of a to b ranges from 1.020 to 1.120. The display substrate formed by this preparation method can adjust the aperture ratio of multiple sub-pixels 102 to achieve a better final light mixing effect. Moreover, the process of preparing the display substrate is simpler and has higher luminous efficiency.

[0174] For example, Figure 17 A flowchart illustrating a method for fabricating a display substrate according to at least one embodiment of this disclosure is shown below. Figure 17 As shown, the preparation method includes the following steps.

[0175] S11: Provides a first substrate;

[0176] S12: A plurality of sub-pixels are formed on a first substrate, wherein forming the plurality of sub-pixels includes forming a first sub-pixel and a second sub-pixel;

[0177] S13: Forming the first sub-pixel includes forming a first pixel circuit and a first effective light-emitting area;

[0178] S14: Forming the second sub-pixel includes forming a second pixel circuit and a second effective light-emitting area;

[0179] S15: A first light-shielding layer is formed between the first pixel circuit and the first substrate, wherein the orthographic projection of the first light-shielding layer on the first substrate and the orthographic projection of the first pixel circuit on the first substrate at least partially overlap.

[0180] S16: A second light-shielding layer is formed between the second pixel circuit and the first substrate. The orthographic projection of the second light-shielding layer on the first substrate and the orthographic projection of the second pixel circuit on the first substrate at least partially overlap. The wavelength of the light emitted from the first effective light-emitting region is greater than the wavelength of the light emitted from the second effective light-emitting region. The ratio of the area of ​​the first light-shielding layer to the area of ​​the first sub-pixel is a, and the ratio of the area of ​​the second light-shielding layer to the area of ​​the second sub-pixel is b. The range of the ratio M1 of a and b is 1.020 to 1.120.

[0181] For example, the material of the first substrate may include glass, plastic, or other light-transmitting materials.

[0182] For example, the multiple sub-pixels formed on the first substrate can be arranged in a matrix, that is, multiple sub-pixels are provided in both the first and second intersecting directions.

[0183] For example, the first sub-pixel and the second sub-pixel included in the plurality of sub-pixels may be two adjacent sub-pixels arranged side by side along the second direction in a pixel unit, or two mutually spaced sub-pixels arranged side by side along the second direction in a pixel unit. The embodiments of this disclosure do not limit this, as long as the first sub-pixel and the second sub-pixel are in the same pixel unit.

[0184] For example, in one instance, the first sub-pixel and the second sub-pixel are a red sub-pixel and a green sub-pixel, respectively. Correspondingly, the first effective light-emitting area is a red light-emitting area, and the second effective light-emitting area is a green light-emitting area. Typically, the light-emitting area of ​​the red sub-pixel is larger than that of the green sub-pixel, meaning the area of ​​the first effective light-emitting area is larger than that of the second effective light-emitting area. By setting the area of ​​the first light-shielding layer to be larger than the area of ​​the second light-shielding layer, the aperture ratio of multiple sub-pixels can be adjusted to achieve better light mixing. Furthermore, the fabrication process of this display substrate is simpler, and it has higher luminous efficiency.

[0185] For example, the first light-shielding layer and the second light-shielding layer can be formed using the same material in the same process step. The materials of the first light-shielding layer and the second light-shielding layer can be metal materials with light-shielding properties or other conductive materials with light-shielding properties. The embodiments of this disclosure do not limit this.

[0186] For example, when the ratio of a to b, M1, is less than 1.020, the ratio 'a' of the area of ​​the first light-blocking layer to the area of ​​the first sub-pixel is small, resulting in a large aperture ratio for the first sub-pixel and a small aperture ratio for the second sub-pixel, leading to poor final color mixing. When the ratio of a to b, M1, is greater than 1.120, the ratio 'a' of the area of ​​the first light-blocking layer to the area of ​​the first sub-pixel is large, resulting in a small aperture ratio for the first sub-pixel and a large aperture ratio for the second sub-pixel, also leading to poor final color mixing.

[0187] For example, in one example, the aperture ratio of the first sub-pixel is n1(1-a), and the aperture ratio of the second sub-pixel is n2(1-b). The formula (n1 / n2)(1-a) / (1-b) = M2*K1*K2 can be used to derive (1-a) / (1-b) = (n2 / n1)M2*K1*K2, where K1 is the ratio of the initial brightness of the second sub-pixel to the initial brightness of the first sub-pixel, K2 is the ratio of the lifetime of the second sub-pixel to the lifetime of the first sub-pixel, n1 is the ratio of the area of ​​the aperture region in the first sub-pixel to the area of ​​the portion of the first sub-pixel excluding the area blocked by the first light-shielding layer, and n2 is the area of ​​the aperture region in the second sub-pixel. The ratio of the product to the area of ​​the part outside the area blocked by the second light-shielding layer in the second sub-pixel, (n2 / n1)M2 has a value range of 1.000 to 1.130, and (1-a) / (1-b) has a value range of 0.877 to 0.997. M2 is a coefficient without a unit, only used to satisfy the equation (1-a) / (1-b)=(n2 / n1)M2*K1*K2. Moreover, (1-a) / (1-b) on the left side of the equation is a ratio without a unit, and (n2 / n1), K1, and K2 on the right side of the equation are also ratios without a unit. Therefore, M2 on the right side of the remaining equation is also without a unit, and is just a coefficient.

[0188] For example, the above formula (n1 / n2)(1-a) / (1-b)=M2*K1*K2 can be expressed as the following formula:

[0189] (Initial brightness of subpixel * aperture ratio of pixel / initial brightness of pixel unit) * luminous lifetime of subpixel = C 常数 The specific derivation process can be found in the relevant description of the display substrate mentioned above, and will not be repeated here.

[0190] For example, the process of forming one sub-pixel (e.g., the first sub-pixel) from a plurality of sub-pixels is as follows: Figures 18A-18H As shown, Figures 18A-18H Taking this sub-pixel as the first sub-pixel as an example, that is... Figures 18A-18H This diagram illustrates the formation process of a first sub-pixel, provided for at least one embodiment of this disclosure.

[0191] For example, such as Figure 18A As shown, a first substrate 101 is provided, and a first light-shielding layer 103 is formed on the first substrate 101. For example, the materials of the first substrate 101 and the first light-shielding layer 103 can be found in the above description of the display substrate, and will not be repeated here.

[0192] For example, a first light-shielding layer film can be formed on the first substrate 101. The process of forming the first light-shielding layer film includes evaporating a metal material with light-shielding properties or forming the first light-shielding layer film by magnetron sputtering. Then, the first light-shielding layer film is patterned by photolithography to form the first light-shielding layer 103.

[0193] For example, such as Figure 18B As shown, a buffer layer 114 and an active layer 115 are sequentially formed on the first light-shielding layer 103.

[0194] For example, the buffer layer 114 covers the entire first substrate 101, and the orthographic projections of the active layer 115 and the first light-shielding layer 103 on the first substrate 101 overlap. For example, the overlapping area of ​​the orthographic projections of the active layer 115 and the first light-shielding layer 103 on the first substrate 101 is 75% to 95% of the orthographic projection area of ​​the active layer 115 on the first substrate 101. For example, the overlapping area of ​​the orthographic projections of the active layer 115 and the first light-shielding layer 103 on the first substrate 101 is more than 90% of the orthographic projection area of ​​the active layer 115 on the first substrate 101.

[0195] For example, such as Figure 18C As shown, a gate insulating layer thin film and a first metal layer thin film are formed on the side of the active layer 115 away from the first substrate 101. The gate insulating layer thin film and the first metal layer thin film are patterned to form a gate insulating layer 113 and a first metal layer 133. The first metal layer 133 includes a second power supply voltage line 111, a first gate line 116 and a second sensing line 109.

[0196] For example, such as Figure 18DAs shown, an interlayer insulating layer 112 is formed on the side of the first metal layer 133 away from the first substrate 101, a first via V11 is formed through the interlayer insulating layer 112, the gate insulating layer 113 and the buffer layer 114, a second via V12 is formed through the interlayer insulating layer 112, and a plurality of third vias V13 are formed through the interlayer insulating layer 112 and the gate insulating layer 113.

[0197] For example, such as Figure 18E As shown, a second metal layer 134 is formed on the side of the interlayer insulating layer 112 away from the first substrate 101. This second metal layer 134 includes a first power supply voltage line 110, a data line 107, a first sensing line 108, a first source S11 of a first driving transistor T11, a first drain D11 of the first driving transistor T11, a source of a first switching transistor N11, a drain of the first switching transistor N11, a source of a first sensing transistor M11, and a drain of the first sensing transistor M11. The first source S11 of the first driving transistor T11 and the second power supply voltage line 111 are connected through a second via V12. The drain of the first sensing transistor M11 and the second sensing line 108 are connected through the second via V12. The first drain D11 of the first driving transistor T11 and the first light-shielding layer 103 are connected through the first via V11. The first source S11 of the first driving transistor T11 is connected to the active layer 115 through the third via V13. The first drain D11 of the first driving transistor T11 is connected to the active layer 115 through the third via V13. The source of the first switching transistor N11 is connected to the active layer 115 through the third via V13. The drain of the first switching transistor N11 is connected to the active layer 115 through the third via V13. The source of the first sensing transistor M11 is connected to the active layer 115 through the third via V13. The drain of the first sensing transistor M11 is connected to the active layer 115 through the third via V13.

[0198] For example, such as Figure 18F As shown, a passivation layer 121 and a planarization layer 122 are formed on the side of the second metal layer 134 away from the first substrate 101, and a fourth via V14 is formed through the passivation layer 121 and the planarization layer 122. For example, the fourth via V14 can be an anode via, that is, the anode formed subsequently can be electrically connected to the second metal layer 134 through the fourth via V14.

[0199] For example, such as Figure 18G As shown, a first electrode 123 is formed on the side of the planarization layer 122 away from the first substrate 101. The first electrode 123 is an anode and is electrically connected to the second metal layer 134 through a fourth via V14.

[0200] For example, such as Figure 18HAs shown, a first color light-emitting unit 1021e is formed on the side of the first electrode 123 away from the first substrate 101. The first color light-emitting unit 1021e includes a first color light-emitting layer. For example, the first color light-emitting layer is a light-emitting layer that emits red light.

[0201] For example, in one example, the formation process of the second, third, and fourth sub-pixels located in the same pixel unit as the first sub-pixel can be found in the relevant description of the formation process of the first sub-pixel, and will not be repeated here.

[0202] For example, in one example, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel can be a green sub-pixel, a blue sub-pixel, and a white sub-pixel, respectively. The structure of the final display substrate can be found in the relevant description of the display substrate above, and will not be repeated here.

[0203] The display substrate, its preparation method, and the display device provided in at least one embodiment of this disclosure have at least one of the following beneficial technical effects:

[0204] (1) The display substrate provided in at least one embodiment of the present disclosure adjusts the aperture ratio of different sub-pixels by designing the size of the light-shielding layer corresponding to different sub-pixels, so as to make the entire process of manufacturing the display substrate simpler.

[0205] (2) The display substrate provided in at least one embodiment of this disclosure sets the range of the ratio M1 of the ratio a of the area of ​​the first light-shielding layer to the area of ​​the first sub-pixel and the ratio b of the area of ​​the second light-shielding layer to the area of ​​the second sub-pixel to be 1.020 to 1.120, which can make the final color mixing effect better.

[0206] (3) The display substrate provided in at least one embodiment of the present disclosure can adjust the aperture ratio of the first sub-pixel and the second sub-pixel by setting the area of ​​the first light-shielding layer to be larger than the area of ​​the second light-shielding layer so as to achieve a better final light mixing effect. Moreover, the process of preparing the display substrate is simpler and the display substrate has higher luminous efficiency.

[0207] The following points need to be explained:

[0208] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0209] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0210] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0211] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A display substrate, comprising: First substrate; A plurality of sub-pixels are disposed on the first substrate, the plurality of sub-pixels including a first sub-pixel and a second sub-pixel; wherein... The first sub-pixel includes a first pixel circuit and a first effective light-emitting area; The second sub-pixel includes a second pixel circuit and a second effective light-emitting area; A first light-shielding layer is disposed between the first pixel circuit and the first substrate, and the orthographic projection of the first light-shielding layer on the first substrate and the orthographic projection of the first pixel circuit on the first substrate at least partially overlap. A second light-shielding layer is disposed between the second pixel circuit and the first substrate, and the orthographic projection of the second light-shielding layer on the first substrate and the orthographic projection of the second pixel circuit on the first substrate at least partially overlap. The area of ​​the first effective light-emitting region is larger than the area of ​​the second effective light-emitting region, and the area of ​​the first light-shielding layer is larger than the area of ​​the second light-shielding layer. The wavelength of the light emitted from the first effective light-emitting area is greater than the wavelength of the light emitted from the second effective light-emitting area. The ratio of the area of ​​the first light-shielding layer to the area of ​​the first sub-pixel is a, and the ratio of the area of ​​the second light-shielding layer to the area of ​​the second sub-pixel is b. The ratio M1 of a and b ranges from 1.020 to 1.

120.

2. The display substrate according to claim 1, wherein, The aperture ratio of the first sub-pixel is n1(1-a), and the aperture ratio of the second sub-pixel is n2(1-b). (1-a) / (1-b)=(n2 / n1)M2*K1*K2, where K1 is the ratio of the initial brightness of the second sub-pixel to the initial brightness of the first sub-pixel, K2 is the ratio of the lifetime of the second sub-pixel to the lifetime of the first sub-pixel, n1 is the ratio of the area of ​​the opening region in the first sub-pixel to the area of ​​the portion of the first sub-pixel excluding the area blocked by the first light-shielding layer, n2 is the ratio of the area of ​​the opening region in the second sub-pixel to the area of ​​the portion of the second sub-pixel excluding the area blocked by the second light-shielding layer, the value range of (n2 / n1)M2 is 1.000~1.130, and the value range of (1-a) / (1-b) is 0.877~0.

997.

3. The display substrate according to claim 2, wherein, The plurality of sub-pixels also includes a third sub-pixel; The third sub-pixel includes a third pixel circuit and a third effective light-emitting area; A third light-shielding layer is disposed between the third pixel circuit and the first substrate, and the orthographic projection of the third light-shielding layer on the first substrate and the orthographic projection of the third pixel circuit on the first substrate at least partially overlap. The wavelength of the light emitted from the third effective light-emitting region is less than the wavelength of the light emitted from the second effective light-emitting region, and on a plane parallel to the main surface of the first substrate, the area ratio c of the third light-shielding layer is equal to the ratio of the area of ​​the third light-shielding layer to the area of ​​the third sub-pixel, and the aperture ratio of the third sub-pixel is n3(1-c). (1-c) / (1-b)=(n2 / n3)M3*K3*K4, where K3 is the ratio of the initial brightness of the second sub-pixel to the initial brightness of the third sub-pixel, K4 is the ratio of the lifetime of the second sub-pixel to the lifetime of the third sub-pixel, n3 is the ratio of the area of ​​the opening region in the third sub-pixel to the area of ​​the part of the third sub-pixel excluding the area blocked by the third light-shielding layer, the value range of (n2 / n3)M3 is 0.190~0.260, and the value range of (1-c) / (1-b) is 1.002~1.

350.

4. The display substrate according to claim 3, wherein, The plurality of sub-pixels also includes a fourth sub-pixel; The fourth sub-pixel includes a fourth pixel circuit and a fourth effective light-emitting area; A fourth light-shielding layer is disposed between the fourth pixel circuit and the first substrate, and the orthographic projection of the fourth light-shielding layer on the first substrate and the orthographic projection of the fourth pixel circuit on the first substrate at least partially overlap. On a plane parallel to the main surface of the first substrate, the area ratio d of the fourth light-shielding layer is equal to the ratio of the area of ​​the fourth light-shielding layer to the area of ​​the fourth sub-pixel. The aperture ratio n4(1-d) of the fourth sub-pixel ranges from 0.230 to 0.950, where n4 is the ratio of the area of ​​the open region in the fourth sub-pixel to the area of ​​the part of the fourth sub-pixel excluding the area blocked by the fourth light-shielding layer.

5. The display substrate according to claim 3, wherein, The first sub-pixel further includes a first light-emitting element, the first pixel circuit controls the first light-emitting element to emit light, and the color of the light emitted by the first light-emitting element is the same as the color of the light emitted from the first effective light-emitting area; The second sub-pixel further includes a second light-emitting element, the second pixel circuit controls the second light-emitting element to emit light, and the color of the light emitted by the second light-emitting element is the same as the color of the light emitted from the second effective light-emitting area; The third sub-pixel also includes a third light-emitting element, the third pixel circuit controls the third light-emitting element to emit light, and the color of the light emitted by the third light-emitting element is the same as the color of the light emitted from the third effective light-emitting area.

6. The display substrate according to claim 4, wherein, The first sub-pixel further includes a first light-emitting element, and the first pixel circuit controls the first light-emitting element to emit light; The second sub-pixel also includes a second light-emitting element, and the second pixel circuit controls the second light-emitting element to emit light; The third sub-pixel also includes a third light-emitting element, and the third pixel circuit controls the third light-emitting element to emit light; The fourth sub-pixel also includes a fourth light-emitting element, and the fourth pixel circuit controls the fourth light-emitting element to emit light. A first filter layer, a second filter layer, a third filter layer, and a light-transmitting layer are respectively disposed on the side of the first light-emitting element, the second light-emitting element, the third light-emitting element, and the fourth light-emitting element away from the first substrate. The color of the light emitted from the first filter layer is the same as the color of the light emitted from the first effective light-emitting region, the color of the light emitted from the second filter layer is the same as the color of the light emitted from the second effective light-emitting region, the color of the light emitted from the third filter layer is the same as the color of the light emitted from the third effective light-emitting region, and the color of the light emitted from the light-transmitting layer is the same as the color of the light emitted from the fourth effective light-emitting region.

7. The display substrate according to claim 6, wherein, The transmittance of the material of the first filter layer is λ1, the transmittance of the material of the second filter layer is λ2, the transmittance of the material of the third filter layer is λ3, and the transmittance of the material of the light-transmitting layer is λ4; The total transmittance T(λ) of the first filter layer, the second filter layer, the third filter layer and the light-transmitting layer is T(λ) = n1(1-a)λ1 + n2(1-b)λ2 + n3(1-c)λ3 + n4(1-d)λ4, and the value of λ4 is in the range of 0.260~0.950; The sum of the transmittance of the first filter layer, the second filter layer, and the third filter layer satisfies the same condition as the transmittance of the light-transmitting layer: [n1(1-a)λ1+ n2(1-b)λ2+ n3(1-c)λ3]:[ n4(1-d)λ4]=1:1, and the value range of n4(1-d) is 0.260~0.

860.

8. The display substrate according to claim 6, wherein, On a plane parallel to the main surface of the first substrate, the ratio of the sum of the areas of the first filter layer, the second filter layer, the third filter layer, and the light-transmitting layer to the sum of the areas of the first light-shielding layer, the second light-shielding layer, the third light-shielding layer, and the fourth light-shielding layer ranges from 1.050 to 6.

800.

9. The display substrate according to claim 8, wherein, On a plane parallel to the main surface of the first substrate, the ratio of the area of ​​the first filter layer to the area of ​​the first light-shielding layer ranges from 2.000 to 3.

000.

10. The display substrate according to claim 8, wherein, On a plane parallel to the main surface of the first substrate, the ratio of the area of ​​the second filter layer to the area of ​​the second light-shielding layer ranges from 1.1074 to 1.6938.

11. The display substrate according to claim 4, further comprising: A data line and a first sensing line extending along a first direction, and a second sensing line extending along a second direction, wherein, The data line and the second sensing line intersect to define a plurality of pixel regions, each of the pixel regions having the sub-pixel; A first power supply voltage line parallel to the data line is provided between adjacent sub-pixels, and a second power supply voltage line parallel to the second direction is provided on the side of the first effective light-emitting area near the first light-shielding layer. The second power supply voltage line intersects with the first power supply voltage line and is connected to the first drain of the first driving transistor in the first pixel circuit. The orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the first light-shielding layer on the first substrate overlap.

12. The display substrate according to claim 11, wherein, The orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the fourth light-shielding layer on the first substrate overlap.

13. The display substrate according to claim 12, wherein, The orthographic projection of the second power supply voltage line on the first substrate overlaps with the orthographic projection of the third light-shielding layer on the first substrate, and also overlaps with the orthographic projection of the second light-shielding layer on the first substrate.

14. The display substrate according to claim 12, wherein, The overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the first light-shielding layer on the first substrate is greater than the overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the second light-shielding layer on the first substrate.

15. The display substrate according to claim 12, wherein, The overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the first light-shielding layer on the first substrate is greater than the overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the third light-shielding layer on the first substrate.

16. The display substrate according to claim 12, wherein, The overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the first light-shielding layer on the first substrate is greater than the overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the fourth light-shielding layer on the first substrate. The overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the fourth light-shielding layer on the first substrate is greater than the overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the third light-shielding layer on the first substrate. The overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the third light-shielding layer on the first substrate is greater than the overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the second light-shielding layer on the first substrate.

17. The display substrate according to claim 12, wherein, In one of the first sub-pixels, the overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the first light-shielding layer on the first substrate is 0.03~0.30 square micrometers. In a second sub-pixel, the overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the fourth light-shielding layer on the first substrate is 0.02~0.20 square micrometers; In one of the third sub-pixels, the overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the third light-shielding layer on the first substrate is 0~0.05 square micrometers. as well as In one of the fourth sub-pixels, the overlapping area of ​​the orthographic projection of the second power supply voltage line on the first substrate and the orthographic projection of the second light-shielding layer on the first substrate is 0~0.08 square micrometers.

18. The display substrate according to claim 11, wherein, The second power supply voltage line includes a first part and a second part that are separate from each other, and the first part and the second part are connected to the first power supply voltage line through different via structures.

19. The display substrate according to claim 18, wherein, The first drain of the first driving transistor in the first part and the first pixel circuit and the second drain of the second driving transistor in the second pixel circuit are connected; The second part and the third drain of the third driving transistor in the third pixel circuit are connected to the fourth drain of the fourth driving transistor in the fourth pixel circuit.

20. The display substrate according to claim 19, wherein, The extension direction of the first part is parallel to the extension direction of the second part. Both the first part and the second part extend along a straight line, and the first part is on the side of the second part closer to the second sensing line.

21. The display substrate according to claim 20, wherein, The first portion is connected to the middle region of the first drain and the second drain, and the second portion is connected to the edge of the third drain away from the second sensing line and the edge of the fourth drain away from the second sensing line.

22. The display substrate according to claim 19, wherein, Both the first portion and the second portion extend along a broken line. The first portion is connected to the edge of the first drain electrode away from the second sensing line and to the middle region of the second drain electrode. The second portion is connected to the edge of the third drain electrode away from the second sensing line and to the middle region of the fourth drain electrode.

23. The display substrate according to claim 19, wherein, The first drain and the first light-shielding layer are connected by a first via that sequentially penetrates the interlayer insulating layer, the gate insulating layer and the buffer layer.

24. The display substrate of claim 11, further comprising a first gate line extending along the second direction, and a first gate extending from the first gate line and toward a side close to the second power supply voltage line, wherein, The planar shape of the first light-shielding layer includes a first sub-part and a second sub-part extending along the first direction. The first distance between the first side of the first sub-part near the first gate line and the first gate line is greater than the second distance between the second side of the second sub-part near the first gate and the first gate.

25. The display substrate according to claim 24, further comprising a second gate line parallel to the first gate line, wherein, The first gate is configured as the gate of a first switching transistor, the second gate is configured as the gate of a first sensing transistor included in the first pixel circuit, the gate of a second sensing transistor included in the second pixel circuit, the gate of a third sensing transistor included in the third pixel circuit, and the gate of a fourth sensing transistor included in the fourth pixel circuit.

26. A display device comprising a display substrate according to any one of claims 1 to 25 and a cover plate disposed opposite to the display substrate, wherein, The cover plate includes a second substrate, and a quantum dot layer is disposed on the side of the second substrate near the display substrate. The quantum dot layer includes a plurality of quantum dot units, and the plurality of quantum dot units correspond one-to-one with the plurality of sub-pixels. The color of each of the plurality of quantum dot units is the same as the color of the corresponding sub-pixel.

27. The display device according to claim 26, further comprising: A black matrix is ​​disposed on the side of the second substrate near the display substrate, the black matrix having multiple openings, and each quantum dot unit is located in one of the openings.

28. A method for preparing a display substrate, comprising: Provide a first substrate; A plurality of sub-pixels are formed on the first substrate, wherein forming the plurality of sub-pixels includes forming a first sub-pixel and a second sub-pixel; Forming the first sub-pixel includes forming a first pixel circuit and a first effective light-emitting region; Forming the second sub-pixel includes forming a second pixel circuit and a second effective light-emitting area; A first light-shielding layer is formed between the first pixel circuit and the first substrate, wherein the orthographic projection of the first light-shielding layer on the first substrate and the orthographic projection of the first pixel circuit on the first substrate at least partially overlap. A second light-shielding layer is formed between the second pixel circuit and the first substrate, wherein the orthographic projection of the second light-shielding layer on the first substrate and the orthographic projection of the second pixel circuit on the first substrate at least partially overlap. The area of ​​the first effective light-emitting region is larger than the area of ​​the second effective light-emitting region, and the area of ​​the first light-shielding layer is larger than the area of ​​the second light-shielding layer. The wavelength of the light emitted from the first effective light-emitting area is greater than the wavelength of the light emitted from the second effective light-emitting area. The ratio of the area of ​​the first light-shielding layer to the area of ​​the first sub-pixel is a, and the ratio of the area of ​​the second light-shielding layer to the area of ​​the second sub-pixel is b. The ratio M1 of a and b ranges from 1.020 to 1.

120.

29. The preparation method according to claim 28, wherein, The aperture ratio of the first sub-pixel is n1(1-a), and the aperture ratio of the second sub-pixel is n2(1-b). (1-a) / (1-b)=(n2 / n1)M2*K1*K2, where K1 is the ratio of the initial brightness of the second sub-pixel to the initial brightness of the first sub-pixel, K2 is the ratio of the lifetime of the second sub-pixel to the lifetime of the first sub-pixel, n1 is the ratio of the area of ​​the opening region in the first sub-pixel to the area of ​​the portion of the first sub-pixel excluding the area blocked by the first light-shielding layer, n2 is the ratio of the area of ​​the opening region in the second sub-pixel to the area of ​​the portion of the second sub-pixel excluding the area blocked by the second light-shielding layer, the value range of (n2 / n1)M2 is 1.000~1.130, and the value range of (1-a) / (1-b) is 0.877~0.997.

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