Display device and multi-screen display device including the same

Abstract

The present application relates to a display apparatus and a multi-screen display apparatus including the same. The display apparatus can include a substrate including a display area including a plurality of pixels disposed along a first direction and a second direction crossing the first direction; a gate driving circuit disposed at the display area, the gate driving circuit including a plurality of branch circuits for providing a scan signal to the plurality of pixels; and a plurality of lines disposed at an area between two pixels adjacent to each other along the first direction, extending in the second direction, and selectively connected to the plurality of branch circuits, the number of lines disposed at the area between the two pixels adjacent to each other along the first direction being the same.

Description

Technical Field

[0001] This disclosure relates to devices, and specifically, for example, but not limited to, display devices and multi-screen display devices including those. Background Technology

[0002] Display devices are installed in household appliances or electronic devices such as televisions (TVs), monitors, laptops, smartphones, tablet PCs, electronic tablets, wearable devices, smartwatches, portable information devices, navigation devices, and vehicle control display devices, and are used as screens for displaying images.

[0003] The display device includes a display panel, a data driving circuit, and a gating driving circuit. The display panel includes a plurality of pixels, each including a thin-film transistor (TFT) connected to a data line and a gating line. The data driving circuit provides a data voltage to the data line, and the gating driving circuit provides a gating signal to the gating line.

[0004] Recently, display devices with in-panel gate (GIP) structures have been used, in which the gate driving circuitry and the process of manufacturing the TFTs for each pixel are simultaneously embedded in the non-display area of ​​the display panel to simplify the configuration of circuit components, reduce manufacturing costs, and reduce bezel width.

[0005] Display panels including gating drive circuits with GIP structures include bezel areas due to the gating drive circuits being located in non-display areas. Therefore, related display devices require bezels or mechanisms for covering the bezel area of ​​the display panel, and the bezel width may increase due to the width of the bezel area.

[0006] Recently, research has been actively conducted on transparent display devices that allow users (or viewers) to see objects or backgrounds located on the back surface of the display device.

[0007] Transparent display devices can be classified into a transmissive part that transmits all or most of the light incident upon it and a light-emitting part that emits light. Users can see objects or backgrounds located on the rear surface of the transparent display device through the transmissive part.

[0008] The descriptions provided in this Background section should not be assumed to be prior art simply because they are mentioned in or associated with this section. The Background section may include information describing one or more aspects of the subject matter art. Summary of the Invention

[0009] Therefore, this disclosure provides a display device and a multi-screen display device including the present invention that substantially eliminates one or more problems caused by the limitations and disadvantages of related technologies.

[0010] One aspect of this disclosure provides a display device or transparent display device in which dimensional (or transmittance or transparency) deviations between transmissive portions can be minimized, reduced, or prevented.

[0011] One aspect of this disclosure provides a display device (or transparent display device) and a multi-screen display device including the same, which can minimize, reduce or prevent image quality defects such as linear stripes caused by dimensional (or transmittance or transparency) deviations between transmissive portions.

[0012] One aspect of this disclosure provides a display device (or transparent display device) having a zero or near-zero bezel width, and a multi-screen display device including the same.

[0013] Additional features and aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the inventive concept provided herein. Other features and aspects of the inventive concept may be realized and obtained by means of structures specifically pointed out in or deduced from the written description, as well as by the claims and drawings.

[0014] To achieve these and other aspects of the inventive concept, as implemented and broadly described herein, a display device may include: a substrate including a display area comprising a plurality of pixels disposed along a first direction and a second direction intersecting the first direction; a gating drive circuit disposed at the display area, the gating drive circuit including a plurality of branch circuits for providing scan signals to the plurality of pixels; and a plurality of lines disposed in a region between two pixels adjacent to each other along the first direction, extending in the second direction and selectively connected to the plurality of branch circuits, the number of lines disposed in the region between two pixels adjacent to each other along the first direction being the same.

[0015] In another aspect of this disclosure, a multi-screen display device may include a plurality of display devices arranged along at least one of a first direction and a second direction intersecting the first direction. Each of the plurality of display devices may include: a substrate including a display area comprising a plurality of pixels disposed along the first direction and the second direction intersecting the first direction; a gating drive circuit disposed at the display area, the gating drive circuit including a plurality of branch circuits for providing scan signals to the plurality of pixels; and a plurality of lines disposed in a region between two pixels adjacent to each other along the first direction, extending in the second direction and selectively connected to the plurality of branch circuits, the number of lines disposed in the region between two pixels adjacent to each other along the first direction being the same.

[0016] Specific details of various examples according to this disclosure, other than the means used to solve the above-described problems, are included in the following description and figures.

[0017] Some embodiments of this disclosure can provide a display device for reducing, minimizing, or preventing dimensional (or transmittance or transparency) deviations between transmissive portions.

[0018] Some embodiments of this disclosure can provide a display device and a multi-screen display device including the same, which can reduce, minimize or prevent image quality defects such as linear stripes caused by dimensional deviations between branch circuits of gating drive circuits between multiple pixels.

[0019] Some embodiments of this disclosure can provide a display device and a multi-screen display device including the same, which can reduce, minimize or prevent image quality defects such as linear stripes caused by the number deviation between gating control lines of branch circuits of gating drive circuits connected between and between multiple pixels.

[0020] Some embodiments of this disclosure can provide a display device and a multi-screen display device including the same, which can reduce, minimize or prevent image quality defects such as linear stripes caused by dimensional (or transmittance or transparency) deviations between transmissive portions disposed between multiple pixels.

[0021] Some embodiments of this disclosure can provide a display device with a zero or near-zero bezel width and a multi-screen display device including the same.

[0022] Some embodiments of this disclosure can provide a display device and a multi-screen display device including the same, which can reduce, minimize or prevent dimensional (or transmittance or transparency) deviations between transmissive portions caused by dimensional (or area) deviations between components of the gating drive circuit without causing a malfunction in the gating drive circuit.

[0023] Some embodiments of this disclosure may provide a display device and a multi-screen display device including the same, which displays an image without discontinuity when displaying an image across the entire screen.

[0024] Some embodiments of this disclosure may provide a transparent display device with enhanced transparency or transmittance and a transparent multi-screen display device including the same.

[0025] Other systems, methods, features, and advantages will be apparent to those skilled in the art upon review of the following figures and detailed description. All such additional systems, methods, features, and advantages are intended to be included within the scope of this specification and disclosure, and are protected by the appended claims. Nothing in this section should be construed as limiting these claims. Other aspects and advantages are discussed below in conjunction with embodiments of this disclosure.

[0026] It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0027] The accompanying drawings are included to provide a further understanding of this disclosure, are incorporated in and constitute a part of this disclosure, and illustrate various aspects and embodiments of this disclosure, and together with the description serve to explain the various principles of this disclosure.

[0028] Figure 1 This is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0029] Figure 2 This illustrates exemplary embodiments according to the present disclosure. Figure 1 The diagram shows the display panel.

[0030] Figure 3 This is an example implementation based on the present disclosure. Figure 2 An enlarged view of area "A" shown.

[0031] Figure 4 This illustrates exemplary embodiments according to the present disclosure. Figure 3 The circuit diagram for one pixel is shown.

[0032] Figure 5 This is an example Figure 2 and Figure 3 The diagram shows a gating drive circuit according to an exemplary embodiment of the present disclosure.

[0033] Figure 6 This illustrates a connection to an exemplary embodiment of the present disclosure. Figure 5 The diagram shows the gate lines of multiple circuit units.

[0034] Figure 7 This illustrates exemplary embodiments according to the present disclosure. Figure 5 and Figure 6 The diagram shows some of the multiple circuit units.

[0035] Figure 8 This is a diagram illustrating a branch network and multiple dummy patterns according to an exemplary embodiment of the present disclosure.

[0036] Figure 9 It is along the exemplary embodiments of this disclosure. Figure 8 The cross-sectional view taken by line I-I' is shown.

[0037] Figure 10 It is along the exemplary embodiments of this disclosure. Figure 8The cross-sectional view taken from line II-II' is shown.

[0038] Figure 11 It is along the exemplary embodiments of this disclosure. Figure 8 Another cross-sectional view taken from line I-I'.

[0039] Figure 12 It is along the exemplary embodiments of this disclosure. Figure 8 Another cross-sectional view taken from line II-II' shown.

[0040] Figure 13 It is a diagram used to describe the dummy network lines according to an exemplary embodiment of the present disclosure.

[0041] Figure 14 This is an illustrative example of an exemplary embodiment according to the present disclosure. Figure 13 The diagram shows the connection structure between the dummy pattern and the dummy network lines.

[0042] Figure 15 This is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0043] Figure 16 It is along the exemplary embodiments of this disclosure. Figure 15 The cross-sectional view taken from line III-III' is shown.

[0044] Figure 17 It is along the exemplary embodiments of this disclosure. Figure 15 Another cross-sectional view taken from line IV-IV'.

[0045] Figure 18 It is along the exemplary embodiments of this disclosure. Figure 15 Another cross-sectional view taken from line III-III' shown.

[0046] Figure 19 This is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0047] Figure 20 This is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0048] Figure 21 It is along the exemplary embodiments of this disclosure. Figure 20 The cross-sectional view shown is taken from line V-V'.

[0049] Figure 22 It is along the exemplary embodiments of this disclosure. Figure 20 Another cross-sectional view taken from line V-V'.

[0050] Figure 23 This is a perspective view illustrating a display device according to another exemplary embodiment of the present disclosure.

[0051] Figure 24 This illustrates exemplary embodiments according to the present disclosure. Figure 23 A diagram of the rear surface of the display device.

[0052] Figure 25 This is a diagram illustrating a multi-screen display device according to an exemplary embodiment of the present disclosure.

[0053] Figure 26 It is along the exemplary embodiments of this disclosure. Figure 25 The cross-sectional view taken by line VI-VI' is shown.

[0054] Throughout the accompanying drawings and detailed embodiments, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. The relative dimensions and depictions of these elements may be exaggerated for clarity, illustrative purposes, and convenience. Detailed Implementation

[0055] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or configurations relevant to this document will be omitted where such descriptions would be deemed unnecessary to obscure the gist of the inventive concept. The described progression of processing steps and / or operations is exemplary; however, the order of steps and / or operations is not limited to that set forth herein and can be varied as is known in the art, except for steps and / or operations that must occur in a specific order. The same reference numerals consistently denote the same elements. The names of corresponding elements used in the following description are chosen solely for convenience in drafting this disclosure and may therefore differ from those used in actual products.

[0056] The advantages and features of this disclosure, and its implementation methods, will become clear from the exemplary embodiments described below with reference to the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are exemplary and provided so that this disclosure may be thorough and complete enough to assist those skilled in the art in fully understanding the inventive concept without limiting the scope of protection of this disclosure.

[0057] The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the details shown. Similar reference numerals always refer to similar elements. In the following description, detailed descriptions of related known functions or configurations will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the essential points of this disclosure. When using terms such as “comprising,” “having,” “including,” “containing,” “constituting,” “made of,” “formed from,” etc., as described in this disclosure, one or more other elements may be added unless terms such as “only” are used. Singular terms may include plural forms unless the context clearly indicates otherwise. Any implementation described herein as an “example” is not necessarily to be construed as preferred or advantageous over other implementations.

[0058] When interpreting a component, it is interpreted as including a range of errors or tolerances, although there is no explicit description of such a range of errors or tolerances.

[0059] When describing positional relationships, for example, when the positional relationship between two components is described as "on," "above," "below," "above," "under," "adjacent," "close to," "adjacent to," "next to," "beside," "next to," etc., one or more other components may be disposed between the two components unless more restrictive terms such as "immediately," "just," or "directly" are used. In the description of embodiments, when a structure is described as being "above or above" or "below or under" another structure, the description should be interpreted to include cases where the structures are in contact with each other and cases where a third structure is disposed therebetween.

[0060] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous situations may be included unless more restrictive terms such as “just,” “immediately,” or “directly” are used.

[0061] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure.

[0062] In describing the elements of this disclosure, terms such as “first,” “second,” “A,” “B,” “(a),” and “(b)” may be used. These terms may be used only to distinguish one element from another, and the substance, order, sequence, or number of corresponding elements shall not be limited by these terms. The expression that an element is “connected,” “joined,” or “adhered” to another element or layer means that the element or layer may be directly connected or adhered to the other element or layer, or indirectly connected or adhered to the other element or layer (with one or more intermediate elements or layers “set” or “inserted” between elements or layers), unless otherwise stated.

[0063] The term "at least one" should be understood to include any and all combinations of one or more of the related listed items. For example, "at least one of the first, second, and third items" means a combination of all items derived from two or more of the first, second, and third items, as well as the first, second, or third item. The expression "first element, second element, and / or third element" should be understood to mean one of the first, second, and third elements, or any or all combinations of the first, second, and third elements. For example, A, B, and / or C can refer to only A; only B; only C; any or some combinations of A, B, and C; or all of A, B, and C.

[0064] Features of the various embodiments of this disclosure may be linked or combined with each other in part or in whole, and may interoperate with each other in various ways and be technically driven, as will be fully understood by those skilled in the art. Embodiments of this disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

[0065] Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It will also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent, for example, with their meaning in the context of the relevant field, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein. For example, the terms “component” or “unit” can be applied, for example, to a single circuit or structure, an integrated circuit, a computational block of a circuit arrangement, or any structure configured to perform the described functions, as would be understood by one of ordinary skill in the art.

[0066] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. For ease of description, the scale of each element shown in the drawings differs from the actual scale, and therefore the scope is not limited to the scale shown in the drawings.

[0067] The display device according to embodiments of this disclosure may be a flexible display device, a display panel, or a flexible display panel, but the embodiments of this disclosure are not limited thereto. For example, the display device according to embodiments of this disclosure may include equipment such as a notebook computer, a television, a computer monitor, equipment including automotive equipment or another type of equipment for vehicles, or a complete set of electronic equipment or a complete set of devices (or complete sets of equipment) such as a smartphone or a tablet computer, which is a complete product (or final product) including a liquid crystal display panel or an organic light-emitting display panel.

[0068] Figure 1 This is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure. Figure 2 This is an example Figure 1 A diagram of the display panel is shown. All components or elements of each display device according to all embodiments of this disclosure are operatively connected and configured.

[0069] Reference Figure 1 and Figure 2 The display device according to the exemplary embodiments of the present disclosure may include a display panel 10 and a driving circuit unit 30.

[0070] The display panel 10 may include: a substrate 100 including a display area AA; a plurality of pixels P arranged on the display area AA of the substrate 100 at a first interval D1; and a gating drive circuit 150 disposed in (or within) the display area AA. The substrate 100 may include glass, plastic, or a flexible polymer film. For example, the flexible polymer film may be made of any of the following: polyimide (PI), polyethylene terephthalate (PET), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyarylate (PAR), polysulfone (PSF), cyclic olefin copolymer (COC), triacetyl cellulose (TAC) film, polyvinyl alcohol (PVA) film, and polystyrene (PS), and this disclosure is not limited thereto.

[0071] The display area AA can be an area for displaying an image and can be referred to as an effective area or display portion. The size of the display area AA can be the same as or substantially the same as that of the substrate 100 (or the display device). For example, the size of the display area AA can be the same as the entire size of the first surface of the substrate 100. Therefore, the substrate 100 may not include an opaque non-display area disposed along the periphery of the first surface to surround all the display areas AA. Thus, the entire front surface of the display device can be configured as the display area AA.

[0072] The end (or outermost portion) of the display area AA may overlap with or be substantially aligned with the outer surface OS of the substrate 100. Therefore, the side surfaces of the display area AA may not be surrounded by a separate mechanism and may be surrounded only by air. For example, all side surfaces of the display area AA may be configured to be in direct contact with air without being surrounded by a separate mechanism.

[0073] The display area AA according to the embodiment may include a plurality of pixels P. The plurality of pixels P according to the embodiment may be arranged (or configured) in the display area AA of the substrate 100 with a first interval D1. Each of the plurality of pixels P may be in direct contact with each other along a first direction X and a second direction Y intersecting (or crossing) the first direction X, without any separation space. The first direction X may be a first length direction (e.g., width direction) of the substrate 100 or the display device, while the second direction Y may be a second length direction (e.g., length direction) of the substrate 100 or the display device.

[0074] The first interval D1 can be the pitch (or pixel pitch) between two adjacent pixels P. For example, the first interval D1 can be the distance (or shortest distance or shortest length) between the center portions of two adjacent pixels P. Each of the plurality of pixels P can have a first length parallel to the first direction X and a second length parallel to the second direction Y. Each of the plurality of pixels P can have a square shape including the first length and the second length, but embodiments of this disclosure are not limited thereto.

[0075] The center portion of each outermost pixel P, disposed along the peripheral (or edge) portion of the substrate 100, can be spaced apart from the outer surface OS of the substrate 100 to have a second interval D2. The second interval D2 can be half or less than the first interval D1, such that the entire front surface of the substrate 100 (or the entire front surface of the display device) is configured as the display area AA. For example, the second interval D2 can be the shortest distance (or shortest length) between the center portion of the outermost pixel Po and the outer surface OS of the substrate 100.

[0076] When the second interval D2 is greater than half of the first interval D1, the substrate 100 can include a non-display area surrounding all display areas AA through the area between the end of the outermost pixel Po (or the end of the display area AA) and the outer surface OS of the substrate 100. Therefore, the substrate 100 may include a border area based on the non-display area surrounding all display areas AA. On the other hand, when the second interval D2 is half or less of the first interval D1, the end of the outermost pixel Po (or the end of the display area AA) can overlap (or align) with the outer surface OS of the substrate or can be disposed in the space outside the outer surface OS of the substrate 100. Therefore, the display area AA can be configured (or disposed) on the entire front surface of the substrate 100, or can have the same size (or area) as the substrate 100.

[0077] Each of the plurality of pixels P may include a light-emitting portion (or light-emitting part) EP. The light-emitting portion EP according to embodiments of the present disclosure may include a first light-emitting region EA1 to a fourth light-emitting region EA4. For example, the first light-emitting region EA1 to the fourth light-emitting region EA4 may be in direct contact with each other in the first direction X and the second direction Y without any separation space. However, the number of light-emitting regions included in the light-emitting portion EP of pixel P is not limited to four, and in other examples may be one, two, three, five, or more.

[0078] According to embodiments of the present disclosure, the first light-emitting regions EA1 to the fourth light-emitting regions EA4 can be configured in a 2×2 form or a quaternary structure. For example, each of the light-emitting regions EA1 to EA4 can have a uniform quaternary structure with the same size (or the same area) or a non-uniform quaternary structure with different sizes (or different areas). For example, the light-emitting regions EA1 to EA4 with uniform or non-uniform quaternary structures can be configured to be concentrated at the central portion CP of pixel P, but embodiments of the present disclosure are not limited thereto.

[0079] According to another embodiment of this disclosure, each of the first light-emitting regions EA1 to the fourth light-emitting regions EA4 may have a rectangular shape comprising a short side parallel to the first direction X and a long side parallel to the second direction Y, and may be arranged, for example, in a 1×4 form or a 1×4 stripe form. The shape of the light-emitting region is not limited to a square or rectangular shape, and other shapes such as circular, elliptical or oval, quadrilateral, pentagonal or hexagonal shapes may also be possible.

[0080] According to embodiments of this disclosure, a first light-emitting region EA1 can be configured to emit light of a first color, a second light-emitting region EA2 can be configured to emit light of a second color, a third light-emitting region EA3 can be configured to emit light of a third color, and a fourth light-emitting region EA4 can be configured to emit light of a fourth color. As an embodiment, each of the first to fourth colors can be different. For example, the first color can be red, the second color can be blue, the third color can be white, and the fourth color can be green. As another embodiment, some of the first to fourth colors can be the same. For example, the first color can be red, the second color can be first green, the third color can be second green, and the fourth color can be blue. In another example, the first color can be cyan, the second color can be magenta, the third color can be yellow, and the fourth color can be any one of cyan, magenta, or yellow, but this disclosure is not limited thereto.

[0081] According to another embodiment, the light-emitting unit EP may include a first light-emitting region EA1 to a third light-emitting region EA3. In this case, the first light-emitting region EA1 to the third light-emitting region EA3 may each have a rectangular shape including a short side parallel to the first direction X and a long side parallel to the second direction Y, and may be arranged, for example, in a 1×3 form or a 1×3 stripe form. For example, the first light-emitting region EA1 may be configured to emit light of a first color, the second light-emitting region EA2 may be configured to emit light of a second color, and the third light-emitting region EA3 may be configured to emit light of a third color. For example, the first color may be red, the second color may be blue, and the third color may be green.

[0082] A gating drive circuit 150 is disposed or installed in (or within) the display area AA to provide scan signals (or gating signals) to pixels P disposed on the substrate 100. The gating drive circuit 150 can simultaneously provide scan signals to pixels P disposed in a horizontal row parallel to the first direction X. For example, the gating drive circuit 150 can provide at least one scan signal to pixels P disposed in a single horizontal row. For example, the gating drive circuit 150 may include multiple branch circuits BC, which are disposed sequentially between one or more pixels P to provide scan signals to multiple pixels P. For example, the gating drive circuit 150 may be a built-in gating drive circuit, a scan drive circuit, a column drive circuit, or a horizontal drive circuit.

[0083] The gating drive circuit 150 according to embodiments of the present disclosure may be configured with a shift register including multiple stages of circuit units 1501 to 150m. For example, a display device according to embodiments of the present disclosure may include a shift register disposed in (or within) the display area AA of the substrate 100 to provide a scan signal to the pixel P.

[0084] Each of the plurality of stage circuit units 1501 to 150m may include a plurality of branch circuits BC disposed along the first direction X in each horizontal row of the substrate 100. The plurality of branch circuits BC may include one or more TFTs (or branch TFTs) and may be configured to be dispersed (or distributed) along the first direction X in (or within) a horizontal row. For example, each of the plurality of branch circuits BC may be disposed one by one between one or more pixels P, but embodiments of the present disclosure are not limited thereto.

[0085] According to embodiments of this disclosure, at least some of the plurality of branch circuits BC may have different dimensions (or areas). For example, at least some of the plurality of branch circuits BC may be configured as a single thin-film transistor, and the remaining branch circuits of the plurality of branch circuits BC may be configured as two or more thin-film transistors.

[0086] Each of the multiple level circuit units 1501 to 150m can generate a scan signal according to the driving of multiple branch circuits BC, and can provide a scan signal to the pixels set in the corresponding horizontal row. The multiple branch circuits BC are driven in response to the gating control signals provided from the driving circuit unit 30 through multiple gating control lines set between multiple pixels P in (or within) the display area AA.

[0087] Each of the multiple stage circuit units 1501 to 150m may include, but is not limited to, node control circuitry, inverter circuitry, node reset circuitry, and multiple output buffer circuitry. Each of the node control circuitry, inverter circuitry, node reset circuitry, and multiple output buffer circuitry may be configured to include one or more branch circuits BC. For example, the node control circuitry, inverter circuitry, and node reset circuitry may be configured as a single stage or a shift register. Therefore, each of the multiple stage circuit units 1501 to 150m configured with multiple branch circuits BC may include one or more stages and multiple output buffer circuitry (or buffers). For example, each of the multiple stage circuit units 1501 to 150m may include one or more first output buffer circuitry configured to provide scan signals to odd-numbered gating lines located in (or within) the corresponding horizontal row, one or more second output buffer circuitry configured to provide scan signals to even-numbered gating lines located in (or within) the corresponding horizontal row, and a carry output buffer circuitry configured to output a carry signal.

[0088] The display panel 10 according to an embodiment of the present disclosure may further include a pad portion 110 having a plurality of pads. The plurality of pads are disposed in the display area AA of the substrate 100 and connected to the gating drive circuit 150 and each of the plurality of pixels P. For example, the pad portion 110 may be a first pad portion or a front pad portion. The pad portion 110 may receive data signals, gating control signals, pixel drive power supplies, and pixel common voltages from the drive circuit unit 30.

[0089] The pad portion 110 may be included in the outermost pixel Po, which is disposed at a first peripheral portion of a first surface of the substrate 100 parallel to the first direction X. For example, the outermost pixel Po disposed at the first peripheral portion of the substrate 100 may include at least one of a plurality of pads. Therefore, a plurality of pads may be disposed or included in (or within) the display area AA, and thus, a non-display area (or border area) based on the pad portion 110 may not be formed or may not be on the substrate 100. For example, according to an embodiment of the present disclosure, the pad portion 110 is disposed between the outer surface OS of the substrate 100 and the light-emitting area of ​​the outermost pixel and is included in (or within) the outermost pixel, and thus, a non-display area (or border area) based on the pad portion 110 may not be formed or may not be in the area between the outer surface OS of the substrate 100 and the outermost pixel. Therefore, the outermost pixel may include the pad portion 110 and may therefore be configured to have a different construction or structure than the inner pixels that do not include the pad portion 110. Figure 2 and Figure 3 The diagram shows that the pad portion 110 is disposed around the upper edge of the substrate 100, but the position and number of the pad portion 110 are not limited thereto. For example, the pad portion 110 may be disposed around at least one of the upper edge, lower edge, left edge and right edge of the substrate 100.

[0090] The display device (or display panel 10 or display area AA) according to the embodiments of the present disclosure may also include a transmissive portion (light-transmitting portion) TP, and therefore, a transparent display device can be constructed using the transmissive portion TP.

[0091] The transmissive portion TP can be the area that transmits all or most of the light incident on the display panel 10 or the display area AA. The transmissive portion TP can be configured to transmit all or most of the light incident on it, so that the user (or viewer) can see the object or background located on the rear surface of the display panel 10 or the display area AA.

[0092] According to embodiments of the present disclosure, the transmissive portion TP can be disposed around the light-emitting portion EP of each of the plurality of pixels P, or it can be the peripheral region of the light-emitting portion EP of each of the plurality of pixels P. For example, each of the plurality of pixels P may include a light-emitting portion EP and a transmissive portion TP surrounding the light-emitting portion EP. For example, the transmissive portion TP can be disposed between the light-emitting portions EP of each of the plurality of pixels P disposed along each of the first direction X and the second direction Y. For example, the transmissive portion TP can be disposed between the light-emitting portions EP of two adjacent pixels P along each of the first direction X and the second direction Y. For example, the transmissive portion TP can be a region other than the light-emitting portions EP of each of the plurality of pixels P in the display area A. For example, the branch circuit BC of the gate drive circuit 150 and the pad portion 110 can be disposed in the transmissive portion TP. For example, each of the plurality of branch circuits BC can be disposed in the transmissive portion TP (or at the transmissive portion TP) between the plurality of pixels P.

[0093] The display device (or display panel 10 or display area AA) according to embodiments of the present disclosure may further include a plurality of dummy patterns 160. For example, the dummy pattern 160 may be a metallic pattern, an auxiliary pattern, an additional pattern, an overlay pattern, a pattern component, or an island pattern.

[0094] Multiple dummy patterns 160 can be disposed on the substrate 100 to overlap with peripheral circuitry (or embedded peripheral circuitry) disposed between the light-emitting portions EP of any two pixels of the plurality of pixels P. For example, the multiple dummy patterns 160 can be configured to cover the peripheral circuitry (or embedded peripheral circuitry) disposed between the light-emitting portions EP of any two pixels of the plurality of pixels P. Therefore, each of the multiple dummy patterns 160 can be configured to reduce, minimize, or prevent dimensional (or transmittance or transparency) deviations between transmissive portions TP caused by peripheral circuitry, etc., thereby reducing, minimizing, or preventing dim phenomena such as smears caused by dimensional (or transmittance or transparency) deviations between transmissive portions TP, thereby enhancing the transmittance or transparency of the display device (or transparent display device) according to the embodiments of the present disclosure.

[0095] Each of the plurality of dummy patterns 160 according to embodiments of the present disclosure may be disposed on the substrate 100 to overlap with the gating drive circuit 150. For example, each of the plurality of dummy patterns 160 may be disposed on the substrate 100 to overlap with each of the plurality of branch circuits BC disposed in the gating drive circuit 150. For example, each of the plurality of dummy patterns 160 may be configured to cover each of the plurality of branch circuits BC disposed in (or at) the gating drive circuit. Therefore, each of the plurality of dummy patterns 160 may be configured to reduce, minimize, or prevent dimensional (or transmittance or transparency) deviations between transmissive portions TP caused by branch circuits BC, etc., and thus reduce, minimize, or prevent dimming phenomena such as streaks (stains) caused by dimensional (or transmittance or transparency) deviations between transmissive portions TP, thereby enhancing the transmittance or transparency of the display device (or transparent display device) according to embodiments of the present disclosure.

[0096] Each of the plurality of dummy patterns 160 can be configured to have the same shape and the same size within the tolerance range of the manufacturing process, thereby reducing, minimizing or preventing dimensional (or transmittance or transparency) deviations between the transmissive portions TP. For example, each of the plurality of dummy patterns 160 can be configured to have a size (or area) larger than the size (or area) of the corresponding peripheral circuit (or embedded peripheral circuit) or the corresponding branch circuit BC, and thus can completely cover the corresponding peripheral circuit (or embedded peripheral circuit) or the corresponding branch circuit BC.

[0097] Each of the plurality of dummy patterns 160 according to embodiments of the present disclosure may be configured as an opaque metallic material, but embodiments of the present disclosure are not limited thereto, and each of the plurality of dummy patterns 160 may be configured as a translucent metallic material.

[0098] The drive circuit unit 30 can be connected to the pad section 110 and can allow each pixel P to display an image corresponding to the image data provided from the display drive system.

[0099] The drive circuit unit 30 according to embodiments of the present disclosure may include a plurality of flexible circuit films 31, a plurality of drive integrated circuits (ICs) 33, a printed circuit board (PCB) 35, a timing controller 37, and a power supply circuit unit 39.

[0100] Each of the plurality of flexible circuit films 31 can be attached to the PCB 35 and the pad portion 110. The flexible circuit film 31 according to embodiments of the present disclosure can be a tape-on-film package (TCP) or a chip-on-film (COF).

[0101] Each of the plurality of driver ICs 33 can be individually mounted on (or at) a corresponding flexible circuit film 31 among the plurality of flexible circuit films 31. Each of the plurality of driver ICs 33 can receive pixel data and data control signals provided from the timing controller 37, convert the pixel data into a pixel-based analog data voltage according to the data control signals, and provide the analog data voltage to the corresponding pixel P. For example, each of the plurality of driver ICs 33 can generate a plurality of grayscale voltages by using a plurality of reference gamma voltages provided from the PCB 35, and can select the grayscale voltage corresponding to the pixel data from the plurality of grayscale voltages as the pixel-based data voltage to output the selected data voltage.

[0102] Furthermore, each of the plurality of driver ICs 33 can generate the pixel driving power supply (or pixel driving voltage) and pixel common voltage (or cathode voltage) required for driving (or emitting light) of pixel P by using a plurality of reference gamma voltages. In one embodiment, each of the plurality of driver ICs 33 can select a predetermined reference gamma voltage or a predetermined grayscale voltage from a plurality of reference gamma voltages or a plurality of grayscale voltages as the pixel driving power supply and pixel common voltage to output the pixel driving power supply and pixel common voltage.

[0103] Furthermore, each of the plurality of driver ICs 33 may additionally generate and output a reference voltage depending on the driving (or operation) method of each pixel P. For example, each of the plurality of driver ICs 33 may select a predetermined reference gamma voltage or a predetermined grayscale voltage from a plurality of reference gamma voltages or a plurality of grayscale voltages as a reference voltage to output a reference voltage. For example, the pixel driving power supply, the pixel common voltage, and the reference voltage may have different voltage levels.

[0104] Each of the multiple driving ICs 33 can sequentially sense the characteristic values ​​of the driving TFTs configured in the pixel P through multiple reference voltage lines disposed on the substrate 100, generate sensing raw data corresponding to the sensed values, and provide sensing raw data to the given timing controller 37.

[0105] PCB 35 can be connected to another edge portion of each of the multiple flexible circuit films 31. PCB 35 can transmit signals and voltages between the components of the drive circuit unit 30.

[0106] The timing controller 37 can be mounted on the PCB 35 and can receive image data and timing synchronization signals from the display driver system via a user connector located on the PCB 35. Alternatively, the timing controller 37 may not be mounted on the PCB 35 and can be configured within the display driver system or mounted on a separate control board connected between the PCB 35 and the display driver system.

[0107] The timing controller 37 can align video data based on a timing synchronization signal to match the pixel arrangement structure set in (or at) the display area AA, and can be configured to provide the generated pixel data to each of the plurality of driver ICs 33.

[0108] According to an embodiment of this disclosure, when pixel P includes a light-emitting area that emits white light, timing controller 37 can extract white pixel data based on digital video data (e.g., red input data, green input data, and blue input data to be provided to the corresponding pixel P respectively), reflect the offset data based on the extracted white pixel data in each of the red input data, green input data, and blue input data to calculate red pixel data, green pixel data, and blue pixel data, and align the calculated red pixel data, green pixel data, and blue pixel data with the white pixel data according to the pixel arrangement structure, so as to provide the aligned pixel data to each driver IC 33.

[0109] The timing controller 37 can generate each of the data control signal and the gating control signal based on the timing synchronization signal, control the driving timing of each of the driver ICs 33 based on the data control signal, and control the driving timing of the gating drive circuit 150 based on the gating control signal. For example, the timing synchronization signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a master clock (or dot clock).

[0110] The data control signal according to embodiments of this disclosure may include a source start pulse, a source shift clock, and a source output signal, etc. The gating control signal according to embodiments of this disclosure may include a start signal (or a gating start pulse) and multiple shift clocks, etc.

[0111] The timing controller 37 can drive each of the gating drive circuit 150 and the driver IC 33 based on an external sensing mode during a predetermined external sensing period, generate compensation data for compensating for characteristic variations of the driving TFT of each pixel P based on the raw sensing data provided from the driver IC 33, and modulate pixel data based on the generated compensation data. For example, the timing controller 37 can drive each of the gating drive circuit 150 and the driver IC 33 based on an external sensing mode for each external sensing period corresponding to the blanking period (or vertical blanking period) of the vertical synchronization signal. For example, the external sensing mode can be executed during the power-on process of the display device, during the power-off process of the display device, during the power-off process after a long period of driving, or during the blanking period of a frame set in real time or periodically. The external sensing mode of the display device can be a technique known to those skilled in the art, and therefore its detailed description is omitted. Alternatively, an internal sensing mode can be executed for the display device according to an exemplary embodiment of the present disclosure to internally compensate for characteristic variations of the driving TFT of each pixel P, and the present disclosure is not limited thereto.

[0112] The power supply circuit unit 39 can be mounted on the PCB 35 and can generate various source voltages required to display the image on pixel P by using an externally supplied input power supply, thereby providing the generated source voltages to the corresponding circuits. For example, the power supply circuit unit 39 can generate and output the logic source voltages required to drive each of the timing controller 37 and the driver IC 33, multiple reference gamma voltages supplied to the driver IC 33, and at least one gating drive power supply and at least one gating common power supply required to drive the gating drive circuit 150. The gating drive power supply and the gating common power supply can have different voltage levels.

[0113] Figure 3 This is an example implementation based on the present disclosure. Figure 2 An enlarged view of area "A" shown. Figure 4 This illustrates exemplary embodiments according to the present disclosure. Figure 3 The circuit diagram for one pixel is shown. Figure 3 and Figure 4 It is a diagram used to describe pixels according to an exemplary embodiment of the present disclosure.

[0114] Reference Figures 2 to 4 According to embodiments of the present disclosure, the substrate (or display area) 100 may include multiple gate lines GL, multiple data lines DL, multiple pixel drive power lines PL, multiple pixel common voltage lines CVL, multiple pixels P, common electrode CE, multiple common electrode contact portions CECP, and pad portions 110.

[0115] Each of the multiple gate lines GL can extend relatively long along the first direction X, and can be positioned at the display area AA of the substrate 100 to have a predetermined interval along the second direction Y.

[0116] Each of the multiple data lines DL can extend a considerable length along the second direction Y, and can be positioned at the display area AA of the substrate 100 with a predetermined interval along the first direction X.

[0117] Each of the multiple pixel driving power lines PL can extend a relatively long distance along the second direction Y, and can be positioned at the display area AA of the substrate 100 to have a predetermined interval along the first direction X.

[0118] Two adjacent pixel driving power lines PL among the multiple pixel driving power lines PL can be connected to multiple power sharing lines PSL in each pixel region PA arranged along the second direction Y. For example, the multiple pixel driving power lines PL can be electrically connected to each other through multiple power sharing lines PSL, and therefore can have a ladder structure or a mesh structure. The multiple pixel driving power lines PL can have a ladder structure or a mesh structure, so the voltage drop (IR drop) of the pixel driving power supply caused by the line resistance of each of the multiple pixel driving power lines PL can be reduced, prevented or minimized. Therefore, the display device 10 according to the embodiments of the present disclosure can reduce, prevent or minimize the image quality degradation caused by the deviation of the pixel driving power supply provided to each pixel P arranged in the display region AA.

[0119] Each of the multiple power sharing lines PSL can branch from the adjacent pixel drive power line PL parallel to the first direction X, and can be set in the middle region (or at) of each pixel region PA.

[0120] Each of the multiple pixel common voltage lines (CVLs) can extend relatively long along the second direction Y, and can be positioned at the display area AA of the substrate 100 to have a predetermined interval along the first direction X.

[0121] Each of the plurality of pixels P can be disposed in (or at) a plurality of pixel regions PA, and the plurality of pixel regions PA can be defined to have equal size in (or at) a display area AA of the substrate 100.

[0122] Each of the plurality of pixels P may include at least three sub-pixels. For example, each of the plurality of pixels P may include a first sub-pixel SP1 through a fourth sub-pixel SP4.

[0123] The first sub-pixel SP1 can be located in the first sub-pixel region (or at) the pixel region PA, the second sub-pixel SP2 can be located in the second sub-pixel region (or at) the pixel region PA, the third sub-pixel SP3 can be located in the third sub-pixel region (or at) the pixel region PA, and the fourth sub-pixel SP4 can be located in the fourth sub-pixel region (or at) the pixel region PA. For example, relative to the center of pixel P, the first sub-pixel SP1 can be the upper-left sub-pixel region of pixel region PA, the second sub-pixel SP2 can be the upper-right sub-pixel region of pixel region PA, the third sub-pixel SP3 can be the lower-left sub-pixel region of pixel region PA, and the fourth sub-pixel SP4 can be the lower-right sub-pixel region of pixel region PA.

[0124] Each of the first sub-pixels SP1 to the fourth sub-pixels SP4 may include a pixel circuit PC and a light-emitting device layer.

[0125] According to embodiments of this disclosure, the pixel circuit PC can be disposed in the circuit region CA of the pixel region PA, and can be connected to the adjacent gating lines GLo and GLe, the adjacent data lines DLo and DLe, and the adjacent pixel driving power line PL. For example, the pixel circuit PC disposed in the first sub-pixel SP1 can be connected to the odd-numbered data line DLo and the odd-numbered gating line GLo, the pixel circuit PC disposed in the second sub-pixel SP2 can be connected to the even-numbered data line DLe and the odd-numbered gating line GLo, the pixel circuit PC disposed in the third sub-pixel SP3 can be connected to the odd-numbered data line DLo and the even-numbered gating line GLe, and the pixel circuit PC disposed in the fourth sub-pixel SP4 can be connected to the even-numbered data line DLe and the even-numbered gating line GLe.

[0126] The pixel circuit PC of each of the first sub-pixels SP1 to the fourth sub-pixels SP4 can sample the data signals provided from the corresponding data lines DLo and DLe in response to the scan signals provided from the corresponding gate lines GLo and GLe, and can control the current flowing from the pixel drive power line PL to the light-emitting device ED based on the sampled data signals.

[0127] The display device 10 according to embodiments of the present disclosure may further include multiple reference voltage lines RL.

[0128] Multiple reference voltage lines RL can extend relatively long along the second direction Y and can be disposed at the display area AA of the substrate 100 with predetermined intervals along the first direction X. Each of the multiple reference voltage lines RL can be disposed in the central region (or at) of each pixel area PA arranged along the second direction Y, but embodiments of this disclosure are not limited thereto. For example, each of the multiple reference voltage lines RL can be disposed between odd-numbered data lines DLo and even-numbered data lines DLe in each pixel area PA.

[0129] Each of the multiple reference voltage lines RL can be shared by two adjacent sub-pixels ((SP1, SP2) or (SP3, SP4)) along the first direction X in each pixel region PA. For example, each of the multiple reference voltage lines RL may include a reference branch line RDL.

[0130] The reference branch line RDL can branch (or protrude) toward two adjacent sub-pixels ((SP1, SP2) or (SP3, SP4)) in each pixel region PA along the first direction X, and can be electrically connected to the two adjacent sub-pixels ((SP1, SP2) or (SP3, SP4)).

[0131] The pad portion 110 according to an embodiment of the present disclosure may further include a plurality of reference power pads RVP.

[0132] Each of the plurality of reference power pads RVP can be individually (or in a one-to-one relationship) connected to one end of a corresponding reference voltage line RL among the plurality of reference voltage lines RL. For example, each of the plurality of reference power pads RVP can be located between two data pads DP located in each of the plurality of outermost pixel regions PAo, but embodiments of this disclosure are not limited thereto. Optionally, based on the circuit configuration of the pixel circuit PC, the plurality of reference voltage lines RL, the plurality of reference power pads RVP, and the reference branch lines RDL can be omitted respectively.

[0133] The pixel circuit PC according to embodiments of the present disclosure may include a first switching thin-film transistor Tsw1, a second switching thin-film transistor Tsw2, a driving thin-film transistor Tdr, and a storage capacitor Cst, but embodiments of the present disclosure are not limited thereto. For example, 4T1C, 5T1C, 3T2C, 4T2C, 5T2C, 6T2C, 7T1C, 7T2C, 8T2C, etc., are also possible. Furthermore, more or fewer transistors and capacitors may be included. In the following description, the thin-film transistor may be referred to as a TFT.

[0134] At least one of the first switching TFT Tsw1, the second switching TFT Tsw2, and the driving TFT Tdr can be an N-type or P-type TFT. At least one of the first switching TFT Tsw1, the second switching TFT Tsw2, and the driving TFT Tdr can be an amorphous silicon (a-Si) TFT, a polycrystalline silicon TFT, an oxide TFT, or an organic TFT. For example, in a pixel circuit PC, some of the TFTs in the first switching TFT Tsw1, the second switching TFT Tsw2, and the driving TFT Tdr can be TFTs comprising a semiconductor layer (or active layer) containing low-temperature polycrystalline silicon (LTPS) with excellent response characteristics, and the other TFTs in the first switching TFT Tsw1, the second switching TFT Tsw2, and the driving TFT Tdr can be TFTs comprising a semiconductor layer (or active layer) containing an oxide with good cutoff current characteristics. The first switching TFT Tsw1, the second switching TFT Tsw2, and the driving TFT Tdr can have different dimensions (or channel dimensions). For example, the size of the driving TFT Tdr can be larger than the size of each of the first switching TFT Tsw1 and the second switching TFT Tsw2, and the size of the second switching TFT Tsw2 can be larger than the size of the first switching TFT Tsw1.

[0135] The first switching TFT Tsw1 may include a gate electrode connected to the corresponding gate line GLo or GLe, a first electrode connected to the corresponding data line DLo or DLe, and a second electrode connected to the gate node n1 of the driving TFT Tdr. The first switching TFT Tsw1 can provide a data signal provided through the corresponding data line DL to the gate electrode n1 of the driving TFT Tdr based on a scan signal provided through the corresponding gate line GLo or GLe.

[0136] The second switching TFT Tsw2 may include a gate electrode connected to the corresponding gate line GLo or GLe, a first electrode connected to the source node n2 of the driving TFT Tdr, and a second electrode connected to the corresponding reference voltage line RL. The second switching TFT Tsw2 can provide a reference voltage provided through the corresponding reference line RL to the source node n2 of the driving TFT Tdr based on a scan signal provided through the corresponding gate line GLo or GLe.

[0137] A storage capacitor Cst can be formed between the gate node n1 and the source node n2 of the driving TFT Tdr. The storage capacitor Cst can be charged using the voltage difference between the gate node n1 and the source node n2 of the driving TFT Tdr, and then the driving TFT Tdr can be turned on or off based on its charging voltage.

[0138] The driving TFT Tdr may include a gate electrode (or gate node n1) connected to the second electrode of the first switching TFT Tsw1 and the first capacitor electrode of the storage capacitor Cst, a gate electrode (or gate node n2) connected to the first electrode of the second switching TFT Tsw2, the second capacitor electrode of the storage capacitor Cst, and the first electrode (or source node n2) of the light-emitting device layer, and a second electrode (or drain node) connected to the corresponding pixel driving power line PL. The driving TFT Tdr can be turned on based on the voltage of the storage capacitor Cst, and the amount of current flowing from the pixel driving power line PL to the light-emitting device layer can be controlled.

[0139] The second switching TFT Tsw2, disposed in the pixel circuit PC of each of the first sub-pixels SP1 to the fourth sub-pixels SP4, can provide a reference voltage to the source node n2 of the driving TFT Tdr via a reference voltage line RL based on an external sensing mode during the data charging period (or segment) of pixel P, and can provide current flowing in the source electrode n2 of the driving TFT Tdr to the reference voltage line RL during the sensing period (or segment) of pixel P. In this case, the driving circuit unit 30 can sense the current supplied to the reference voltage line RL to generate compensation data for compensating for characteristic changes of the driving TFT Tdr, and can modulate the pixel data based on the generated compensation data. For example, characteristic changes of the driving TFT Tdr may include threshold voltage and / or mobility.

[0140] Optionally, in each of the first sub-pixels SP1 to the fourth sub-pixels SP4, the pixel circuit PC, including the first switch TFT Tsw1, the second switch TFT Tsw2, the storage capacitor Cst, and the driving TFT Tdr, can be implemented as a pixel driver chip type (or semiconductor integrated circuit), disposed in (or at) the circuit region CA of the corresponding pixel region PA, and connected to the adjacent gate lines GLo and GLe, the adjacent data lines DLo and DLe, and the adjacent pixel driver power line PL. For example, the pixel driver chip according to embodiments of this disclosure can be a microchip or chipset corresponding to the smallest unit, and can be a semiconductor packaged device with fine dimensions including two or more transistors and one or more capacitors. The pixel driver chip can sample the data signal provided through the corresponding data lines DLo and DLe in response to the scan signal provided through the corresponding gate lines GLo and GLe, and can control the current flowing from the pixel driver power line PL to the light-emitting device ED based on the sampled data signal.

[0141] The light-emitting device layer can be disposed in the light-emitting area EA of the pixel area PA (or at that location) and electrically connected to the pixel circuit PC.

[0142] The light-emitting device layer according to embodiments of the present disclosure may include a pixel electrode PE electrically connected to a pixel circuit PC, a common electrode CE electrically connected to a pixel common voltage line CVL, and a light-emitting device ED inserted between the pixel electrode PE and the common electrode CE.

[0143] The pixel electrode PE can be referred to as the anode electrode, reflective electrode, lower electrode, or first electrode of the light-emitting device (ED). According to embodiments of this disclosure, the pixel electrode PE can comprise a metallic material with a high work function and good reflectivity. For example, the pixel electrode PE can be formed as a three-layer structure of IZO / MoTi / ITO or ITO / MoTi / ITO, or as a four-layer structure of ITO / Cu / MoTi / ITO, but embodiments of this disclosure are not limited thereto. In another example, the pixel electrode PE can have a multilayer structure comprising a transparent conductive film and an opaque conductive film with high reflectivity. The transparent conductive film can be made of a material with a relatively high work function value (such as indium tin oxide (ITO) or indium zinc oxide (IZO)), and the opaque conductive film can have a single-layer or multilayer structure comprising Al, Ag, Cu, Pb, Mo, Ti, or alloys thereof.

[0144] The pixel electrode PE can overlap with the light-emitting region EA of each of the multiple pixel regions PA. The pixel electrode PE can be patterned into an island shape, can be disposed in (or at) each pixel region PA, and can be electrically connected to the first electrode of the driving TFT Tdr of the corresponding pixel circuit PC.

[0145] The light-emitting device (ED) can be formed on the pixel electrode (PE) and can be in direct contact with the pixel electrode (PE). The ED can be a common device or a common device layer co-formed in each (or at) a plurality of sub-pixels (SPs), thus not distinguishable by sub-pixel SP units. The ED can respond to a current flowing between the pixel electrode (PE) and the common electrode (CE) to emit white or blue light. The ED can be an organic light-emitting device or an inorganic light-emitting device, but this disclosure is not limited thereto.

[0146] The common electrode CE can be disposed above the display area AA of the substrate 100, and can be electrically connected and jointly connected to the light-emitting device ED of each of the multiple sub-pixels SP. For example, the common electrode CE can be disposed in the display area AA of the substrate 100, excluding the pad portion 110 disposed in (or at) the substrate 100.

[0147] Each of the plurality of common electrode contact portions CECP can be disposed between a plurality of pixels P that overlap with a plurality of pixel common voltage lines CVL, and the common electrode CE can be electrically connected to (or contact) each of the plurality of pixel common voltage lines CVL. Relative to one or more of the first direction X and the second direction Y, each of the plurality of common electrode contact portions CECP according to embodiments of the present disclosure can be electrically connected to each of the plurality of pixel common voltage lines CVL in a portion (or at) between two adjacent pixel groups and can be electrically connected to a portion of the common electrode CE, thus allowing the common electrode CE to be electrically connected to each of the plurality of pixel common voltage lines CVL. For example, the common electrode CE can be electrically connected to each of the plurality of common electrode contact portions CECP via a side contact structure corresponding to an undercut structure. For example, a plurality of pixels P can be classified or grouped into a plurality of pixel groups. A pixel group may include two or more adjacent pixels P along one or more of the first direction X and the second direction Y.

[0148] Each of the multiple common electrode contact portions CECP can be disposed between two adjacent pixels P in the multiple pixels P to electrically connect the common electrode CE to each of the multiple pixel common voltage lines CVL. Therefore, the voltage drop (IR drop) of the pixel common voltage caused by the surface resistance of the common electrode CE can be reduced, prevented, or minimized. Thus, the display device 10 according to the embodiments of the present disclosure can reduce, prevent, or minimize image quality degradation caused by deviations in the pixel common voltage provided to each pixel P arranged in the display area AA (or at the display area AA).

[0149] According to embodiments of this disclosure, each of the plurality of common electrode contact portions (CECPs) can be formed together with a pixel electrode (PE) having at least a three-layer structure, thereby electrically connecting to each of the plurality of pixel common voltage lines (CVLs). Each of the plurality of common electrode contact portions (CECPs) can be electrically connected to the common electrode (CE) via a side contact structure having a () shaped cross-section structure or a <" shaped cross-section structure. For example, when each of the plurality of common electrode contact portions (CECPs) is formed of three or more metal layers, each of the plurality of common electrode contact portions (CECPs) can include a side contact structure corresponding to an undercut structure or a tapered structure formed on the side surface of one or more intermediate metal layers by the etching rate between the three or more metal layers.

[0150] The pad portion 110 may be disposed parallel to the first direction X at a first peripheral portion of a first surface of the substrate 100. The pad portion 110 may be disposed at a third peripheral portion of each of the outermost pixel regions Pao disposed at the first peripheral portion of the substrate 100. Relative to the second direction Y, the end of the pad portion 110 may overlap with or be aligned with the end of each outermost pixel region. Therefore, the pad portion 110 may be included (or disposed) in each outermost pixel region disposed at the first peripheral portion of the substrate 100, and thus, a non-display area (or border area) based on the pad portion 110 may not be formed or may not be on the substrate 100.

[0151] According to an embodiment of the present disclosure, the pad portion 110 may include a plurality of first pads arranged parallel to each other along a first direction X on a first peripheral portion of the substrate 100.

[0152] The pad section 110 according to an embodiment of the present disclosure may include a plurality of pad groups PG arranged along a first direction X in the order of pixel drive power pad PVP, two data pads DP, strobe pad GP, pixel common voltage pad CVP, two data pads DP and pixel drive power pad PVP, but the present disclosure is not limited thereto.

[0153] Each of a plurality of pad groups PG can be connected to two adjacent pixels P disposed along a first direction X. For example, each of the plurality of pad groups PG may include a first pad group PG1 and a second pad group PG2. The first pad group PG1 may include a pixel drive power pad PVP, two data pads DP, and a strobe pad GP disposed continuously along the first direction X within an odd-numbered pixel region PA. The second pad group PG2 may include a pixel common voltage pad CVP, two data pads DP, and a pixel drive power pad PVP disposed continuously along the first direction X within an even-numbered pixel region PA.

[0154] The substrate 100 according to embodiments of the present disclosure may further include multiple secondary voltage lines SVL and multiple secondary voltage contact portions SVCP.

[0155] Each of the plurality of secondary voltage lines SVL can extend relatively long along the second direction Y and can be configured to be adjacent to a corresponding pixel common voltage line CVL among the plurality of pixel common voltage lines CVL. Each of the plurality of secondary voltage lines SVL can be electrically connected to the adjacent pixel common voltage line CVL, but not electrically connected to the pixel common voltage pad CVP, and can be provided with a pixel common voltage through the adjacent pixel common voltage line CVL. For example, the substrate 100 according to an embodiment of the present disclosure may further include a plurality of line connection patterns LCP that electrically connect adjacent pixel common voltage lines CVL and secondary voltage lines SVL. Each of the plurality of line connection patterns LCP can be disposed on the substrate 100 such that adjacent pixel common voltage lines CVL and secondary voltage lines SVL intersect each other, and adjacent pixel common voltage lines CVL and secondary voltage lines SVL can be electrically connected by using a jumper structure.

[0156] Each of the plurality of secondary voltage contact portions SVCP can be arranged parallel to each of the plurality of common electrode contact portions CECP, and the common electrode CE can be electrically connected to each of the plurality of secondary voltage lines SVL. Therefore, the common electrode CE can be additionally connected to each of the plurality of secondary voltage lines SVL via the plurality of secondary voltage contact portions SVCP. Thus, the display device 10 according to the embodiments of the present disclosure can reduce, prevent, or minimize image quality degradation caused by deviations in the pixel common voltage supplied to each pixel P arranged in (or at) the display area AA. Furthermore, in the display device 10 according to the present disclosure, although pixel common voltage pads CVP connected to each of the plurality of secondary voltage lines SVL are not additionally provided (or formed), the pixel common voltage can be supplied to the common electrode CE in each of the plurality of pixel areas PA.

[0157] Each of the multiple secondary voltage contact portions SVCP can electrically connect the corresponding secondary voltage line in the multiple secondary voltage lines SVL to the common electrode CE through a side contact structure. Similar to each of the multiple common electrode contact portions CECP, the side contact structure has a "(" shaped cross-section structure or a "<" shaped cross-section structure.

[0158] Figure 5 This is an example Figure 2 and Figure 3 The diagram shows a gating drive circuit according to an exemplary embodiment of the present disclosure. Figure 6 This illustrates a connection to an exemplary embodiment of the present disclosure. Figure 5 The diagram shows the gate lines of multiple circuit units. Figure 7 This is an example implementation based on the present disclosure. Figure 5 and Figure 6The diagram shows some of the multiple circuit units.

[0159] Reference Figure 2 and Figures 5 to 7 According to embodiments of the present disclosure, the gating drive circuit 150 can be configured to include a shift register comprising multiple stages of circuit units 1501 to 150m.

[0160] Each of the plurality of stage circuit units 1501 to 150m can be individually disposed in each horizontal row HL on the first surface of the substrate 100 along a first direction X, and the plurality of stage circuit units 1501 to 150m can be interconnected along a second direction Y. Each of the plurality of stage circuit units 1501 to 150m can generate a scan signal in a predetermined sequence in response to a gating control signal provided by the pad portion 110 and a plurality of gating control lines GCL, and can provide the scan signal to the corresponding gating line GL. For example, the plurality of gating control lines GCL may include a start signal line, a plurality of scan shift clock lines, a plurality of advance shift clock lines, one or more gating drive power lines, and one or more gating common power lines. For example, the plurality of gating control lines GCL may be a plurality of scan control lines, a plurality of first gating control lines, or a plurality of vertical control lines.

[0161] The driving of each of the plurality of stage circuit units 1501 to 150m according to embodiments of the present disclosure can be initiated based on carry signals (or set carry signals) provided from two or more previous stage circuit units via a first carry signal line (or previous stage carry signal line) CSL1, and can be reset based on carry signals (or reset carry signals) provided from two or more next stage circuit units via a second carry signal line (or next stage carry signal line) CSL2. For example, the driving of each of the first stage circuit unit 1501 to the fourth stage circuit unit 1504 can be initiated based on a first strobe start signal to a fourth strobe start signal provided from a timing controller, and the driving of each of the m-3 stage circuit unit 150m-3 to the m stage circuit unit 150m can be reset based on a first reset signal to a fourth reset signal provided from a timing controller, respectively. For example, the driving of odd-numbered stage circuit units among the multiple stage circuit units 1501 to 150m can be initiated based on a carry signal provided from the previous odd-numbered stage circuit unit via a first carry signal line CSL1, and can be reset based on a carry signal provided from the next odd-numbered stage circuit unit via a second carry signal line CSL2. Similarly, the driving of even-numbered stage circuit units among the multiple stage circuit units 1501 to 150m can be initiated based on a carry signal provided from the previous even-numbered stage circuit unit, and can be reset based on a carry signal provided from the next even-numbered stage circuit unit.

[0162] Each of the plurality of stage circuit units 1501 to 150m according to embodiments of the present disclosure may include a first stage circuit SC1 to an xth stage circuit SCx (where x is a natural number of 2 or greater).

[0163] The first-level circuits SC1 to the x-th-level circuits SCx can be respectively disposed in (or within) the first horizontal division region HDA1 to the x-th horizontal division region HDAx in each horizontal row of the display area AA defined along the first direction X. Each of the first-level circuits SC1 to the x-th-level circuits SCx can generate scan signals in a predetermined order in response to the gating control signal provided by the pad portion 110 and the gating control line GCL, and can simultaneously provide scan signals to the corresponding gating line GL.

[0164] Each of the multiple gate lines GL according to embodiments of this disclosure may include first gate lines GLd1 to xth gate lines GLdx respectively disposed in (or at) the first horizontal division regions HDA1 to xth horizontal division regions HDAx of each horizontal row relative to the first direction X, and electrically disconnected from each other. In this case, a plurality of pixels P disposed in (or at) each of the first horizontal division regions HDA1 to xth horizontal division regions HDAx may be jointly connected to the first gate lines GLd1 to xth gate lines GLdx disposed in (or at) the corresponding horizontal division regions HDA1 to HDAx. For example, a plurality of pixels P disposed in (or at) the first horizontal division region HDA1 may be jointly connected to the first gate line GLd1 disposed in (or at) the first horizontal division region HDA1.

[0165] According to another embodiment of this disclosure, each of the multiple gate lines GL can be configured as a line type that continuously connects from one side of each horizontal row to the other side of each horizontal row relative to a first direction X. In this case, multiple pixels P disposed in (or at) each horizontal row can be collectively connected to a single gate line GL.

[0166] Each of the plurality of stage circuit units 1501 to 150m according to embodiments of the present disclosure may include a plurality of branch circuits BC1 to BCn and a branch network BN. For example, each of the first stage circuit SC1 to the xth stage circuit SCx may include a plurality of branch circuits BC1 to BCn and a branch network BN.

[0167] Each of the multiple branch circuits BC1 to BCn can be selectively connected to a line of the gating control line GCL via a branch network BN, and can be electrically connected to each other via the branch network BN. Each of the multiple branch circuits BC1 to BCn can generate a scan signal based on the gating control signal provided by each line of the gating control line GCL and the branch network BN, as well as the signals transmitted between the branch networks BN, and can provide a scan signal to the corresponding gating line GL.

[0168] Each of the multiple branch circuits BC1 to BCn can be disposed in a region between two adjacent pixels P along the first direction X or in a region between one or more pixels P in each horizontal row of the substrate 100, but the embodiments of this disclosure are not limited thereto. For example, the multiple branch circuits BC1 to BCn can be separately disposed (or distributed, or arrayed) between multiple pixels P based on the number of TFTs constituting a stage circuit unit 1501 to 150m and the number of pixels P disposed in (or at) a horizontal row.

[0169] Each of the plurality of branch circuits BC1 to BCn according to embodiments of the present disclosure may include one or more thin-film transistors (TFTs) of a plurality of TFTs constituting one of the stage circuits SC1 to SCx. For example, the i-th branch circuit BCI of the plurality of branch circuits BC1 to BCn may include one TFT, and the j-th branch circuit BCj of the plurality of branch circuits BC1 to BCn may include two TFTs, but embodiments of the present disclosure are not limited thereto.

[0170] The branch network BN can be configured to electrically connect multiple branch circuits BC1 to BCn disposed in each horizontal row of the substrate 100. The branch network BN can be disposed along the second direction Y in the region between multiple pixels P or in the region between one or more pixels P. For example, the branch network BN can be disposed in the transmissive portion TP between any two light-emitting portions EP of multiple pixels P arranged along the second direction Y.

[0171] Relative to the second direction Y, the display area AA may include a first horizontal row to an m-th horizontal row, and the branch network BN may be disposed at the same position (or in the middle) of each of the first horizontal rows to the m-th horizontal row. The branch network BN may be disposed in the lower edge region (or upper edge region) of each pixel region disposed in the middle (or at) of each of the first horizontal rows to the m-th horizontal row, thereby reducing or minimizing the transmittance deviation between the transmissive portions TP of each horizontal row to the m-th horizontal row. For example, the branch network BN may be disposed in the lower edge region (or at) of each pixel region disposed in the middle (or at) of each of the first horizontal rows to the m-th horizontal row. For example, the branch network BN may be disposed in the transmissive portion TP below the light-emitting portion EP of each pixel P disposed in the middle (or at) of each of the first horizontal rows to the m-th horizontal row, but the embodiments of this disclosure are not limited thereto. Therefore, the positions of the branch network BN set in (or at) the transmissive portion TP of each of the multiple pixels P can be the same or regular, thus reducing, minimizing or preventing the transmittance deviation between horizontal rows caused by the branch network BN set in the transmissive portion TP.

[0172] According to embodiments of this disclosure, the branch network BN may include a transparent conductive material capable of transmitting light. Therefore, since the branch network BN may include a transparent conductive material, the light transmittance (or transmissivity) of the transmissive portion TP can be increased or enhanced by light passing through the branch network BN, thereby enhancing or increasing the total light transmittance (or transmissivity) of the light display area AA.

[0173] According to embodiments of this disclosure, a branch network BN can be disposed between one edge portion and another edge portion of each horizontal row of the substrate 100. For example, the branch network BN can be disposed in (or at) the transmissive portion TP of each of the plurality of pixels P, and in order to reduce or minimize the transmittance deviation of the transmissive portion TP of each of the plurality of pixels P, the branch network BN can extend in (or at) each horizontal row of the substrate 100 to the edge portion of the outermost pixel. Therefore, the deviation between the transmittance (or translucency) of the transmissive portion TP of the pixel P with the branch network BN disposed and the transmittance (or translucency) of the transmissive portion TP of the pixel P without the branch network BN disposed can be reduced, minimized, or prevented.

[0174] The branch network BN can be configured to be electrically connected to the gating control line GCL and one or more branch circuits BC1 to BCn. For example, the branch network BN can be a branch connection section, a branch circuit connection section, an internal circuit connection section, an internal circuit connection line section, an internal signal transmission section, an internal signal transmission line section, or an internal bridging section.

[0175] The branch network (BN) according to embodiments of this disclosure may include multiple control nodes and multiple network lines, or may include multiple circuit connection lines arranged in parallel at certain intervals. For example, each of the multiple circuit connection lines may be a branch connection line, a branch circuit connection line, an internal circuit connection line, an internal signal transmission line, or an internal bridging line.

[0176] Multiple control nodes can be disposed at (or within) each horizontal row of the substrate 100 and can be selectively connected to multiple branch circuits BC1 to BCn in a horizontal row. For example, each of the multiple control nodes can be electrically connected to the gate of one or more TFTs in one or more branch circuits configured in (or at) each of the inverter circuit and output buffer circuit of the stage circuit unit. Furthermore, each of the multiple control nodes can be electrically connected to any one of the gate electrode, first electrode, and second electrode of one or more TFTs in one or more branch circuits configured in (or at) each of the node reset circuit and node control circuit constituting the stage circuit unit.

[0177] Each of the multiple network lines can be selectively connected to multiple branch circuits BC1 to BCn. Each of the multiple network lines can be configured to connect one or more TFTs disposed in (or at) each of the multiple branch circuits BC1 to BCn to each other. For example, the network lines can include one or more of jumpers, bridging wires, vertical line patterns, and horizontal line patterns.

[0178] According to embodiments of this disclosure, each of the first-stage circuit SC1 to the x-th-stage circuit SCx may include a node control circuit, an inverter circuit, a node reset circuit, and an output buffer circuit configured with multiple branch circuits BC1 to BCn. For example, the node control circuit may include one or more branch circuits configured to control the voltage of each of the multiple control nodes. The inverter circuit may include two or more branch circuits configured to conversely control or discharge the voltage of a first control node and one or more second control nodes. The output buffer circuit may include two or more branch circuits configured to output a scan shift clock provided via a gating control line GGL as a scan signal based on the voltage of the first control node.

[0179] According to another embodiment of this disclosure, one or more portions of the first-level circuit SC1 to the x-th-level circuit SCx may be configured as a stage (or shift register) including node control circuits, inverter circuits, and node reset circuits configured from some of the multiple branch circuits BC1 to BCn. Other stage circuits in the first-level circuit SC1 to the x-th-level circuit SCx, besides those configuring the stage itself, may be configured with multiple output buffer circuits. For example, when each of the multiple stage circuit units 1501 to 150m configured by the multiple branch circuits BC is configured as one or more stages and multiple output buffer circuits (or buffers), one or more of the first-level circuit SC1 to the x-th-level circuit SCx may be configured with only one or more stages, and other stage circuits in the first-level circuit SC1 to the x-th-level circuit SCx may be configured with only multiple output buffer circuits (or buffers). For example, one or more of the first-level circuit SC1 to the x-th-level circuit SCx may be configured as a stage portion of a stage circuit unit, while other stage circuits in the first-level circuit SC1 to the x-th-level circuit SCx may be configured as a buffer portion of a stage circuit unit.

[0180] Figure 8 This is a diagram illustrating a branch network and multiple dummy patterns according to an exemplary embodiment of the present disclosure. Figure 8 Examples include Figure 2 A diagram showing a portion of the branch circuit and multiple dummy patterns.

[0181] Reference Figure 8 In the gating drive circuit 150 according to an embodiment of the present disclosure, a plurality of branch circuits BC can be disposed along the first direction X between the light-emitting portions EP of a plurality of pixels P.

[0182] One or more branch circuits BCI and BCj from BC1 to BCn can be electrically connected to the gating control line GCL, and other branch circuits from BC1 to BCn can be interconnected through the branch network BN and can provide or receive signals.

[0183] Each of the multiple branch circuits BC1 to BCn may include one or more thin-film transistors (TFTs). For example, in the multiple branch circuits BC1 to BCn, the i-th branch circuit BCI may include one TFT, and the j-th branch circuit BCj may include two TFTs.

[0184] According to embodiments of this disclosure, Figure 8The TFT in the i-th branch circuit BCI shown may be a pull-up TFT that outputs a scan signal to the gating line, but the embodiments of this disclosure are not limited thereto. For example, the pull-up TFT may include a gate electrode connected to the scan shift clock line connected to the gating control line GCL and a second electrode connected to a network line connected to the gating line GL.

[0185] According to embodiments of this disclosure, Figure 8 The two TFTs in the j-th branch circuit BCj shown can be configured to output a gating drive power supply based on the voltage of the first control node. For example, the two TFTs can be arranged in parallel with the gating control line GCL located between them. For example, each of the two TFTs in the j-th branch circuit BCj may include a gate electrode connected to the first control node, a first electrode connected to a network line connected to the gating drive power supply line, and a second electrode connected to another network line.

[0186] The branch network BN can be positioned above (or above) or below (or below) the light-emitting part EP in each horizontal row of the display area AA. For example, each horizontal row may include a middle area (or horizontal middle area) MA containing the light-emitting part EP, an upper area (or horizontal upper area) UA above the middle area MA, and a lower area (or horizontal upper area) LA below the middle area MA.

[0187] According to embodiments of this disclosure, the branch network BN can be disposed in the lower region LA of each of a plurality of horizontal rows. For example, the branch network BN can be disposed in the lower transmissive portion TP of the light-emitting portion EP in the transmissive portion TP of each of a plurality of pixels P arranged in each of the plurality of horizontal rows. For example, in Figure 3 , Figure 5 and Figure 8 In the diagram, the branch network BN is shown as being disposed in the lower region LA of each of the plurality of horizontal rows, but embodiments of the present disclosure are not limited thereto, and the branch network BN may be disposed in the upper region UA ​​of each of the plurality of horizontal rows.

[0188] A branch network BN may include multiple control nodes CN and multiple network lines NL, or it may include multiple circuit connection lines arranged in parallel at intervals. Each of the multiple control nodes CN may be electrically connected to the gate electrode of a thin-film transistor (TFT) disposed in one or more of the multiple branch circuits BC1 to BCn. For example, a first control node of the multiple control nodes may be configured to charge a voltage supplied from the branch circuit in response to a strobe start signal (or set carry signal). One or more second control nodes of the multiple control nodes may be configured to charge a voltage supplied from the branch circuit in response to a reset carry signal. For example, the voltages of the first control node and the second control node may have opposite voltage levels. For example, when the voltage of the first control node has a gate on voltage level, the voltage of the second control node may have a gate off voltage level.

[0189] Each of the multiple network lines NL can be configured to connect the gate electrode, first electrode, and second electrode of the TFT disposed in (or at) multiple branch circuits BC1 to BCn to each other. For example, the multiple branch circuits BC1 to BCn can be organically connected to each other via multiple network lines. Therefore, each of the multiple branch circuits BC1 to BCn can be organically connected to the gating control line GCL, multiple control nodes, and multiple network lines, and thus a scan signal can be output based on the gating start signal provided by the gating control line GCL, the scan shift clock, and the voltage of each of the multiple control nodes.

[0190] One or more of the multiple control nodes CN and multiple network lines NL may include a transparent conductive material capable of transmitting light. Each of the multiple control nodes CN and multiple network lines NL may include a transparent conductive material capable of transmitting light. The transparent conductive material may include a metal oxide such as indium gallium zinc oxide (IGZO). For example, the transparent conductive material may include an amorphous metal oxide. Therefore, each of the multiple control nodes and multiple network lines can be configured as a transparent conductive material, so that the transmittance (or transmissivity) of the transmissive portion TP can be increased or enhanced by light passing through the branch network BN, thereby enhancing or increasing the total transmittance (or transmissivity) of the display area AA.

[0191] According to embodiments of this disclosure, the branch network BN and multiple network lines NL may include multiple first network lines NL1 and multiple second network lines NL2.

[0192] Multiple first network lines NL1 can be configured to be spaced apart along a second direction Y and extend in a first direction X. For example, the multiple first network lines NL1 can be arranged parallel to multiple control nodes CN. For example, each of the multiple first network lines NL1 can be a horizontal network line or a horizontal line pattern. Each of the multiple first network lines NL1 can be configured to be made of a transparent conductive material.

[0193] Each of the plurality of second network lines NL2 can be configured to include one or more of a first linear line parallel to the first direction X, a second linear line parallel to the second direction Y, a nonlinear line, and a curve. Each of the plurality of second network lines NL2 can be configured to be electrically connected between the first network line NL1 and the TFT. For example, the first network line NL1 and the second network line NL2 can be configured in different layers. For example, the second network line NL2 can be electrically connected to one or more of the first network line NL1, the electrode of the TFT, and the gating control line GCL through contact holes or vias.

[0194] In the gating drive circuit 150 according to an embodiment of the present disclosure, the branch network BN disposed in each of a plurality of horizontal rows (or locations) may include a plurality of circuit connection lines CN and NL, and some of the plurality of circuit connection lines CN and NL disposed in each of the plurality of horizontal rows (or locations) may share a plurality of branch circuits BC arranged in horizontal rows (or locations) that are perpendicularly adjacent to each other along the second direction Y. For example, there may be a plurality of control nodes CN and a plurality of network lines NL, and some of the plurality of network lines NL disposed in each of the plurality of horizontal rows (or locations) may be shared by a plurality of branch circuits BC arranged in horizontal rows (or locations) that are perpendicularly adjacent to each other along the second direction Y.

[0195] According to embodiments of this disclosure, a plurality of branch circuits BC disposed in (or at) the 2k-1 horizontal row can be configured to connect to a plurality of control nodes CN disposed in (or at) the 2k-1 horizontal row, and the plurality of branch circuits BC disposed in (or at) the 2k horizontal row can be configured to connect to the plurality of control nodes CN disposed in (or at) the 2k horizontal row. Some of the plurality of branch circuits BC disposed in (or at) the 2k-1 horizontal row and some of the plurality of branch circuits BC disposed in (or at) the 2k horizontal row can be configured to connect to some of the plurality of network lines NL disposed in (or at) the 2k-1 horizontal row. For example, some of the plurality of network lines NL disposed in each of the plurality of horizontal rows can be shared by some of the plurality of branch circuits BC disposed in (or at) the 2k-1 horizontal row and some of the plurality of branch circuits BC disposed in (or at) the 2k horizontal row.

[0196] According to embodiments of this disclosure, the first electrode of the TFT in the j-th branch circuit BCj of a plurality of branch circuits BC disposed in the 2k-1 horizontal row can be configured to be connected to some of the plurality of network lines NL disposed in the 2k-1 horizontal row. For example, some of the plurality of network lines NL disposed in the 2k-1 horizontal row can be shared with the first electrode of the TFT disposed in the j-th branch circuit BCj disposed in the 2k-1 horizontal row and the first electrode of the TFT disposed in the j-th branch circuit BCj disposed in the 2k-1 horizontal row, or can be shared by the first electrode of the TFT disposed in the j-th branch circuit BCj disposed in the 2k-1 horizontal row and the first electrode of the TFT disposed in the j-th branch circuit BCj disposed in the 2k-1 horizontal row. For example, a network line connected to a gate drive power supply line among multiple first network lines NL1 located in (or at) the 2k-1 horizontal row can be commonly connected to the first electrode of a TFT located in (or at) the j-th branch circuit BCj located in (or at) each of the 2k-1 horizontal rows and the 2k horizontal row, or shared by the first electrode of a TFT located in (or at) the j-th branch circuit BCj located in (or at) each of the 2k-1 horizontal rows and the 2k horizontal row. The TFT is located in (or at) the j-th branch circuit BCj located in (or at) each of the 2k-1 horizontal rows and the 2k horizontal row. For example, a second network line NL2 located in (or at) the 2k horizontal row can be configured to electrically connect the first electrode of the TFT located in (or at) the j-th branch circuit BCj located in (or at) the 2k horizontal row to the network line located in (or at) the 2k-1 horizontal row.

[0197] According to embodiments of this disclosure, by reducing the number of network lines NL shared by multiple branch circuits arranged in (or at) horizontal rows that are vertically adjacent to each other, the number of network lines NL arranged in each of the multiple horizontal rows can be reduced. Therefore, the arrangement area of ​​branch network BN in the transmissive portion TP of each of the multiple horizontal rows can be reduced, thereby enhancing or increasing the total light transmittance (or translucency) of the display area AA.

[0198] The branch network BN according to embodiments of this disclosure may also include multiple carry signal lines CSL.

[0199] Multiple carry signal lines (CSLs) can be configured to transmit carry signals between adjacent stage circuit cells 1501 to 150m along the second direction Y. For example, multiple carry signal lines (CSLs) can be positioned between two adjacent pixels P along the first direction X, spaced apart along the second direction Y, and can be electrically connected to one or more of multiple first network lines (NL1). Figure 6 In one or more of the multiple stage circuits SC1 to SCx shown (or at one location).

[0200] like Figure 7 and Figure 8 As shown, each of the multiple carry signal lines CSL according to the embodiments of this disclosure may include multiple first carry signal lines CSL1 and multiple second carry signal lines CSL2.

[0201] Each of the plurality of first carry signal lines CSL1 can be spaced apart from its corresponding second carry signal line CSL2 along a first direction X, and can be arranged parallel to each of the plurality of second carry signal lines CSL2 along the first direction X. For example, the plurality of first carry signal lines CSL1 can be arranged to intersect with each of the plurality of second carry signal lines CSL2.

[0202] Multiple first carry signal lines CSL1 can be disposed between two adjacent pixels P along the first direction X to transmit a first carry signal between adjacent stage circuit units 1501 to 150m along the second direction Y. For example, the first carry signal can be an odd-numbered carry signal, but embodiments of this disclosure are not limited thereto, and the first carry signal can also be an even-numbered carry signal. For example, the multiple first carry signal lines CSL1 can be configured to transmit a first carry signal between odd-numbered stage circuit units 1501 to 150m disposed in (or at) the display area AA. For example, the multiple first carry signal lines can be odd-numbered carry signal lines, but embodiments of this disclosure are not limited thereto, and the multiple first carry signal lines can also be even-numbered carry signal lines.

[0203] Each of the multiple first carry signal lines CSL1 can be arranged at certain intervals along the second direction Y, and can be electrically disconnected from each other every four pixels P (or horizontal rows) along the second direction Y. For example, each of the multiple first carry signal lines CSL1 can have a length corresponding to the size of four pixels P (or horizontal rows) along the second direction Y.

[0204] According to embodiments of this disclosure, each of the plurality of first carry signal lines CSL1 can be configured to provide a first carry signal output from the stage circuit unit 150n in the nth horizontal row (or at) as a start signal (or a first node set signal) to the stage circuit unit 150n+2 in the (n+2)th horizontal row (or at), and to provide the first carry signal as a reset signal (or a first node reset signal) to the stage circuit unit 150n-2 in the (n-2)th horizontal row (or at). For example, each of the plurality of first carry signal lines CSL1 can be connected to a branch network BN in the nth horizontal row (or at) of a plurality of horizontal rows, and can be connected to the branch network BN in the (n-2)th horizontal row (or at) and the branch network BN in the (n+2)th horizontal row (or at). Therefore, the first carry signal output from the carry branch circuit of the output buffer circuit in the nth horizontal row (or at the nth position) can be provided to the first node set branch circuit of the node control circuit in the (n+2th horizontal row) through the network line of the branch network BN in the (n+2th horizontal row) and the first carry signal line CSL1, and at the same time, it can be provided to the first node reset branch circuit of the node control circuit in the (n-2th horizontal row) through the network line of the branch network BN in the (n-2th horizontal row) and the first carry signal line CSL1.

[0205] Therefore, the odd-numbered stage circuit units among the multiple stage circuit units 1501 to 150m located in (or at) the display area AA can transmit and receive the first carry signal through each of the multiple first carry signal lines CSL1, thus enabling sequential drive to begin or to be reset.

[0206] Multiple second carry signal lines CSL2 can be disposed between two adjacent pixels P along the first direction X to transmit a second carry signal between adjacent stage circuit units 1501 to 150m along the second direction Y. The second carry signal can be an even-numbered carry signal, but embodiments of this disclosure are not limited thereto; the second carry signal can also be an odd-numbered carry signal. For example, the multiple second carry signal lines CSL2 can be configured to transmit a second carry signal between even-numbered stage circuit units 1501 to 150m disposed in (or at) the display area AA. For example, the multiple second carry signal lines can be even-numbered carry signal lines, but embodiments of this disclosure are not limited thereto; and the multiple second carry signal lines can also be odd-numbered carry signal lines.

[0207] Each of the multiple second carry signal lines CSL2 can be arranged at certain intervals along the second direction Y, and can be electrically disconnected from each other every four pixels P (or horizontal rows) along the second direction Y. For example, each of the multiple second carry signal lines CSL2 can have a length corresponding to the size of four pixels P (or horizontal rows) along the second direction Y.

[0208] According to embodiments of this disclosure, each of the plurality of second carry signal lines CSL2 can be configured to provide a second carry signal output from the stage circuit unit 150n+1 in the (n+1)th horizontal row (or at) as a start signal (or a first node set signal) to the stage circuit unit 150n+3 in the (n+3)th horizontal row (or at), and to provide the second carry signal as a reset signal (or a first node reset signal) to the stage circuit unit 150n-1 in the (n-1)th horizontal row (or at). For example, each of the plurality of second carry signal lines CSL2 can be connected to a branch network BN in the (n+1)th horizontal row (or at) of a plurality of horizontal rows, and can be connected to both the branch network BN in the (n-1)th horizontal row (or at) and the branch network BN in the (n+3)th horizontal row (or at). Therefore, the second carry signal output from the carry branch circuit of the output buffer circuit in the (n+1)th horizontal row can be provided to the first node set branch circuit of the node control circuit in the (n+3)th horizontal row through the network line of the branch network BN and the second carry signal line CSL2. At the same time, it can be provided to the first node reset branch circuit of the node control circuit in the (n-1)th horizontal row through the network line of the branch network BN and the second carry signal line CSL2.

[0209] Therefore, the even-numbered stage circuit units 1501 to 150m of the multiple stage circuit units located in (or at) the display area AA can transmit and receive the second carry signal through each of the multiple second carry signal lines CSL2, and thus, sequential drive can be started or sequential drive can be reset.

[0210] Each of the plurality of dummy patterns 160 according to embodiments of the present disclosure may be disposed on the substrate 100 to overlap with the gating drive circuit 150. For example, each of the plurality of dummy patterns 160 may be disposed in (or at) the display area AA to overlap with a plurality of branch circuits BC disposed in (or at) the gating drive circuit 150, respectively.

[0211] According to embodiments of this disclosure, each of the plurality of dummy patterns 160 can be configured to respectively cover a plurality of branch circuits BC disposed in (or at) the gating drive circuit 150. Each of the plurality of dummy patterns 160 can be configured to have the same shape and the same size. Each of the plurality of dummy patterns 160 can be configured to be disposed at the same position (or in the middle) between two adjacent pixels P along the first direction X. For example, the plurality of dummy patterns 160 can be located or aligned on the same line (or at) relative to the first direction X. For example, the central portion (or middle portion) of each of the plurality of dummy patterns 160 can be located or aligned on a dummy horizontal line (or at) parallel to the first direction X.

[0212] According to embodiments of this disclosure, one or more first dummy patterns 161 of a plurality of dummy patterns 160 can be configured to cover the i-th branch circuit BCI, which includes one TFT, among a plurality of branch circuits BC. For example, one or more second dummy patterns 162 of a plurality of dummy patterns 160 can be configured to cover the j-th branch circuit BCj, which includes two or more TFTs, among a plurality of branch circuits BC. One or more first dummy patterns 161 and one or more second dummy patterns 162 can be configured to have the same shape and the same size. For example, one or more first dummy patterns 161 and one or more second dummy patterns 162 can be configured to have a size (or area) relatively larger than the size (or area) of each of the corresponding branch circuits BCI and BCj, so as to completely cover the corresponding branch circuits BCI and BCj. Therefore, each of the plurality of dummy patterns 160 can reduce, minimize, or prevent dulling phenomena such as streaks or spots that occur due to size (or transmittance or transparency) deviations between the transmissive portions TP caused by size (or area) deviations between the corresponding branch circuits BCI and BCj.

[0213] According to embodiments of this disclosure, one or more third dummy patterns 163 of a plurality of dummy patterns 160 may be configured to cover a plurality of carry signal lines CSL disposed between two pixels P that are adjacent to each other along the first direction X.

[0214] One or more third dummy patterns 163 may be configured to have the same shape and the same size as each of one or more first dummy patterns 161 and one or more second dummy patterns 162. For example, each of one or more first dummy patterns 161, one or more second dummy patterns 162 and one or more third dummy patterns 163 may be located or aligned on the same line (or at the same location) relative to the first direction X. For example, in the region between the light-emitting portions EP of pixel P, the size (or transmittance or transparency) of the transmissive portion TP (or the first region) provided with branch circuits BCI and BCj may be different from the size (or transmittance or transparency) of the transmissive portion TP (or the second region) provided with multiple carry signal lines CSL but without branch circuits BCI and BCj. Therefore, one or more third dummy patterns 163 may be configured to cover multiple carry signal lines CSL, thereby further reducing, minimizing or preventing dimming phenomena such as streaks or stains caused by size (or transmittance or transparency) deviations between transmissive portions TP due to size (or area) deviations between branch circuits BCI and BCj and multiple carry signal lines CSL.

[0215] Each of the plurality of dummy patterns 160 according to embodiments of the present disclosure may be configured to include a material for collecting hydrogen or capable of capturing hydrogen atoms. That is, the plurality of dummy patterns 160 may be formed of a material capable of collecting hydrogen (i.e., a hydrogen-collecting material). For example, each of the plurality of dummy patterns 160 may include a metallic material comprising titanium (Ti). For example, each of the plurality of dummy patterns 160 may include a metallic material comprising Ti or a molybdenum-titanium alloy (MoTi). For example, each of the plurality of dummy patterns 160 may be a single layer of titanium, a double layer of molybdenum (Mo) and titanium (Ti), or an alloy of molybdenum (Mo) and titanium (Ti). Therefore, each of the plurality of dummy patterns 160 may collect or block hydrogen diffusion from the hydrogen-containing material formed or disposed around it, thereby reducing, minimizing, or preventing changes in the electrical characteristics of the TFT of the pixel P and / or the TFT of the gate drive circuit 150 disposed in (or at) the display area AA caused by hydrogen.

[0216] The display device (or display panel 10 or display area AA) according to the embodiments of this disclosure may also include a plurality of dummy lines 170.

[0217] The multiple dummy lines 170 can be configured such that the number of signal lines located in the region (or at) between two adjacent pixels P along the first direction X is constant (or the same or equal). Each of the multiple dummy lines 170 can be set to be adjacent to each of the multiple gating control lines GCL and each of the multiple carry signal lines CSL.

[0218] According to embodiments of this disclosure, one or more of the plurality of dummy lines 170 may be arranged adjacent to each of the plurality of gating control lines GCL. For example, one or more of the plurality of dummy lines 170 may be arranged adjacent to a start signal line, a plurality of scan shift clock lines, a plurality of feed shift clock lines, one or more gating drive power lines, and one or more gating common power lines.

[0219] According to embodiments of this disclosure, one or more of the plurality of dummy lines 170 may be configured to be adjacent to each of the plurality of carry signal lines CSL.

[0220] According to embodiments of this disclosure, multiple gate control lines GCL can be arranged one by one between multiple pixels P, and multiple carry signal lines CSL can be arranged two by two between multiple pixels P. Therefore, in the region between the light-emitting portions EP of pixel P, the size (or transmittance or transparency) of the transmissive portion (or first transmissive portion) TP with one gate control line GCL can be different from the size (or transmittance or transparency) of the transmissive portion (or second transmissive portion) TP with multiple carry signal lines CSL. Therefore, multiple dummy lines 170 can be arranged to be adjacent to each of the multiple gate control lines GCL and each of the multiple carry signal lines CSL, thereby additionally reducing, minimizing, or preventing dimness phenomena such as streaks or stains caused by deviations in the size (or transmittance or transparency) of the transmissive portion TP due to deviations in the number of gate control lines GCL and carry signal lines CSL arranged in (or at) the light-emitting portions EP of pixel P.

[0221] According to embodiments of this disclosure, the first dummy line 171 and the second dummy line 172 among the plurality of dummy lines 170 can be configured to be adjacent to each of the plurality of gating control lines GCL. For example, the first dummy line 171 and the second dummy line 172 can be configured to overlap with each of the branch circuit BC and the dummy pattern 160 in a transmissive portion TP between two adjacent pixels P along the first direction X, parallel to the gating control line GCL. For example, the first dummy line 171 and the second dummy line 172 can be arranged parallel to the gating control line GCL between them, but embodiments of this disclosure are not limited thereto. For example, the first dummy line 171 and the second dummy line 172 can be arranged parallel to one side or the other side of the gating control line GCL. Therefore, a transmissive portion (or a first transmissive portion) between two adjacent pixels P along the first direction X, wherein a branch circuit BC is provided, can include three lines, such as a gating control line GCL and the first dummy line 171 and the second dummy line 172. For example, a first region (or transmissive portion TP) among multiple regions between two adjacent pixels P along the first direction X may include three lines, such as a gating control line GCL and a first dummy line 171 and a second dummy line 172. For example, the first region may be a first transmissive region, a circuit setting region, or a branch circuit setting region among multiple regions between two adjacent pixels P along the first direction X.

[0222] According to embodiments of this disclosure, the third dummy line 173 among the plurality of dummy lines 170 can be configured to be adjacent to each of the plurality of carry signal lines CSL. For example, the third dummy line 173 can be configured to overlap with the dummy pattern 160 in parallel with each of the plurality of carry signal lines CSL in the transmissive portion TP between two adjacent pixels P along the first direction X, but embodiments of this disclosure are not limited thereto.

[0223] According to embodiments of this disclosure, the third dummy line 173 can be configured parallel to the first carry signal line CSL1, or it can be configured between the configuration areas of multiple first carry signal lines CSL1 and multiple second carry signal lines CSL2. For example, the third dummy line 173 can be configured parallel to the second carry signal line CSL2, or it can be configured between the configuration areas of multiple first carry signal lines CSL1 and multiple second carry signal lines CSL2. For example, the third dummy line 173 can also be configured on one side or the other side of the multiple carry signal lines CSL. Therefore, the transmissive portion TP between two adjacent pixels P along the first direction X, wherein the carry signal line CSL is configured and there is no branch circuit BC, can include three lines, for example, two signal lines SSL1 and SSL2 and one third dummy line 173. For example, a second region (or transmissive portion TP) among multiple regions between two adjacent pixels P along the first direction X may include three lines, such as two signal lines SSL1 and SSL2 and a third dummy line 173. For example, the second region may be a second transmissive region, a circuit-free region, or a branch circuit-free region among multiple regions between two adjacent pixels P along the first direction X.

[0224] According to embodiments of this disclosure, the gating control line GCL, the carry signal line CSL, and the dummy line 170 can be disposed at the same position in the transmission section TP, or they can be disposed at the same position at a constant interval. Therefore, the position of the transmission area of ​​the transmission section TP based on the placement position of each of the gating control line GCL, the carry signal line CSL, and the dummy line 170 disposed in (or at) the transmission section TP can be equal or uniform.

[0225] According to embodiments of this disclosure, in a transmissive section TP including a branch circuit BC, a gating control line GCL can be disposed at the boundary portion (or center portion) between two adjacent pixels P along the first direction X, and each of the first dummy line 171 and the second dummy line 172 can be spaced apart from the gating control line GCL by a first distance. For example, in a transmissive section (or first transmissive section) TP including a branch circuit BC, the interval between the gating control line GCL and the first dummy line 171 and the second dummy line 172 can be equal.

[0226] According to embodiments of this disclosure, in a transmissive portion TP including a carry signal line CSL, a third dummy line 173 may be disposed at the boundary portion (or center portion) between two adjacent pixels P along the first direction X, and each of the two carry signal lines CSL may be spaced apart from the third dummy line 173 by a first distance. For example, in a transmissive portion (or second transmissive portion) TP including a carry signal line CSL, the interval between the carry signal line CSL and the first dummy line 171 and the second dummy line 172 may be equal.

[0227] According to embodiments of this disclosure, when multiple gating control lines GCL and multiple carry signal lines CSL, which are disposed in the region (or location) between two adjacent pixels P along the first direction X and selectively connected to multiple branch circuits BC, are referred to as multiple lines, the number of lines disposed in the region (or location) between two adjacent pixels P along the first direction X and selectively connected to multiple branch circuits BC can be equal. For example, the number of lines disposed in the display area AA in the region (or location) between two adjacent pixels P along the first direction X can be equal.

[0228] According to embodiments of this disclosure, each of the transmissive portion (or first transmissive portion) TP provided with a branch circuit BC and a gating control line GCL and the transmissive portion (or second transmissive portion) TP provided with a carry signal line CSL can include the same number of lines based on one or more dummy lines 170, thereby additionally reducing, minimizing or preventing dulling phenomena such as streaks or stains that occur due to deviations in the size (or transmittance or transparency) of the transmissive portion TP caused by deviations in the number of gating control lines GCL and carry signal lines CSL.

[0229] Figure 9 It is along the exemplary embodiments of this disclosure. Figure 8 The cross-sectional view taken by line I-I' is shown. Figure 9 This is an example Figure 8 The diagram shows the gating control line, the TFT of the branch circuit, the dummy pattern, and the cross-sectional view of multiple dummy lines.

[0230] Reference Figure 8 and Figure 9 According to embodiments of the present disclosure, the gating control line GCL can be disposed on the substrate 100 between two adjacent pixels P along the first direction X and can be parallel to the second direction Y. For example, the gating control line GCL can be configured to directly contact the upper surface 100a of the substrate 100, but embodiments of the present disclosure are not limited thereto.

[0231] The gating control line GCL can be implemented by a patterning process of a light-blocking layer (or lower metal layer) disposed between the substrate 100 and the TFTs of the pixel circuits disposed in (or at) each of the plurality of pixels P. For example, the light-blocking layer can be used as a signal line parallel to the first direction X among the signal lines disposed in (or at) the display area AA. Figure 8 The strobe control line GCL shown may be a scan shift clock line, but the embodiments of this disclosure are not limited thereto.

[0232] The gate control line GCL or light blocking layer according to embodiments of the present disclosure can be made of a single-layer or multi-layer structure including at least one of molybdenum (Mo), titanium (Ti), molybdenum-titanium alloy (MoTi), and copper (Cu), but embodiments of the present disclosure are not limited thereto. The gate control line GCL or light blocking layer can be covered by a buffer layer 101a.

[0233] According to embodiments of the present disclosure, the TFT of the branch circuit BC can be disposed on a buffer layer 101a adjacent to the gate control line GCL. The TFT of the branch circuit BC can be formed together with the TFTs of the pixel circuits disposed at each (or in) a plurality of pixels P. For example, the TFT of the branch circuit BC may include an active layer ACT, a gate insulating layer GI, a gate electrode GE, an interlayer insulating layer 101b, a first electrode E1, and a second electrode E2.

[0234] The active layer ACT can be disposed on the buffer layer 101a of the branch circuit region. The active layer ACT may include a source region and a drain region, as well as a channel region between the source region and the drain region. For example, the active layer ACT may be conductive in the conductivity process, and therefore can be used as a bridging wire in the jumper structure, which directly connects the signal lines in the display area AA (within) or electrically connects lines disposed on different layers (or locations).

[0235] The gate insulating layer GI can be disposed on the channel region of the active layer ACT. The gate insulating layer GI can insulate the active layer ACT from the gate electrode GE.

[0236] The gate electrode GE can be disposed on the gate insulating layer GI. The gate electrode GE can overlap with the channel region of the active layer ACT, wherein the gate insulating layer GI is located therebetween. The gate electrode GE according to embodiments of the present disclosure can be made of a single-layer structure or a multi-layer structure including at least one of molybdenum (Mo), titanium (Ti), Mo-Ti alloy (MoTi) and copper (Cu), but embodiments of the present disclosure are not limited thereto.

[0237] An interlayer insulating layer 101b may be disposed on the substrate 100 to cover the gate electrode GE and the active layer ACT of the TFT. The interlayer insulating layer 101b can electrically insulate (or isolate) the gate electrode GE.

[0238] The first electrode E1 can be disposed on the interlayer insulating layer 101b overlapping the source region (or drain region) of the active layer ACT, and can be electrically connected to the source region (or drain region) of the active layer ACT through the first contact hole disposed at (or in) the interlayer insulating layer 101b.

[0239] The second electrode E2 can be disposed on the interlayer insulating layer 101b overlapping the drain region (or source region) of the active layer ACT, and can be electrically connected to the drain region (or source region) of the active layer ACT through the second contact hole disposed at the interlayer insulating layer 101b.

[0240] According to embodiments of this disclosure, the first electrode E1 and the second electrode E2 may have a single-layer structure or a multi-layer structure made of the same material as the gate electrode GE.

[0241] According to embodiments of this disclosure, in the TFT of the branch circuit BC, each of the gate electrode GE, the first electrode E1, and the second electrode E2 can be selectively connected to the gating control line GCL and the branch network BN. For example, in Figure 8 and Figure 9 In the branch circuit BCI shown, the gate electrode GE can be connected to the first control node. The first electrode E1 can be electrically connected to the gating control line GCL through the line contact hole LCH disposed in (or at) the buffer layer 101a and the interlayer insulating layer 101b. The second electrode E2 can be connected to any one of the multiple network lines.

[0242] The TFT of the branch circuit BC can be covered by a passivation layer 101c. For example, the passivation layer 101c can be formed of an inorganic material. For example, the passivation layer 101c can be omitted.

[0243] The branch circuit BC or passivation layer 101c can be covered by a first outer coating layer (or a first planarization layer) 102. The first outer coating layer 102 can planarize the upper part (or upper surface) of the passivation layer 101c and protect the TFT. For example, the first outer coating layer 102 can be formed to have a relatively thick thickness, thus providing a flat surface on the upper part (or upper surface) of the passivation layer 101c.

[0244] According to embodiments of the present disclosure, a dummy pattern 160 may be disposed on the first outer coating 102 to overlap with or cover the branch circuit BC. For example, a first dummy pattern 161 of a plurality of dummy patterns 160 may be disposed on the first outer coating 102 to overlap with or cover the branch circuit BC, which includes one or more TFTs. For example, a second dummy pattern 162 of a plurality of dummy patterns 160 may be disposed on the first outer coating 102 to overlap with or cover the branch circuit BC, which includes two or more TFTs.

[0245] According to embodiments of this disclosure, a dummy pattern 160 may be disposed on the first outer coating 102 to cover the branch circuit BC. For example, the dummy pattern 160 may be disposed on the first outer coating 102 to cover the TFT of the branch circuit BC. For example, the dummy pattern 160 may be configured to block light incident from the outside onto the TFT of the branch circuit BC.

[0246] According to embodiments of this disclosure, the dummy pattern 160 may have a size larger than the size of the branch circuit BC. For example, the size of the dummy pattern 160 may be larger than the size of the TFT of the branch circuit BC. For example, the dummy pattern 160 may have a size larger than the size of the TFT of the branch circuit BC, which is within the range for reducing or minimizing the reduction in the size (or area) of the transmissive portion TP disposed between two adjacent pixels P where the branch circuit BC is disposed.

[0247] According to embodiments of the present disclosure, the dummy pattern 160 may have a shape and size that completely covers the branch circuit BC or the TFT that completely covers the branch circuit BC. For example, the dummy pattern 160 may have a square or circular shape, but the present disclosure is not limited thereto, and various other shapes are also possible. Each of the plurality of dummy patterns 160 according to embodiments of the present disclosure may be implemented in the shape of an island within the display area AA, and thus may be electrically floating. Therefore, the potential of each of the plurality of dummy patterns 160 may change based on a change in the signal applied to the branch circuit BC, and a failure of the branch circuit BC or the TFT of the branch circuit BC may occur due to the potential change of each of the plurality of dummy patterns 160. In order to reduce, minimize, or prevent failure of the branch circuit BC caused by the potential change of each of the plurality of dummy patterns 160, the first outer coating 102 between the dummy pattern 160 and the branch circuit BC may be formed to have a sufficiently large thickness.

[0248] The dummy pattern 160 may be covered by a second outer coating (or a second planarization layer) 104. The second outer coating 104 may be disposed on the first outer coating 102 to cover or surround the dummy pattern 160, and may provide a flat surface on the upper portion (or upper surface) of the dummy pattern 160 and the first outer coating 102. For example, the second outer coating 104 may comprise the same material as the first outer coating 102, and may be formed to have a thickness that is the same as or different from that of the first outer coating 102.

[0249] According to embodiments of this disclosure, multiple dummy lines 170 can be disposed on a second outer coating 104 overlapping with the dummy pattern 160. For example, a first dummy line 171 and a second dummy line 172 of the multiple dummy lines 170 can be disposed on the second outer coating 104 overlapping with the dummy pattern 160 (with a gating control line GCL located therebetween). For example, the interval (or distance) between the gating control line GCL and the first dummy line 171 and the second dummy line 172 can be equal.

[0250] According to embodiments of the present disclosure, multiple dummy lines 170 can be formed together with pixel electrodes PE disposed at the second outer coating 104 in the light-emitting portion EP of each of the plurality of pixels P. For example, each of the plurality of second dummy patterns 180 can be formed from the same material in the same process as the pixel electrode PE, but embodiments of the present disclosure are not limited thereto.

[0251] The second outer coating 104 and the multiple dummy lines 170 on the dummy pattern 160, which are disposed between the light-emitting portions EP of each of the plurality of pixels P, can be covered by the dike layer 105. The dike layer 105 can be disposed in other areas (or locations) of the display area AA besides the light-emitting portions EP of each of the plurality of pixels P. For example, the dike layer 105 may include multiple opening patterns corresponding to the central portion of the pixel electrode disposed in (or at) the light-emitting portion EP of each of the plurality of pixels P. The dike layer 105 may include a transparent inorganic material or a transparent organic material.

[0252] According to embodiments of this disclosure, light-emitting devices and common electrodes can be sequentially arranged on the dam layer 105. An encapsulation layer including multiple inorganic encapsulation layers and one or more organic encapsulation layers can be disposed on the common electrode, and color filters can be disposed on the encapsulation layer overlapping with the light-emitting portion EP of each of the multiple pixels P or each of the multiple opening patterns of the dam layer 105.

[0253] As described above, the dummy pattern 160 can reduce, minimize, or prevent dimensional (or transmittance or transparency) deviations between transmissive portions TP caused by dimensional (or area) deviations between branch circuits BC, thereby enhancing the light transmittance or translucency of the display device (or transparent display device) according to embodiments of the present disclosure. Furthermore, the multiple dummy lines 170 can additionally reduce, minimize, or prevent dulling phenomena such as streaks or spots caused by dimensional (or transmittance or transparency) deviations in the transmissive portions TP due to quantity deviations between the gate control line GCL and carry signal line CSL disposed in (or at) the light-emitting portions EP of pixels P.

[0254] The dummy pattern 160 according to embodiments of the present disclosure can be configured to include a material for collecting hydrogen. For example, the dummy pattern 160 may include a metallic material comprising titanium (Ti). For example, the dummy pattern 160 may include a metallic material comprising Ti or a molybdenum-titanium alloy (MoTi). Therefore, the dummy pattern 160 can collect or block hydrogen generated in one or more of the buffer layer 101a, interlayer insulating layer 101b, passivation layer 101c, first outer coating layer 102, second outer coating layer 104, dam layer 105, and encapsulation layer disposed in (or at) the display area AA, thereby reducing, minimizing, or preventing changes in the electrical characteristics of the TFT of pixel P and / or the TFT of the gate driving circuit 150 caused by hydrogen.

[0255] Figure 10 It is along the exemplary embodiments of this disclosure. Figure 8 The cross-sectional view taken from line II-II' is shown. Figure 10 This is an example Figure 8 The diagram shows multiple carry signal lines, dummy patterns, and cross-sectional views of the dummy lines.

[0256] Reference Figure 8 and Figure 10 According to embodiments of the present disclosure, each of the multiple carry signal lines CSL can be disposed on a substrate 100 between two adjacent pixels P along a first direction X, and can be parallel to a second direction Y. For example, the multiple carry signal lines CSL can be configured to directly contact the upper surface 100a of the substrate 100, but embodiments of the present disclosure are not limited thereto. For example, the multiple carry signal lines CSL can be formed from the same material in the same process as the gating control line GCL, but embodiments of the present disclosure are not limited thereto.

[0257] Each of the multiple carry signal lines CSL can be located in a region (or second region) of the area between two adjacent pixels P along the first direction X (or the transmissive portion TP) where no branch circuit BC is located. For example, each of the multiple carry signal lines CSL can be located in one or more first carry signal regions and second carry signal regions within the area between two adjacent pixels P along the first direction X. For example, the multiple carry signal lines CSL can include multiple first carry signal lines CSL1 and multiple second carry signal lines CSL2. For example, the multiple first carry signal lines CSL1 can be located at intervals along the second direction Y in the first carry signal region. The multiple second carry signal lines CSL2 can be located at intervals along the second direction Y in the second carry signal region adjacent to the first carry signal region.

[0258] Multiple carry signal lines CSL can be covered by interlayer insulating layer 101b, passivation layer 101c, and first outer coating layer 102. For example, when passivation layer 101c is omitted, multiple carry signal lines CSL can be covered by interlayer insulating layer 101b and first outer coating layer 102.

[0259] Multiple dummy patterns 160 can be disposed on a first outer coating 102 on multiple carry signal lines CSL. The dummy patterns 160 can be configured to cover a portion of each of the multiple carry signal lines CSL disposed in (or at) a transmissive portion (or second transmissive portion) TP between two adjacent pixels P along the first direction X. For example, a third dummy pattern 163 of the multiple dummy patterns 160 can be disposed on the first outer coating 102 on the multiple carry signal lines CSL. The dummy patterns 160 can be covered by a second outer coating 104.

[0260] According to embodiments of the present disclosure, a third dummy pattern 163 among a plurality of dummy patterns 160 can be disposed on a second outer coating 104 overlapping with a plurality of carry signal lines CSL and the third dummy pattern 160. A third dummy line 173 can be disposed parallel to a first carry signal line CSL1, or can be disposed between a first carry signal region and a second carry signal region. A third dummy line 173 can be disposed parallel to a second carry signal line CSL2, or can be disposed between a first carry signal region and a second carry signal region. For example, the interval (or distance) between the plurality of carry signal lines CSL and the third dummy line 173 can be equal.

[0261] Figure 11 It is along the exemplary embodiments of this disclosure. Figure 8 Another cross-sectional view taken from line I-I'. Figure 12 It is along the exemplary embodiments of this disclosure. Figure 8Another cross-sectional view taken from line II-II' shown. Figure 11 and Figure 12 An example is shown by... Figure 8 The illustrated implementation involves the dummy patterns and dummy lines being electrically connected to each other. Therefore, in the following description, repeated descriptions of other elements besides the connection structure between the dummy patterns and dummy lines and related components are omitted or can be briefly provided.

[0262] Reference Figure 8 , Figure 10 and Figure 11 In the display device according to an embodiment of the present disclosure, each of the plurality of dummy lines 170 may be disposed on the second outer coating 104 to overlap with each of the plurality of dummy patterns 160 along the second direction Y, and may be electrically connected to the corresponding dummy pattern in the plurality of dummy patterns 160 through a contact hole 170h disposed in (or at) the second outer coating 104 overlapping with each of the plurality of dummy patterns 160.

[0263] According to embodiments of this disclosure, one or more of the first dummy line 171 and the second dummy line 172 in a plurality of dummy lines 170 can be electrically connected to the first dummy pattern 161 and the second dummy pattern 162 in a plurality of dummy patterns 160, respectively. For example, one or more of the first dummy line 171 and the second dummy line 172 can be disposed on the second outer coating 104 to overlap with a plurality of first dummy patterns 161 disposed along the second direction Y in a plurality of dummy patterns 160, and can be electrically connected to a corresponding first dummy pattern 161 in a plurality of first dummy patterns 161 through a corresponding contact hole 170h in a plurality of contact holes 170h. For example, one or more of the first dummy line 171 and the second dummy line 172 can be disposed on the second outer coating 104 to overlap with a plurality of second dummy patterns 162 disposed along the second direction Y in a plurality of dummy patterns 160, and can be electrically connected to a corresponding second dummy pattern 162 in a plurality of second dummy patterns 162 through a corresponding contact hole 170h in a plurality of contact holes 170h.

[0264] According to embodiments of this disclosure, a third dummy line 173 among the plurality of dummy lines 170 can be disposed on the second outer coating 104 to overlap with a plurality of third dummy patterns 163 disposed along the second direction Y among the plurality of dummy patterns 160, and can be electrically connected to a corresponding third dummy pattern 163 among the plurality of third dummy patterns 163 through a corresponding contact hole 170h among the plurality of contact holes 170h.

[0265] Each of the plurality of dummy lines 170 can be configured to maintain a specific potential of each of the plurality of dummy patterns 160 in an electrically floating state. For example, each of the plurality of dummy lines 170 can provide a direct current (DC) voltage to each of the plurality of dummy patterns 160. For example, each of the plurality of dummy lines 170 can be configured to provide a common pixel voltage provided from the pad portion 110 to each of the plurality of dummy patterns 160.

[0266] Each of the plurality of dummy lines 170 according to embodiments of the present disclosure can be configured to be electrically connected to Figure 3 The pixel common voltage pad CVP is shown in the pad portion 110. For example, each of the plurality of dummy lines 170 can be configured to be electrically connected to one or more of the line connection pattern LCP, pixel common voltage line CVL, and auxiliary voltage line SVL that are electrically connected to the pixel common voltage pad CVP. For example, each of the plurality of dummy lines 170 can be configured to intersect with one or more of the plurality of line connection patterns LCP, and can be electrically connected to the line connection pattern LCP through a contact hole provided in (or at) the intersection with one or more line connection patterns LCP.

[0267] Additionally, an intermediate metal pattern can be additionally disposed between each of the plurality of dummy lines 170 and the line-connecting pattern LCP. The intermediate metal pattern can be configured to reduce the height difference (or step height) between the dummy line 170 and the line-connecting pattern LCP. Therefore, each of the plurality of dummy lines 170 can be stably connected to the line-connecting pattern LCP through the intermediate metal pattern. Thus, each of the plurality of dummy lines 170 can provide the pixel common voltage provided through the pixel common voltage pad CVP and the pixel common voltage line CVL to the corresponding dummy pattern in the plurality of dummy patterns 160.

[0268] According to embodiments of this disclosure, each of the plurality of dummy patterns 160 can be electrically connected to the dummy line 170, thus not affecting changes in the signal applied to the branch circuit BC or the gating control line GCL, and can be fixed or maintained at a certain potential or the pixel common voltage. Therefore, each of the plurality of dummy patterns 160 can reduce, minimize, or prevent dimensional (or transmittance or transparency) deviations between the transmissive portions TP caused by dimensional (or area) deviations between the branch circuits BC, without causing malfunctions in the branch circuit BC or the TFT of the branch circuit BC, thereby enhancing the light transmittance or translucency of the display device (or transparent display device) according to embodiments of this disclosure.

[0269] Figure 13 It is a diagram used to describe the dummy network lines according to an exemplary embodiment of the present disclosure. Figure 14This is an illustrative example of an exemplary embodiment according to the present disclosure. Figure 13 The diagram shows the connection structure between the dummy pattern and the dummy network lines. Figure 13 and Figure 14 Examples of other services provided with Figures 8 to 10 The embodiment of the dummy pattern connection of the dummy network lines is shown. Therefore, in the following description, repeated descriptions of other elements besides the connection structure between the dummy pattern and the dummy network lines and related elements are omitted or can be briefly provided.

[0270] Reference Figure 13 and Figure 14 In a display device according to an embodiment of the present disclosure, the branch network BN in each of a plurality of horizontal rows disposed in the display area AA may include a dummy network line DNL.

[0271] A dummy network line (DNL) can include a first dummy network line (DNL1) and a second dummy network line (DNL2).

[0272] The first dummy network line DNL1 can extend relatively long parallel to the first direction X, and can be configured to be parallel to multiple control nodes CN. For example, the first dummy network line DNL1 can be disposed between the light-emitting part EP and the control node CN in each horizontal row (or at each location), but the embodiments of this disclosure are not limited thereto. For example, the first dummy network line DNL1 can be formed from the same material as the multiple control nodes CN in the same process, but the embodiments of this disclosure are not limited thereto.

[0273] According to embodiments of this disclosure, the first dummy network line DNL1 can be configured to be electrically connected to Figure 3 The pixel common voltage pad CVP is located in (or at) the pad portion 110 shown. For example, the first dummy network line DNL1 can be configured to be electrically connected to the pixel common voltage line CVL, which is electrically connected to the pixel common voltage pad CVP. For example, the first dummy network line DNL1 can be configured to cross the pixel common voltage line CVL, and can be electrically connected to the pixel common voltage line CVL through a first contact hole CH1 provided in (or at) the intersection region between the first dummy network line DNL1 and the pixel common voltage line CVL.

[0274] According to another embodiment of this disclosure, the first dummy network line DNL1 can be configured to be electrically connected to... Figure 3The gated common power pad of the gated pad GP in the pad portion 110 shown. For example, the first dummy netline DNL1 can be configured to be electrically connected to the gated common power line GCPL which is electrically connected to the gated common power pad. For example, the first dummy netline DNL1 can be configured to cross the gated common power line GCPL, and can be electrically connected to the gated common power line GCPL through the first contact hole CH1 provided in the cross region (or location) between the first dummy netline DNL1 and the gated common power line GCPL.

[0275] The second dummy network line DNL2 can be configured to be electrically connected to the first dummy network line DNL1 and the dummy pattern 160.

[0276] According to embodiments of this disclosure, the second dummy network line DNL2 can be formed from the same material and in the same process as the gated common power line GCPL, but embodiments of this disclosure are not limited thereto. The second dummy network line DNL2 can be electrically connected to the first dummy network line DNL1 via a second contact hole CH2 disposed in the intersection region (or location) between the second dummy network line DNL2 and the first dummy network line DNL1. The dummy pattern 160 can be electrically connected to the second dummy network line DNL2 via a third contact hole CH3 disposed in the overlapping region (or location) between the dummy pattern 160 and the second dummy network line DNL2. Therefore, the dummy pattern 160 can be fixed or maintained at a specific DC potential or the potential of the pixel common voltage provided by the pixel common voltage line CVL (or gated common power line GCPL), the first dummy network line DNL1, and the second dummy network line DNL2.

[0277] According to another embodiment of this disclosure, a second dummy network line DNL2 can extend from one side of the first dummy network line DNL1 to overlap with the dummy pattern 160. The second dummy network line DNL2 can be formed from the same material and in the same process as the first dummy network line DNL1. The dummy pattern 160 can be electrically connected to the second dummy network line DNL2 through a third contact hole CH3 disposed in the overlapping region (or location) between the dummy pattern 160 and the second dummy network line DNL2.

[0278] Therefore, the plurality of dummy patterns 160 can be fixed or maintained at a specific DC potential or the potential of the pixel common voltage provided by the pixel common voltage line CVL (or gate common power line GCPL), the first dummy network line DNL1, and the second dummy network line DNL2. Thus, each of the plurality of dummy patterns 160 can reduce, minimize, or prevent dimensional (or transmittance or transparency) deviations between the transmissive portions TP caused by dimensional (or area) deviations between the branch circuits BC, without causing malfunctions in the branch circuits BC or the TFTs of the branch circuits BC, thereby enhancing the light transmittance or translucency of the display device (or transparent display device) according to embodiments of the present disclosure.

[0279] Figure 15 This is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure. Figure 16 It is along the exemplary embodiments of this disclosure. Figure 15 The cross-sectional view taken from line III-III' is shown. Figure 17 It is along the exemplary embodiments of this disclosure. Figure 15 Another cross-sectional view taken from line IV-IV'. Figures 15 to 17 This is an example Figure 2 The displayed area is a portion of the area, and an example is shown by modifying... Figures 2 to 8 The embodiment shown is implemented using carry signal lines and dummy lines in a display device according to an exemplary embodiment of this disclosure. Therefore, in the following description, repeated descriptions of other elements besides carry signal lines, dummy lines, and related components are omitted or may be briefly provided.

[0280] Combination Figure 7 Reference Figures 15 to 17 According to embodiments of the present disclosure, each of the multiple carry signal lines CSL may include multiple first carry signal lines CSL1 and multiple second carry signal lines CSL2.

[0281] Besides the fact that multiple first carry signal lines CSL1 and multiple second carry signal lines CSL2 are located on different layers (or locations), each of the multiple carry signal lines CSL can be referenced above. Figure 8 and Figure 10 Each of the multiple carry signal lines CSL described is the same, therefore, their repeated descriptions are omitted or will be briefly given below.

[0282] According to embodiments of this disclosure, each of the plurality of first carry signal lines CSL1 can be configured to intersect with each of the plurality of second carry signal lines CSL2, with a dummy pattern 160 between them. For example, the central portion between the setting area of ​​the plurality of first carry signal lines CSL1 and the setting area of ​​the plurality of second carry signal lines CSL2 can be located at the center (or in the middle) of two pixels P that are adjacent to each other along the first direction X.

[0283] According to embodiments of this disclosure, each of the plurality of first carry signal lines CSL1 can be configured to directly contact the upper surface 100a of the substrate 100. For example, each of the plurality of first carry signal lines CSL1 can be formed of the same material and in the same process as the gating control line GCL, but embodiments of this disclosure are not limited thereto.

[0284] According to embodiments of this disclosure, each of the plurality of second carry signal lines CSL2 can be disposed on the plurality of first carry signal lines CSL1 or the dummy pattern 160. For example, each of the plurality of second carry signal lines CSL2 can be formed from the same material and in the same process as the pixel electrode, but embodiments of this disclosure are not limited thereto.

[0285] According to embodiments of this disclosure, multiple dummy lines 170 can be disposed adjacent to multiple gating control lines GCL to overlap with the dummy pattern 160. For example, each of the multiple dummy lines 170 can be disposed adjacent to one side or the other side of the corresponding gating control line GCL. For example, each of the multiple dummy lines 170 can be configured to be adjacent to each of a start signal line, multiple shift clock lines, multiple feed shift clock lines, one or more gating drive power lines, and one or more gating common power lines.

[0286] The gating control line GCL can be configured to intersect with the dummy line 170, with the dummy pattern 160 located therebetween. For example, the central portion between the setting area of ​​the first carry signal line CSL1 and the setting area of ​​the second carry signal line CSL2 can be arranged at the center (or in the middle) of two adjacent pixels P along the first direction X.

[0287] According to embodiments of this disclosure, the distance (or shortest distance) between the gating control line GCL and the dummy line 170 relative to the first direction X can be equal to the distance (or shortest distance) between the first carry signal line CSL1 and the second carry signal line CSL2. The gating control line GCL, the dummy line 170, and the carry signal line CSL can be positioned at the same location in the transmissive portion TP between two adjacent pixels P along the first direction X, or they can be positioned at the same location at a constant interval. Therefore, the positions of the transmissive regions of the transmissive portion TP based on the positioning positions of each of the gating control line GCL, the carry signal line CSL, and the dummy line 170 positioned in (or at) the transmissive portion TP can be equal or uniform.

[0288] According to embodiments of this disclosure, a transmissive portion (or first transmissive portion or first region) with a branch circuit BC between two adjacent pixels P along the first direction X, comprising a transmissive portion TP (or region) between two adjacent pixels P, may include two lines, for example, a gating control line GCL and a dummy line 170. A transmissive portion (or second transmissive portion or second region) with a carry signal line CSL but no branch circuit BC between two adjacent pixels P along the first direction X, comprising two lines, for example, two signal lines CSL1 and CSL2. For example, each of the first and second transmissive portions may include two signal lines disposed in different layers on the substrate 100, and the arrangement structure of the two signal lines disposed in (or at) different layers may be the same.

[0289] According to embodiments of this disclosure, each of the transmissive portion (or first transmissive portion or first region) TP provided with a branch circuit BC and the transmissive portion (or second transmissive portion or second region) TP provided with a carry signal line CSL may include the same number of lines or may include two lines, thereby additionally reducing, minimizing or preventing dulling phenomena such as streaks or stains due to deviations in the size (or transmittance or transparency) of the transmissive portion TP caused by the quantity deviation between the gating control line GCL and the carry signal line CSL.

[0290] Figure 18 It is along the exemplary embodiments of this disclosure. Figure 15 Another cross-sectional view taken from line III-III' shown. Figure 18 An example is shown by... Figure 15 and Figure 16 The illustrated implementation involves the dummy patterns and dummy lines being electrically connected to each other. Therefore, in the following description, repeated descriptions of other elements besides the connection structure between the dummy patterns and dummy lines and related components are omitted or can be briefly provided.

[0291] Reference Figure 15 and Figure 18 Multiple dummy lines 170 can be electrically connected to multiple dummy patterns 161 that overlap with branch circuit BC in multiple dummy patterns 160. Multiple dummy lines 170 can also be electrically connected to first dummy patterns 161 and second dummy patterns 162 in multiple dummy patterns 160. For example, a dummy line 170 overlapping with multiple first dummy patterns 161 can be electrically connected to each of the multiple first dummy patterns 161 arranged along the second direction Y through each of the multiple contact holes 170h. Similarly, a dummy line 170 overlapping with multiple second dummy patterns 162 can be electrically connected to each of the multiple second dummy patterns 162 arranged along the second direction Y through each of the multiple contact holes 170h.

[0292] Each of the plurality of dummy lines 170 can be configured to maintain a specific potential of each of the plurality of dummy patterns 160 in an electrically floating state. For example, each of the plurality of dummy lines 170 can provide a direct current (DC) voltage to each of the plurality of dummy patterns 160 that overlap with the branch circuit BC. For example, each of the plurality of dummy lines 170 can be configured to provide a pixel common voltage provided from the pad portion 110 to each of the plurality of dummy patterns 160.

[0293] Each of the plurality of dummy lines 170 according to embodiments of the present disclosure can be configured to be electrically connected to Figure 3 The pixel common voltage pad CVP is shown in the pad portion 110. For example, each of the plurality of dummy lines 170 can be configured to be electrically connected to one or more of the line connection pattern LCP, pixel common voltage line CVL, and auxiliary voltage line SVL that are electrically connected to the pixel common voltage pad CVP. For example, each of the plurality of dummy lines 170 can be configured to intersect with one or more of the plurality of line connection patterns LCP, and can be electrically connected to the line connection pattern LCP through a contact hole provided in (or at) the intersection with one or more line connection patterns LCP.

[0294] Additionally, an intermediate metal pattern can be additionally disposed between each of the plurality of dummy lines 170 and the line-connecting pattern LCP. The intermediate metal pattern can be configured to reduce the height difference (or step height) between the dummy line 170 and the line-connecting pattern LCP. Therefore, each of the plurality of dummy lines 170 can be stably connected to the line-connecting pattern LCP through the intermediate metal pattern. Thus, each of the plurality of dummy lines 170 can provide the pixel common voltage provided through the pixel common voltage pad CVP and the pixel common voltage line CVL to the corresponding dummy pattern in the plurality of dummy patterns 160.

[0295] According to embodiments of this disclosure, each of the plurality of dummy patterns 160 overlapping with the branch circuit BC can be electrically connected to the dummy line 170. Therefore, changes in the signal applied to the branch circuit BC or the gating control line GCL can be avoided, and the signal can be fixed or maintained at a certain potential or the pixel common voltage. Thus, each of the plurality of dummy patterns 160 can reduce, minimize, or prevent dimensional (or transmittance or transparency) deviations between the transmissive portions TP caused by dimensional (or area) deviations between the branch circuits BC, without causing malfunctions in the branch circuit BC or the TFT of the branch circuit BC. Therefore, the transmittance or light transmittance of the display device (or transparent display device) according to embodiments of this disclosure can be enhanced.

[0296] Figure 19 This is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure. Figure 19 This is an example Figure 2 The diagram shows a portion of the display area, and illustrates the situation in... Figures 1 to 14 The embodiment shown is a display device according to an embodiment of the present disclosure in which a plurality of second dummy patterns are additionally configured. Therefore, in the following description, repeated descriptions of other elements besides the plurality of second dummy patterns and related elements are omitted or may be briefly provided. Figure 9 or Figure 11 Examples are shown along Figure 19 The cross-sectional view taken by line I-I' is shown. Figure 10 or Figure 12 Examples are shown along Figure 19 The cross-sectional view taken from line II-II' is shown.

[0297] Reference Figure 19 The display device according to embodiments of the present disclosure may further include a plurality of second dummy patterns 180. For example, the second dummy pattern 180 may be a second metal pattern, a second auxiliary pattern, a second additional pattern, a second overlay pattern, a second pattern component, or a second island pattern. Therefore, the dummy pattern 160 may be a first metal pattern, a first auxiliary pattern, a first additional pattern, a first overlay pattern, a first pattern component, or a first island pattern.

[0298] Each of the plurality of second dummy patterns 180 can be disposed between the plurality of dummy patterns 160. Each of the plurality of second dummy patterns 180 can be disposed in the region (or location) between two pixels P between the plurality of dummy patterns 160. Each of the plurality of second dummy patterns 180 can be disposed in the transmissive portion TP between the plurality of pixels P between the plurality of dummy patterns 160. For example, each of the plurality of second dummy patterns 180 can be disposed in the region (or transmissive portion TP) of the region (or transmissive portion TP) between two pixels P that are adjacent to each other along the first direction X, where no dummy pattern 160 is disposed. For example, the display area AA may include: a circuit setting region (or a first region) which includes a branch circuit BC disposed between two adjacent pixels P; and a circuit non-setting region (or a second region) in which no branch circuit BC is disposed between two adjacent pixels P. Therefore, each of the plurality of second dummy patterns 180 can be disposed in the circuit non-setting region (or location) of the region between the plurality of pixels P.

[0299] According to embodiments of this disclosure, when the first pixel to the nth pixel P are disposed in a horizontal row (or at a location) and the dummy pattern 160 is disposed between the 2k-1 (where k is 1 to n-1)th pixel and the 2kth pixel, the second dummy pattern 180 may be disposed between the 2kth pixel and the 2k+1th pixel, but embodiments of this disclosure are not limited thereto. For example, the dummy pattern 160 and the second dummy pattern 180 may be disposed individually (or distributedly) between multiple pixels P in each horizontal row (or within a horizontal row) based on the number of TFTs configuring a level circuit unit and the number of pixels P disposed in a horizontal row (or at a location).

[0300] According to embodiments of the present disclosure, the dummy pattern 160 or the second dummy pattern 180 can be disposed between all pixels P disposed in (or at) the display area AA. For example, the dummy pattern 160 or the second dummy pattern 180 can be disposed in the region (or at) between two adjacent pixels P disposed in (or at) the display area AA along the first direction X. Therefore, the size (or transmittance or transparency) of the transmissive portions TP disposed or arranged between all pixels P disposed in (or at) the display area AA along the first direction X can be substantially equal to each other, thereby reducing, minimizing or preventing dullness phenomena such as streaks or stains due to size (or transmittance or transparency) deviations between the transmissive portions TP, thereby enhancing the transmittance or transparency of the display device (or transparent display device) according to embodiments of the present disclosure.

[0301] Each of the plurality of second dummy patterns 180 can be configured to have the same shape and the same size. Each of the plurality of second dummy patterns 180 can be configured to be located at the same position (or in the middle) between two adjacent pixels P along the first direction X. For example, the plurality of second dummy patterns 180 can be located or aligned on the same line (or at the same location) relative to the first direction X. For example, the central portion (or middle portion) of each of the plurality of second dummy patterns 180 can be located or aligned on a dummy horizontal line (or at the same location) parallel to the first direction X.

[0302] According to embodiments of this disclosure, each of the plurality of second dummy patterns 180 may have the same shape and the same size as each of the plurality of dummy patterns 160. Each of the plurality of second dummy patterns 180 and the plurality of dummy patterns 160 may be configured to be located at the same position (or in the middle) between two adjacent pixels P along the first direction X. For example, each of the plurality of second dummy patterns 180 and the plurality of dummy patterns 160 may be located or aligned on the same line (or at) relative to the first direction X. For example, the central portion (or middle portion) of each of the plurality of second dummy patterns 180 and the plurality of dummy patterns 160 may be located or aligned on a dummy horizontal line parallel to the first direction X (or at).

[0303] Each of the plurality of second dummy patterns 180 may be formed of the same material in the same process as each of the plurality of dummy patterns 160, but embodiments of this disclosure are not limited thereto.

[0304] A display device according to an embodiment of the present disclosure may include a plurality of dummy patterns 160 and 180 disposed between all pixels P disposed in (or at) a display area AA along a first direction X, and the plurality of dummy patterns 160 and 180 may be classified into a plurality of first dummy patterns 160 overlapping with a branch circuit BC and a plurality of second dummy patterns 180 not overlapping with the branch circuit BC and disposed in (or at) a transmissive portion TP. For example, each of the plurality of first dummy patterns 160 may be a circuit overlapping pattern or a circuit covering pattern, and each of the plurality of second dummy patterns 180 may be a circuit non-overlapping pattern.

[0305] In addition, multiple second dummy patterns 180 can be applied in the same way. Figures 15 to 18 The display device shown is an embodiment of the present disclosure. For example, in Figures 15 to 18 In this context, multiple second dummy patterns 180 can be applied to the transmission section TP (or location) provided between multiple dummy patterns 160, therefore, their repeated description is omitted.

[0306] As described above, since the display device according to the embodiments of the present disclosure also includes a plurality of second dummy patterns 180 disposed in (or at) the transmissive portion TP between a plurality of dummy patterns 160, the size (or transmittance or transparency) of the transmissive portion TP disposed or arranged between all pixels P disposed in (or at) the display area AA along the first direction X can be substantially equal to each other. Therefore, dimming phenomena such as streaks or stains due to size (or transmittance or transparency) deviations between the transmissive portions TP can be reduced, minimized, or prevented, thereby enhancing the transmittance or transparency of the display device (or transparent display device) according to the embodiments of the present disclosure.

[0307] Figure 20 This is a diagram illustrating a display device according to an exemplary embodiment of the present disclosure. Figure 21 It is along the exemplary embodiments of this disclosure. Figure 20 The cross-sectional view shown is taken from line V-V'. Figure 22 It is along the exemplary embodiments of this disclosure. Figure 20 Another cross-sectional view taken from line V-V'. Figures 20 to 22 Examples are shown in Figure 19 The illustrated embodiment of the display device according to the present disclosure includes an additional second dummy line. Therefore, in the following description, repeated descriptions of elements other than the second dummy line and related components are omitted or may be briefly provided. Figure 9 or Figure 11 Examples are shown along Figure 20 The cross-sectional view taken by line I-I' is shown. Figure 10 or Figure 12 Examples are shown along Figure 20 The cross-sectional view taken from line II-II' is shown.

[0308] Reference Figure 20 and Figure 21 The display device according to embodiments of the present disclosure may further include multiple second dummy lines 190. For example, the second dummy line 190 may be a second pattern connecting line, a second pattern connecting member, a second pattern bridging line, or a second pattern link line. Therefore, the dummy line 170 may be a first pattern connecting line, a first pattern connecting member, a first pattern bridging line, or a first pattern link line.

[0309] Each of the plurality of second dummy lines 190 may extend parallel to the second direction Y for a considerable length, and may be configured or disposed on the substrate 100 to overlap with a corresponding second dummy pattern in a plurality of second dummy patterns 180 disposed along the second direction Y in the display area AA. For example, each of the plurality of second dummy lines 190 may be disposed between the substrate 100 and each of the plurality of second dummy patterns 180, or may be disposed on each of the plurality of second dummy patterns 180.

[0310] According to embodiments of this disclosure, each of the plurality of second dummy lines 190 can be additionally configured to reduce, minimize, or compensate for the size (or transmittance or transparency) deviation of the transmissive portion TP between adjacent pixels P caused by carry signal lines CSL or gating control lines GCL that overlap with each of the plurality of dummy patterns 160. For example, the display area AA may include a line setting area and a line non-setting area, the line setting area including carry signal lines CSL or gating control lines GCL disposed between two adjacent pixels P, and the line non-setting area not having carry signal lines CSL or gating control lines GCL disposed between two adjacent pixels P. Therefore, a transmittance deviation may occur between the line setting area and the line non-setting area. Therefore, each of the plurality of second dummy lines 190 can be configured such that the transmittance of the line setting area is similar to or the same as the transmittance of the line non-setting area. For example, each of the plurality of second dummy lines 190 may be disposed in the non-setting area (or at a location) such that the transmittance of the non-setting area is reduced to the level of the transmittance of the wiring setting area.

[0311] According to embodiments of this disclosure, each of the plurality of second dummy lines 190 may have a line width equal to that of each of the gating control line GCL, the carry signal line CSL, and the dummy lines 170 overlapping with the dummy pattern 160. The number of second dummy lines 190 overlapping with the second dummy pattern 180 may be the same as the number of lines overlapping with the dummy pattern 160. Furthermore, the spacing and arrangement of the second dummy lines 190 overlapping with the second dummy pattern 180 may be the same as the spacing and arrangement of the lines overlapping with the dummy pattern 160. For example, when the number of lines overlapping with the dummy pattern 160 is three, the number of second dummy lines 190 overlapping with the second dummy pattern 180 may be three. For example, the number of lines overlapping with the dummy pattern 160 may be two, and the number of second dummy lines 190 overlapping with the second dummy pattern 180 may be two.

[0312] According to embodiments of the present disclosure, each of the plurality of second dummy lines 190 may be disposed on (or at) the upper surface 100a of the substrate 100 to overlap with a corresponding second dummy pattern among the plurality of second dummy patterns 180 along the second direction Y and may be parallel to the second direction Y. For example, each of the plurality of second dummy lines 190 may be configured to directly contact the upper surface 100a of the substrate 100. Each of the plurality of second dummy lines 190 may be disposed on (or at) the same layer as the gating control line GCL. For example, each of the plurality of second dummy lines 190 may be formed of the same material in the same process as the gating control line GCL, but embodiments of the present disclosure are not limited thereto. For example, each of the plurality of second dummy lines 190 may be disposed in a non-deposition area, and therefore may not be electrically connected to each of the plurality of second dummy patterns 180 and may be electrically disconnected (or insulated) from each of the plurality of second dummy patterns 180, but embodiments of the present disclosure are not limited thereto. For example, similar to dummy line 170, each of the plurality of second dummy lines 190 can be configured to be electrically connected to a corresponding second dummy pattern in a plurality of second dummy patterns 180.

[0313] like Figure 22 As shown, each of the plurality of second dummy lines 190 according to embodiments of the present disclosure may be disposed on (or at) the second outer coating 104 to overlap with the corresponding second dummy pattern of the plurality of second dummy patterns 180 along the second direction Y. For example, each of the plurality of second dummy lines 190 may be disposed on (or at) the same layer as the pixel electrode. For example, each of the plurality of second dummy lines 190 may be formed of the same material in the same process as the pixel electrode, but embodiments of the present disclosure are not limited thereto. For example, each of the plurality of second dummy lines 190 may be disposed in a non-deposition area, and therefore may not be electrically connected to each of the plurality of second dummy patterns 180 and may be electrically disconnected (or insulated) from each of the plurality of second dummy patterns 180, but embodiments of the present disclosure are not limited thereto. For example, similar to dummy line 170, each of the plurality of second dummy lines 190 may be configured to be electrically connected to the corresponding second dummy pattern of the plurality of second dummy patterns 180.

[0314] In addition, multiple second dummy patterns 190 can be applied in the same way. Figures 15 to 18 The display device shown is an embodiment of the present disclosure. For example, in Figures 15 to 18 In this context, multiple second dummy patterns 190 can be applied to overlap with multiple second dummy patterns 180 respectively positioned along the second direction Y, thus their repeated description is omitted. For example, in Figures 15 to 18In this case, the number of lines overlapping with the dummy pattern 160 can be two, therefore the number of second dummy lines 190 overlapping with the second dummy pattern 180 can be two.

[0315] As described above, since the display device according to the embodiments of the present disclosure also includes a plurality of second dummy patterns 180 disposed in (or at) the transmissive portion TP between a plurality of dummy patterns 160 and a plurality of second dummy lines 190 overlapping with the corresponding second dummy patterns in the plurality of second dummy patterns 180, the size (or transmittance or transparency) of the transmissive portion TP disposed or arranged between all pixels P disposed in (or at) the display area AA along the first direction X can be substantially equal to each other. Therefore, dimming phenomena such as streaks or stains due to size (or transmittance or transparency) deviations between the transmissive portions TP can be reduced, minimized, or prevented, thereby enhancing the transmittance or transparency of the display device (or transparent display device) according to the embodiments of the present disclosure.

[0316] Figure 23 This is a perspective view illustrating a display device according to another exemplary embodiment of the present disclosure. Figure 24 This illustrates another exemplary implementation according to the present disclosure. Figure 23 A diagram of the rear surface of the display device. Figure 23 An enlarged view of area "A" is shown in Figure 3 middle.

[0317] Reference Figure 23 and Figure 24 According to another embodiment of the present disclosure, the display device may include a first substrate 100, a second substrate 200, a connecting member 300, and a wiring portion 400.

[0318] The first substrate 100 may be referred to as a display substrate, pixel array substrate, upper substrate, front substrate, or base substrate. The first substrate 100 may include a display area AA, multiple gate lines GL, multiple data lines DL, multiple pixel drive power lines PL, multiple pixel common voltage lines CVL, multiple pixels P, a common electrode CE, multiple common electrode contact portions CECP, a pad portion 110, a gate drive circuit 150, and multiple dummy patterns 160, etc. The first substrate 100 can be coupled with... Figures 1 to 22 The display panel 10 of the shown display device is basically the same, so its repeated description is omitted. For example, Figures 1 to 22 The substrate 100 of the display device shown can be used Figure 23 and Figure 24 The first substrate 100 shown is used instead; therefore, similar reference numerals refer to similar elements, and descriptions that are repeated below are omitted or will be briefly given. The pad portion 110 provided on the first substrate 100 may be a first pad portion 110.

[0319] The second substrate 200 may be referred to as a wire substrate, wiring substrate, linking substrate, lower substrate, rear substrate, or linking glass. The second substrate 200 may be a glass substrate, a thin-film glass substrate, or a bendable or flexible plastic substrate. For example, the second substrate 200 may comprise the same material as the first substrate 100 or may be made of the same material as the first substrate 100. For example, the dimensions of the second substrate 200 may be equal to or substantially equal to the dimensions of the first substrate 100.

[0320] The second substrate 200 can be connected (or joined) to the second surface of the first substrate 100 using a connecting member 300. The second substrate 200 may include a front surface (or forward surface) facing the second surface of the first substrate 100, or a rear surface (or back surface) connected to the connecting member 300, and an outer surface OSb between the front and rear surfaces. The second substrate 200 can transmit signals to pixel drive signal lines and can increase the rigidity of the first substrate 100.

[0321] According to another embodiment of the present disclosure, the display device may further include a second pad portion 210 disposed on a second substrate 200.

[0322] The second pad portion 210 may be disposed on the rear surface of the second substrate 200 at a first edge portion (or first peripheral portion) that overlaps with the first pad portion 110 disposed on (or at) the first substrate 100. The first edge portion of the rear surface of the second substrate 200 may include a first outer surface (or a side surface) OS1b in its outer surface OS.

[0323] The second pad portion 210 may include a plurality of second pads arranged at certain intervals along the first direction X and overlapping the pads of the first pad portion 110 respectively.

[0324] According to another embodiment of the present disclosure, the display device may further include a third pad portion (or input pad portion) 230, a link line portion 250, and a gating control signal transmission line portion 270 disposed on (or at) the second substrate 200.

[0325] The third pad portion 230 may be disposed on (or at) the rear surface 200b of the second substrate 200. For example, the third pad portion 230 may be disposed at the center portion of the rear surface 200b of the second substrate 200 adjacent to the first edge portion (or the first edge portion). The third pad portion 230 according to embodiments of the present disclosure may include a plurality of third pads (or input pads) spaced apart from each other.

[0326] The link portion 250 may be disposed between the second pad portion 210 and the third pad portion 230. For example, the link portion 250 may include multiple link lines that individually (or in a one-to-one relationship) connect the second pad of the second pad portion 210 to the third pad of the third pad portion 230.

[0327] The gating control signal transmission line section 270 may be disposed between the third pad section 230 and the link line section 250. For example, the gating control signal transmission line section 270 may include a gating control signal transmission line that separately connects the gating control signal pad disposed in (or at) the third pad section 230 to the gating control signal link line disposed in (or at) the link line section 250.

[0328] The connecting member 300 can be inserted between the first substrate 100 and the second substrate 200. The first substrate 100 and the second substrate 200 can be joined to each other via the connecting member 300. For example, the second surface of the first substrate 100 can be connected to one surface of the connecting member 300, and the front surface of the second substrate 200 can be connected to the other surface of the connecting member 300. Therefore, the first substrate 100 and the second substrate 200 joined (connected) to each other via the connecting member 300 can be a display panel.

[0329] The wiring portion 400 may be configured to surround the outer surface OS of the first substrate 100 and the outer surface OS of the second substrate 200. The wiring portion 400 according to an embodiment of the present disclosure may include a plurality of wirings 410 disposed at each of the first outer surface (or a side surface) OS1a of the outer surface OS of the first substrate 100 and the first outer surface (or a side surface) OS1b of the outer surface OS of the second substrate 200.

[0330] Each of the plurality of wirings 410 can be formed to surround each of the first outer surface OS1a of the first substrate 100 and the first outer surface OS1b of the second substrate 200. As an embodiment, the plurality of wirings 410 can be individually (or in a one-to-one relationship) connected to the pads of the first pad portion 110 provided on (or at) the first substrate 100 and the pads of the second pad portion 210 provided on (or at) the second substrate 200.

[0331] The display device according to another embodiment of the present disclosure may further include a driving circuit unit 500.

[0332] The driving circuit unit 500 can drive (or cause to emit light) the pixel P disposed on (or at) the first substrate 100 based on digital image data and synchronization signals provided from the display driving system, thus displaying an image corresponding to the image data on (or at) the display area AA. The driving circuit unit 30 can be connected to the third pad portion 230 disposed on (or at) the rear surface 200b of the substrate 200, and can output data signals, gating control signals, and driving power to the third pad portion 230 for driving (or causing to emit light) the pixel P disposed on (or at) the first substrate 100. For example, the driving circuit unit 500 can have a size smaller than that of the second substrate 200, so it can be covered by the second substrate 200 and can not be exposed outside the outer surface of the first substrate 100 or the second substrate 200.

[0333] The drive circuit unit 500 according to embodiments of this disclosure may include a flexible circuit film 510, a drive integrated circuit (IC) 530, a printed circuit board (PCB) 550, a timing controller 570, and a power supply 590. The drive circuit unit 500 including such components can be used with… Figure 1 The driving circuit unit 30 shown is basically the same, therefore, its description will be omitted or will be briefly repeated below.

[0334] The flexible circuit film 510 can be connected to the third pad portion 230 disposed on (or at) the second surface 200b of the second substrate 200.

[0335] The driver IC 530 can be mounted on (or at) the flexible circuit film 510. The driver IC 530 can be connected to each of multiple data lines DL, multiple pixel drive power lines PL, multiple pixel common voltage lines CVL, and multiple reference voltage lines RL via the flexible circuit film 510, the third pad portion 230, the link line portion 250, the second pad portion 210, the wiring portion 400, and the first pad portion 110. The driver IC 530 can receive sub-pixel data and data control signals provided from the timing controller 570, convert the sub-pixel data into analog data signals based on the data control signals, and provide the analog data signals to the corresponding data lines DL. Furthermore, the driver IC 530 can generate reference voltages, pixel drive power supplies, and pixel common voltages, and can provide these voltages to the corresponding voltage lines RL, PL, and CVL, respectively.

[0336] The driver IC 530 can sense the characteristic value of the driving TFT disposed in the pixel P through multiple reference voltage lines RL disposed on (or at) the first substrate 100, generate raw sensing data corresponding to the sensed value, and provide the raw sensing data to the timing controller 570.

[0337] PCB 550 can be connected to another edge portion of flexible circuit film 510. PCB 550 can transmit signals and power between components of drive circuit unit 500.

[0338] The timing controller 570 can be mounted on (or at) PCB 550 and can receive digital image data and timing synchronization signals from the display driver system via a user connector located on PCB 550. The timing controller 570 can be used with... Figure 1 The timing controller 37 of the panel driving circuit unit 30 shown is basically the same, so its repeated description is omitted.

[0339] As described above, a display device according to another embodiment of this disclosure may have the same... Figures 1 to 22 The display device shown has the same effect, and can have a zero-bezel structure or an air-bezel structure in which the display area AA is surrounded by air (instead of an opaque non-display area).

[0340] Figure 25 This is a diagram illustrating a multi-screen display device according to an exemplary embodiment of the present disclosure. Figure 26 It is along the exemplary embodiments of this disclosure. Figure 25 The cross-sectional view taken by line VI-VI' is shown. Figure 25 and Figure 26 Examples of tiling Figure 23 and Figure 24 The multi-screen display device shown is implemented according to another exemplary embodiment of the present disclosure.

[0341] Reference Figure 25 and Figure 26 According to embodiments of the present disclosure, a multi-screen display device may include a plurality of display devices DA1 to DA4.

[0342] Multiple display devices DA1 to DA4 can each display a separate image or can display an image separately. Each of the multiple display devices DA1 to DA4 may include Figure 23 and Figure 24 The display device shown is according to another embodiment of this disclosure, and therefore its repeated description is omitted.

[0343] Multiple display devices DA1 to DA4 can be tiled on (or at) a separate tile frame so that they are in contact with each other on their side surfaces (or lateral surfaces). For example, multiple display devices DA1 to DA4 can be tiled in the form of N×M (where N is a positive integer of 2 or greater and M is a positive integer of 2 or greater), thereby realizing a multi-screen display device with a large screen.

[0344] Each of the plurality of display devices DA1 to DA4 may not include a border area (or non-display area) surrounding the entire display area AA of the displayed image, and may have an air border structure in which the display area AA is surrounded by air. For example, in each of the plurality of display devices DA1 to DA4, all the first surfaces of the first substrate 100 may be implemented as the display area AA.

[0345] According to embodiments of this disclosure, in each of the plurality of display devices DA1 to DA4, the second interval D2 between the central portion CP of the outermost pixel Po and the outermost outer surface VL of the first substrate 100 can be implemented as half or less of the first interval (or pixel pitch) D1 between adjacent pixels Pi and Po. Therefore, in two adjacent display devices connected (or in contact) to each other at their side surfaces along the first direction X and the second direction Y based on a lateral connection, the interval “D2+D2” between adjacent outermost pixels Po can be equal to or less than the first interval D1 between two adjacent pixels Pi and Po.

[0346] Reference Figure 26 In a first display device DA1 and a third display device DA3 that are connected (or in contact) to each other on their side surfaces along the second direction Y, the interval “D2+D2” between the center portion CP of the outermost pixel Po of the first display device DA1 and the center portion CP of the outermost pixel Po of the third display device DA3 can be equal to or less than the first interval D1 set between two adjacent pixels Pi and Po in each of the first display device DA1 and the third display device DA3.

[0347] Therefore, the interval "D2+D2" between the central portions CP of the outermost pixels Po of two adjacent display devices that are connected (or in contact) with each other on their side surfaces along the first direction X and the second direction Y can be equal to or smaller than the first interval D1 between two adjacent pixels Pi and Po located in each of the display devices DA1 to DA4. Thus, there can be no seam or boundary portion between the two adjacent display devices, thereby eliminating dark areas caused by the boundary portions located between the display devices DA1 to DA4. As a result, the images displayed on a multi-screen display device in which each of the multiple display devices DA1 to DA4 is tiled in a 2×2 configuration can be displayed continuously, without any sense of break (or discontinuity) at the boundary portions between the multiple display devices DA1 to DA4.

[0348] exist Figure 25 and Figure 26The example illustrates multiple display devices DA1 to DA4 tiled in a 2×2 configuration, but embodiments of this disclosure are not limited to this, and the multiple display devices DA1 to DA4 may be tiled in an x×1 configuration, a 1×y configuration, or an x×y configuration. Here, x can be a natural number of two or greater, or equal to y. y can be a natural number of two or greater, or greater than or less than x.

[0349] As described above, when the display area AA of each of the multiple display devices DA1 to DA4 is a screen and displays an image, the multi-screen display device according to the embodiments of the present disclosure can display an unbroken and continuous image at the boundary portion between the multiple screen display devices DA1 to DA4, thereby enhancing the viewer's immersive experience of viewing the image displayed by the multi-screen display device.

[0350] Alternatively, in a multi-screen display device according to this disclosure, each of the plurality of display devices DA1 to DA4 may include Figures 1 to 22 The display device shown is an embodiment of the present disclosure. In this case, in Figure 1 In the display device shown according to an embodiment of the present disclosure, the flexible circuit film 31 can be bent to surround the side surface of the substrate 100, and the PCB 35 can be disposed on the rear surface (or location) of the substrate 100. Figure 1 The substrate 100 of the display device shown can be coupled with Figure 23 The first substrate 100 shown is basically the same, therefore, Figure 1 The display devices shown can be tiled in an x×1, 1×y, or x×y configuration to achieve multi-screen display devices (or transparent multi-screen display devices). Therefore, Figure 1 The multi-screen display device shown can display a continuous image at the boundary between multiple display devices DA1 to DA4 without any sense of image breakage (or discontinuity).

[0351] The following describes a display device according to the present disclosure and a multi-screen display device including the same.

[0352] A display device according to some embodiments of the present disclosure may include: a substrate including a display area comprising a plurality of pixels disposed along a first direction and a second direction intersecting the first direction; a gating drive circuit disposed at the display area, the gating drive circuit including a plurality of branch circuits for providing scan signals to the plurality of pixels; and a plurality of lines disposed in a region between two pixels adjacent to each other along the first direction, extending in the second direction, and selectively connected to the plurality of branch circuits, the number of lines disposed in the region between two pixels adjacent to each other along the first direction may be the same.

[0353] According to some embodiments of this disclosure, all side surfaces of the display area can be configured to be in direct contact with the air.

[0354] According to some embodiments of the present disclosure, the display device may further include: a pad portion disposed in the display area and having a plurality of pads connected to a gating drive circuit and each of a plurality of pixels.

[0355] According to some embodiments of this disclosure, the pad portion may be disposed in the outermost pixel of a peripheral portion of a substrate parallel to a first direction.

[0356] According to some embodiments of this disclosure, the gating drive circuit may further include a branch network that electrically connects multiple branch circuits.

[0357] According to some embodiments of this disclosure, the branch network may include a transparent conductive material capable of transmitting light.

[0358] According to some embodiments of this disclosure, the branch network may include multiple network lines extending parallel to a first direction and multiple control nodes, and each of the multiple control nodes may be electrically connected to the gate electrode of a thin-film transistor included in one or more of the multiple branch circuits.

[0359] According to some embodiments of this disclosure, some of the control nodes among a plurality of control nodes and some of the network lines among a plurality of network lines can be configured to share a plurality of branch circuits arranged adjacent to each other along a second direction.

[0360] According to some embodiments of this disclosure, the display area may include multiple pixel groups, each pixel group including two or more adjacent pixels, and each of the multiple branch circuits may be disposed between the multiple pixel groups.

[0361] According to some embodiments of this disclosure, the multiple lines may include gating control lines, carry signal lines, and dummy lines, and the multiple lines disposed in the region between two adjacent pixels along the first direction may include gating control lines and dummy lines, or may include carry signal lines and dummy lines.

[0362] According to some embodiments of this disclosure, the carry signal line may have a length corresponding to the size of four adjacent pixels along the second direction.

[0363] According to some embodiments of this disclosure, each of the different first and second regions in a plurality of regions between two adjacent pixels along a first direction may include one or more dummy lines, and the number of dummy lines disposed in the first region may be different from the number of dummy lines disposed in the second region.

[0364] According to some embodiments of this disclosure, a first region among a plurality of regions between two adjacent pixels along a first direction may include a branch circuit, a gating control line, and two dummy lines, and a second region among a plurality of regions between two adjacent pixels along the first direction may include two carry signal lines and a dummy line.

[0365] According to some embodiments of this disclosure, a gating control line can be set at the boundary region between two adjacent pixels along a first direction, and each of the two dummy lines can be spaced apart from the gating control line by a first distance, and a dummy line can be set at the boundary region between two adjacent pixels along the first direction, and each of the two carry signal lines can be spaced apart from the dummy line by a first distance.

[0366] According to some embodiments of this disclosure, the display device may also include a plurality of dummy patterns that respectively cover a plurality of branch circuits.

[0367] According to some embodiments of this disclosure, multiple dummy patterns may have the same shape and the same size as each other and may be arranged in an array within a display area.

[0368] According to some embodiments of this disclosure, a first dummy line and a second dummy line among a plurality of dummy lines can be disposed on a plurality of dummy patterns disposed along a second direction, and one or more of the first dummy line and the second dummy line can be configured to transmit a direct current (DC) voltage to each of the plurality of dummy patterns disposed along the second direction.

[0369] According to some embodiments of this disclosure, each of the plurality of dummy patterns may include a material capable of collecting hydrogen.

[0370] According to some embodiments of this disclosure, the multiple lines may include a gating control line, a carry signal line, and a dummy line. A first region in a plurality of regions between two adjacent pixels along a first direction may include a branch circuit, a gating control line, and a dummy line. A second region in a plurality of regions between two adjacent pixels along a first direction, which is different from the first region, may include two carry signal lines.

[0371] According to some embodiments of this disclosure, the two carry signal lines can be located on different layers.

[0372] According to some embodiments of this disclosure, the two carry signal lines can be set on different layers, and a gating control line and a dummy line can be set on different layers.

[0373] According to some embodiments of this disclosure, the display device may further include a plurality of dummy patterns that respectively cover a plurality of branch circuits, and the plurality of dummy lines may respectively overlap with the plurality of dummy patterns arranged along a second direction.

[0374] According to some embodiments of this disclosure, each of the plurality of dummy lines can be configured to provide a direct current (DC) voltage to each of the plurality of dummy patterns arranged along a second direction.

[0375] According to some embodiments of this disclosure, the display device may further include a plurality of second dummy patterns disposed between a plurality of dummy patterns along a first direction.

[0376] According to some embodiments of this disclosure, each of the plurality of second dummy patterns can be configured not to overlap with the plurality of branch circuits.

[0377] According to some embodiments of this disclosure, each of the plurality of second dummy patterns can be disposed between two pixels between the plurality of dummy patterns.

[0378] According to some embodiments of this disclosure, the display device may further include a plurality of second dummy lines that overlap with a plurality of second dummy patterns along a second direction.

[0379] According to some embodiments of this disclosure, the number of second dummy lines overlapping each of the plurality of second dummy patterns can be the same as the number of lines overlapping each of the plurality of dummy patterns.

[0380] According to some embodiments of the present disclosure, the display device may further include: a rear substrate connected to the rear surface of a substrate by means of a connecting member; and a wiring portion disposed on the outer surface of the substrate and the outer surface of the rear substrate, the wiring portion including multiple wirings connected to a plurality of pixels.

[0381] According to some embodiments of this disclosure, each of the plurality of pixels may include: a light-emitting portion, which includes a light-emitting device; and a transmissive portion, which is located around the light-emitting portion, and each of the plurality of branch circuits may be disposed at the transmissive portion.

[0382] A multi-screen display device according to some embodiments of the present disclosure may include a plurality of display devices arranged along at least one of a first direction and a second direction intersecting the first direction. Each of the plurality of display devices may include: a substrate including a display area including a plurality of pixels disposed along the first direction and the second direction intersecting the first direction; a gating drive circuit disposed at the display area, the gating drive circuit including a plurality of branch circuits for providing scan signals to the plurality of pixels; and a plurality of lines disposed in a region between two pixels adjacent to each other along the first direction, extending in the second direction, and selectively connected to the plurality of branch circuits, the number of lines disposed in the region between two pixels adjacent to each other along the first direction may be the same.

[0383] According to some embodiments of the present disclosure, each of a plurality of pixels disposed at a display area of ​​each of a plurality of display devices may include: a light-emitting portion comprising a light-emitting device; and a transmissive portion located around the light-emitting portion, and each of a plurality of branch circuits may be disposed at the transmissive portion.

[0384] According to some embodiments of this disclosure, in a first display device and a second display device that are adjacent to each other along a first direction and a second direction, the distance between the center portion of the outermost pixel of the first display device and the center portion of the outermost pixel of the second display device may be less than or equal to the pixel pitch, and the pixel pitch may be the distance between the center portions of two adjacent pixels disposed at each of the plurality of display devices.

[0385] The display device (or transparent display device) according to embodiments of this disclosure can be applied to all electronic devices including display panels. For example, the display device (or transparent display device) according to embodiments of this disclosure can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop personal computers (PCs), laptop PCs, netbooks, workstations, navigation devices, car navigation devices, car display devices, automotive equipment, cinema equipment, cinema display devices, TVs, wallpaper display devices, signage devices, game consoles, laptop computers, monitors, cameras, camcorders, home appliances, etc.

[0386] The features, structures, and effects described above in this disclosure are included in at least one embodiment, but are not limited to only one embodiment. Furthermore, those skilled in the art can achieve the features, structures, and effects described in at least one embodiment of this disclosure through combinations or modifications of other embodiments. Therefore, anything relating to combinations and modifications should be understood within the scope of this disclosure.

[0387] It will be apparent to those skilled in the art that various modifications and variations can be made to the display device and multi-screen display device including the present disclosure without departing from the technical spirit or scope of the present disclosure. Therefore, the present disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

[0388] Cross-reference to related applications

[0389] This application claims the benefit and priority of Korean Patent Application No. 10-2022-0090960, filed in Korea on July 22, 2022, the entire contents of which are incorporated herein by reference for all purposes, as if fully set forth herein.

Claims

1. A display device, the display device comprising: A substrate, the substrate including a display area, the display area including a plurality of pixels disposed along a first direction and a second direction intersecting the first direction; A gating driving circuit is disposed in the display area, and the gating driving circuit includes multiple branch circuits for providing scanning signals to the plurality of pixels; as well as Multiple lines are disposed in regions between two adjacent pixels along the first direction, extend in the second direction, and selectively connect to the multiple branch circuits. The number of lines set in the region between two adjacent pixels along the first direction is the same. The multiple lines include a gating control line, a carry signal line, and a dummy line. Each of the gating control line, the carry signal line, and the dummy line extends relatively long in the second direction, and The plurality of lines located in the region between two adjacent pixels along the first direction include the gating control line and the dummy line, or include the carry signal line and the dummy line.

2. The display device according to claim 1, wherein, All side surfaces of the display area are configured to be in direct contact with air.

3. The display device according to claim 1, further comprising: A pad portion is disposed in the display area and has a plurality of pads connected to the gating drive circuit and each of the plurality of pixels.

4. The display device according to claim 3, wherein, The pad portion is disposed in the outermost pixel of the peripheral portion of the substrate, which is parallel to the first direction.

5. The display device according to claim 1, wherein, The gating drive circuit also includes a branch network that is electrically connected to the plurality of branch circuits.

6. The display device according to claim 5, wherein, The branch network includes a transparent conductive material capable of transmitting light.

7. The display device according to claim 5, wherein, The branch network includes multiple network lines extending parallel to the first direction and multiple control nodes, and Each of the plurality of control nodes is electrically connected to the gate electrode of a thin-film transistor included in one or more of the plurality of branch circuits.

8. The display device according to claim 7, wherein, Some of the multiple control nodes and some of the multiple network lines are configured to share the multiple branch circuits arranged adjacent to each other along the second direction.

9. The display device according to claim 1, wherein, The display area comprises multiple pixel groups, each pixel group comprising two or more adjacent pixels, and Each of the plurality of branch circuits is positioned between the plurality of pixel groups.

10. The display device according to claim 1, wherein, The carry signal line has a length corresponding to the size of four adjacent pixels along the second direction.

11. The display device according to claim 1, wherein, Each of the different first and second regions in a plurality of regions between two adjacent pixels along the first direction includes one or more dummy lines, and The number of dummy lines set in the first region is different from the number of dummy lines set in the second region.

12. The display device according to claim 1, wherein, The first region among multiple regions between two adjacent pixels along the first direction includes the branch circuit, a gating control line, and two dummy lines, and The second region among the plurality of regions between two adjacent pixels along the first direction includes two carry signal lines and one dummy line.

13. The display device according to claim 12, wherein, The gating control line is positioned at the boundary region between two adjacent pixels along the first direction, and each of the two dummy lines is spaced apart from the gating control line by a first distance. The dummy line is positioned at the boundary region between two adjacent pixels along the first direction, and each of the two carry signal lines is spaced apart from the dummy line by the first distance.

14. The display device according to claim 1, further comprising a plurality of dummy patterns respectively covering the plurality of branch circuits.

15. The display device according to claim 14, wherein, The plurality of dummy patterns have the same shape and size and are arranged in an array within the display area.

16. The display device according to claim 14, wherein, The first and second dummy lines of the plurality of dummy lines are set on the plurality of dummy patterns arranged along the second direction, and One or more of the first dummy line and the second dummy line are configured to deliver a DC voltage to each of the plurality of dummy patterns arranged along the second direction.

17. The display device according to claim 14, wherein, Each of the plurality of dummy patterns includes a material capable of collecting hydrogen.

18. The display device according to claim 1, wherein, The first region among multiple regions between two adjacent pixels along the first direction includes the branch circuit, a gating control line, and a dummy line, and The second region, which differs from the first region, in the plurality of regions between two adjacent pixels along the first direction includes two carry signal lines.

19. The display device according to claim 18, wherein, The two carry signal lines are located on different layers.

20. The display device according to claim 18, wherein, The two carry signal lines are located on different layers, and The gating control line and the dummy line are set at different layers.

21. The display device according to claim 1, further comprising a plurality of dummy patterns respectively covering the plurality of branch circuits, in, Multiple dummy lines overlap with the multiple dummy patterns set along the second direction.

22. The display device according to claim 21, wherein, Each of the plurality of dummy lines is configured to provide a DC voltage to each of the plurality of dummy patterns arranged along the second direction.

23. The display device according to claim 14, further comprising a plurality of second dummy patterns disposed between the plurality of dummy patterns along the first direction.

24. The display device according to claim 23, wherein, Each of the plurality of second dummy patterns is configured not to overlap with the plurality of branch circuits.

25. The display device according to claim 23, wherein, Each of the plurality of second dummy patterns is positioned between two pixels between the plurality of dummy patterns.

26. The display device according to claim 23, further comprising a plurality of second dummy lines overlapping the plurality of second dummy patterns along the second direction.

27. The display device according to claim 26, wherein, The number of second dummy lines overlapping each of the plurality of second dummy patterns is the same as the number of lines overlapping each of the plurality of dummy patterns.

28. The display device according to claim 1, further comprising: A rear substrate, which is connected to the rear surface of the substrate by means of a connecting member; as well as The wiring portion is disposed on the outer surface of the substrate and the outer surface of the rear substrate, and the wiring portion includes multiple wirings connected to the plurality of pixels.

29. The display device according to any one of claims 1 to 28, wherein, Each of the plurality of pixels includes: The light-emitting part includes a light-emitting device; and The transmission portion is located at the periphery of the light-emitting portion, and Each of the plurality of branch circuits is disposed at the transmissive portion.

30. A multi-screen display device, the multi-screen display device comprising: A plurality of display devices arranged along at least one of a first direction and a second direction intersecting the first direction. Each of the plurality of display devices is a display device according to any one of claims 1 to 28.

31. The multi-screen display device according to claim 30, wherein, Each of the plurality of pixels disposed at the display area of ​​each of the plurality of display devices includes: The light-emitting part includes a light-emitting device; and The transmission portion is located at the periphery of the light-emitting portion, and Each of the plurality of branch circuits is disposed at the transmissive portion.

32. The multi-screen display device according to claim 30, wherein, In a first display device and a second display device that are adjacent to each other along the first direction and the second direction, the distance between the center portion of the outermost pixel of the first display device and the center portion of the outermost pixel of the second display device is less than or equal to the pixel pitch, and The pixel pitch is the distance between the center portions of two adjacent pixels located at each of the plurality of display devices.

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