Array substrate and liquid crystal display panel

Abstract

The application provides an array substrate and a liquid crystal display panel, the array substrate comprising: a substrate; a first conductive layer arranged on one side of the substrate, the first conductive layer comprising a common electrode; a second conductive layer arranged on the side of the first conductive layer away from the substrate, the second conductive layer comprising a transparent shielding electrode; and a third conductive layer arranged on the side of the second conductive layer away from the substrate, the third conductive layer comprising a connecting electrode; wherein the connecting electrode is connected to the common electrode through a first via, the connecting electrode is connected to the transparent shielding electrode through a second via, so that the common electrode and the transparent shielding electrode are electrically connected; and the first via and the second via are arranged at intervals.

Description

Technical Field

[0001] This application relates to the display field, and more particularly to an array substrate and a liquid crystal display panel. Background Technology

[0002] In current Liquid Crystal Display (LCD) panels, a metal electrode on the same layer as the gate electrode is commonly used as the array substrate-side common electrode (Acom), and a transparent electrode on the same layer as the pixel electrode is used as the data line shielding electrode (Data BM Less, DBS) to reduce the impact of parasitic capacitance on the display. However, due to the opacity of the metal electrode and the gap between the pixel electrode and the transparent electrode, the light-emitting area of ​​the LCD panel is reduced, thus decreasing the transmittance of the display panel.

[0003] Based on this, researchers proposed an auxiliary transparent storage capacity and shielding (TSS) design: by adding a transparent conductive layer to the array substrate, the transparent shielding electrode within the transparent conductive layer replaces the original shielding electrode and part of the common electrode. Because the transparent shielding electrode and the pixel electrode are not located on the same layer, this TSS design can effectively improve the transmittance of the display panel while reducing the impact of parasitic capacitance.

[0004] However, please refer to Figure 1 In existing TSS designs, the common electrode 121 and the transparent shielding electrode 161 are electrically connected via a connecting electrode 181. The connecting electrode 181 is disposed on the same layer as the pixel electrode. The connecting electrode 181 is connected to the common electrode 121 through a deep hole 101 and to the transparent shielding electrode 161 through a shallow hole 102. The deep hole 101 and the shallow hole 102 are interconnected. However, during the fabrication of the deep hole 101 and the shallow hole 102, the presence of undercutting introduces a risk of cracks in the gate insulating layer at the junction of the deep hole 101 and the shallow hole 102, thus affecting the stability of the display panel. Summary of the Invention

[0005] This invention provides an array substrate and a liquid crystal display panel to prevent the risk of cracks in the gate insulating layer of the array substrate and improve the stability of the liquid crystal display panel.

[0006] To solve the above problems, the technical solution provided by the present invention is as follows:

[0007] This invention provides an array substrate, the array substrate comprising:

[0008] Substrate;

[0009] A first conductive layer is disposed on one side of the substrate, and the first conductive layer includes a common electrode;

[0010] A second conductive layer is disposed on the side of the first conductive layer away from the substrate, and the second conductive layer includes a transparent shielding electrode.

[0011] A third conductive layer is disposed on the side of the second conductive layer away from the substrate, and the third conductive layer includes a connecting electrode.

[0012] The connecting electrode is connected to the common electrode through a first via, and the connecting electrode is connected to the transparent shielding electrode through a second via, thereby achieving electrical connection between the common electrode and the transparent shielding electrode; the first via and the second via are spaced apart.

[0013] Optionally, in some embodiments of the present invention, the first via and the second via are respectively set to two blue sub-pixels.

[0014] Optionally, in some embodiments of the present invention, the array substrate further includes a first insulating layer, a second insulating layer, a color resist layer, and a leveling layer, wherein the first insulating layer, the second insulating layer, and the color resist layer are disposed between the first conductive layer and the second conductive layer, and the leveling layer is disposed between the second conductive layer and the third conductive layer;

[0015] The first via penetrates the first insulating layer, the second insulating layer, the color resist layer, and the leveling layer, and exposes the common electrode; the second via penetrates the leveling layer and exposes the transparent shielding electrode.

[0016] Optionally, in some embodiments of the present invention, the common electrode includes a common connection portion and a common connection line, the common connection portion being connected to the common connection line; the transparent shielding electrode includes a shielding electrode strip and a transparent connection portion, the transparent connection portion connecting two adjacent shielding electrode strips; the connecting electrode includes a first connection portion, a second connection portion, and a connecting line, the connecting line connecting the first connection portion and the second connection portion;

[0017] The first via exposes the common connection portion, and the first connection portion is connected to the common connection portion through the first via; the second via exposes the transparent connection portion, and the second connection portion is connected to the transparent connection portion through the second via.

[0018] Optionally, in some embodiments of the present invention, the array substrate includes a thin-film transistor, the first conductive layer further includes a gate line and a gate of the thin-film transistor, the gate line and the gate are connected and disposed together, and the common electrode is spaced apart from the gate and the gate line; the array substrate further includes a fourth conductive layer, the fourth conductive layer includes a data line; the third conductive layer further includes a pixel electrode, the pixel electrode is spaced apart from the connection electrode;

[0019] The shielding electrode strip extends along the extension direction of the gate line and is arranged along the extension direction of the data line; the projection of the shielding electrode strip on the substrate covers the projection of the pixel electrode on the substrate, at least a portion of the projection of the gate line on the substrate, and a portion of the projection of the data line on the substrate.

[0020] Optionally, in some embodiments of the present invention, the connection electrode extends along the extension direction of the gate line.

[0021] Optionally, in some embodiments of the present invention, the projection of the connecting line on the substrate and the projection of the shielding electrode strip on the substrate completely cover the projection of the data line on the substrate.

[0022] Optionally, in some embodiments of the present invention, the common connection line includes a first common connection line and a second common connection line, wherein the first common connection line is parallel to the gate line and the second common connection line is perpendicularly connected to the first common connection line;

[0023] The projection of the second common connection line onto the substrate overlaps with the projection of the main stem of the pixel electrode onto the substrate.

[0024] Optionally, in some embodiments of the present invention, the reduction in the pixel area of ​​the blue sub-pixel is 5%-15%.

[0025] Meanwhile, this invention also provides a liquid crystal display panel, which includes a color filter substrate, an array substrate as described in any embodiment of this invention, and a liquid crystal layer disposed between the color filter substrate and the array substrate.

[0026] This invention provides an array substrate and a liquid crystal display panel. By setting the first via and the second via on the array substrate at intervals, the risk of gate insulating layer cracks is mitigated and the stability of the array substrate is improved. Attached Figure Description

[0027] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0028] Figure 1 A cross-sectional structural diagram of an array substrate provided for the prior art;

[0029] Figure 2 This is a schematic diagram of the planar structure of the first conductive layer of the array substrate provided in an embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of the planar structure of the second conductive layer of the array substrate provided in an embodiment of the present invention;

[0031] Figure 4 A schematic diagram of the planar structure of the third conductive layer of the array substrate provided in an embodiment of the present invention;

[0032] Figure 5 A schematic diagram of the planar structure of the fourth conductive layer of the array substrate provided in an embodiment of the present invention;

[0033] Figure 6 A schematic diagram of the planar superposition structure of the first to fourth conductive layers of the array substrate provided in an embodiment of the present invention;

[0034] Figure 7 The array substrate provided in the embodiments of the present invention is along Figure 6 A schematic diagram of the cross-sectional structure along the aa' direction;

[0035] Figure 8 The array substrate provided in the embodiments of the present invention is along Figure 6 A schematic diagram of the cross-sectional structure along the bb' direction;

[0036] Figure 9 This is a cross-sectional structural diagram of a liquid crystal display panel provided in an embodiment of the present invention. Attached image description:

[0038] The array substrate 10, substrate 11, first conductive layer 12, common electrode 121, gate line 122, gate 123, common connection portion 124, first common connection line 125, second common connection line 126, first insulating layer 13, second insulating layer 14, color resist layer 15, second conductive layer 16, transparent shielding electrode 161, shielding electrode strip 162, transparent connection portion 163, leveling layer 17, third conductive layer 18, connection electrode 181, first connection portion 182, second connection portion 183, connection line 184, fourth conductive layer 19, data line 191, source electrode 192, drain electrode 193, pixel electrode connection portion 194, first via 101, second via 102, thin film transistor 111, pixel area PA, element area EA, red pixel area R, green pixel area G, and blue pixel area B. Detailed Implementation

[0039] The technical solutions in the embodiments and / or examples of the present invention will be clearly and completely described below with reference to specific implementation schemes. Obviously, the embodiments and / or examples described below are only a part of the embodiments and / or examples of the present invention, and not all of them. Based on the embodiments and / or examples of the present invention, all other embodiments and / or examples obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0040] The directional terms used in this invention, such as [up], [down], [left], [right], [front], [back], [inside], [outside], [side], etc., are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrating and understanding this invention, and not for limiting it. The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature.

[0041] In existing TSS designs, the interconnecting lines connect the common electrode and the transparent shielding electrode through deep and shallow vias, respectively. The interconnection of the deep and shallow vias leads to the risk of cracks in the gate insulating layer. This application provides an array substrate and liquid crystal display panel to alleviate this problem.

[0042] In one embodiment, please refer to Figures 2 to 8 The array substrate 10 provided in this embodiment of the invention includes:

[0043] Substrate 11;

[0044] A first conductive layer 12 is disposed on one side of the substrate 11, and the first conductive layer 12 includes a common electrode 121;

[0045] The second conductive layer 16 is disposed on the side of the first conductive layer 12 away from the substrate 11, and the second conductive layer 16 includes a transparent shielding electrode 161.

[0046] A third conductive layer 18 is disposed on the side of the second conductive layer away from the substrate 11, and the third conductive layer 18 includes a connecting electrode 181.

[0047] The connecting electrode 181 is connected to the common electrode 121 through the first via 101, and the connecting electrode 181 is connected to the transparent shielding electrode 161 through the second via 102, thereby realizing the electrical connection between the common electrode 121 and the transparent shielding electrode 161; the first via 101 and the second via 102 are spaced apart.

[0048] By setting the first via and the second via at an interval, the present invention mitigates the risk of gate insulating layer cracks and improves the stability of the array substrate.

[0049] The array substrate includes pixel regions PA and component regions EA arranged in an array. The component regions EA are located between two adjacent rows of pixel regions PA and are used to house components such as thin-film transistors 111 and some signal traces. The pixel regions PA include, for example, Figure 6 The diagram shows a horizontally arranged blue pixel area B, a red pixel area R, and a green pixel area G. Each pixel area PA corresponds to one element area EA.

[0050] In one embodiment, the substrate 11 may be an inorganic substrate, such as glass; the substrate 11 may also be an organic substrate, such as PET.

[0051] In one embodiment, please refer to Figure 2 and Figure 6 The first conductive layer 12 further includes a gate line 122 and a gate 123 of a thin-film transistor. The gate line 122 and the gate 123 are connected. The common electrode 121 is spaced apart from the gate line 122 and the gate 123, thereby insulating the common electrode 121 from the gate line 122. The common electrode 121 includes a common connection portion 124 and a common connection line, and the common connection portion 124 is connected to the common connection line. The common connection lines include a first common connection line 125 and a second common connection line 126. The first common connection line 125 is parallel to the gate line 122, and the projection of the first common connection line 125 on the substrate 11 is located outside the projection of the pixel electrode (not shown) on the substrate 11, or overlaps with the edge of the projection of the pixel electrode (not shown) on the substrate 11, so as to avoid the first common connection line 125 affecting the transmittance of the pixel region PA. The second common connection line 126 is perpendicularly connected to the first common connection line 125 and passes through the pixel region PA. The projection of the second common connection line 126 on the substrate 11 coincides with the projection of the main stem of the pixel electrode on the substrate 11. The second common connection line 126 reduces the shadow problem at the position of the main stem of the pixel electrode.

[0052] In one embodiment, please refer to Figure 3 and Figure 6 The array substrate 10 further includes a fourth conductive layer 19, which includes a data line 191, a source 192 and a drain 193 of the thin-film transistor, and a pixel electrode connection portion 194. The pixel electrode connection portion 194 is connected to the drain 193 and electrically connected to the corresponding pixel electrode.

[0053] In one embodiment, please refer to Figure 4 and Figure 6 The transparent shielding electrode 161 includes a shielding electrode strip 162 and a transparent connecting portion 163. The shielding electrode strip 162 extends along the extension direction of the gate line 122 and is arranged along the extension direction of the data line 191. The transparent connecting portion 163 connects adjacent shielding electrode strips 162. The projection of the shielding electrode strip 162 on the substrate 11 covers part or all of the projection of the gate line 122 on the substrate 11, thereby reducing the influence of the parasitic capacitance on the gate line 122 on the pixel electrode. The projection of the shielding electrode strip 162 on the substrate 11 covers part of the projection of the data line 191 on the substrate 11 and also covers the projection of the pixel electrode on the substrate 11, thereby reducing the influence of the parasitic capacitance on the data line 191 on the pixel electrode.

[0054] In one embodiment, please refer to Figure 5 and Figure 6 The third conductive layer 18 further includes a pixel electrode (for clarity, the pixel electrode is not shown in the accompanying drawings; however, the pixel electrode design can be referenced from pixel electrode designs well-known to those skilled in the art, and is not limited here). The pixel electrode is disposed within the pixel region PA, and the connection electrode 181 is disposed within the element region EA and extends along the extension direction of the gate line 122, even penetrating a row of the element region EA. The pixel electrode and the connection electrode 181 are spaced apart and insulated from each other. The connection electrode 181 includes a first connection portion 182, a second connection portion 183, and a connection line 184 connecting the first connection portion 182 and the second connection portion 183. The projection of the first connection portion 182 on the substrate 11 partially or completely overlaps with the projection of the common connection portion 124 on the substrate 11, and the projection of the second connection portion 183 on the substrate 11 partially or completely overlaps with the projection of the transparent connection portion 163 on the substrate 11. The projection of the connecting line 184 on the substrate 11 and the projection of the shielding electrode strip 162 on the substrate completely cover the projection of the data line 191 on the substrate 11; in this way, the influence of the parasitic capacitance on the data line 191 on the pixel electrode can be further reduced.

[0055] For further details, please refer to... Figure 7 and Figure 8The array substrate 10 further includes a first insulating layer 13, a second insulating layer 14, a color resist layer 15, and a leveling layer 17. The first insulating layer 13 is disposed between the first conductive layer 12 and the fourth conductive layer 19. The second insulating layer 14 and the color resist layer 15 are disposed between the fourth conductive layer 19 and the second conductive layer 16. The leveling layer 17 is disposed between the second conductive layer 16 and the third conductive layer 18. The color resist layer includes a red color resist, a green color resist, and a blue color resist arranged sequentially along the extension direction of the gate line 122. The red color resist corresponds to the red pixel area R, the green color resist corresponds to the green pixel area G, and the blue color resist corresponds to the blue pixel area B.

[0056] The first via 101 penetrates the first insulating layer 13, the second insulating layer 14, the color resist layer 15, and the leveling layer 17, exposing the common connection portion 124. The first connection portion 182 is connected to the common connection portion 124 through the first via 101. The second via 102 penetrates the leveling layer 17, exposing the transparent connection portion 163, and the second connection portion 183 is connected to the transparent connection portion 163 through the second via 102. This achieves an electrical connection between the common electrode 121, the connection electrode 181, and the transparent shielding electrode 161, with the common electrode 121 receiving a common electrical signal.

[0057] The first via 101 and the second via 102 are respectively located within two component areas EA, and the two component areas EA can correspond to two adjacent blue pixel areas B in the same row (separated by a red pixel area R and a green pixel area G), such as... Figure 6 As shown, this can also correspond to two non-adjacent blue pixel areas B in the same row; thus, all common electrodes 121 and transparent shielding electrodes 161 are electrically connected through the connecting electrode 181. In this way, due to the arrangement of the first via 101 and the second via 102, the size of the corresponding element area EA is increased, resulting in a reduction in the area of ​​the corresponding blue pixel area B by 5%-15%, for example 5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15%, preferably 13%. Since blue pixels are typically truncated during subsequent white point correction, resulting in a loss of approximately 10%, the array substrate provided in this embodiment of the invention is equivalent to truncating the blue pixels in the design of the first and second vias. The pre-truncation amount of the blue pixels is similar to the truncation amount during white point correction, and will not affect the light emission effect of the blue pixels.

[0058] Based on the same inventive concept, please refer to Figure 9This invention also provides a liquid crystal display panel, comprising: a color filter substrate 20, a liquid crystal layer 30, and an array substrate 10 as described in any embodiment of this invention. The color filter substrate 20 and the array substrate 10 are disposed opposite to each other, and the liquid crystal layer 30 is sandwiched between the array substrate 10 and the color filter substrate 20. The color filter substrate 20 includes a substrate 21, a black matrix layer 22, and a common electrode layer 23.

[0059] In summary, the embodiments of the present invention provide an array substrate and a liquid crystal display panel. By setting the first via and the second via on the array substrate at intervals, the risk of gate insulating layer cracks is mitigated and the stability of the array substrate is improved.

[0060] The array substrate and liquid crystal display panel provided in the embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An array substrate, characterized in that, include: Substrate; A first conductive layer is disposed on one side of the substrate, and the first conductive layer includes a common electrode; A second conductive layer is disposed on the side of the first conductive layer away from the substrate, and the second conductive layer includes a transparent shielding electrode. A third conductive layer is disposed on the side of the second conductive layer away from the substrate, and the third conductive layer includes a connecting electrode. The connecting electrode is connected to the common electrode through a first via, and the connecting electrode is connected to the transparent shielding electrode through a second via, thereby achieving an electrical connection between the common electrode and the transparent shielding electrode. The first via and the second via are spaced apart; The array substrate includes multiple pixel areas and multiple element areas arranged in an array. Each element area is located between two adjacent rows of pixel areas. The first via and the second via are located in two element areas corresponding to the two pixel areas, respectively.

2. The array substrate as described in claim 1, characterized in that, The plurality of pixel regions include a plurality of blue pixel regions, a plurality of red pixel regions, and a plurality of green pixel regions, wherein the first via and the second via are respectively located in two element regions corresponding to two of the blue pixel regions.

3. The array substrate as described in claim 1, characterized in that, The array substrate further includes a first insulating layer, a second insulating layer, a color resist layer, and a leveling layer. The first insulating layer, the second insulating layer, and the color resist layer are disposed between the first conductive layer and the second conductive layer, and the leveling layer is disposed between the second conductive layer and the third conductive layer. The first via penetrates the first insulating layer, the second insulating layer, the color resist layer, and the leveling layer, and exposes the common electrode; the second via penetrates the leveling layer and exposes the transparent shielding electrode.

4. The array substrate as described in claim 3, characterized in that, The common electrode includes a common connection portion and a common connection line, the common connection portion being connected to the common connection line; the transparent shielding electrode includes a shielding electrode strip and a transparent connection portion, the transparent connection portion connecting two adjacent shielding electrode strips; the connecting electrode includes a first connection portion, a second connection portion, and a connecting line, the connecting line connecting the first connection portion and the second connection portion; The first via exposes the common connection portion, and the first connection portion is connected to the common connection portion through the first via; the second via exposes the transparent connection portion, and the second connection portion is connected to the transparent connection portion through the second via.

5. The array substrate as described in claim 4, characterized in that, The array substrate includes a thin-film transistor. The first conductive layer further includes a gate line and a gate of the thin-film transistor, the gate line and the gate being connected together. The common electrode is spaced apart from the gate and the gate line. The array substrate further includes a fourth conductive layer, which includes a data line. The third conductive layer further includes a pixel electrode, which is spaced apart from the connecting electrode. The shielding electrode strips extend along the extension direction of the gate line and are arranged along the extension direction of the data line; The projection of the shielding electrode strip on the substrate covers the projection of the pixel electrode on the substrate, at least a portion of the projection of the gate line on the substrate, and a portion of the projection of the data line on the substrate.

6. The array substrate as described in claim 5, characterized in that, The connecting electrode extends along the extension direction of the gate line.

7. The array substrate as described in claim 6, characterized in that, The projection of the connecting line on the substrate and the projection of the shielding electrode strip on the substrate completely cover the projection of the data line on the substrate.

8. The array substrate as described in claim 5, characterized in that, The common connection line includes a first common connection line and a second common connection line, wherein the first common connection line is parallel to the gate line and the second common connection line is perpendicularly connected to the first common connection line; The projection of the second common connection line onto the substrate overlaps with the projection of the main stem of the pixel electrode onto the substrate.

9. The array substrate as described in claim 2, characterized in that, The reduction in the number of blue pixel areas is 5%-15%.

10. A liquid crystal display panel, characterized in that, The liquid crystal display panel includes a color filter substrate, an array substrate as described in any one of claims 1 to 9, and a liquid crystal layer disposed between the color filter substrate and the array substrate.

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