Timing violation repair methods, devices, electronic equipment and storage media

Abstract

This application provides a timing violation repair method, apparatus, electronic device, and storage medium, belonging to the field of electronic circuits. The method includes: obtaining path values ​​between adjacent registers in a chip; determining path information related to a timing violation register based on a preset level N and the path values ​​between the adjacent registers; and determining a clock offset for repairing the timing violation register based on the worst-case timing value of the timing violation register, the worst-case timing values ​​of multi-level registers connected to the timing violation register, and the path information related to the timing violation register. By analyzing the path values ​​and worst-case timing values ​​between multi-level registers before and after the timing violation register, a global clock offset is achieved through the timing logic, improving the effectiveness of timing violation repair.

Description

Technical Field

[0001] This application relates to the field of electronic circuits, and more specifically, to a timing violation repair method, apparatus, electronic device, and storage medium. Background Technology

[0002] Within the digital circuits of a chip, due to unbalanced register pipeline partitioning in the register transfer stage design, the combinational logic of a certain register pipeline stage may become excessively long, leading to timing violations. A timing violation occurs when the actual delay time of a timing path in the chip does not meet the designer's required delay time for that path.

[0003] Timing violations can typically be corrected by setting a clock offset. Current timing correction processes analyze the timing states of the registers preceding and following the timing violation register, and then correct the timing violation based on these states. However, if the registers preceding and following the timing violation register do not have sufficient time margin for clock offsetting, timing violation correction cannot be performed, resulting in poor timing violation correction performance. Summary of the Invention

[0004] The purpose of this application is to provide a timing violation repair method, apparatus, electronic device, and storage medium to improve the repair effect of timing violations.

[0005] In a first aspect, this application provides a timing violation repair method, comprising: obtaining path values ​​between adjacent registers in a chip; wherein the path values ​​between adjacent registers are path margins between adjacent registers; determining path information related to a timing violation register based on a preset number of stages N and the path values ​​between adjacent registers; wherein the path information includes: path information between the timing violation register and the preceding N stages of registers of the timing violation register, and path information between the timing violation register and the following N stages of registers of the timing violation register; N is a positive integer greater than or equal to 2; determining a clock offset for timing violation repair of the timing violation register based on the worst timing value of the timing violation register, the worst timing values ​​of multi-stage registers connected to the timing violation register, and the path information related to the timing violation register; wherein the worst timing value is the minimum path value among the path values ​​from each fan-in device of the register to the register.

[0006] In this embodiment, when repairing timing violations in a timing violation register, the path information between the timing violation register and its preceding N-level registers, as well as the path information between the timing violation register and its following N-level registers, is determined based on a preset level N and the path values ​​between adjacent registers. The clock offset is then determined based on the timing information of the timing violation register and its preceding and following N-level registers. By analyzing the path values ​​and worst-case timing values ​​between multiple levels of registers before and after the timing violation register, a global clock offset is achieved by penetrating the timing logic, thus improving the effectiveness of timing violation repair.

[0007] In an optional implementation, before determining the path information related to the timing violation register based on the preset level N and the path value between the adjacent registers, the method further includes: obtaining the worst timing value of each register in the chip; and determining the register with the worst timing value less than or equal to the timing threshold as the timing violation register.

[0008] In this embodiment, by setting a timing threshold, the user can determine the timing threshold according to the stringency of the chip's timing requirements, identifying registers with high timing violation rates as timing violation registers, and then using the timing repair method provided in this embodiment for timing repair. For registers with low timing violation rates, the timing violation repair function built into the EDA can be used to achieve timing violation repair, thereby improving the timing violation repair efficiency.

[0009] In an optional implementation, the path information includes path values ​​between multiple adjacent registers; determining the path information related to the timing violation register based on the preset level N and the path values ​​between the adjacent registers includes: determining the path values ​​between two adjacent registers in the timing violation register and the first N level registers of the timing violation register level by level based on the preset level N and the path values ​​between the adjacent registers; and determining the path values ​​between two adjacent registers in the timing violation register and the last N level registers of the timing violation register level by level based on the preset level N and the path values ​​between the adjacent registers.

[0010] In an optional implementation, determining the clock offset for timing violation repair of the timing violation register based on the worst timing value of the timing violation register, the worst timing values ​​of the multi-level registers connected to the timing violation register, and the path information related to the timing violation register includes: determining a first clock offset based on the worst timing value of the timing violation register, the worst timing value of the first-level register connected to the timing violation register, and the path value between the timing violation register and the first-level register; and determining a second clock offset based on the worst timing value of the timing violation register, the worst timing values ​​of the first-level register and the second-level register connected to the timing violation register, and the path information between the timing violation register and the second-level register.

[0011] In an optional implementation, after determining the second clock offset, the method further includes: if the sum of the first clock offset and the second clock offset is less than the absolute value of the worst timing value of the timing violation register, determining the i-th clock offset based on the worst timing value of the timing violation register, the worst timing values ​​of the first to i-th level registers connected to the timing violation register, and the path information between the timing violation register and the i-th level register, where i is greater than or equal to 2 and less than or equal to N; until, if the sum of the first clock offset and the i-th clock offset is greater than or equal to the absolute value of the worst timing value of the timing violation register, or i is equal to N.

[0012] In an optional implementation, the first-level register includes a first-level fan-out register, the worst-case timing value of the first-level fan-out register, and a first-level fan-in register. Determining the first clock offset based on the worst-case timing value of the timing violation register, the worst-case timing value of the first-level register connected to the timing violation register, and the path value between the timing violation register and the first-level register includes: determining the first fan-out clock offset based on the worst-case timing value of the timing violation register and the path value between the timing violation register and the first-level fan-out register; if the first fan-out clock offset is less than the absolute value of the worst-case timing value of the timing violation register, determining the first fan-out clock offset based on the worst-case timing value of the timing violation register, the worst-case timing value of the first-level fan-in register, and the path value between the timing violation register and the first-level fan-in register.

[0013] In this embodiment, when determining the first clock offset, the first fan-out clock offset is first determined from the fan-out direction of the timing violation register, and then the first fan-out clock offset is determined from the fan-in direction of the timing violation register. Prioritizing the repair of the timing violation register from the fan-out direction reduces modifications to the overall timing path and improves repair efficiency and effectiveness.

[0014] In an optional implementation, the first-level register includes a first-level fan-out register and a first-level fan-in register, and the second-level register includes a second-level fan-out register and a second-level fan-in register. Determining the second clock offset based on the worst-case timing value of the timing violation register, the worst-case timing values ​​of the first-level register and the second-level register connected to the timing violation register, and the path information between the timing violation register and the second-level register includes: if the number of first-level fan-out registers is greater than the number of first-level fan-in registers, determining the second fan-in clock offset based on the worst-case timing value of the timing violation register, the worst-case timing value of the first-level fan-in register, the worst-case timing value of the second-level fan-in register, and the path information between the timing violation register and the second-level fan-in register; or, if the number of first-level fan-out registers is less than the number of first-level fan-in registers, determining the second fan-out clock offset based on the worst-case timing value of the timing violation register, the worst-case timing value of the first-level fan-out register, the worst-case timing value of the second-level fan-in register, and the path information between the timing violation register and the second-level fan-in register.

[0015] In this embodiment of the application, when determining the second clock offset, the number of the first-stage fan-out register and the number of the first-stage fan-in register are compared, and the direction with the smaller number is selected to perform timing analysis on the second-stage register. This results in less modification to the overall timing path when performing timing violation repair, thereby improving repair efficiency and repair effect.

[0016] In an optional implementation, determining the second fan-in clock offset based on the worst timing value of the timing violation register, the worst timing value of the first-level fan-in register, the worst timing value of the second-level fan-in register, and the path information between the timing violation register and the second-level fan-in register includes: determining the cumulative timing value between the second-level fan-in register and the timing violation register based on the path value between the first-level fan-in register and the timing violation register and the worst timing value of the first-level fan-in register; and determining the second fan-in clock offset based on the cumulative timing value between the second-level fan-in register and the timing violation register and the worst timing value of the second-level fan-in register.

[0017] In this embodiment of the application, by calculating the cumulative timing value, timing violations existing in other fan-in registers connected to the timing violation register can be repaired together, thereby improving the repair efficiency.

[0018] In an optional implementation, determining the second fan-out clock offset based on the worst timing value of the timing violation register, the worst timing value of the first-stage fan-out register, the worst timing value of the second-stage fan-out register, and the path information between the timing violation register and the second-stage fan-out register includes: determining the cumulative timing value from the timing violation register to the second-stage fan-out register based on the worst timing value of the timing violation register and the path value between the timing violation register and the first-stage fan-out register; and determining the second fan-out clock offset based on the cumulative timing value from the timing violation register to the second-stage fan-out register and the worst timing value of the second-stage fan-out register.

[0019] In this embodiment of the application, by calculating the cumulative timing value, timing violations existing in other fan-out registers connected to the timing violation register can be repaired together, thereby improving the repair efficiency.

[0020] Secondly, this application provides a timing violation repair device, comprising: an acquisition module, configured to acquire path values ​​between adjacent registers in a chip; wherein the path values ​​between adjacent registers are path margins between adjacent registers;

[0021] The path information determination module is used to determine the path information related to the timing violation register based on the preset level N and the path value between the adjacent registers; wherein, the path information includes: the path information between the timing violation register and the N level registers before the timing violation register, and the path information between the timing violation register and the N level registers after the timing violation register; N is a positive integer greater than or equal to 2;

[0022] The clock offset determination module is used to determine the clock offset for timing violation repair of the timing violation register based on the worst timing value of the timing violation register, the worst timing value of the multi-level registers connected to the timing violation register, and the path information related to the timing violation register; wherein the worst timing value is the minimum path value among the path values ​​from each fan-in device of the register to the register.

[0023] In an optional embodiment, the apparatus further includes: a timing violation register determination module, used to obtain the worst timing value of each register in the chip; and to determine the registers whose worst timing value is less than or equal to a timing threshold as the timing violation registers.

[0024] In an optional implementation, the path information includes path values ​​between multiple adjacent registers; the path information determination module is specifically used to determine, step by step, the path values ​​between two adjacent registers in the timing violation register and the first N level registers of the timing violation register according to a preset level N and the path values ​​between adjacent registers; and to determine, step by step, the path values ​​between two adjacent registers in the timing violation register and the last N level registers of the timing violation register according to the preset level N and the path values ​​between adjacent registers.

[0025] In an optional implementation, the clock offset determination module is specifically used to determine a first clock offset based on the worst timing value of the timing violation register, the worst timing value of the first-level register connected to the timing violation register, and the path value between the timing violation register and the first-level register; and to determine a second clock offset based on the worst timing value of the timing violation register, the worst timing values ​​of the first-level register and the second-level register connected to the timing violation register, and the path information between the timing violation register and the second-level register.

[0026] In an optional implementation, the clock offset determination module is further configured to determine the i-th clock offset, i being greater than or equal to 2 and less than or equal to N, based on the worst timing value of the timing violation register, the worst timing values ​​of the first to i-th level registers connected to the timing violation register, and the path information between the timing violation register and the i-th level register, if the sum of the first clock offset and the i-th clock offset is less than the absolute value of the worst timing value of the timing violation register; until, if the sum of the first clock offset and the i-th clock offset is greater than or equal to the absolute value of the worst timing value of the timing violation register, or if i equals N.

[0027] In an optional implementation, the first-level register includes a first-level fan-out register and a first-level fan-in register. The clock offset determination module is specifically used to determine a first fan-out clock offset based on the worst timing value of the timing violation register, the worst timing value of the first-level fan-out register, and the path value between the timing violation register and the first-level fan-out register. If the first fan-out clock offset is less than the absolute value of the worst timing value of the timing violation register, the first fan-out clock offset is determined based on the worst timing value of the timing violation register, the worst timing value of the first-level fan-in register, and the path value between the timing violation register and the first-level fan-in register.

[0028] In an optional implementation, the first-level register includes a first-level fan-out register and a first-level fan-in register, and the second-level register includes a second-level fan-out register and a second-level fan-in register. Specifically, the clock offset determination module is used to determine a second fan-in clock offset if the number of first-level fan-out registers is greater than the number of first-level fan-in registers, based on the worst-case timing value of the timing violation register, the worst-case timing value of the first-level fan-in register, the worst-case timing value of the second-level fan-in register, and the path information between the timing violation register and the second-level fan-in register; or, if the number of first-level fan-out registers is less than the number of first-level fan-in registers, to determine a second fan-out clock offset based on the worst-case timing value of the timing violation register, the worst-case timing value of the first-level fan-in register, the worst-case timing value of the second-level fan-out register, and the path information between the timing violation register and the second-level fan-in register.

[0029] In an optional implementation, the clock offset determination module is specifically used to determine the cumulative timing value between the second-level fan-in register and the timing violation register based on the path value between the first-level fan-in register and the timing violation register and the worst timing value of the first-level fan-in register; and to determine the second fan-in clock offset based on the cumulative timing value between the second-level fan-in register and the timing violation register and the worst timing value of the second-level fan-in register.

[0030] In an optional implementation, the clock offset determination module is specifically used to determine the cumulative timing value from the timing violation register to the second-level fan-out register based on the worst timing value of the timing violation register and the path value between the timing violation register and the first-level fan-out register; and to determine the second fan-out clock offset based on the cumulative timing value from the timing violation register to the second-level fan-out register and the worst timing value of the second-level fan-out register.

[0031] Thirdly, this application provides an electronic device, including: a processor, a memory, and a bus; the processor and the memory communicate with each other through the bus; the memory stores program instructions that can be executed by the processor, and the processor can execute the timing violation repair method as described in any of the foregoing embodiments by calling the program instructions.

[0032] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the timing violation repair method as described in any of the foregoing embodiments. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 A flowchart illustrating a timing violation repair method provided in this application embodiment. Figure 1 ;

[0035] Figure 2 This is a schematic diagram of a register timing path provided in an embodiment of this application;

[0036] Figure 3 A flowchart illustrating a timing violation repair method provided in this application embodiment. Figure 2 ;

[0037] Figure 4 A flowchart illustrating a timing violation repair method provided in this application embodiment. Figure 3 ;

[0038] Figure 5 A schematic diagram illustrating timing repair of a timing violation register provided in an embodiment of this application;

[0039] Figure 6 A schematic diagram of a process for determining clock offset is provided for an unusual embodiment.

[0040] Figure 7 A structural block diagram of a timing violation repair device provided in an embodiment of this application;

[0041] Figure 8 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0042] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0043] It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one…" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0044] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.

[0045] In existing timing repair processes, timing violations are corrected by analyzing the timing states of the registers before and after the timing violation register. However, if the registers before and after the timing violation register do not have sufficient time margin for clock offsetting, timing violation repair cannot be performed, resulting in poor timing violation repair performance.

[0046] Based on this, this application provides a timing violation repair method. By analyzing the path values ​​and worst timing values ​​between multi-level registers before and after the timing violation register, the method penetrates the timing logic to achieve global clock offset, thereby improving the timing violation repair effect.

[0047] Please see Figure 1 , Figure 1 A flowchart of a timing violation repair method provided in this application embodiment, the timing violation repair method may include:

[0048] S10: Obtain the path values ​​between adjacent registers in the chip.

[0049] In this embodiment, the path value between adjacent registers is the path margin between adjacent registers. Adjacent registers refer to two registers that are connected to each other. For example... Figure 2 As shown, register A (corresponding to Figure 2 RegA in the middle) and register B (corresponding to Figure 2 RegB in the table represents a group of adjacent registers, where the path value between register A and register B (corresponding to...) Figure 2 The slack value is -50 picoseconds; registers B and C (corresponding to...) Figure 2 RegC in the table represents a group of adjacent registers, with a path value of -10ps between register B and register C; register D (corresponding to...) Figure 2 RegD in the middle) and register E (corresponding to Figure 2 In the above, RegD is a group of adjacent registers, and the path value between register D and register C is -30ps; register E and register C are a group of adjacent registers, and the path value between register E and register C is 100ps.

[0050] The path values ​​between adjacent registers can be obtained using EDA (Electronic Design Automation) tools. EDA tools can be DesignCompiler, ICC2, PrimeTime developed by Synopsys, or Innovus developed by Cadence, etc., and this application does not limit them.

[0051] After obtaining the path values ​​between adjacent registers, these values ​​can be saved in a file as path pairs. A path pair includes the start point, end point, and corresponding path value.

[0052] For example, with Figure 2 For example, the path pair corresponding to register A and register B is: the starting point is the CLK pin of register A, the ending point is the D pin of register B, and the path value is -50ps.

[0053] S20: Determine the path information related to the timing violation register based on the preset level N and the path value between adjacent registers.

[0054] In this embodiment of the application, the path information includes: path information between the timing violation register and the first N level registers of the timing violation register, and path information between the timing violation register and the last N level registers of the timing violation register; N is a positive integer greater than or equal to 2.

[0055] The timing violation register is a register in which timing violations exist in the chip. Before executing step S20, the timing information of each register in the chip can be analyzed to determine the timing violation register.

[0056] In some embodiments, the timing violation register can be analyzed by static timing analysis of the chip using EDA tools to determine the timing information of each path. Based on the timing information of each path, the registers with timing violations are identified as timing violation registers.

[0057] In other embodiments, timing violation registers are determined by: obtaining the worst timing value of each register in the chip; and identifying registers whose worst timing value is less than a timing threshold as timing violation registers.

[0058] In this embodiment, the worst-case timing value of a register is the minimum path value among the path values ​​from each fan-in device to the register. A fan-in device is the next-level device adjacent to the register. A fan-in device can be a register or a module port.

[0059] by Figure 2 For example, the fan-in devices of registers A and D are the module input ports (corresponding to...). Figure 2 In the input field (inputA), register B's fan-in device is register A, register C's fan-in devices are registers B and E, and register E's fan-in device is register D. Since register A has only one fan-in device, the worst-case timing value of register A is the path value from inputA to register A, which is 100ps. Similarly, the worst-case timing value of register B is -50ps, the worst-case timing value of register D is -20ps, and the worst-case timing value of register E is -30ps. Register C has two fan-in devices; the path value from register B to register C is -10ps, and the path value from register E to register C is 100ps. Therefore, the worst-case timing value of register C is -10ps.

[0060] After obtaining the worst-case timing values ​​of each register in the chip, these values ​​are compared with timing thresholds. Registers with timing values ​​less than the threshold are identified as timing violation registers. The timing threshold can be set according to the chip's timing stringency. Higher timing stringency requires a larger timing threshold, and vice versa.

[0061] For example, with Figure 2 For example, if the chip has a high timing strictness and the timing threshold is set to 0ps, then registers B, C, D, and E are timing violation registers, while register A is not a timing violation register. If the chip has a low timing strictness and the timing threshold is set to -30ps, then registers B and E are timing violation registers, while registers A, C, and D are not timing violation registers.

[0062] When the timing violation severity of a register is low (i.e., the register's timing value is less than zero but its absolute value is small), it can often be repaired using the timing violation repair function built into the EDA module. Therefore, this embodiment of the application sets a timing threshold, allowing users to set the threshold according to the chip's timing requirements, identifying registers with high timing violation severity as timing violation registers, and then using the timing repair method provided in this embodiment for timing repair. For registers with low timing violation severity, the timing violation repair function built into the EDA module can be used to achieve timing violation repair, thereby improving the timing violation repair efficiency.

[0063] After determining the timing violation register from the chip, in order to analyze the path between the multi-level registers before and after the timing violation register, a preset number of levels N is set to obtain the path information between the timing violation register and the N-level registers before the timing violation register, as well as the path information between the timing violation register and the N-level registers after the timing violation register.

[0064] When analyzing the paths between multiple register levels before and after the timing violation register, considering that some functional modules in the chip have a large number of register levels, tracing forward from the timing violation register to the input port or backward to the output port of the functional module would significantly increase the runtime without improving the timing violation repair effect. Therefore, a preset number of levels N is set. When determining the path information related to the timing violation register, only the path information between the N levels before and after the timing violation register and the timing violation register itself is obtained, thus improving processing efficiency.

[0065] In some embodiments, the preset level N is set to 3, 4, or 5, etc.

[0066] The implementation of S20 described above will be explained below with reference to the embodiments.

[0067] The above-mentioned S20 determines the path information related to the timing violation register based on the preset level N and the path value between adjacent registers, which may include: determining the path value between two adjacent registers in the timing violation register and the first N level registers of the timing violation register step by step based on the preset level N and the path value between adjacent registers; determining the path value between two adjacent registers in the timing violation register and the last N level registers of the timing violation register step by step based on the preset level N and the path value between adjacent registers.

[0068] In this embodiment of the application, after determining the path values ​​between each adjacent register in the chip, the path values ​​between two adjacent registers in the timing violation register and the first N level registers of the timing violation register are determined step by step from the data input direction of the timing violation register according to the preset level N; the path values ​​between two adjacent registers in the timing violation register and the first N level registers of the timing violation register are determined step by step from the data output direction of the timing violation register according to the preset level N.

[0069] Specifically, such as Figure 3 As shown, the path value between two adjacent registers can be determined from the data input direction of the timing violation register in the following way:

[0070] S31: Determine the path value between the first-level fan-in register of the timing violation register and the timing violation register.

[0071] S32: i takes values ​​from 1 to N-1 in sequence to determine the path value between the (i+1)th level fan-in register of the timing violation register and the i-th level fan-in register of the timing violation register.

[0072] Similarly, such as Figure 4 As shown, the path value between two adjacent registers can be determined from the data output direction of the timing violation register in the following way:

[0073] S41: Determine the path value between the first-level fan-out register of the timing violation register and the timing violation register.

[0074] S42: i takes values ​​from 1 to N-1 in sequence to determine the path value between the (i+1)th level fan-out register of the timing violation register and the i-th level fan-out register of the timing violation register.

[0075] Based on the worst timing value of the timing violation register, the worst timing values ​​of the multi-level registers connected to the timing violation register, and the path information associated with the timing violation register, determine the clock offset used to repair timing violations in the timing violation register.

[0076] In this embodiment, step S20 determines the connection relationships and path values ​​between adjacent registers and the timing violation register, including the timing violation register, its preceding N-level registers, and its subsequent N-level registers. Based on the worst-case timing values ​​of the timing violation register, its preceding N-level registers, and its subsequent N-level registers, and the path values ​​between these registers, a clock offset for timing violation repair of the timing violation register is determined.

[0077] As an optional implementation, step S30 includes: determining a first clock offset based on the worst timing value of the timing violation register, the worst timing value of the first-level register connected to the timing violation register, and the path value between the timing violation register and the first-level register; and determining a second clock offset based on the worst timing value of the timing violation register, the worst timing values ​​of the first-level register and the second-level register connected to the timing violation register, and the path information between the timing violation register and the second-level register.

[0078] In this embodiment, the timing information of the timing violation register and the first-level register connected to the timing violation register is first analyzed to determine the first clock offset. If the first clock offset can repair the timing violation of the timing violation register, there is no need to further determine the second clock offset; if the first clock offset cannot repair the timing violation of the timing violation register or can only reduce the timing violation degree of the timing violation register, then the second clock offset is further determined based on the worst timing values ​​of each register between the timing violation register and the second-level register connected to the timing violation register, and the path information between the timing violation register and the second-level register, and the timing violation of the timing violation register is repaired based on the first clock offset and the second clock offset.

[0079] When performing timing violation repair on a timing violation register, the path between the timing violation register and its fan-in register should meet the following conditions:

[0080] T_launch+T_ck2q+T_dp+T_margin<=T_capture+T_clk-T_setup

[0081] Where T_launch is the clock offset of the starting register, T_ck2q is the time from inside the register to the output, T_dp is the path delay, and T_margin is the reserved margin. T_capture is the clock offset of the ending register, T_clk is one clock cycle, and T_setup is the setup time of the ending register.

[0082] It should be noted that the first clock offset adjusts the T_launch and T_capture in the path between the timing violation register and the first-level register connected to the timing violation register. The second clock offset adjusts the T_launch and T_capture in the path between the first-level register connected to the timing violation register and the second-level register connected to the timing violation register. Through this step-by-step adjustment, the path between the adjusted timing violation register and its fan-in register satisfies the above conditions, thus achieving the effect of repairing the timing violation of the timing violation register.

[0083] The following explains how the first clock offset is determined.

[0084] As an optional implementation, the first-stage register includes a first-stage fan-out register and a first-stage fan-in register, and the first clock offset can be determined in the following way:

[0085] The first fan-out clock offset is determined based on the worst timing value of the timing violation register, the worst timing value of the first-level fan-out register, and the path value between the timing violation register and the first-level fan-out register.

[0086] If the first fan-out clock offset is less than the absolute value of the worst timing value of the timing violation register, the first fan-in clock offset value is determined based on the worst timing value of the timing violation register, the worst timing value of the first-level fan-in register, and the path value between the timing violation register and the first-level fan-in register.

[0087] In this embodiment, when determining the first clock offset, timing analysis is first performed from the fan-out direction of the timing violation register to determine whether the minimum path value among the multiple first-level fan-out registers is greater than or equal to the absolute value of the worst timing value of the timing violation register. If it is greater than or equal to, the first fan-out clock offset is determined to be the absolute value of the worst timing value of the timing violation register, and the clock of the timing violation register is delayed backward by the absolute value of the worst timing value, thereby completing the repair of the timing violation. If it is less than and the minimum path value among the multiple first-level fan-out registers is greater than 0, the first fan-out clock offset is determined to be the minimum path value among the multiple first-level fan-out registers, and the clock of the timing violation register is delayed backward by the minimum path value among the multiple first-level fan-out registers.

[0088] If the minimum path value among multiple first-stage fan-out registers is less than 0, it indicates that the timing violation cannot be mitigated by delaying the clock of the timing violation register itself; otherwise, a new timing violation will occur in the first-stage fan-out register. Therefore, the clock of the timing violation register itself is not delayed, and the first fan-out clock offset is set to 0.

[0089] It should be noted that after determining the first fan-out clock offset, the path value between the first-level fan-in register and the timing violation register is updated according to the first fan-out clock offset.

[0090] If the first fan-out clock offset is less than the absolute value of the worst timing value of the timing violation register, it indicates that timing violation repair of the timing violation register cannot be achieved through the first fan-out clock offset. Therefore, further timing analysis is performed from the fan-in direction of the timing violation register. It is then determined whether the worst timing value of each first-level fan-in register is greater than or equal to the path value between the updated first-level fan-in register and the timing violation register. If it is greater than or equal to, the first fan-in clock offset value corresponding to that first-level fan-in register is determined to be the path value between the updated first-level fan-in register and the timing violation register. The clock of that first-level fan-in register is then advanced by the first fan-in clock offset value.

[0091] If the worst timing value of the first-level fan-in register is less than the path value between the updated first-level fan-in register and the timing violation register, there are several ways to handle it.

[0092] In one approach: if the worst-case timing value in the first-stage fan-in register is greater than 0, the first fan-in clock offset value corresponding to the first-stage fan-in register is determined to be the worst-case timing value of the first-stage fan-in register, and the clock of the first-stage fan-in register is advanced by the first fan-in clock offset value. If the worst-case timing value in the first-stage fan-in register is less than 0, it indicates that the timing violation cannot be mitigated by advancing the clock of the first-stage fan-in register; otherwise, it would lead to a new timing violation in the first-stage fan-in register. Therefore, the clock of the first-stage fan-in register is not advanced, and the first fan-in clock offset value is set to 0.

[0093] In another approach: if the value is less than 0, the first fan-in clock offset is set to 0. Subsequently, the timing violation register is repaired using the second clock offset.

[0094] For example, such as Figure 5 As shown in Example 1, the timing violation register (corresponding to...) Figure 5The worst-case timing value wns of the timing violation register (the violation Node) is -50ps. The timing violation register corresponds to two first-level fanout registers: fanout Node1 (fanout register 1) and fanout Node2 (fanout register 2). The path value between the timing violation register and fanout Node1 is 60ps, and the path value between the timing violation register and fanout Node2 is 50ps. Both are greater than the absolute value of the worst-case timing value of the timing violation register. Therefore, the first fanout clock offset is determined to be 50ps. The clock of the timing violation register itself is delayed by 50ps, thereby correcting the timing violation. The corrected clock is shown in the clock diagram on the right side of Example 1.

[0095] like Figure 5 As shown in Example 2, the worst-case timing value wns of the timing violation register is -50ps. The timing violation register has two first-stage fanout registers: fanout Node1 and fanout Node2. The path value between the timing violation register and fanout Node1 is 20ps, and the path value between the timing violation register and fanout Node2 is 50ps. Since the path value between the timing violation register and fanout Node1 is less than the absolute value of the worst-case timing value of the timing violation register, the first fanout clock offset is determined to be 20ps, and the clock of the timing violation register itself is delayed by 20ps.

[0096] The first fan-out clock offset is less than the absolute value of the worst timing value in the timing violation register. Therefore, the first fan-in clock offset needs to be further determined based on the first-level fan-in registers. The timing violation register corresponds to two first-level fan-in registers: fanin Node1 and fanin Node2. Since the first fan-out clock offset is 20ps, the path value between fanin Node1 and the timing violation register is updated from -30ps to -10ps, and the path value between fanin Node2 and the timing violation register is updated from -50ps to -30ps. The worst timing value of fanin Node1 is 50ps, which is greater than 10ps, so the first fan-in clock offset value corresponding to fanin Node1 is 10ps. The worst timing value of fanin Node2 is 40ps, which is greater than 30ps, so the first fan-in clock offset value corresponding to fanin Node2 is 30ps. The corrected clock is shown in the clock diagram on the right side of Example 2.

[0097] As another optional implementation, the first-stage register includes a first-stage fan-out register and a first-stage fan-in register, and the first clock offset can be determined in the following way:

[0098] The first fan-in clock offset value is determined based on the worst timing value of the timing violation register, the worst timing value of the first-level fan-in register, and the path value between the timing violation register and the first-level fan-in register.

[0099] If the first fan-in clock offset is less than the absolute value of the worst timing value of the timing violation register, the first fan-out clock offset is determined based on the worst timing value of the timing violation register, the worst timing value of the first-level fan-out register, and the path value between the timing violation register and the first-level fan-out register.

[0100] In this embodiment of the application, when determining the first clock offset, timing analysis is first performed from the fan-in direction of the timing violation register to determine the first fan-in clock offset value; then timing analysis is performed from the fan-out direction of the timing violation register to determine the first fan-out clock offset.

[0101] The method for determining the first fan-in clock offset and the first fan-out clock offset is the same as that for determining the first fan-in clock offset and the first fan-out clock offset in the previous embodiment. For the sake of brevity, it will not be repeated here.

[0102] The following explains how the second clock offset is determined.

[0103] As an optional implementation, the first-stage register includes a first-stage fan-out register and a first-stage fan-in register, the second-stage register includes a second-stage fan-out register and a second-stage fan-in register, and the second clock offset can be determined in the following way:

[0104] If the number of first-stage fan-out registers is greater than the number of first-stage fan-in registers, the second fan-in clock offset is determined based on the worst timing value of the timing violation register, the worst timing value of the first-stage fan-in register, the worst timing value of the second-stage fan-in register, and the path information between the timing violation register and the second-stage fan-in register.

[0105] Alternatively, if the number of first-level fan-out registers is less than the number of first-level fan-in registers, the second fan-out clock offset is determined based on the worst timing value of the timing violation register, the worst timing value of the first-level fan-in register, the worst timing values ​​of each register between the second-level fan-out registers, and the path information between the timing violation register and the second-level fan-out register.

[0106] In this embodiment of the application, when determining the second clock offset, the number of the first-stage fan-out register and the number of the first-stage fan-in register are compared, and the direction with the smaller number is selected to perform timing analysis on the second-stage register.

[0107] The following explains how the second fan-in clock offset is determined.

[0108] As an optional implementation, the second fan-in clock offset can be determined in the following way:

[0109] Based on the path value between the first-level fan-in register and the timing violation register, and the worst timing value of the first-level fan-in register, determine the cumulative timing value between the second-level fan-in register and the timing violation register;

[0110] The second fan-in clock offset is determined based on the cumulative timing value between the second-level fan-in register and the timing violation register, and the worst timing value of the second-level fan-in register.

[0111] In this embodiment, the cumulative timing value between the second-level fan-in register and the timing violation register can be obtained through... wns(i) represents the path value between the first-level fan-in register and the timing violation register, and represents the worst timing value of the i-th-level fan-in register.

[0112] It should be noted that when calculating the cumulative timing value between the second-level fan-in register and the timing violation register, n in the above formula is set to 2. When calculating the cumulative timing value between the i-th-level fan-in register and the timing violation register, n is set to i.

[0113] After calculating the cumulative timing value from the second-level fan-in register to the timing violation register using the above formula, it is determined whether the worst-case timing value of the second-level fan-in register is greater than or equal to the absolute value of the cumulative timing value. If it is greater than or equal to the absolute value, the second fan-in clock offset corresponding to the second-level fan-in register is determined to be the absolute value of the cumulative timing value; and the second fan-in clock offset corresponding to the first-level fan-in register is determined to be the absolute value of the worst-case timing value of the timing violation register.

[0114] If the worst timing value of the second-stage fan-in register is less than the absolute value of the cumulative timing value, there are several ways to handle it.

[0115] In one approach: if the worst timing value of the second-level fan-in register is less than the absolute value of the cumulative timing value and the worst timing value of the second-level fan-in register is greater than 0, the second fan-in clock offset value corresponding to the second-level fan-in register is determined to be the worst timing value of the second-level fan-in register, and the clock of the second-level fan-in register is advanced by the second fan-in clock offset value. If the worst timing value of the second-level fan-in register is less than the absolute value of the cumulative timing value and the worst timing value in the second-level fan-in register is less than 0, it means that the timing violation cannot be mitigated by advancing the clock of the second-level fan-in register, otherwise it will lead to a new timing violation in the second-level fan-in register. Therefore, the clock of the second-level fan-in register is not advanced, and the second fan-in clock offset value is set to 0.

[0116] In another approach: if the worst timing value of the second-stage fan-in register is less than the absolute value of the cumulative timing value, the second fan-in clock offset value is set to 0.

[0117] It should be noted that when there are multiple second-level fan-in registers, the above process will be performed once for each second-level fan-in register to determine the second fan-in clock offset value corresponding to each second-level fan-in register.

[0118] For example, such as Figure 5 As shown in Example 3, according to the aforementioned embodiment, timing violations in the timing violation register cannot be corrected based on the timing information between the first-level register and the timing violation register. The number of first-level fan-in registers is less than the number of first-level fan-out registers. Timing analysis is performed on the second-level fan-in registers from the fan-in direction of the timing violation register. The timing violation register corresponds to two second-level fan-in registers: level2 fanin Node1 (second-level fan-in register 1) and level2 fanin Node2 (second-level fan-in register 2). The cumulative timing value between level2 fanin Node1 and the timing violation register is -60ps. The worst-case timing value of level2 fanin Node1 is 70ps, which is greater than 60ps. The second fan-in clock offset value corresponding to level2 fanin Node1 is 60ps. The cumulative timing value between level2 fanin Node2 and the timing violation register is -60ps. The worst-case timing value of level2 fanin Node1 is 60ps, which is equal to 60ps. The second fan-in clock offset value corresponding to level2 fanin Node1 is 60ps. The second fan-in clock offset value corresponding to the fanin node (first-stage fan-in register) is 50ps. The repaired clock is shown in the clock diagram on the right side of Example 3.

[0119] The following explains how to determine the second fan-out clock offset.

[0120] As an optional implementation, the second fan-out clock offset can be determined in the following way:

[0121] Based on the worst timing value of the timing violation register and the path value between the timing violation register and the first-level fan-out register, determine the cumulative timing value from the timing violation register to the second-level fan-out register;

[0122] The second fan-out clock offset is determined based on the cumulative timing value between the timing violation register and the second-level fan-out register, and the worst timing value of the second-level fan-out register.

[0123] In this embodiment, the cumulative timing value between the second-level fan-out register and the timing violation register can be obtained through... The path value between the (n-1)th level fanout register and the nth level fanout register, wns(0) represents the worst timing value of the timing violation register.

[0124] It should be noted that when calculating the cumulative timing value between the second-level fan-out register and the timing violation register, n in the above formula is set to 2. When calculating the cumulative timing value between the i-th-level fan-out register and the timing violation register, n is set to i.

[0125] After calculating the cumulative timing value from the second-level fan-out register to the timing violation register using the above formula, it is determined whether the minimum path value between each second-level fan-out register and its corresponding first-level fan-out register is greater than or equal to the absolute value of the cumulative timing value. If it is greater than or equal to the cumulative timing value, the second fan-out clock offset is determined to be the absolute value of the cumulative timing value, the second fan-out clock deviation corresponding to the timing violation register is determined to be the absolute value of the worst timing value of the timing violation register, and the clock deviation corresponding to the first-level fan-out register is the difference between the absolute value of the cumulative timing value and the absolute value of the worst timing value of the timing violation register.

[0126] For example, such as Figure 5 As shown in Example 4, according to the aforementioned embodiment, the timing violation of the timing violation register cannot be repaired based on the timing information between the first-level register and the timing violation register. The number of first-level fan-out registers is less than the number of first-level fan-in registers. Timing analysis is performed on the second-level fan-out registers from the fan-out direction of the timing violation register. The timing violation register corresponds to two second-level fan-out registers: level2 fanout Node1 and level2 fanout Node2. The cumulative timing value between level2 fanout Node1 and level2 fanout Node2 and the timing violation register is -70ps. The path from level2 fanin Node1 to the first-level fanout register fanout Node is 100ps, and the path from level2 fanin Node2 to the first-level fanout register fanout Node is 140ps, both greater than 70ps. The second fan-out clock offset value corresponding to the timing violation register is 70ps, and the second fan-out clock offset value corresponding to the first-level fanout register is 50ps. The repaired clock is shown in the clock diagram on the right side of Example 4.

[0127] Furthermore, after determining the second clock offset, the timing violation repair method provided in this application embodiment also includes:

[0128] If the sum of the first clock offset and the second clock offset is less than the absolute value of the worst timing value of the timing violation register, the i-th clock offset is determined based on the worst timing value of the timing violation register, the worst timing values ​​of the first to i-th level registers connected to the timing violation register, and the path information between the timing violation register and the i-th level register, where i is greater than or equal to 2 and less than or equal to N; until the sum of the first clock offset to the i-th clock offset is greater than or equal to the absolute value of the worst timing value of the timing violation register, or i is equal to N.

[0129] In this embodiment, the worst timing value of the first to i-th level registers connected to the timing violation register refers to the worst timing value of each level of registers connected to the timing violation register. Taking i equals N and N is 5 as an example, the worst timing values ​​of the first to fifth level registers connected to the timing violation register are the worst timing values ​​of the first level register, the second level register, the third level register, the fourth level register, and the fifth level register connected to the timing violation register.

[0130] After analyzing the timing information of the first and second level registers of the timing violation register to determine the first and second clock offsets, if the sum of the first and second clock offsets is less than the absolute value of the worst timing value of the timing violation register, it indicates that a timing violation still exists in the timing violation register. In this case, the timing information of the third level register of the timing violation register is further analyzed to determine the third clock offset. If the sum of the first to third clock offsets is less than the absolute value of the worst timing value of the timing violation register, the timing information of the fourth level register of the timing violation register is further analyzed to determine the fourth clock offset. This process continues until the sum of the first to the i-th clock offset is greater than or equal to the absolute value of the worst timing value of the timing violation register. If, after i equals N, the sum of the first to the i-th clock offset is still less than the absolute value of the worst timing value of the timing violation register, it indicates that the timing violation in the timing violation register cannot be completely repaired. The reason for the repair failure can be recorded and sent to the user.

[0131] It is understandable that the method for determining the i-th clock offset is similar to the method for determining the second clock offset described above, and will not be repeated here for the sake of brevity.

[0132] After determining the first clock offset, two types of timing violation repair logic can be set.

[0133] The first method: When the first clock offset cannot completely repair the timing violation register, compare the number of first-stage fan-out registers and first-stage fan-in registers, and select the direction with the smaller number to repair the timing violation register.

[0134] If the first-level fan-out register is small, the second fan-out clock offset is determined based on the timing information of the second-level fan-out register. If the first and second clock offsets are still insufficient to completely correct the timing violation register, the third fan-out clock offset is determined based on the timing information of the third-level fan-out register. This process continues until the Nth-level fan-out register. If the determined clock offsets are still insufficient to completely correct the timing violation register, the second fan-in clock offset is determined based on the timing information of the second-level fan-out register, starting from the fan-in direction of the timing violation register. This process continues until the Nth-level fan-in register.

[0135] If the number of first-stage fan-in registers is small, the processing method is similar to that for cases where the number of first-stage fan-out registers is small.

[0136] The following combination Figure 6 The overall process for determining the clock offset is explained.

[0137] Starting with a timing violation register Node, currently at level 0, the process first checks if Node has fanouts and if the minimum path value from Node to each fanout exceeds Node's wns (the worst-case timing value of the timing violation register). If it does, Node's own clock delay is set to the absolute value of wns. If not, the process checks if the minimum path value from Node to each fanout is greater than 0. If it is, Node can delay the clock to the minimum path value from each fanout, reducing the timing violation. Next, the worst-case timing value of Node's fanin (corresponding to...) is determined. Figure 6 Does wns(fanin) in the Node exceed the absolute value of the path value between the Node and its fanin (corresponding to...)? Figure 6 If the Slack (fanin to violation node) exceeds the limit, the node is repaired using the method described above for determining the first fanin clock offset. If the limit is not met, the number of fanins for the node (corresponding to...) is then checked. Figure 6 The number (fanin) and fanout number (corresponding to) Figure 6In the process of repairing fanout nodes, the process prioritizes nodes with smaller fanout numbers. The flowchart prioritizes fanin nodes, while the fanout priority section is omitted. Then, fanin repair is performed, using the previously described method for determining the second fanout clock offset. If the current level can be repaired, the repair is complete. If not, the process continues tracking the next fanin level. The recursive algorithm in the diagram increments the level by 1 during the fanin repair process. The process exits when the level reaches the set threshold (thresholdlevel, i.e., the preset level N) or when the current level no longer has fanout nodes, indicating that fanin repair has failed and the process enters the fanout repair procedure. The fanout repair process is similar to the previously described method for determining the second fanout clock offset. If fanout repair is successful, the repair procedure exits. If the threshold is exceeded or the current level no longer has fanout nodes, the repair fails. The dashed box in the diagram represents the recursive process of fanout repair.

[0138] The second approach is to compare the number of first-stage fan-out registers and first-stage fan-in registers when the first clock offset cannot completely repair the timing violation registers, select the direction with the smaller number, and repair the timing violation registers based on the timing information of the second-stage registers.

[0139] If the number of first-level fan-out registers is small, the second fan-out clock offset is determined based on the timing information of the second-level fan-out registers. If the first clock offset and the second fan-out clock offset are still insufficient to completely correct the timing violation register, the second fan-in clock offset is determined based on the timing information of the second-level fan-in register. If the second fan-out clock offset and the second fan-in clock offset determined based on the timing information of the second-level registers are still insufficient to completely correct the timing violation register, the number of second-level fan-in registers and second-level fan-out registers are compared again, and the direction with the smaller number is selected to correct the timing violation register based on the timing information of the third-level register. The process of correcting the timing violation register based on the timing information of the third-level register is similar to the process of correcting the timing violation register based on the timing information of the second-level register. This process continues until the Nth level register.

[0140] If the number of first-stage fan-in registers is small, the processing method is similar to that for cases where the number of first-stage fan-out registers is small.

[0141] Based on the same inventive concept, this application also provides a timing violation repair device, such as... Figure 7 As shown, the timing violation repair device 700 includes:

[0142] The acquisition module 701 is used to acquire the path value between each adjacent register in the chip; wherein, the path value between the adjacent registers is the path margin between the adjacent registers;

[0143] The path information determination module 702 is used to determine path information related to the timing violation register based on a preset level N and the path value between the adjacent registers; wherein, the path information includes: path information between the timing violation register and the N level registers before the timing violation register, and path information between the timing violation register and the N level registers after the timing violation register; N is a positive integer greater than or equal to 2;

[0144] The clock offset determination module 703 is used to determine a clock offset for timing violation repair of the timing violation register based on the worst timing value of the timing violation register, the worst timing value of the multi-level registers connected to the timing violation register, and the path information related to the timing violation register; wherein the worst timing value is the minimum path value among the path values ​​from each fan-in device of the register to the register.

[0145] In an optional embodiment, the device further includes: a timing violation register determination module 704, used to obtain the worst timing value of each register in the chip; and to determine the registers whose worst timing value is less than or equal to a timing threshold as the timing violation registers.

[0146] In an optional implementation, the path information includes path values ​​between multiple adjacent registers; the path information determination module 702 is specifically used to determine, step by step, the path values ​​between two adjacent registers in the timing violation register and the first N level registers of the timing violation register according to a preset level N and the path values ​​between adjacent registers; and to determine, step by step, the path values ​​between two adjacent registers in the timing violation register and the last N level registers of the timing violation register according to the preset level N and the path values ​​between adjacent registers.

[0147] In an optional implementation, the clock offset determination module 703 is specifically used to determine a first clock offset based on the worst timing value of the timing violation register, the worst timing value of the first-level register connected to the timing violation register, and the path value between the timing violation register and the first-level register; and to determine a second clock offset based on the worst timing value of the timing violation register, the worst timing values ​​of the first-level register and the second-level register connected to the timing violation register, and the path information between the timing violation register and the second-level register.

[0148] In an optional implementation, the clock offset determination module 703 is further configured to determine the i-th clock offset, i being greater than or equal to 2 and less than or equal to N, based on the worst timing value of the timing violation register, the worst timing values ​​of the first to i-th level registers connected to the timing violation register, and the path information between the timing violation register and the i-th level register, if the sum of the first clock offset and the i-th clock offset is less than the absolute value of the worst timing value of the timing violation register; until, if the sum of the first clock offset and the i-th clock offset is greater than or equal to the absolute value of the worst timing value of the timing violation register, or if i is equal to N.

[0149] In an optional implementation, the first-level register includes a first-level fan-out register and a first-level fan-in register. The clock offset determination module 703 is specifically used to determine a first fan-out clock offset based on the worst timing value of the timing violation register, the worst timing value of the first-level fan-out register, and the path value between the timing violation register and the first-level fan-out register. If the first fan-out clock offset is less than the absolute value of the worst timing value of the timing violation register, the first fan-out clock offset is determined based on the worst timing value of the timing violation register, the worst timing value of the first-level fan-in register, and the path value between the timing violation register and the first-level fan-in register.

[0150] In an optional implementation, the first-level register includes a first-level fan-out register and a first-level fan-in register, and the second-level register includes a second-level fan-out register and a second-level fan-in register; the clock offset determination module 703 is specifically used to determine a second fan-in clock offset if the number of first-level fan-out registers is greater than the number of first-level fan-in registers, based on the worst timing value of the timing violation register, the worst timing value of the first-level fan-in register, the worst timing value of the second-level fan-in register, and the path information between the timing violation register and the second-level fan-in register; or, if the number of first-level fan-out registers is less than the number of first-level fan-in registers, determine a second fan-out clock offset based on the worst timing value of the timing violation register, the worst timing value of the first-level fan-out register, the worst timing value of the second-level fan-in register, and the path information between the timing violation register and the second-level fan-in register.

[0151] In an optional implementation, the clock offset determination module 703 is specifically used to determine the cumulative timing value between the second-level fan-in register and the timing violation register based on the path value between the first-level fan-in register and the timing violation register and the worst timing value of the first-level fan-in register; and to determine the second fan-in clock offset based on the cumulative timing value between the second-level fan-in register and the timing violation register and the worst timing value of the second-level fan-in register.

[0152] In an optional implementation, the clock offset determination module 703 is specifically used to determine the cumulative timing value between the timing violation register and the second-level fan-out register based on the worst timing value of the timing violation register and the path value between the timing violation register and the first-level fan-out register; and to determine the second fan-out clock offset based on the cumulative timing value between the timing violation register and the second-level fan-out register and the worst timing value of the second-level fan-out register.

[0153] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of an electronic device 800 according to an embodiment of this application. The electronic device 800 includes: at least one processor 801, at least one communication interface 802, at least one memory 803, and at least one bus 804. The bus 804 is used to enable direct communication between these components. The communication interface 802 is used for signaling or data communication with other node devices. The memory 803 stores machine-readable instructions executable by the processor 801. When the electronic device 800 is running, the processor 801 communicates with the memory 803 via the bus 804. When the machine-readable instructions are invoked by the processor 801, the timing violation repair method described above is executed.

[0154] The processor 801 can be an integrated circuit chip with signal processing capabilities. The processor 801 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor.

[0155] The memory 803 may include, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0156] Furthermore, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when run by a computer, performs the steps of the timing violation repair method as described in the above embodiments.

[0157] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0158] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0159] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0160] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, laptop, server, or electronic device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned computer-readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0161] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for repairing timing violations, characterized in that, include: Obtain the path values ​​between adjacent registers in the chip; wherein, the path values ​​between adjacent registers are the path margin between adjacent registers; Based on the preset level N and the path values ​​between the adjacent registers, the path information related to the timing violation register is determined; wherein, the path information includes: the path information between the timing violation register and the N level registers before the timing violation register, and the path information between the timing violation register and the N level registers after the timing violation register; N is a positive integer greater than or equal to 2; Based on the worst timing value of the timing violation register, the worst timing values ​​of the multi-level registers connected to the timing violation register, and the path information associated with the timing violation register, a clock offset for timing violation repair of the timing violation register is determined; wherein, the worst timing value is the minimum path value among the path values ​​from each fan-in device of the register to the register. The step of determining the clock offset for timing violation repair of the timing violation register based on the worst-case timing value of the timing violation register, the worst-case timing values ​​of the multi-level registers connected to the timing violation register, and the path information associated with the timing violation register includes: The first clock offset is determined based on the worst timing value of the timing violation register, the worst timing value of the first-level register connected to the timing violation register, and the path value between the timing violation register and the first-level register. The second clock offset is determined based on the worst timing value of the timing violation register, the worst timing values ​​of the first-level register and the second-level register connected to the timing violation register, and the path information between the timing violation register and the second-level register.

2. The timing violation repair method according to claim 1, characterized in that, Before determining the path information related to the timing violation register based on the preset level N and the path value between the adjacent registers, the method further includes: Obtain the worst-case timing values ​​of each register in the chip; The register with the worst timing value less than or equal to the timing threshold is identified as the timing violation register.

3. The timing violation repair method according to claim 1, characterized in that, The path information includes path values ​​between multiple adjacent registers; The step of determining the path information related to the timing violation register based on the preset level N and the path value between the adjacent registers includes: Based on the preset level N and the path value between the adjacent registers, the path value between two adjacent registers in the timing violation register and the first N level registers of the timing violation register is determined level by level; Based on the preset level N and the path value between the adjacent registers, the path value between two adjacent registers in the timing violation register and the N level registers following the timing violation register is determined level by level.

4. The timing violation repair method according to claim 1, characterized in that, After determining the second clock offset, the method further includes: If the sum of the first clock offset and the second clock offset is less than the absolute value of the worst timing value of the timing violation register, the i-th clock offset is determined based on the worst timing value of the timing violation register, the worst timing values ​​of the first to i-th level registers connected to the timing violation register, and the path information between the timing violation register and the i-th level register, where i is greater than or equal to 2 and less than or equal to N; until, if the sum of the first clock offset and the i-th clock offset is greater than or equal to the absolute value of the worst timing value of the timing violation register, or if i is equal to N.

5. The timing violation repair method according to claim 1, characterized in that, The first-level register includes a first-level fan-out register and a first-level fan-in register. Determining the first clock offset based on the worst-case timing value of the timing violation register, the worst-case timing value of the first-level register connected to the timing violation register, and the path value between the timing violation register and the first-level register includes: The first fan-out clock offset is determined based on the worst timing value of the timing violation register, the worst timing value of the first-level fan-out register, and the path value between the timing violation register and the first-level fan-out register. If the first fan-out clock offset is less than the absolute value of the worst timing value of the timing violation register, the first fan-out clock offset is determined based on the worst timing value of the timing violation register, the worst timing value of the first-stage fan-in register, and the path value between the timing violation register and the first-stage fan-in register.

6. The timing violation repair method according to claim 1, characterized in that, The first-level register includes a first-level fan-out register and a first-level fan-in register, and the second-level register includes a second-level fan-out register and a second-level fan-in register; determining the second clock offset based on the worst-case timing value of the timing violation register, the worst-case timing values ​​of the first-level register and the second-level register connected to the timing violation register, and the path information between the timing violation register and the second-level register includes: If the number of first-stage fan-out registers is greater than the number of first-stage fan-in registers, the second fan-in clock offset is determined based on the worst-case timing value of the timing violation register, the worst-case timing value of the first-stage fan-in register, the worst-case timing value of the second-stage fan-in register, and the path information between the timing violation register and the second-stage fan-in register; or... If the number of first-stage fan-out registers is less than the number of first-stage fan-in registers, the second fan-out clock offset is determined based on the worst timing value of the timing violation register, the worst timing value of the first-stage fan-out register, the worst timing value of the second-stage fan-out register, and the path information between the timing violation register and the second-stage fan-out register.

7. The timing violation repair method according to claim 6, characterized in that, The step of determining the second fan-in clock offset based on the worst-case timing value of the timing violation register, the worst-case timing value of the first-stage fan-in register, the worst-case timing value of the second-stage fan-in register, and the path information between the timing violation register and the second-stage fan-in register includes: Based on the path value between the first-level fan-in register and the timing violation register, and the worst timing value of the first-level fan-in register, determine the cumulative timing value between the second-level fan-in register and the timing violation register; The second fan-in clock offset is determined based on the cumulative timing value between the second-level fan-in register and the timing violation register, and the worst timing value of the second-level fan-in register.

8. The timing violation repair method according to claim 6, characterized in that, The step of determining the second fan-out clock offset based on the worst timing value of the timing violation register, the worst timing value of the first-stage fan-out register, the worst timing value of the second-stage fan-out register, and the path information between the timing violation register and the second-stage fan-out register includes: Based on the worst timing value of the timing violation register and the path value between the timing violation register and the first-level fan-out register, determine the cumulative timing value from the timing violation register to the second-level fan-out register; The second fan-out clock offset is determined based on the cumulative timing value between the timing violation register and the second-level fan-out register, and the worst timing value of the second-level fan-out register.

9. A timing violation repair device, characterized in that, include: An acquisition module is used to acquire the path values ​​between adjacent registers in the chip; wherein, the path values ​​between adjacent registers are the path margin between adjacent registers; The path information determination module is used to determine the path information related to the timing violation register based on the preset level N and the path value between the adjacent registers; wherein, the path information includes: the path information between the timing violation register and the N level registers before the timing violation register, and the path information between the timing violation register and the N level registers after the timing violation register; N is a positive integer greater than or equal to 2; The clock offset determination module is used to determine the clock offset for timing violation repair of the timing violation register based on the worst timing value of the timing violation register, the worst timing value of the multi-level registers connected to the timing violation register, and the path information related to the timing violation register; wherein, the worst timing value is the minimum path value among the path values ​​from each fan-in device of the register to the register. Specifically, based on the worst-case timing value of the timing violation register, the worst-case timing values ​​of the multi-level registers connected to the timing violation register, and the path information associated with the timing violation register, a clock offset for timing violation repair of the timing violation register is determined, including: The first clock offset is determined based on the worst timing value of the timing violation register, the worst timing value of the first-level register connected to the timing violation register, and the path value between the timing violation register and the first-level register. The second clock offset is determined based on the worst timing value of the timing violation register, the worst timing values ​​of the first-level register and the second-level register connected to the timing violation register, and the path information between the timing violation register and the second-level register.

10. An electronic device, characterized in that, include: Processor, memory, and bus; The processor and the memory communicate with each other via the bus; The memory stores program instructions that can be executed by the processor, and the processor can execute the method as described in any one of claims 1-8 by calling the program instructions.

11. A computer-readable storage medium, characterized in that, It stores a computer program, which, when executed by a processor, performs the method as described in any one of claims 1-8.

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