Pixel circuit and display panel

Abstract

The present application discloses a pixel circuit and a display panel. The pixel circuit includes a first light-emitting control transistor, a driving transistor, a second light-emitting control transistor and a light-emitting device. By constructing the source or drain of the driving transistor to be reset a greater number of times in a frame than the anode of the light-emitting device is reset a certain number of times in a frame, the number of times the anode of the light-emitting device is repeatedly charged can be reduced, thereby improving the uniformity at low grayscales.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel circuit and a display panel. Background Art

[0002] At present, in order to improve the flicker phenomenon at low refresh rates, the reset frequency of some nodes in pixel circuits is getting higher and higher. However, with the increase in reset frequency, the uniformity of display at low grayscales also deteriorates, which seriously affects the display quality. Summary of the invention

[0003] The present application provides a pixel circuit and a display panel to alleviate the technical problem that flicker and low grayscale uniformity are difficult to improve synchronously at a low refresh rate.

[0004] In a first aspect, the present application provides a pixel circuit, which includes a first light-emitting control transistor, a driving transistor, a second light-emitting control transistor and a light-emitting device, wherein one of the source or the drain of the first light-emitting control transistor is electrically connected to a first power line; one of the source or the drain of the driving transistor is electrically connected to the other of the source or the drain of the first light-emitting control transistor; one of the source or the drain of the second light-emitting control transistor is electrically connected to the other of the source or the drain of the driving transistor; the anode of the light-emitting device is electrically connected to the other of the source or the drain of the second light-emitting control transistor, and the cathode of the light-emitting device is electrically connected to the second power line; wherein the number of reset times of the source or the drain of the driving transistor in a frame is greater than the number of reset times of the anode of the light-emitting device in a frame.

[0005] In some embodiments, the pixel circuit further includes a first reset transistor and a bias transistor, one of the source or drain of the first reset transistor is electrically connected to the anode of the light-emitting device, the other of the source or drain of the first reset transistor is electrically connected to the first reset line, and the gate of the first reset transistor is electrically connected to the first control line; one of the source or drain of the bias transistor is electrically connected to the source or drain of the driving transistor, the other of the source or drain of the bias transistor is electrically connected to the first wiring, and the gate of the bias transistor is electrically connected to the second wiring; wherein, a frame includes at least one first time period and at least one second time period, in the first time period, the first reset transistor and the bias transistor are both turned on; in the second time period, the first reset transistor is turned off and the bias transistor is turned on.

[0006] In some embodiments, the bias transistor is a second reset transistor, the first wiring is a second reset line, and the second wiring is a second control line; one of the source or the drain of the second reset transistor is electrically connected to the source or the drain of the driving transistor, the other of the source or the drain of the second reset transistor is electrically connected to the second reset line, and the gate of the second reset transistor is electrically connected to the second control line; wherein the number of times the second reset transistor is turned on in one frame is greater than the number of times the first reset transistor is turned on in one frame.

[0007] In some embodiments, a frame includes a write frame and a hold frame, the second reset transistor is turned on a greater number of times in the write frame than the first reset transistor is turned on a greater number of times in the write frame, and the second reset transistor is turned on a greater number of times in the hold frame than the first reset transistor is turned on a greater number of times in the hold frame.

[0008] In some embodiments, the first control line is used to transmit a first control signal, the second control line is used to transmit a second control signal, and the second control signal has a greater number of pulses in a frame than the first control signal.

[0009] In some embodiments, a frame includes a write frame and a hold frame, the second control signal has a greater number of pulses in the write frame than the first control signal in the write frame, and the second control signal has a greater number of pulses in the hold frame than the first control signal in the hold frame.

[0010] In some embodiments, the bias transistor is a write transistor, the first wiring is a data line, and the second wiring is a third control line; one of the source or drain of the write transistor is electrically connected to the source or drain of the drive transistor, the other of the source or drain of the write transistor is electrically connected to the data line, and the gate of the write transistor is electrically connected to the third control line; wherein the number of times the write transistor is turned on in a frame is greater than the number of times the first reset transistor is turned on in a frame.

[0011] In some embodiments, a frame includes a write frame and a hold frame, the write transistor is turned on a greater number of times in the write frame than the first reset transistor is turned on a greater number of times in the write frame, and the write transistor is turned on a greater number of times in the hold frame than the first reset transistor is turned on a greater number of times in the hold frame.

[0012] In some embodiments, the first control line is used to transmit a first control signal, the third control line is used to transmit a third control signal, and the third control signal has a greater number of pulses in a frame than the first control signal.

[0013] In some embodiments, the data line is used to transmit a data signal, a frame includes a write frame and a hold frame, the number of pulses of the third control signal in the write frame is greater than the number of pulses of the first control signal in the write frame, and the data signal has at least one pulse in the write frame; the number of pulses of the third control signal in the hold frame is greater than the number of pulses of the first control signal in the hold frame, and the number of pulses of the data signal in the hold frame is zero.

[0014] In a second aspect, the present application provides a display panel, which includes a plurality of pixel circuits according to at least one of the above-mentioned embodiments and at least two gate drive circuits, wherein one gate drive circuit outputs a first drive signal to control the source or drain of the drive transistor for reset; wherein the other gate drive circuit outputs a second drive signal to control the anode of the light-emitting device for reset; wherein the frequency of the first drive signal is higher than the frequency of the second drive signal.

[0015] The pixel circuit and display panel provided by the present application can reduce the drift amplitude of the threshold voltage of the driving transistor by resetting the potential of the source or drain of the driving transistor, thereby improving the flicker phenomenon under low refresh frequency; at the same time, the number of times the source or drain of the driving transistor is reset in one frame is greater than the number of times the anode of the light-emitting device is reset in one frame, which can reduce the number of times the anode of the light-emitting device is reset, and can reduce the number of times the anode of the light-emitting device is repeatedly charged, thereby improving the problem of insufficient charging of the anode potential of the light-emitting device, thereby improving the uniformity under low grayscale. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0017] Figure 1 It is a structural schematic diagram of a pixel circuit in the related art.

[0018] Figure 2 for Figure 1 Timing diagram of the pixel circuit shown.

[0019] Figure 3 for Figure 1 A schematic diagram of the structure of a display panel where a pixel circuit is located is shown.

[0020] Figure 4 A first structural schematic diagram of a pixel circuit provided in an embodiment of the present application.

[0021] Figure 5 for Figure 4 Timing diagram of the pixel circuit shown.

[0022] Figure 6 for Figure 4 A schematic diagram of the structure of a display panel where a pixel circuit is located is shown.

[0023] Figure 7 A second structural schematic diagram of a pixel circuit provided in an embodiment of the present application.

[0024] Figure 8 for Figure 7 Timing diagram of the pixel circuit shown.

[0025] Fig. 9 for Figure 7 A schematic diagram of the structure of a display panel where a pixel circuit is located is shown.

[0026] Fig.10 A third structural schematic diagram of the pixel circuit provided in an embodiment of the present application.

[0027] Fig.11 for Fig.10 Timing diagram of the pixel circuit shown.

[0028] Fig.12 for Fig.10 A schematic diagram of the structure of a display panel where a pixel circuit is located is shown. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0030] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. Therefore, the features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0031] See also Figures 1 to 3 , Figure 1 It is a structural schematic diagram of a pixel circuit in the related art. Figure 2 for Figure 1 Timing diagram of the pixel circuit shown.

[0032] Most thin-film transistors in self-luminous pixel circuits use a single low-temperature polysilicon thin-film transistor (LTPS TFT) or a mixed low-temperature polysilicon thin-film transistor and metal oxide thin-film transistor (LTPO TFT) to drive the light-emitting device D1. When driving at a low refresh rate (40 Hz or less), the common design is to apply a high-frequency bias voltage to the driving transistor T1 through the second reset transistor T8 and reset the anode of the light-emitting device D1 through the first reset transistor T7, so as to improve flicker at low frequencies. Specifically, Figure 1 The driving process of the pixel circuit shown in one frame is as follows Figure 2 As shown, the driving process is as follows:

[0033] 1) Write frame

[0034] Phase ①: the control signal EM1 is at a high level, turning off the first light-emitting control transistor T5 and the second light-emitting control transistor T6; the control signal EM2 is at a low level, turning on the third reset transistor T4, and the second initialization signal VI1 resets the gate potential of the driving transistor T1.

[0035] Phase ②: the scan signal Scan

n

[0036] Phase ③: The control signal EM4 is at a low level, the first reset transistor T7 and the second reset transistor T8 are turned on, the first initialization signal VI2 resets the anode of the light-emitting device D1, and the bias voltage signal V-bias is applied to the source and drain of the driving transistor T1 for reset, which can improve the hysteresis of the driving transistor T1 and thus improve the flicker at low frequency.

[0037] Phase ④: the control signal EM1 is at a low level, the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on, and the light emitting device D1 emits light.

[0038] 2) Keep the frame

[0039] Stage ⑤: The control signal EM1 is at a high level, turning off the first light-emitting control transistor T5 and the second light-emitting control transistor T6; the control signal EM4 is at a low level, turning on the first reset transistor T7 and the second reset transistor T8, and the first initialization signal VI2 resets the anode of the light-emitting device D1, and applies the bias voltage signal V-bias to the source and drain of the driving transistor T1 for reset, which can improve the hysteresis of the driving transistor T1, and further improve the flicker at low frequency.

[0040] It should be noted that the higher the frequency of the control signal EM4, the better the improvement effect on the flicker. Since the gate of the first reset transistor T7 and the gate of the second reset transistor T8 share the control signal EM4 and switch synchronously, as the frequency of the control signal EM4 increases, the anode reset frequency of the light-emitting device D1 also increases, which will deteriorate the display uniformity of the pixel circuit or the display panel at low grayscale and reduce the display quality.

[0041] Among them, the inventors have found through research that the display uniformity at low grayscale is strongly related to the charging process of the anode of the light-emitting device D1. The working process of the light-emitting device D1 at low grayscale is: the anode of the light-emitting device D1 is first reset to a low voltage, and then slowly charged to the working voltage or the start-up voltage. Such a charging process will affect the display uniformity at low grayscale. If the anode reset frequency of the light-emitting device D1 is too high, the light-emitting device D1 will be frequently in the reset-charging process, which will cause the anode of the light-emitting device D1 to be insufficiently charged, deteriorating the display uniformity at low grayscale.

[0042] Figure 3 for Figure 1 The structure diagram of the display panel where the pixel circuit is located is shown. The display panel includes a pixel circuit that provides red (R) light emission, a pixel circuit that provides green (G) light emission, and a pixel circuit that provides blue (B) light emission in the display area, and these pixel circuits can be distributed in the display area in an array. The display panel also includes multiple gate drive circuits in the non-display area to provide various signals required for each pixel circuit.

[0043] For example, the first gate driving circuit, the second gate driving circuit, the third gate driving circuit, and the fourth gate driving circuit can respectively provide control signals EM1, EM2, EM3, and EM4 to each pixel circuit in sequence. The fifth gate driving circuit and the sixth gate driving circuit distributed on both sides of the display area can provide the same scan signal Scan

n

n

[0044] In view of the technical problem mentioned above that flicker and low grayscale uniformity are difficult to improve simultaneously under low refresh rate, this embodiment provides a pixel circuit, see Figures 4 to 12 ,like Figure 4 , Figure 7 as well as Fig.10As shown, the pixel circuit includes a first light-emitting control transistor T5, a driving transistor T1, a second light-emitting control transistor T6 and a light-emitting device D1, wherein one of the source or the drain of the first light-emitting control transistor T5 is electrically connected to the first power line; one of the source or the drain of the driving transistor T1 is electrically connected to the other of the source or the drain of the first light-emitting control transistor T5; one of the source or the drain of the second light-emitting control transistor T6 is electrically connected to the other of the source or the drain of the driving transistor T1; the anode of the light-emitting device D1 is electrically connected to the other of the source or the drain of the second light-emitting control transistor T6, and the cathode of the light-emitting device D1 is electrically connected to the second power line; wherein the number of reset times of the source or the drain of the driving transistor T1 in one frame is greater than the number of reset times of the anode of the light-emitting device D1 in one frame.

[0045] It can be understood that the pixel circuit provided in this embodiment can reduce the drift amplitude of the threshold voltage of the driving transistor T1 by resetting the potential of the source or drain of the driving transistor T1, thereby improving the flicker phenomenon under low refresh frequency; at the same time, the number of times the source or drain of the driving transistor T1 is reset in one frame is greater than the number of times the anode of the light-emitting device D1 is reset in one frame, which can reduce the number of times the anode of the light-emitting device D1 is reset, and can reduce the number of times the anode of the light-emitting device D1 is repeatedly charged, thereby improving the problem of insufficient charging of the anode potential of the light-emitting device D1, thereby improving the uniformity under low gray scale.

[0046] It should be noted that the gate of the first light-emitting control transistor T5 and the gate of the second light-emitting control transistor T6 can share the same control line, which is used to transmit the control signal EM1; the gate of the first light-emitting control transistor T5 and the gate of the second light-emitting control transistor T6 can also each use a separate control line.

[0047] The first power line is used to transmit a positive power signal VDD, and the second power line is used to transmit a negative power signal VSS. The potential of the positive power signal VDD is higher than that of the negative power signal VSS.

[0048] The light emitting device D1 may be an organic light emitting diode, a micro light emitting diode, a mini light emitting diode or a quantum dot light emitting diode.

[0049] In one embodiment, if Figure 4 , Figure 7As shown, the pixel circuit also includes a first reset transistor T7 and a bias transistor, one of the source or drain of the first reset transistor T7 is electrically connected to the anode of the light emitting device D1, the other of the source or drain of the first reset transistor T7 is electrically connected to the first reset line, and the gate of the first reset transistor T7 is electrically connected to the first control line; one of the source or drain of the bias transistor is electrically connected to the source or drain of the driving transistor T1, the other of the source or drain of the bias transistor is electrically connected to the first wiring, and the gate of the bias transistor is electrically connected to the second wiring; wherein, one frame includes at least one first time period and at least one second time period, in the first time period, the first reset transistor T7 and the bias transistor are both turned on; in the second time period, the first reset transistor T7 is turned off, and the bias transistor is turned on.

[0050] It can be understood that the pixel circuit provided in this embodiment uses different control lines to separately control the first reset transistor T7 and the bias transistor, so that the first reset transistor T7 and the bias transistor can be controlled to be turned on in the first time period, and the first reset transistor T7 can be controlled to be turned off and the bias transistor can be turned on in the second time period, thereby constructing a structure in which the number of reset times of the source or drain of the driving transistor T1 in one frame is greater than the number of reset times of the anode of the light-emitting device D1 in one frame, which can reduce the number of reset times of the anode of the light-emitting device D1, and can reduce the number of times the anode of the light-emitting device D1 is repeatedly charged, thereby improving the problem of insufficient charging of the anode potential of the light-emitting device D1, and thereby improving the uniformity under low grayscale.

[0051] It should be noted that the first period can be Figure 5 or Figure 8 In stage ③, the second period can be Figure 5 Stage ⑤; the first period can be as follows Fig.11 In stage ② or stage ⑤, the second period can be Fig.11 Stage ④.

[0052] In one embodiment, if Figure 4 , Figure 7 As shown, the bias transistor is a second reset transistor T8, the first wiring is a second reset line, and the second wiring is a second control line; one of the source or drain of the second reset transistor T8 is electrically connected to the source or drain of the driving transistor T1, the other of the source or drain of the second reset transistor T8 is electrically connected to the second reset line, and the gate of the second reset transistor T8 is electrically connected to the second control line.

[0053] It should be noted that in Figure 4In the embodiment, the first reset line is used to transmit the first initialization signal VI2. The first control line is used to transmit the control signal EM4. The second reset line is used to transmit the bias voltage signal V-bias to reset the source or drain of the driving transistor T1. The second control line is used to transmit the control signal EM5.

[0054] It can be understood that the pixel circuit provided in this embodiment, by adopting different control lines to separately control the first reset transistor T7 and the second reset transistor T8, can be constructed so that the number of times the source or drain of the driving transistor T1 is reset in one frame is greater than the number of times the anode of the light-emitting device D1 is reset in one frame, which can reduce the number of times the anode of the light-emitting device D1 is reset, and can reduce the number of times the anode of the light-emitting device D1 is repeatedly charged, thereby improving the problem of insufficient charging of the anode potential of the light-emitting device D1, thereby improving the uniformity under low grayscale.

[0055] In one embodiment, if Figure 4 , Figure 7 as well as Fig.10 As shown, the pixel circuit further includes a storage capacitor Cst, one end of the storage capacitor Cst is electrically connected to the gate of the driving transistor T1, and the other end of the storage capacitor Cst is electrically connected to the first power line.

[0056] In one embodiment, if Figure 4 , Figure 7 as well as Fig.10 As shown, the pixel circuit also includes a third reset transistor T4, one of the source or drain of the third reset transistor T4 is electrically connected to the gate of the driving transistor T1, the other of the source or drain of the third reset transistor T4 is electrically connected to the third reset line, and the gate of the third reset transistor T4 is electrically connected to the fifth control line.

[0057] It should be noted that the third reset line is used to transmit the second initialization signal VI1. Figure 4 Used to transmit control signal EM2.

[0058] The third reset transistor T4 may be formed by two low-temperature polysilicon thin film transistors connected in series, which can improve the dynamic performance and reduce the leakage current of the driving transistor T1.

[0059] In one embodiment, if Figure 4 , Figure 7 as well as Fig.10As shown, the pixel circuit also includes a compensation transistor T3, one of the source or drain of the compensation transistor T3 is electrically connected to the gate of the driving transistor T1, the other of the source or drain of the compensation transistor T3 is electrically connected to the other of the source or drain of the driving transistor T1, and the gate of the compensation transistor T3 is electrically connected to the fourth control line.

[0060] It should be noted that the fourth control line is Figure 4 Used to transmit control signal EM3.

[0061] The compensation transistor T3 may be formed by two low-temperature polysilicon thin film transistors connected in series, which can improve the dynamic performance and reduce the leakage current of the driving transistor T1.

[0062] In one embodiment, if Figure 4 , Figure 7 As shown, the pixel circuit also includes a write transistor T2, one of the source or drain of the write transistor T2 is electrically connected to one of the source or drain of the drive transistor T1, the other of the source or drain of the write transistor T2 is electrically connected to the data line, and the gate of the write transistor T2 is electrically connected to the third control line.

[0063] It should be noted that the third control line is Figure 4 Used to transmit the scan signal Scan.

[0064] Figure 4 The working process of the pixel circuit shown in one frame is as follows Figure 5 As shown, it includes the following driving processes:

[0065] 1) Write frame

[0066] Phase ①: the control signal EM1 is at a high level, turning off the first light-emitting control transistor T5 and the second light-emitting control transistor T6; the control signal EM2 is at a low level, turning on the third reset transistor T4, and the second initialization signal VI1 resets the gate of the driving transistor T1.

[0067] Phase ②: the scan signal Scan is at a low level, turning on the write transistor T2; the control signal EM3 is at a low level, turning on the compensation transistor T3, and the data signal Data is written to the gate of the drive transistor T1 and the storage capacitor Cst.

[0068] Phase ③: The control signal EM4 and the control signal EM5 are both at a low level, the first reset transistor T7 and the second reset transistor T8 are turned on, the first initialization signal VI2 resets the anode of the light-emitting device D1, and the bias voltage signal V-bias is applied to the source and drain of the driving transistor T1, which improves the hysteresis of the driving transistor T1 and also improves the flicker at low frequency.

[0069] Phase ④: the control signal EM1 is at a low level, the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on, and the light emitting device D1 emits light.

[0070] Phase ⑤: the control signal EM5 is at a low level, the second reset transistor T8 is turned on, and the bias voltage signal V-bias resets the source and drain of the driving transistor T1.

[0071] 2) Keep the frame

[0072] Repeat the steps ③, ④, and ⑤ in the writing frame.

[0073] Specifically, the frequency of the control signal EM5 may be twice the frequency of the control signal EM4. For example, the frequency of the control signal EM5 may be 240 Hz, and the frequency of the control signal EM4 may be 120 Hz.

[0074] Figure 6 for Figure 4 The structure diagram of the display panel where the pixel circuit is located is shown, and the display panel includes a pixel circuit that provides red (R) light emission, a pixel circuit that provides green (G) light emission, and a pixel circuit that provides blue (B) light emission in the display area, and these pixel circuits can be distributed in the display area in an array. The display panel also includes multiple gate drive circuits in the non-display area to provide various signals required by each pixel circuit.

[0075] For example, the first gate driving circuit, the second gate driving circuit, the third gate driving circuit, the fourth gate driving circuit and the fifth gate driving circuit can respectively provide control signals EM1, EM2, EM3, EM4 and EM5 to each pixel circuit in sequence. The sixth gate driving circuit and the seventh gate driving circuit distributed on both sides of the display area can provide the same scan signal Scan to the same scan line to improve the driving capability of the scan signal Scan through bilateral driving.

[0076] and Figure 4 Compared to the pixel circuit shown in Figure 7 In the embodiment, the gate of the write transistor T2 and the gate of the compensation transistor T3 share the same third control line. The first control line is used to transmit the control signal EM2. The second control line is used to transmit the control signal EM3. The third control line is used to transmit the scan signal Scan [n]. The fifth control line is used to transmit the scan signal Scan [n-1].

[0077] Figure 7 The working process of the pixel circuit shown in one frame is as follows Figure 8 As shown, it includes the following driving processes:

[0078] 1) Write frame

[0079] Phase ①: the control signal EM1 is at a high level, turning off the first light-emitting control transistor T5 and the second light-emitting control transistor T6; the scan signal Scan[n-1] is at a low level, turning on the third reset transistor T4, and the second initialization signal VI1 resets the gate of the driving transistor T1.

[0080] Phase ②: The scan signal Scan

n

[0081] Phase ③: The control signal EM2 and the control signal EM3 are both at a low level, the first reset transistor T7 and the second reset transistor T8 are turned on, the first initialization signal VI2 resets the anode of the light-emitting device D1, and the bias voltage signal V-bias is applied to the source and drain of the driving transistor T1, which improves the hysteresis of the driving transistor T1 and also improves the flicker at low frequency.

[0082] Phase ④: the control signal EM1 is at a low level, the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on, and the light emitting device D1 emits light.

[0083] Phase ⑤: the control signal EM3 is at a low level, the second reset transistor T8 is turned on, and the bias voltage signal V-bias resets the source and drain of the driving transistor T1.

[0084] 2) Keep the frame

[0085] Repeat the steps ③, ④, and ⑤ in the writing frame.

[0086] Specifically, the frequency of the control signal EM3 may be twice the frequency of the control signal EM2. For example, the frequency of the control signal EM3 may be 240 Hz, and the frequency of the control signal EM2 may be 120 Hz.

[0087] Fig. 9 for Figure 7 The structure diagram of the display panel where the pixel circuit is located is shown, and the display panel includes a pixel circuit that provides red (R) light emission, a pixel circuit that provides green (G) light emission, and a pixel circuit that provides blue (B) light emission in the display area, and these pixel circuits can be distributed in the display area in an array. The display panel also includes multiple gate drive circuits in the non-display area to provide various signals required by each pixel circuit.

[0088] For example, the first gate driving circuit, the second gate driving circuit, and the third gate driving circuit can respectively provide control signals EM1, EM2, and EM3 to each pixel circuit in sequence. The fourth gate driving circuit and the fifth gate driving circuit distributed on both sides of the display area can provide the same scan signal Scan [n] and scan signal Scan [n-1] to the same scan line, so as to improve the driving capability of the two scan signals through bilateral driving.

[0089] It can be understood that since the scan signal Scan [n] and the scan signal Scan [n-1] can be provided by the fourth gate drive circuit and the fifth gate drive circuit without the need for other gate drive circuits, the number of gate drive circuits is reduced, which is conducive to achieving a narrower border.

[0090] At the same time, since the gate of the compensation transistor T3 and the gate of the write transistor T2 share the same third control line, the number of wirings or the wiring area in the display area is saved, which is beneficial to improving the density of the pixel circuit or the aperture ratio of the display panel.

[0091] In one embodiment, see Figures 4 to 9 , the number of times the second reset transistor T8 is turned on in one frame is greater than the number of times the first reset transistor T7 is turned on in one frame.

[0092] It should be noted that, in this embodiment, the first reset transistor T7 can reset the anode of the light emitting device D1 once each time it is turned on, and the second reset transistor T8 can reset the source and / or drain of the driving transistor T1 once each time it is turned on.

[0093] In one embodiment, a frame includes a write frame and a hold frame, the second reset transistor T8 is turned on a greater number of times in the write frame than the first reset transistor T7 is turned on a greater number of times in the write frame, and the second reset transistor T8 is turned on a greater number of times in the hold frame than the first reset transistor T7 is turned on a greater number of times in the hold frame.

[0094] It should be noted that in this embodiment, keeping the first reset transistor T7 turned on less times in the frame can reduce the number of reset times of the anode of the light-emitting device D1 and the number of charge and discharge times of the anode of the light-emitting device D1, which is beneficial to improving the display uniformity under low grayscale.

[0095] In one embodiment, the first control line is used to transmit a first control signal, the second control line is used to transmit a second control signal, and the number of pulses of the second control signal in one frame is greater than the number of pulses of the first control signal in one frame.

[0096] It should be noted that, in this embodiment, the first control signal can be Figures 4 to 6 The control signal EM4 or Figures 7 to 9 The second control signal can be Figures 4 to 6 The control signal EM5 or Figures 7 to 9 The control signal EM3 in.

[0097] In one embodiment, a frame includes a write frame and a hold frame, the number of pulses of the second control signal in the write frame is greater than the number of pulses of the first control signal in the write frame, and the number of pulses of the second control signal in the hold frame is greater than the number of pulses of the first control signal in the hold frame.

[0098] It should be noted that each pulse of the first control signal can turn on the first reset transistor T7 once to reset the anode potential of the light emitting device D1. Each pulse of the second control signal can turn on the second reset transistor T8 once to reset the source or drain of the driving transistor T1.

[0099] In one embodiment, see Figures 10 to 12 ,like Fig.10 , Fig.11 As shown, the bias transistor is a write transistor T2, the first wiring is a data line, and the second wiring is a third control line; one of the source or drain of the write transistor T2 is electrically connected to the source or drain of the drive transistor T1, the other of the source or drain of the write transistor T2 is electrically connected to the data line, and the gate of the write transistor T2 is electrically connected to the third control line; wherein the number of times the write transistor T2 is turned on in one frame is greater than the number of times the first reset transistor T7 is turned on in one frame.

[0100] It should be noted that it is understandable that the pixel circuit provided in this embodiment can be constructed so that the number of times the source or drain of the driving transistor T1 is reset in one frame is greater than the number of times the anode of the light-emitting device D1 is reset in one frame by separately controlling the first reset transistor T7 and the write transistor T2, thereby reducing the number of times the anode of the light-emitting device D1 is reset, and reducing the number of times the anode of the light-emitting device D1 is repeatedly charged, thereby improving the problem of insufficient charging of the anode potential of the light-emitting device D1, and thereby improving the display uniformity under low grayscale.

[0101] Furthermore, this embodiment reuses the write transistor T2 as the source and / or drain of the drive transistor T1 for resetting, which not only reduces the number of transistors required for the pixel circuit, but also reduces the area occupied by the pixel circuit, which is beneficial to improving the density of the pixel circuit in the display area.

[0102] and Figure 7 Compared to the pixel circuit shown in Fig.10In the embodiment, the first control line is used to transmit the control signal EM4. The third control line is used to transmit the scan signal Scan. The fourth control line is used to transmit the control signal EM3. The fifth control line is used to transmit the control signal EM2.

[0103] Fig.10 The working process of the pixel circuit shown in one frame is as follows Fig.11 As shown, it includes the following driving processes:

[0104] 1) Write frame

[0105] Phase ①: the control signal EM1 is at a high level, turning off the first light-emitting control transistor T5 and the second light-emitting control transistor T6; the control signal EM2 is at a low level, turning on the third reset transistor T4, and the second initialization signal VI1 resets the gate of the driving transistor T1.

[0106] Phase ②: The control signal EM4 is at a low level, the first reset transistor T7 is turned on, and the first initialization signal VI2 resets the anode of the light-emitting device D1; the scan signal Scan is at a low level, the write transistor T2 is turned on, the control signal EM3 is at a low level, the compensation transistor T3 is turned on, and the data signal Data is written to the gate of the driving transistor T1 and the storage capacitor Cst.

[0107] Phase ③: the control signal EM1 is at a low level, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the light-emitting device D1 emits light.

[0108] Phase ④: the control signal EM1 is at a high level, turning off the first light-emitting control transistor T5 and the second light-emitting control transistor T6; the scan signal Scan is at a low level, turning on the second reset transistor T8, and the bias voltage signal V-bias resets the source and drain of the driving transistor T1.

[0109] Phase ⑤: The control signal EM4 is at a low level, the first reset transistor T7 is turned on, and the first initialization signal VI2 resets the anode of the light-emitting device D1; the scan signal Scan is at a low level, the second reset transistor T8 is turned on, and the bias voltage signal V-bias resets the source and drain of the driving transistor T1.

[0110] 2) Keep the frame

[0111] Repeat the steps ③, ④, and ⑤ in the writing frame.

[0112] Specifically, the frequency of the scan signal Scan may be twice the frequency of the control signal EM4. For example, the frequency of the scan signal Scan may be 240 Hz, and the frequency of the control signal EM4 may be 120 Hz.

[0113] Fig.12 for Fig.10 The structure diagram of the display panel where the pixel circuit is located is shown, and the display panel includes a pixel circuit that provides red (R) light emission, a pixel circuit that provides green (G) light emission, and a pixel circuit that provides blue (B) light emission in the display area, and these pixel circuits can be distributed in the display area in an array. The display panel also includes multiple gate drive circuits in the non-display area to provide various signals required by each pixel circuit.

[0114] For example, the first gate driving circuit, the second gate driving circuit, the third gate driving circuit and the fourth gate driving circuit can respectively provide control signals EM1, EM2, EM3 and EM4 to each pixel circuit in sequence. The fifth gate driving circuit and the sixth gate driving circuit distributed on both sides of the display area can provide the same scan signal Scan to the same scan line to improve the driving capability of the two scan signals through bilateral driving.

[0115] In one embodiment, see Figures 10 to 12 , a frame includes a write frame and a hold frame, the write transistor T2 is turned on a greater number of times in the write frame than the first reset transistor T7 is turned on a greater number of times in the write frame, and the write transistor T2 is turned on a greater number of times in the hold frame than the first reset transistor T7 is turned on a greater number of times in the hold frame.

[0116] It should be noted that the first conduction of the write transistor T2 in the write frame is to write the data signal Data to the gate of the drive transistor T1, and the second conduction of the write transistor T2 in the write frame is to use the low potential of the data signal Data to reset the source and drain of the drive transistor T1. In the hold frame, each conduction of the write transistor T2 is to reset the source and drain of the drive transistor T1.

[0117] In one embodiment, the first control line is used to transmit a first control signal, the third control line is used to transmit a third control signal, and the number of pulses of the third control signal in one frame is greater than the number of pulses of the first control signal in one frame.

[0118] It needs to be explained that if Figures 10 to 12 As shown, the first control signal may be a control signal EM4. The third control signal may be a scan signal Scan.

[0119] In one embodiment, the data line is used to transmit a data signal Data, the number of pulses of the third control signal in a write frame is greater than the number of pulses of the first control signal in the write frame, and the data signal Data has at least one pulse in the write frame; the number of pulses of the third control signal in a hold frame is greater than the number of pulses of the first control signal in the hold frame, and the number of pulses of the data signal Data in the hold frame is zero.

[0120] It should be noted that, in this embodiment, each pulse in the first control signal can turn on the first reset transistor T7 once, and each pulse in the third control signal can turn on the write transistor T2 once.

[0121] It should be noted that at least one of the first reset transistor T7, the second reset transistor T8, the third reset transistor T4, the compensation transistor T3, the write transistor T2, the driving transistor T1, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 can be a low-temperature polycrystalline silicon thin film transistor, and / or can also be an oxide thin film transistor.

[0122] In one of the embodiments, the present embodiment provides a display panel, which includes multiple pixel circuits of at least one of the above-mentioned embodiments and at least two gate driving circuits, wherein one gate driving circuit outputs a first driving signal to control the source or drain of the driving transistor T1 to reset; wherein the other gate driving circuit outputs a second driving signal to control the anode of the light-emitting device D1 to reset; wherein the frequency of the first driving signal is higher than the frequency of the second driving signal.

[0123] It can be understood that since the display panel provided in this embodiment includes multiple pixel circuits in at least one of the above-mentioned embodiments, it is also possible to reduce the drift amplitude of the threshold voltage of the driving transistor T1 by resetting the potential of the source or drain of the driving transistor T1, thereby improving the flicker phenomenon under low refresh frequency; at the same time, the number of times the source or drain of the driving transistor T1 is reset in one frame is greater than the number of times the anode of the light-emitting device D1 is reset in one frame, which can reduce the number of times the anode of the light-emitting device D1 is reset, and can reduce the number of times the anode of the light-emitting device D1 is repeatedly charged, thereby improving the problem of insufficient charging of the anode potential of the light-emitting device D1, thereby improving the uniformity under low grayscale.

[0124] It should be noted that the first driving signal can be Figure 4 , Figure 5 The control signal EM5 in the second driving signal can be Figure 4 , Figure 5 , Figure 6 Alternatively, the first drive signal may be Figure 7 , Figure 8 The control signal EM3 in the second driving signal can be Figure 7 , Figure 8 , Fig. 9 Alternatively, the first drive signal may be Fig.10 , Fig.11 , Fig.12 The scanning signal Scan in the second driving signal can be Fig.10 , Fig.11 , Fig.12 The control signal EM4 in.

[0125] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0126] The pixel circuit and display panel provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A pixel circuit, characterized in that: The pixel circuit comprises: a first light emission control transistor, wherein one of a source or a drain of the first light emission control transistor is electrically connected to a first power line; a driving transistor, wherein one of a source electrode or a drain electrode of the driving transistor is electrically connected to the other of a source electrode or a drain electrode of the first light emission control transistor; a second light emission control transistor, wherein one of a source electrode or a drain electrode of the second light emission control transistor is electrically connected to the other of a source electrode or a drain electrode of the driving transistor; a light emitting device, wherein an anode of the light emitting device is electrically connected to the other of a source or a drain of the second light emitting control transistor, and a cathode of the light emitting device is electrically connected to a second power line; a first reset transistor, wherein one of a source or a drain of the first reset transistor is electrically connected to an anode of the light emitting device, the other of the source or the drain of the first reset transistor is electrically connected to a first reset line, and a gate of the first reset transistor is electrically connected to a first control line; and a bias transistor, wherein one of a source or a drain of the bias transistor is electrically connected to the source or the drain of the drive transistor, the other of the source or the drain of the bias transistor is electrically connected to the first wiring, and the gate of the bias transistor is electrically connected to the second wiring; The number of times the source or drain of the driving transistor is reset in one frame is greater than the number of times the anode of the light-emitting device is reset in one frame; the one frame includes at least one first time period and at least one second time period, in the first time period, the first reset transistor and the bias transistor are both turned on; in the second time period, the first reset transistor is turned off, and the bias transistor is turned on; Wherein, when the bias transistor is a second reset transistor, the frame includes a write frame and a hold frame, the second reset transistor is turned on a greater number of times in the write frame than the first reset transistor is turned on a greater number of times in the write frame, and the second reset transistor is turned on a greater number of times in the hold frame than the first reset transistor is turned on a greater number of times in the hold frame.

2. The pixel circuit according to claim 1, characterized in that: The first wiring is a second reset line, and the second wiring is a second control line; one of the source or the drain of the second reset transistor is electrically connected to the source or the drain of the drive transistor, the other of the source or the drain of the second reset transistor is electrically connected to the second reset line, and the gate of the second reset transistor is electrically connected to the second control line; The number of times the second reset transistor is turned on in one frame is greater than the number of times the first reset transistor is turned on in one frame.

3. The pixel circuit according to claim 2, characterized in that: The first control line is used to transmit a first control signal, and the second control line is used to transmit a second control signal. The second control signal has a greater number of pulses in one frame than the first control signal.

4. The pixel circuit according to claim 3, characterized in that: The frame includes a write frame and a hold frame, the number of pulses of the second control signal in the write frame is greater than the number of pulses of the first control signal in the write frame, and the number of pulses of the second control signal in the hold frame is greater than the number of pulses of the first control signal in the hold frame.

5. The pixel circuit according to claim 1, characterized in that: When the bias transistor is a write transistor, the first wiring is a data line, and the second wiring is a third control line; one of the source or the drain of the write transistor is electrically connected to the source or the drain of the drive transistor, the other of the source or the drain of the write transistor is electrically connected to the data line, and the gate of the write transistor is electrically connected to the third control line; The number of times the write transistor is turned on in one frame is greater than the number of times the first reset transistor is turned on in one frame.

6. The pixel circuit according to claim 5, characterized in that: The frame includes a write frame and a hold frame, the write transistor is turned on a greater number of times in the write frame than the first reset transistor is turned on a greater number of times in the write frame, and the write transistor is turned on a greater number of times in the hold frame than the first reset transistor is turned on a greater number of times in the hold frame.

7. The pixel circuit according to claim 5, characterized in that: The first control line is used to transmit a first control signal, and the third control line is used to transmit a third control signal. The third control signal has a greater number of pulses in one frame than the first control signal.

8. The pixel circuit according to claim 7, characterized in that: The data line is used to transmit a data signal, the frame includes a write frame and a hold frame, the number of pulses of the third control signal in the write frame is greater than the number of pulses of the first control signal in the write frame, and the data signal has at least one pulse in the write frame; The number of pulses of the third control signal in the hold frame is greater than the number of pulses of the first control signal in the hold frame, and the number of pulses of the data signal in the hold frame is zero.

9. A display panel, characterized in that: The display panel comprises: A plurality of pixel circuits according to any one of claims 1 to 8; and At least two gate drive circuits, one of which outputs a first drive signal to control the source or drain of the drive transistor to reset; and the other gate drive circuit outputs a second drive signal to control the anode of the light emitting device to reset; Wherein, the frequency of the first driving signal is higher than the frequency of the second driving signal.

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