Driver board and display panel

Abstract

This application discloses a driving substrate and a display panel. In this embodiment, the output electrode is used to electrically connect to a light-emitting device. The active layer includes a semiconductor portion, a first conductive portion, and a second conductive portion. The first conductive portion is connected to the side of the semiconductor portion near the output electrode, and the second conductive portion is connected to the side of the semiconductor portion away from the output electrode. The first conductive portion is connected to the output electrode, and the surface resistivity of the first conductive portion is less than that of the second conductive portion. A gate is disposed overlapping the semiconductor portion. An input electrode is connected to the second conductive portion. The input electrode, output electrode, active layer, and gate are used to form a thin-film transistor. In this application embodiment, because the surface resistivity of the first conductive portion is less than that of the second conductive portion, the voltage drop of the active layer near the output electrode is reduced, thereby reducing the influence of hot carriers on the threshold voltage.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a driving substrate and a display panel. Background Technology

[0002] Mini / Micro LED (MLED) display technology has entered a phase of accelerated development in the past two years and can be used in small to medium-sized high-value-added display applications. Compared to OLED screens, MLED displays offer superior performance in terms of cost, contrast, high brightness, and slim profile. Backplane technology is a key technology in MLED displays.

[0003] In the process of researching and practicing existing technologies, the inventors of this application discovered that because light-emitting diode (LED) devices require high current, as the driving voltage of the thin-film transistor increases, a high electric field is generated between the channel region and the drain region, exciting hot carriers. Due to the influence of hot carriers, the threshold voltage (Vth) of the driving thin-film transistor will change. Summary of the Invention

[0004] This application provides a driving substrate and a display panel that can reduce the risk of threshold voltage drift in thin-film transistors.

[0005] This application provides a driving substrate, which includes:

[0006] substrate;

[0007] A first metal layer, the first metal layer including an output electrode, the output electrode being used for electrically connecting to a light-emitting device;

[0008] A first insulating layer is disposed on the first metal layer and covers the substrate;

[0009] An active layer is disposed on the first insulating layer. The active layer includes a semiconductor portion, a first conductive portion, and a second conductive portion. The first conductive portion is connected to the side of the semiconductor portion near the output electrode, and the second conductive portion is connected to the side of the semiconductor portion away from the output electrode. The first conductive portion is connected to the output electrode, and the surface resistivity of the first conductive portion is less than the surface resistivity of the second conductive portion.

[0010] A second insulating layer is disposed on the semiconductor portion;

[0011] At least one gate, wherein one of the gates is disposed on the second insulating layer and overlaps with the semiconductor portion; and

[0012] The second metal layer includes an input electrode connected to the second conductive portion, and the input electrode, the output electrode, the active layer, and the gate are used to form a thin-film transistor.

[0013] Optionally, in some embodiments of this application, the concentration of doped ions in the first conductive portion is greater than the concentration of doped ions in the second conductive portion.

[0014] Optionally, in some embodiments of this application, the material of the first conductive portion includes a metal oxide and the doped ions, wherein the doped ions are doped into the metal oxide, and the material of the second conductive portion includes at least the metal oxide.

[0015] Optionally, in some embodiments of this application, the material of the second conductive portion further includes the doped ions.

[0016] Optionally, in some embodiments of this application, at least one of the gates includes a first gate and a second gate, the first gate is disposed on a second insulating layer, the second gate is disposed in the same layer as the output electrode, and the second gate is disposed between the first insulating layer and the substrate;

[0017] The semiconductor portion includes a channel, a first gate covering the channel, a second gate partially overlapping the channel, the overlapping portion of the channel and the second gate being connected to the first conductive portion, and the non-overlapping portion of the channel and the second gate being connected to the second conductive portion.

[0018] Optionally, in some embodiments of this application, in the direction from the first conductive portion to the second conductive portion, the length of the portion of the channel overlapping with the second gate is 1 / 4 to 1 / 2 of the channel length.

[0019] Optionally, in some embodiments of this application, the first conductive portion, the semiconductor portion, and the second conductive portion are disposed in the same layer and integrally formed.

[0020] Optionally, in some embodiments of this application, the first conductive portion and the second conductive portion are disposed on the same layer and spaced apart. The semiconductor portion further includes a first overlapping portion and a second overlapping portion. The first overlapping portion is connected to the side of the first conductive portion away from the substrate, and the second overlapping portion is connected to the side of the second conductive portion away from the substrate. One end of the channel is connected to the first overlapping portion and the first conductive portion, and the other end of the channel is connected to the second overlapping portion and the second conductive portion.

[0021] Optionally, in some embodiments of this application, the output electrode is disposed overlapping the active layer.

[0022] Optionally, in some embodiments of this application, the portion of the first conductive part that overlaps with the first overlapping portion has a first resistance value, and the portion of the first conductive part that does not overlap with the first overlapping portion has a second resistance value, wherein the first resistance value is greater than the second resistance value.

[0023] Optionally, in some embodiments of this application, the driving substrate further includes a third insulating layer, the third insulating layer being disposed on the at least one gate and covering the active layer and the first insulating layer, and the second metal layer being disposed on the third insulating layer;

[0024] The input electrode blocks the semiconductor portion and the second conductive portion, and in the orthographic projection pattern of the driving substrate, at least a portion of the first conductive portion is located outside the input electrode.

[0025] Accordingly, this application also provides a display panel, which includes a light-emitting device and a driving substrate as described in any of the above embodiments, wherein the light-emitting device is disposed on the driving substrate and the output electrode is electrically connected to the light-emitting device.

[0026] Beneficial effects:

[0027] The driving substrate of this embodiment includes a substrate, a first metal layer, a first insulating layer, an active layer, a second insulating layer, at least one gate electrode, and a second metal layer. The first metal layer includes an output electrode for electrically connecting to a light-emitting device. The first insulating layer is disposed on the first metal layer and covers the substrate. The active layer is disposed on the first insulating layer and includes a semiconductor portion, a first conductive portion, and a second conductive portion. The first conductive portion is connected to the side of the semiconductor portion near the output electrode, and the second conductive portion is connected to the side of the semiconductor portion away from the output electrode. The first conductive portion is connected to the output electrode, and the surface resistivity of the first conductive portion is less than the surface resistivity of the second conductive portion. The second insulating layer is disposed on the semiconductor portion. A gate electrode is disposed on the second insulating layer and overlaps with the semiconductor portion. The second metal layer includes an input electrode connected to the second conductive portion. The input electrode, output electrode, active layer, and gate electrode are used to form a thin-film transistor.

[0028] In this embodiment, because the surface resistivity of the first conductive part is less than that of the second conductive part, the resistance of the active layer near the output electrode is less than that of the active layer near the input electrode, thereby reducing the voltage drop of the active layer near the output electrode and thus reducing the influence of hot carriers on the threshold voltage. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the structure of the driving substrate provided in the first embodiment of this application;

[0030] Figure 2 This is a schematic diagram of step B11 in the fabrication process of the driving substrate provided in the first embodiment of this application;

[0031] Figure 3 This is a schematic diagram of step B12 in the fabrication process of the driving substrate provided in the first embodiment of this application;

[0032] Figure 4 This is a schematic diagram of step B13 in the fabrication process of the driving substrate provided in the first embodiment of this application;

[0033] Figure 5 This is a schematic diagram of step B14 in the fabrication process of the driving substrate provided in the first embodiment of this application;

[0034] Figure 6 This is a schematic diagram of the structure of the driving substrate provided in the second embodiment of this application;

[0035] Figure 7 This is a schematic diagram of the structure of the driving substrate provided in the third embodiment of this application;

[0036] Figure 8 This is a schematic diagram of step B21 in the fabrication process of the driving substrate provided in the third embodiment of this application;

[0037] Figure 9 This is a schematic diagram of step B22 in the fabrication process of the driving substrate provided in the third embodiment of this application;

[0038] Figure 10 This is a schematic diagram of step B23 in the fabrication process of the driving substrate provided in the third embodiment of this application;

[0039] Figure 11 This is a schematic diagram of step B24 in the fabrication process of the driving substrate provided in the third embodiment of this application;

[0040] Figure 12 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0042] This application provides a driving substrate and a display panel, which will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0043] Please refer to Figure 1 The first embodiment of this application provides a driving substrate 100, which includes a substrate 11, a first metal layer 12, a first insulating layer 13, an active layer 14, a second insulating layer 15, at least one gate 16, and a second metal layer 17.

[0044] The first metal layer 12 includes an output electrode 121 for electrically connecting to a light-emitting device. A first insulating layer 13 is disposed on the first metal layer 12 and covers the substrate 11. An active layer 14 is disposed on the first insulating layer 13.

[0045] The active layer 14 includes a semiconductor portion 141, a first conductive portion 142, and a second conductive portion 143. The first conductive portion 142 is connected to the semiconductor portion 141 on the side closer to the output electrode 121, and the second conductive portion 143 is connected to the semiconductor portion 141 on the side farther from the output electrode 121. The first conductive portion 142 is connected to the output electrode 121. The surface resistivity of the first conductive portion 142 is less than the surface resistivity of the second conductive portion 143.

[0046] A second insulating layer 15 is disposed on the semiconductor portion 141. A gate electrode 16 is disposed on the second insulating layer 15 and overlaps with the semiconductor portion 141. A second metal layer 17 includes an input electrode 171, which is connected to a second conductive portion 143. The input electrode 171, the output electrode 121, the active layer 14, and the gate electrode 16 are used to form a thin-film transistor.

[0047] In this embodiment, since the surface resistivity of the first conductive portion 142 is less than that of the second conductive portion 143, the resistance of the portion of the active layer 14 near the output electrode 121 is less than that of the portion of the active layer 14 near the input electrode 171, thereby reducing the voltage drop of the portion of the active layer 14 near the output electrode 121 and thus reducing the influence of hot carriers on the threshold voltage.

[0048] It should be noted that in the active layer 14, if the channel is divided in half, and the total resistance of the first conductive part 142 and half of the channel is set as the first total resistance, and the total resistance of the second conductive part 143 and the other half of the channel is set as the second total resistance, then if the first total resistance is less than the second total resistance, the influence of hot carriers on the threshold voltage of the thin film transistor can be reduced.

[0049] Optionally, one of the input electrode 171 and the output electrode 121 can be the source and the other the drain. This embodiment uses the input electrode 171 as the source and the output electrode 121 as the drain as an example for explanation.

[0050] In other words, when the resistance of the active layer 14 near the drain is less than the resistance of the active layer 14 near the source, the voltage drop near the drain region can be reduced, thereby reducing the influence of hot carriers on the threshold voltage of the thin film transistor.

[0051] Optionally, the material of the substrate 11 includes one of glass, sapphire, silicon, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene dicarboxylate, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyethersulfone, aromatic fluorotoluene containing polyarylate, polycyclic olefins, polyimide, or polyurethane.

[0052] Optionally, the first metal layer 12 is formed from metal elements selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, and cobalt, alloys with any of the above metal elements as components, or alloys combining any of the above metal elements. Furthermore, the first metal layer 12 may have a single-layer structure or a stacked structure of two or more layers.

[0053] Optionally, the output electrode 121 overlaps with the active layer 14. Since the output electrode 121 blocks the active layer 14, the risk of light radiating to the active layer 14 is reduced, thus improving the stability of the thin-film transistor.

[0054] Optionally, the first insulating layer 13 and the second insulating layer 15 may be formed from a plurality of inorganic layers stacked in an alternating manner. For example, the first insulating layer 13 and the second insulating layer 15 may be formed as a bilayer by stacking inorganic layers comprising at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide, or as a multilayer by alternating stacking inorganic layers comprising at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide. However, this disclosure is not limited thereto, and the first insulating layer 13 and the second insulating layer 15 may be formed as a single inorganic layer comprising the aforementioned insulating material.

[0055] Optionally, in the active layer 14, the first conductive portion 142 and the second conductive portion 143 are disposed on the same layer and spaced apart. The semiconductor portion 141 includes a first overlapping portion 14a, a channel 14b, and a second overlapping portion 14c. The first overlapping portion 14a is connected to the side of the first conductive portion 142 away from the substrate 11. The second overlapping portion 14c is connected to the side of the second conductive portion 143 away from the substrate 11. One end of the channel 14b is connected to the first overlapping portion 14a and the first conductive portion 142, and the other end of the channel 14b is connected to the second overlapping portion 14c and the second conductive portion 143.

[0056] The materials of the first conductive part 142 and the second conductive part 143 include metal oxides with low resistivity, such as ITO and IZO.

[0057] The material of the semiconductor section 141 may include at least one of indium gallium zinc oxide, indium zinc oxide, zinc tin oxide, indium gallium oxide, indium tin oxide, indium zirconium oxide, indium zirconium zinc oxide, indium zirconium tin oxide, indium zirconium gallium oxide, indium aluminum oxide, indium zinc aluminum oxide, indium tin aluminum oxide, indium aluminum gallium oxide, indium tantalum oxide, indium tantalum zinc oxide, indium tantalum tin oxide, indium tantalum gallium oxide, indium germanium oxide, indium germanium zinc oxide, indium germanium tin oxide, indium germanium gallium oxide, titanium indium zinc oxide, and hafnium indium zinc oxide.

[0058] Optionally, the concentration of doped ions in the first conductive part 142 is greater than the concentration of doped ions in the second conductive part 143.

[0059] Understandably, in ion implantation, the higher the concentration of doped particles implanted, the better the conductivity. Since the concentration of doped particles in the first conductive part 142 is greater than the concentration of doped ions in the second conductive part 143, the resistance of the first conductive part 142 is less than the resistance of the second conductive part 143, thereby reducing the voltage drop near the drain region.

[0060] Optionally, the material of the first conductive portion 142 includes a metal oxide and doped ions, with the doped ions doped in the metal oxide. The material of the second conductive portion 143 includes at least a metal oxide.

[0061] In this embodiment, the material of the second conductive part 143 may consist only of metal oxide, that is, the second conductive part 143 does not need to be ion-doped.

[0062] When both the first conductive portion 142 and the second conductive portion 143 include the same metal oxide, only the first conductive portion 142 can be ion-doped to make the surface resistivity of the first conductive portion 142 less than that of the second conductive portion 143.

[0063] In some embodiments, the material of the second conductive portion 143 further includes doped ions. That is, the second conductive portion 143 can also be ion-doped to improve its conductivity, but the ion doping concentration of the second conductive portion 143 is lower than that of the first conductive portion 142.

[0064] Optionally, the portion of the first conductive part 142 that overlaps with the first overlapping portion 14a has a first resistance value, and the portion of the first conductive part 142 that does not overlap with the first overlapping portion 14a has a second resistance value, wherein the first resistance value is greater than the second resistance value.

[0065] That is, the portion of the first conductive part 142 that overlaps with the first overlapping part 14a is not ion-doped, while the portion of the first conductive part 142 that does not overlap with the first overlapping part 14a is ion-doped, so that the first resistance value is greater than the second resistance value.

[0066] In this case, since the resistance values ​​of the overlapping portions of the first conductive portion 142 and the first overlapping portion 14a and the overlapping portions of the second conductive portion 143 and the second overlapping portion 14c are both less than the resistance value of the semiconductor portion 141, and the first conductive portion 142 and the second conductive portion 143 are overlapped with the semiconductor portion 141, that is, the auxiliary setting of the first conductive portion 142 and the second conductive portion 143 on the semiconductor portion 141, the length of the channel is narrowed and the electron mobility is improved.

[0067] In addition, since the resistance value of the portion where the first conductive portion 142 overlaps with the first overlapping portion 14a is less than the resistance value of the semiconductor portion 141, the voltage drop near the drain region can be further reduced, thereby reducing the influence of hot carriers on the threshold voltage of the thin film transistor.

[0068] Optionally, the surface resistivity of the portion where the first conductive part 142 overlaps with the first overlapping part 14a is 3 to 10 times that of the non-overlapping portion of the first conductive part 142 and the first overlapping part 14a.

[0069] For example, the surface resistivity of the overlapping portion of the first conductive part 142 and the first overlapping part 14a is 10 to 100 Ω / sq, such as 10 Ω / sq, 20 Ω / sq, 30 Ω / sq, 40 Ω / sq, 50 Ω / sq, 60 Ω / sq, 70 Ω / sq, 80 Ω / sq, 90 Ω / sq or 100 Ω / sq.

[0070] The surface resistivity of the non-overlapping portion of the first lap joint 14a is 1 to 10 Ω / sq, for example, it can be 1 Ω / sq, 2 Ω / sq, 3 Ω / sq, 4 Ω / sq, 5 Ω / sq, 6 Ω / sq, 7 Ω / sq, 8 Ω / sq, 9 Ω / sq or 10 Ω / sq.

[0071] Optionally, the area of ​​the portion overlapping the first conductive portion 142 and the first overlapping portion 14a is larger than the area of ​​the portion overlapping the second conductive portion 143 and the second overlapping portion 14c, so as to further reduce the influence of hot carriers on the threshold voltage of the thin film transistor.

[0072] Optionally, the driving substrate 100 further includes a third insulating layer 18, which is disposed on at least one gate 16 and covers the active layer 14 and the first insulating layer 13. A second metal layer 17 is disposed on the third insulating layer 18.

[0073] The input electrode 171 blocks the semiconductor portion 141 and the second conductive portion 143. In the orthographic projection pattern of the driving substrate 100, at least a portion of the first conductive portion 142 is located outside the input electrode 171.

[0074] In some embodiments, the input electrode 171 may be formed directly on the second conductive portion 143, thus saving the third insulating layer 18.

[0075] In this embodiment, since the input electrode 171 blocks the semiconductor portion 141 and the second conductive portion 143, and exposes the first conductive portion 142, the first conductive portion 142 can be ion-doped using the input electrode 171 as a mask.

[0076] Optionally, the material of the second metal layer 17 is selected from metallic elements selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, and cobalt, alloys composed of any of the above metallic elements, or alloys combining any of the above metallic elements. Furthermore, the first metal layer 12 may have a single-layer structure or a stacked structure of two or more layers.

[0077] Optionally, the second metal layer 17 also includes a bonding pad 172 for bonding with a light-emitting device.

[0078] Optionally, the driving substrate 100 further includes a fourth insulating layer 19 and a conductive layer 20. The fourth insulating layer 19 covers the second metal layer 17 and the third insulating layer 18. The conductive layer 20 is disposed on the fourth insulating layer 19 and includes wirings that are electrically connected to the output electrode 121 and the bonding pad 172.

[0079] Optionally, the third insulating layer 18 and the fourth insulating layer 19 may be formed of a plurality of inorganic layers stacked in an alternating manner. For example, the first insulating layer 13 and the second insulating layer 15 may be formed as a bilayer by stacking inorganic layers comprising at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide, or as a multilayer by alternatingly stacking inorganic layers comprising at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide. However, this disclosure is not limited thereto, and the third insulating layer 18 and the fourth insulating layer 19 may be formed as a single inorganic layer comprising the aforementioned insulating material.

[0080] Furthermore, in one or more embodiments, the third insulating layer 18 may be made of an organic insulating material such as polyimide.

[0081] Optionally, the material of the conductive layer 20 may include metal oxides, such as ITO and IZO.

[0082] The fabrication process of the driving substrate 100 in this first embodiment is as follows:

[0083] Step B11, as follows Figure 2 As shown, a patterned first metal layer 12, a first insulating layer 13, and a first conductive layer 14f are sequentially formed on a substrate 11. The first conductive layer 14f includes a first conductive portion 142 and a second conductive portion 143. The first conductive portion 142 and the second conductive portion 143 are made of the same material and are formed using the same photomask.

[0084] In some embodiments, the materials of the first conductive part 142 and the second conductive part 143 may also be different.

[0085] Step B12, as follows Figure 3 As shown, a semiconductor portion 141, a second insulating layer 15, and a gate 16 are sequentially formed on a substrate 11. The semiconductor portion 141 is formed between a first conductive portion 142 and a second conductive portion 143, and the semiconductor portion 141 is connected to the first conductive portion 142 and the second conductive portion 143 to form an active layer 14.

[0086] The patterning of the second insulating layer 15 can be completed using a top gate self-alignment process.

[0087] In some embodiments, the exposed portions of the first conductive portion 142 and the second conductive portion 143 may also be conductiveized using the top gate 16 as a mask.

[0088] Step B13, as follows Figure 4 As shown, a third insulating layer 18 and a second metal layer 17 are sequentially formed on the substrate 11. The third insulating layer 18 covers the gate 16, the active layer 14, and the first insulating layer 13. The second metal layer 17 includes an input electrode 171 and a bonding pad 172.

[0089] In addition, in this step, ion implantation is performed on the active layer 14 using the input electrode 171 as a mask, thereby reducing the resistance value of the first conductive part 142.

[0090] Optionally, the doping ions include, but are not limited to, H, He, B, Al, N, F, P, Ar, S, etc.

[0091] It should be noted that before ion implantation, the surface resistivity of the first conductive part 142 and the second conductive part 143 is 10 to 100 Ω / sq, for example, it can be 10 Ω / sq, 20 Ω / sq, 30 Ω / sq, 40 Ω / sq, 50 Ω / sq, 60 Ω / sq, 70 Ω / sq, 80 Ω / sq, 90 Ω / sq or 100 Ω / sq.

[0092] After ion doping, the surface resistivity of the doped portion of the first conductive part 142 is 1 to 10 Ω / sq, for example, it can be 1 Ω / sq, 2 Ω / sq, 3 Ω / sq, 4 Ω / sq, 5 Ω / sq, 6 Ω / sq, 7 Ω / sq, 8 Ω / sq, 9 Ω / sq or 10 Ω / sq.

[0093] Step B14, as follows Figure 5 As shown, a fourth insulating layer 19 and a conductive layer 20 are sequentially formed on the second metal layer 17. The fourth insulating layer 19 covers the second metal layer 17 and the third insulating layer 18.

[0094] Optionally, a conductive material layer is formed by physical vapor deposition and patterned to form the conductive layer 20.

[0095] This completes the fabrication process of the driving substrate 100 of this first embodiment.

[0096] Please refer to Figure 6 The driving substrate 100 of this second embodiment differs from the above embodiments in that at least one gate 16 includes a first gate 161 and a second gate 162. The first gate 161 is disposed on the second insulating layer 15. The second gate 162 is disposed on the same layer as the output electrode 121. The second gate 162 is disposed between the first insulating layer 13 and the substrate 11.

[0097] The first gate 161 covers the channel 14b. The second gate 162 partially overlaps with the channel 14b. The overlapping portion of the channel 14b and the second gate 162 is connected to the first conductive portion 142. The non-overlapping portion of the channel 14b and the second gate 162 is connected to the second conductive portion 143.

[0098] In other words, compared to the first embodiment, the output electrode 121 in this embodiment is located outside the active layer 14. This second embodiment uses the first gate 161 and the second gate 162 to simultaneously control the portion of the active layer 14 near the drain side, thereby reducing the voltage drop in the drain side region and improving mobility.

[0099] Optionally, in the direction from the first conductive portion 142 to the second conductive portion 143, the length of the portion of the channel 14b overlapping the second gate 162 is 1 / 4 to 1 / 2 of the length of the channel 14b. This arrangement can suppress the influence of hot carriers to a greater extent.

[0100] Optionally, the length of the portion of the channel 14b that overlaps with the second gate 162 is 1 / 4, 1 / 3, or 1 / 2 of the length of the channel 14b.

[0101] Please refer to Figure 7 The difference between the driving substrate 100 of this third embodiment and the first and second embodiments is that the first conductive part 142, the semiconductor part 141 and the second conductive part 143 are disposed in the same layer and integrally formed.

[0102] Compared to the two embodiments described above, the steps for preparing the active layer 14 in this embodiment are simpler.

[0103] The driving substrate 100 of this third embodiment is described based on the second embodiment. The fabrication process of the driving substrate 100 of this third embodiment is as follows:

[0104] Step B21, as follows Figure 8 As shown, a patterned first metal layer 12, a first insulating layer 13, and an active layer 14 are sequentially formed on a substrate 11. The first metal layer 12 includes an output electrode 121 and a second gate electrode 162.

[0105] The first insulating layer 13 covers the first metal layer 12 and the substrate 11.

[0106] In step B21, the active layer 14 is made of a metal oxide. For example, it may include at least one of the following: indium gallium zinc oxide, indium zinc oxide, zinc tin oxide, indium gallium oxide, indium tin oxide, indium zirconium oxide, indium zirconium zinc oxide, indium zirconium tin oxide, indium zirconium gallium oxide, indium aluminum oxide, indium zinc aluminum oxide, indium tin aluminum oxide, indium aluminum gallium oxide, indium tantalum oxide, indium tantalum zinc oxide, indium tantalum tin oxide, indium tantalum gallium oxide, indium germanium oxide, indium germanium zinc oxide, indium germanium tin oxide, indium germanium gallium oxide, titanium indium zinc oxide, and hafnium indium zinc oxide.

[0107] Step B22, as follows Figure 9 As shown, a second insulating layer 15 and a first gate 161 are sequentially formed on the active layer 14. The second insulating layer 15 is patterned using a self-aligned process with the first gate 161, and the non-channel portion of the active layer 14 is conductiveized using the first gate 161 as a mask to form a first conductive portion 142, a semiconductor portion (channel) 141, and a second conductive portion 143.

[0108] Step B23, as follows Figure 10 As shown, a third insulating layer 18 and a second metal layer 17 are sequentially formed on the substrate 11. The third insulating layer 18 covers the gate 16, the active layer 14, and the first insulating layer 13. The second metal layer 17 includes an input electrode 171 and a bonding pad 172.

[0109] In addition, in this step, ion implantation is performed on the first conductive part 142 of the active layer 14 using the input electrode 171 as a mask, thereby reducing the resistance value of the first conductive part 142.

[0110] Optionally, the doping ions include, but are not limited to, H, He, B, Al, N, F, P, Ar, S, etc.

[0111] Step B24, as follows Figure 11 As shown, a fourth insulating layer 19 and a conductive layer 20 are sequentially formed on the second metal layer 17. The fourth insulating layer 19 covers the second metal layer 17 and the third insulating layer 18.

[0112] Optionally, a conductive material layer is formed by physical vapor deposition and patterned to form the conductive layer 20.

[0113] This completes the fabrication process of the driving substrate 100 in this third embodiment.

[0114] Please refer to Figure 12 Accordingly, this application also provides a display panel 1000, which includes a light-emitting device 200 and a driving substrate 100 as described in any of the above embodiments. The light-emitting device 200 is disposed on the driving substrate 100, and the output electrode 121 is electrically connected to the light-emitting device 200.

[0115] Optionally, the light-emitting device 200 is a sub-millimeter-scale light-emitting diode (Mini-LED), a micro-light-emitting diode (Micro-LED), or an organic light-emitting diode (OLED).

[0116] In this embodiment, the structure of the driving substrate 100 of the display panel 1000 is similar to or the same as that of the driving substrate 100 in the above embodiments, so the driving substrate 100 will not be described here.

[0117] The driving substrate 100 of the display panel 1000 in this embodiment includes a substrate 11, a first metal layer 12, a first insulating layer 13, an active layer 14, a second insulating layer 15, at least one gate 16, and a second metal layer 17.

[0118] The first metal layer 12 includes an output electrode 121 for electrically connecting to a light-emitting device. A first insulating layer 13 is disposed on the first metal layer 12 and covers the substrate 11. An active layer 14 is disposed on the first insulating layer 13.

[0119] The active layer 14 includes a semiconductor portion 141, a first conductive portion 142, and a second conductive portion 143. The first conductive portion 142 is connected to the semiconductor portion 141 on the side closer to the output electrode 121, and the second conductive portion 143 is connected to the semiconductor portion 141 on the side farther from the output electrode 121. The first conductive portion 142 is connected to the output electrode 121. The surface resistivity of the first conductive portion 142 is less than the surface resistivity of the second conductive portion 143.

[0120] A second insulating layer 15 is disposed on the semiconductor portion 141. A gate electrode 16 is disposed on the second insulating layer 15 and overlaps with the semiconductor portion 141. A second metal layer 17 includes an input electrode 171, which is connected to a second conductive portion 143. The input electrode 171, the output electrode 121, the active layer 14, and the gate electrode 16 are used to form a thin-film transistor.

[0121] In this embodiment, since the surface resistivity of the first conductive portion 142 is less than that of the second conductive portion 143, the resistance of the portion of the active layer 14 near the output electrode 121 is less than that of the portion of the active layer 14 near the input electrode 171, thereby reducing the voltage drop of the portion of the active layer 14 near the output electrode 121 and thus reducing the influence of hot carriers on the threshold voltage.

[0122] The foregoing has provided a detailed description of a driving substrate and display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A driving substrate, characterized in that, include: substrate; A first metal layer, the first metal layer including an output electrode, the output electrode being used for electrically connecting to a light-emitting device; A first insulating layer is disposed on the first metal layer and covers the substrate; An active layer is disposed on the first insulating layer. The active layer includes a semiconductor portion, a first conductive portion, and a second conductive portion. The first conductive portion is connected to the side of the semiconductor portion near the output electrode, and the second conductive portion is connected to the side of the semiconductor portion away from the output electrode. The first conductive portion is connected to the output electrode, and the surface resistivity of the first conductive portion is less than the surface resistivity of the second conductive portion. A second insulating layer is disposed on the semiconductor portion; At least one gate is disposed on the second insulating layer and overlaps with the semiconductor portion; as well as The second metal layer includes an input electrode connected to the second conductive portion, and the input electrode, the output electrode, the active layer, and the gate are used to form a thin-film transistor.

2. The driving substrate according to claim 1, characterized in that, The concentration of doped ions in the first conductive part is greater than the concentration of doped ions in the second conductive part.

3. The driving substrate according to claim 2, characterized in that, The material of the first conductive portion includes a metal oxide and the doped ions, wherein the doped ions are doped into the metal oxide, and the material of the second conductive portion includes at least the metal oxide.

4. The driving substrate according to claim 3, characterized in that, The material of the second conductive part also includes the doped ions.

5. The driving substrate according to claim 1, characterized in that, At least one of the gates includes a first gate and a second gate, the first gate is disposed on a second insulating layer, the second gate is disposed in the same layer as the output electrode, and the second gate is disposed between the first insulating layer and the substrate; The semiconductor portion includes a channel, a first gate covering the channel, a second gate partially overlapping the channel, the overlapping portion of the channel and the second gate being connected to the first conductive portion, and the non-overlapping portion of the channel and the second gate being connected to the second conductive portion.

6. The driving substrate according to claim 5, characterized in that, In the direction from the first conductive portion to the second conductive portion, the length of the portion of the channel that overlaps with the second gate is 1 / 4 to 1 / 2 of the channel length.

7. The driving substrate according to claim 5, characterized in that, The first conductive part, the semiconductor part, and the second conductive part are disposed in the same layer and integrally formed.

8. The driving substrate according to claim 5, characterized in that, The first conductive portion and the second conductive portion are disposed on the same layer and spaced apart. The semiconductor portion further includes a first overlapping portion and a second overlapping portion. The first overlapping portion is connected to the side of the first conductive portion away from the substrate, and the second overlapping portion is connected to the side of the second conductive portion away from the substrate. One end of the channel is connected to the first overlapping portion and the first conductive portion, and the other end of the channel is connected to the second overlapping portion and the second conductive portion.

9. The driving substrate according to claim 1, characterized in that, The output electrode is disposed overlapping the active layer.

10. The driving substrate according to claim 8 or 9, characterized in that, The portion of the first conductive part that overlaps with the first overlapping portion has a first resistance value, and the portion of the first conductive part that does not overlap with the first overlapping portion has a second resistance value, wherein the first resistance value is greater than the second resistance value.

11. The driving substrate according to claim 1, characterized in that, The driving substrate further includes a third insulating layer, which is disposed on the at least one gate and covers the active layer and the first insulating layer, and the second metal layer is disposed on the third insulating layer; The input electrode blocks the semiconductor portion and the second conductive portion, and in the orthographic projection pattern of the driving substrate, at least a portion of the first conductive portion is located outside the input electrode.

12. A display panel, characterized in that, It includes a light-emitting device and a driving substrate as described in any one of claims 1-11, wherein the light-emitting device is disposed on the driving substrate and the output electrode is electrically connected to the light-emitting device.

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