Anti-aging bandwidth extension device

Abstract

The present disclosure relates to an anti-aging bandwidth extension device. A circuit for inductive peaking can include a driver, an inverter, a resistor between an output node of the driver and an input node of the inverter, and a switch. For example, a first node of the resistor can be connected to the output node of the driver, and a second node of the resistor can be connected to the input node of the inverter. The switch can be connected between an output node of the inverter and the first node of the resistor. An input node of the driver can correspond to an input node of the circuit, and the output node of the driver can correspond to an output node of the circuit.

Description

Technical Field

[0001] This disclosure relates to an apparatus for performing bandwidth expansion, and more specifically to an apparatus for providing bandwidth expansion in a manner that mitigates aging problems. Background Technology

[0002] To meet the stringent data rate requirements of high-end serializer / deserializer (SERDES) products, advanced complementary metal-oxide-semiconductor (CMOS) technology and on-chip bandwidth extension technology are generally considered to achieve reasonable inter-symbol interference (ISI) and reliable bit error rate (BER).

[0003] Inductor peaking is a method that can be employed to increase high-frequency gain to compensate for bandwidth limitations (i.e., limitations within wavelength, frequency, or energy band). Specifically, active inductor implementations using only transistors may be desirable because active inductors can occupy a relatively smaller area than passive inductors and are further compatible with switching CMOS circuits.

[0004] However, active inductors are typically subject to destructive aging effects, which can lead to performance degradation over time and ultimately limit their operational life. Aging issues are often exacerbated by the adverse operating conditions of high-speed SERDES circuits, such as high-temperature operation and power supplied by voltages higher than those typically recommended by foundries.

[0005] Therefore, it is necessary to develop systems and methods to overcome the above-mentioned deficiencies. Summary of the Invention

[0006] A circuit is disclosed according to one or more illustrative embodiments of the present disclosure. In one illustrative embodiment, the circuit includes a driver and an inverter. In another illustrative embodiment, the circuit includes a resistor between the output node of the driver and the input node of the inverter, wherein a first node of the resistor is connected to the output node of the driver, and a second node of the resistor is connected to the input node of the inverter. In another illustrative embodiment, the circuit includes a switch between the output node of the inverter and the first node of the resistor, wherein the input node of the driver corresponds to the input node of the circuit, and wherein the output node of the driver corresponds to the output node of the circuit.

[0007] A system is disclosed according to one or more illustrative embodiments of this disclosure. In one illustrative embodiment, the system includes one or more circuits, each of which includes a driver, an inverter, a resistor connected between an output node of the driver and an input node of the inverter, and a switch between the output node of the inverter and a first node of the resistor. The first node of the resistor may be connected to the output node of the driver, and a second node of the resistor may be connected to the input node of the inverter. The input node of the driver may correspond to the input node of the circuit, and the output node of the driver may correspond to the output node of the circuit. In another illustrative embodiment, the system includes a controller coupled to the one or more circuits, wherein the controller independently directs the switch in each of the one or more circuits to operate in either an open or closed state.

[0008] A method is disclosed according to one or more illustrative embodiments of this disclosure. In one illustrative embodiment, the method includes generating a circuit design that includes a driver having a first bandwidth, an inverter, and a resistor connected between an output node of the driver and an input node of the inverter. In another illustrative embodiment, the resistor is formed of two or more transistors. A first node of the resistor may be connected to the output node of the driver, and a second node of the resistor may be connected to the input node of the inverter. In another illustrative embodiment, the output node of the inverter is connected to the output node of the driver. The input node of the driver may correspond to the input node of the circuit, wherein the output node of the driver corresponds to the output node of the circuit. In another illustrative embodiment, the method includes selecting at least one of the value of the resistor, the size of the driver, or the size of the inverter in the circuit design such that the circuit has a second bandwidth greater than the first bandwidth. In another illustrative embodiment, the method includes, in the design of the circuit, converting at least one of the two or more transistors in the resistor into a switch, wherein a first node of the switch is connected to the output node of the inverter, wherein a second node of the switch is connected to the output node of the driver, and wherein the circuit has a third bandwidth less than the second bandwidth. In another illustrative embodiment, the method includes, in the design of the circuit, adding one or more additional transistors to the resistor. In another illustrative embodiment, the method includes, in the design of the circuit, increasing the size of the switch to provide the circuit with the second bandwidth.

[0009] It should be understood that the foregoing overview and the following detailed description are merely illustrative and explanatory, and are not necessarily intended to limit the claimed invention. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the overview, explain the principles of the invention. Attached Figure Description

[0010] Those skilled in the art can better understand the many advantages of this disclosure by referring to the accompanying drawings.

[0011] Figure 1A This is a schematic diagram of a bandwidth expansion circuit according to one or more embodiments of the present disclosure.

[0012] Figure 1B This invention describes a bandwidth extension circuit comprising a complementary metal-oxide-semiconductor (CMOS) component according to one or more embodiments of the present disclosure.

[0013] Figure 2A It is an active inductor according to one or more embodiments of this disclosure and does not have Figure 1A and 1B The diagram illustrates the CMOS bandwidth extension circuit of the switch.

[0014] Figure 2B It is a response to an input signal according to one or more embodiments of this disclosure. Figure 2A The voltage curves at each node of the bandwidth extension circuit.

[0015] Figure 3A It is a state of newness (e.g., before aging) according to one or more embodiments of this disclosure. Figure 1B Eye diagram of the bandwidth extension circuit in [the circuit].

[0016] Figure 3B According to one or more embodiments of this disclosure Figure 1B The eye diagram of the bandwidth extension circuit after 10 years of aging.

[0017] Figure 4A It is a state of newness (e.g., before aging) according to one or more embodiments of this disclosure. Figure 2A Eye diagram of the bandwidth extension circuit in [the circuit].

[0018] Figure 4B According to one or more embodiments of this disclosure Figure 2A The eye diagram of the bandwidth extension circuit after 10 years of aging.

[0019] Figure 5 This is a block diagram of a system including bandwidth extension circuitry 100 according to one or more embodiments of the present disclosure.

[0020] Figure 6This is a flowchart illustrating the steps performed in a method for designing a bandwidth extension circuit according to one or more embodiments of the present disclosure.

[0021] Figure 7A According to one or more embodiments of this disclosure, such as Figure 2A A simplified schematic diagram of an active inductor formed as an inverter and resistor, as depicted in the bandwidth extension circuit 202.

[0022] Figure 7B It is a graph of the voltage at the output node of a bandwidth extension circuit for a series of bits, according to one or more embodiments of the present disclosure.

[0023] Figure 8A According to one or more embodiments of this disclosure Figure 7A A simplified schematic diagram of an active inductor, in which a transistor pair of resistors is converted into a switch.

[0024] Figure 8B It is included according to one or more embodiments of this disclosure. Figure 7B Plus based on Figure 8A The curve of the additional voltage at the output node of the bandwidth extension circuit of the active inductor design.

[0025] Figure 9 It is included according to one or more embodiments of this disclosure. Figure 8B Plus based on Figure 8A The curve of the additional voltage at the output node of the bandwidth extension circuit of the active inductor design.

[0026] Figure 10 It is included according to one or more embodiments of this disclosure. Figure 9 Plus based on Figure 8A The curve of the voltage at the output node of the bandwidth extension circuit of the active inductor design is an additional curve after the size of the switch is increased. Detailed Implementation

[0027] Reference will now be made in detail to the disclosed subject matter, which is illustrated in the accompanying drawings. This disclosure has shown and described with respect to certain embodiments and specific features thereof. The embodiments set forth herein are to be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of this disclosure.

[0028] As used herein, directional terms such as “top,” “bottom,” “above,” “below,” “upper,” “upward,” “lower,” “downward,” and “downward” are intended to provide relative positions for descriptive purposes and are not intended to specify an absolute frame of reference. Various modifications to the described embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments.

[0029] It should be understood that the architecture depicted is merely exemplary, and many other architectures can be implemented to achieve the same functionality. Conceptually, any arrangement of components that achieve the same function is effectively “associated” to achieve the desired functionality. Therefore, any two components combined in this paper to achieve a particular function can be considered “associated” with each other to achieve the desired functionality, regardless of the architecture or intermediate components. Similarly, any two such associated components can also be considered “connected” or “coupled” to each other to achieve the desired functionality, and any two components that can be suchly associated can also be considered “coupleable” to each other to achieve the desired functionality. Furthermore, it is envisioned that coupling may include intermediary elements or components between electrically or communicatively coupled components.

[0030] Unless otherwise indicated, descriptions indicating that a component is “connected to” another component (or, alternatively, “located on”, “seat”, etc.) or “between” two components indicate that such components are functionally connected and do not necessarily indicate that such components are in physical contact. More precisely, such components may be in physical contact or may alternatively contain intervening elements. The term node (or alternatively, terminal) is used herein to indicate a connection point between circuit elements or portions thereof. In this way, components connected to a node can be physically connected in any suitable manner. In some embodiments, components connected to a node share a common electrical contact and therefore may not be required to be physically close. In some embodiments, components connected to a node are connected via one or more conductive paths, such as (but not limited to) traces or wires. Further, a component may be described as having one or more nodes (e.g., input nodes, output nodes, etc.) to indicate points for connection to other components. It is understood that the descriptions of connections between circuit components using nodes are for illustrative purposes only and do not imply any particular technique used to connect such components.

[0031] Embodiments of this disclosure relate to systems and methods for providing bandwidth extension of a driver in a manner that mitigates the adverse effects of aging to promote a relatively long operating life. The driver may comprise any type of means for repeating and / or amplifying signals (e.g., logic signals), such as (but not limited to) inverters (e.g., means for converting logic high to logic low or vice versa) or buffers (e.g., means for providing a logic high output in response to a logic high input and a logic low output in response to a logic low input). Some embodiments of this disclosure relate to bandwidth extension utilizing active inductors that provide inductance peaking. For example, a driver (e.g., an inductor, buffer, etc.) may provide a baseline bandwidth (e.g., a first bandwidth). However, this first bandwidth may be extended (e.g., to a second bandwidth) by an inverter or more generally bandwidth extension circuitry. For example, a bandwidth extension circuit may include a driver in which the output node of the driver is connected to the input node of an inverter via a resistor, and wherein the active inductor further comprises a switch between the output node of the inverter and the output node of the driver. The resistor may be any component that limits or regulates the flow of current in the circuit. Such circuits can operate with the switch in the closed position to provide inductance peaking based on feedback from the inverter, or with the switch in the open position without feedback.

[0032] Bandwidth extension circuitry and associated components (e.g., forming an inverter, etc.) can operate as logic devices designed to input and output high bits (e.g., logic "1") or low bits (e.g., logic "0"). The actual voltage values ​​associated with a high bit (e.g., a high voltage value) or a low bit (e.g., a low voltage value) can depend on the manufacturing process and / or specific design. In some embodiments, a high voltage value associated with a high bit corresponds to an ideal value of 1V, while a low voltage value associated with a low bit corresponds to an ideal value of 0V. Such configurations can be suitable for a variety of manufacturing processes, including (but not limited to) complementary metal-oxide-semiconductor (CMOS) processes or transistor-transistor logic (TTL) processors. However, other embodiments may allow different high voltage values ​​for the high bit, such as (but not limited to) 5V, 10V, or 18V. Furthermore, it should be understood that logic devices can generally operate at input and output voltages within the operating range for both high and low bits. For the purposes of this disclosure, the terms high voltage, high voltage value, and high bit are used interchangeably to refer to a logic high state and may include an associated operating voltage range. Similarly, the terms low voltage, low voltage value, and low bit are used interchangeably to refer to a logic low state and may include the associated operating voltage range.

[0033] Inverters (e.g., drivers for bandwidth extension and / or inverters coupled to drivers) may include any means of providing inverse logic operations. For example, an inverter may output a low bit when a high bit is received, and may output a high bit when a low bit is received. Furthermore, such inverters may be manufactured using any suitable process or technology. In this way, inverters in bandwidth extension circuits disclosed herein may include (but are not limited to) one or more field-effect transistors (FETs), one or more finned FETs, one or more MOSFETs, one or more bipolar junction transistors (BJTs), one or more junction field-effect transistors (JFETs), one or more insulated-gate bipolar transistors (IGBTs), one or more high electron mobility transistors (HEMTs), one or more tunnel field-effect transistors (TFETs), one or more carbon nanotube FETs (CNTFETs), or one or more junctionless nanowire transistors (JLNTs). By way of non-limiting illustration, an inverter manufactured according to a CMOS process (e.g., a CMOS inverter) may include two complementary transistors (e.g., a PMOS transistor and an NMOS transistor) having a common gate electrode, wherein the drain of the PMOS transistor is connected to the drain of the NMOS transistor. The transistors may be any device for regulating, controlling, amplifying, or switching electrical signals.

[0034] An active inductor may include one or more transistors and potentially other components arranged to provide inductance. Active inductors contrast with passive inductors, which are typically formed by wires wound around a coil to store energy in a magnetic field. Active inductors can generally be manufactured in a smaller size than passive inductors, offering additional flexibility and / or tunability compared to passive inductors, and are compatible with common manufacturing processes, such as (but not limited to) CMOS manufacturing processes. As used herein, component size may refer to the physical size of the component (e.g., width). In this way, active inductors can be manufactured as on-chip devices with tight form factors using CMOS-compatible manufacturing techniques.

[0035] Furthermore, as used herein, a switch may comprise one or more transistors arranged to operate in a closed or open state relative to an input node and an output node, wherein the operating state of the switch may be controlled by a drive signal. For example, a switch operating in an open state (e.g., non-conducting state) may limit or eliminate current flow between the input and output nodes, while a switch operating in a closed state (e.g., conducting state) may allow current flow between the input and output nodes.

[0036] This document recognizes that operating a transistor under certain conditions (referred to herein as aging conditions) may induce structural changes that may degrade performance but not lead to sudden device failure, a phenomenon referred to herein as aging. Transistors can operate under such aging conditions for extended periods without catastrophic failure. However, prolonged operation under aging conditions typically results in a shortened operating life of the transistor compared to operation under less damaging conditions.

[0037] As an illustration, two important sources of transistor aging include hot carrier injection (HCI) and bias temperature instability (BTI). When a transistor simultaneously experiences a high drain-source voltage (V0) that can be associated with large currents... ds ) and gate-source voltage (V gs High-frequency inertia (HCI) typically occurs when the gate voltage is high and / or the temperature is high. Under these conditions, charge can be trapped in the transistor's gate, leading to reduced carrier mobility and current capacity. In many cases, the effects of HCI aging are irreversible. Battery-induced aging (BTI) is typically induced under conditions of high gate voltage and / or high temperature, resulting in charge trapping and a lower operating voltage threshold. In many cases, the long-term effects of BTI can be partially reversed by periodically inverting the gate voltage polarity. Therefore, one way to mitigate BTI is to modulate the gate voltage where possible (e.g., alternating between high and low bits). It should be understood that the description of aging conditions in MOS devices is provided for illustrative purposes only and is not intended to limit the circuits, systems, and methods disclosed herein. It is considered that bandwidth-extending circuits as disclosed herein can operate in a manner that mitigates aging, regardless of the chosen manufacturing process. In this way, the circuits, systems and methods disclosed herein are not limited to devices using CMOS inverters, but can be extended to alternative technologies, including (but not limited to) FET inverters, and more generally, BJT inverters or other inverter types that include switches.

[0038] Many active inductor designs contain transistors that are exposed to aging conditions for extended periods under normal operation, and therefore typically suffer from a relatively short operating lifetime. Furthermore, typical methods for mitigating aging in active inductors depend on the circuit's operating mode, which prioritizes mitigation of one aging source (e.g., HCI or BTI) over another.

[0039] However, bandwidth-extending circuits incorporating active inductors, as disclosed herein, can substantially limit the exposure of constituent transistors to aging conditions and thus can have a significantly longer lifespan than alternative designs. In this way, such circuits (or components thereof, including active inductors) can be resistant to aging.

[0040] Depending on the state of the switch, the bandwidth extension circuit disclosed herein can operate in different modes to provide anti-aging operation.

[0041] For example, the operation of a bandwidth extension circuit with the switch in closed mode is referred to herein as active mode. In this active mode, the closed switch can connect the output nodes of two inverters, which also induces feedback across the inverters, causing the device to operate as an active inductor. Furthermore, the circuit in active mode can provide inductance peaking and can therefore be used to compensate for bandwidth limitations in communication systems, such as (but not limited to) serializer / deserializer (SERDES) systems.

[0042] This paper takes into account that the signals provided to the bandwidth extension circuit during active mode (e.g., signals containing data to be transmitted) typically contain many transitions between high and low voltages (e.g., signals containing transitions between high and low bits), making the BTI effect negligible or at least within acceptable tolerances.

[0043] However, operation in active mode may expose at least some transistors within the inverter to conditions that generate HCI. For example, operation with a high input voltage (e.g., the high bit of the input signal) may result in a relatively large drain-source voltage (V0) due to feedback from the inverter. ds ) and / or gate-source voltage (V gs This, along with the associated relatively high current flow, leads to HCI under these conditions, which may be somewhat unavoidable, as such feedback conditions are necessary for the device to provide inductance peaking operation. However, this paper further considers that the presence of a switch reduces the required drain-source (Vt) crossover of the transistors that make up the inverter compared to a design without a switch. ds This allows for a significant reduction in aging compared to designs without switches.

[0044] As another example, the operation of the bandwidth extension circuit when the switch is in the off mode is referred to in this paper as the power-off mode.

[0045] This paper considers that when the input signal is constant over an extended period (e.g., as a high or low bit), typical bandwidth extension circuit designs operate under particularly detrimental aging conditions. In the context of communication systems, this can occur even when no information is being communicated. Under these conditions, both HCI and BTI conditions may exist. Modulation of the input signal under these conditions (e.g., providing an arbitrary input signal with randomized data) can mitigate BTI but not HCI. This may be especially true when the frequency of alternating input data patterns is slow (e.g., when data is not actively provided to the circuit). To avoid HCI in this operating mode, the driver gate voltage and inverter gate voltage can be connected to opposite polarities via an additional power-off switch, while simultaneously disconnecting the feedback resistor. However, in this case, the input data cannot be continuously switched to mitigate BTI aging, as is the case without using the additional power-off switch. That is, for active peaking circuits, there is some conflict between mitigating BTI and HCI simultaneously.

[0046] However, the bandwidth extension circuit disclosed herein can mitigate both BTI and HCI in power-down mode. In this power-down mode, the output nodes of the two inverters are decoupled, allowing the two inverters to be simply connected in series with the resistor between them. This eliminates the struggle between them to pull the output nodes in the opposite direction, just as in the case without switches. Therefore, the feedback condition contributing to HCI is removed. Furthermore, modulation of the input signal in this power-down mode also mitigates BTI because it is not necessary to continuously reverse the gate voltages of the driver and inverter as in the case where this decoupling is not implemented between the driver and inverter.

[0047] Additional embodiments of this disclosure relate to a communication system comprising at least one bandwidth extension circuit having a switch as disclosed herein, and a controller for controlling the operating mode of the switch. In this manner, the controller can selectively operate one or more bandwidth extension circuits in an active mode or a power-off mode. The communication system may further include a source for providing or otherwise controlling input signals to the one or more bandwidth extension circuits. In some embodiments, the controller is further coupled to the source and can direct the source to provide modulated input signals (e.g., including randomized data, alternating high and low voltages, etc.) to the one or more bandwidth extension circuits in a power-off mode to mitigate aging of the active inductor during power-off mode.

[0048] Additional embodiments of this disclosure relate to methods for designing bandwidth extension circuits as disclosed herein. For example, the method may include (but is not limited to) selecting initial values ​​and / or sizes of various components of a bandwidth extension circuit having an active inductor to provide a desired amount of inductance peaking, adding switches to selectively provide feedback based on the active inductor, determining a reduction in inductance peaking performance attributable to the switches, and adjusting the values ​​and / or sizes of at least some of the components to at least partially compensate for the performance reduction attributable to the switches.

[0049] As is well known, one or more transistors (e.g., FET transistors) can be fabricated using different designs of the physical layout between the gate structure and the doped material forming the drain and source regions. Specifically, the gate structure (e.g., gate electrode) can be fabricated as a single stripe on the doped region (e.g., a one-finger design) or multiple connected stripes (e.g., a multi-finger design), wherein the term "finger" (e.g., a transistor pair) refers to multiple such stripes. For example, a one-finger design may include a gate structure with a single stripe, a two-finger design may include a gate structure with two stripes, and so on. Multi-finger designs can be utilized for various reasons, including (but not limited to) controlling the physical layout size or gate resistance. Furthermore, multi-finger layouts can be used to fabricate devices with multiple connections, as will be described in more detail below.

[0050] Now for reference Figures 1A to 10 The present disclosure describes in more detail circuits, systems, and methods for bandwidth expansion using active inductors (e.g., inductor peaking) according to one or more embodiments.

[0051] Figure 1A This is a schematic diagram of a bandwidth extension circuit 100 according to one or more embodiments of the present disclosure. In some embodiments, the bandwidth extension circuit 100 includes a first driver (referred to herein as driver 102) connected in series with resistor 104 and inverter 106. Driver 102 may include any type of driver circuit known in the art, such as (but not limited to) a buffer or inverter (e.g., such as...). Figure 1A (As described in the text). Furthermore, inverter 106 may be (but is not limited to) an inverter. For example, resistor 104 may be connected between the output node of driver 102 and the input node of inverter 106. Bandwidth extension circuit 100 may further include switch 106 between the output node of inverter 106 and the output node of driver 102. In this configuration, the input node of bandwidth extension circuit 100 (V... in ) can correspond to the input node of driver 102, and the output node (V) of bandwidth extension circuit 100 out This can correspond to the output node of driver 102. Figure 1AThe load capacitor 108 is further described, which may be associated with various internal capacitances of components of the bandwidth extension circuit 100 (e.g., driver 102, inverter 106 and / or any additional components) and / or additional capacitors.

[0052] In a general sense, the bandwidth extension circuit 100 can be characterized as a driver circuit and can be adapted as a repeater to enhance the transmitted signal, which can be adapted to, but is not limited to, extending the transmission range of the signal.

[0053] The bandwidth extension circuit 100 may operate in different modes depending on the state of the switch 106 (e.g., whether the switch 106 is closed or open).

[0054] Operation of switch 106 in the closed state enables feedback across inverter 106. In this mode, referred to herein as the active mode, resistor 104 and inverter 106 can operate as a load for the active inductor 110 of driver 102. Such a bandwidth extension circuit 100 can be characterized as a parallel peaking driver using active inductor 110. This active inductor 110 can be adapted to provide inductance peaking to enhance the high-frequency gain of the bandwidth extension circuit 100. For example, a typical driver circuit containing only driver 102 may have a bandwidth limited by its drive resistor and load capacitance. However, this bandwidth can be achieved using a series peaking inductor (e.g., such as...) with a resonant frequency at or near the 3-dB bandwidth of the bandwidth extension circuit 100. Figure 1A The inductance peaking of the active inductor 110 (described herein) is increased. Specifically, in the bandwidth extension circuit 100, inductance peaking is generated by inducing a weaker, inverted, and delayed version of the signal at the output of the driver 102 using an inverter 106. For rapidly changing data, the inverter 106 does not have enough time to react, and the gain of the driver 102 may be large. For slowly changing data, the output of the inverter 106 competes with the output of the driver 102, thereby reducing its gain. Using an active inductor (e.g., Figure 1A The active inductor 110 in the middle can replace the passive inductor for inductance peaking, providing a compact solution that is compatible with digital circuit system manufacturing processes (e.g., CMOS process) and suitable for use on multiple bit lines.

[0055] The operation of switch 106 in the open state decouples the outputs of inverter 106 and driver 102. In this mode, referred to herein as the power-down mode, driver 102 and inverter 106 operate as two cascaded inverters without feedback between the corresponding output nodes. Therefore, the bandwidth extension circuit 100 does not provide active peaking in this power-down mode. However, this document considers that in this power-down mode (e.g., when V is applied...),... inWhen the input signal does not contain meaningful data, inductor peaking may not be necessary, and interrupting the feedback between inverter 106 and driver 102 can mitigate aging.

[0056] The bandwidth extension circuit 100 can be fabricated using any type of component known in the art. In some embodiments, the bandwidth extension circuit is fabricated using MOS components. For example, the driver 102 and / or the active inductor 110 may comprise CMOS transistors (e.g., complementary p-type and n-type MOSFET pairs). As another example, the switch 106 and / or the resistor 104 may be fabricated as MOS elements. However, in a general sense, any transistor technology or manufacturing process can be used to fabricate the components of the bandwidth extension circuit 100. For example, the components of the bandwidth extension circuit 100 may comprise (but are not limited to) FETs, MOSFETs, FinFETs, BJTs, JFETs, IGBTs, HEMTs, TFETs, CNTFETs, or JLNTs.

[0057] Figure 1B This section describes a bandwidth extension circuit 100 including CMOS components according to one or more embodiments of the present disclosure. In this configuration, the bandwidth extension circuit 100 may be a CMOS bandwidth extension circuit or a CMOS driver. Panel 112 depicts a schematic diagram of the bandwidth extension circuit 100 in an active operation mode when switch 106 is in the closed state. Panel 114 depicts a schematic diagram of the bandwidth extension circuit 100 in a power-off operation mode when switch 106 is in the open state.

[0058] exist Figure 1B In this context, the driver 102 consists of complementary transistor pairs (e.g., PMOS transistors (M... p ) and NMOS transistors (M n A CMOS inverter formed by two complementary transistor pairs (e.g., PMOS transistors, M...). Similarly, inverter 106 can also be a CMOS inverter formed by two complementary transistor pairs (e.g., PMOS transistors, M...). pa ) and NMOS transistors (M na A CMOS inverter is formed. In this configuration, the gates of the transistors in driver 102 are connected and provide the input node (V) of driver 102 and bandwidth extension circuit 100. in The output node (V) of driver 102 and bandwidth extension circuit 100 out The output node of inverter 106 is located between the drain of the PMOS transistor and the drain of the NMOS transistor. Similarly, the gate of the transistor in inverter 106 is connected and provides the input node of the inverter, while the output node of inverter 106 is located between the drain of the PMOS transistor and the drain of the NMOS transistor.

[0059] Now for reference Figures 2A to 4BThe inductance peaking and aging performance of active inductors are described in more detail according to one or more embodiments of this disclosure. Although Figures 2A to 4B The associated description focuses on the bandwidth extension circuit 100 implemented using CMOS components, but Figures 2A to 4B The descriptions and related information provided herein are for illustrative purposes only and should not be construed as limiting. Specifically, the systems and methods disclosed herein are suitable for anti-aging operation of active inductors in any suitable application.

[0060] Figure 2A This is a schematic diagram of a conventional CMOS bandwidth extension circuit 202 including an active inductor 110, according to one or more embodiments of the present disclosure. The bandwidth extension circuit 202 is similar to... Figure 1B The bandwidth extension circuit 100 in the circuit is identical except that the switch 106 is absent. In this circuit, the input voltage V... in The driver 102 inverts the phase to generate V. d Then V g Corresponding to V through resistor 104 d The delayed version is provided as the input to inverter 106. The output node of inverter 106 is then connected back to V. d As a feedback loop. Therefore, V d It is also the output node (V) of the bandwidth extension circuit 202. out Furthermore, V g Transistor M corresponding to inverter 106 pa and M na The gate voltage, while V d Transistor M corresponding to inverter 106 pa and M na The drain voltage. Considering this bandwidth extension circuit 202 may help in a general understanding. Figure 1B The operation of the CMOS bandwidth extension circuit 100 in the circuit can be further provided for evaluation. Figure 1B The baseline for the performance and aging characteristics of the bandwidth extension circuit 100 in the circuit is established. This allows for a better understanding of... Figure 1B The effects of switch 106 and the various associated benefits of bandwidth extension circuit 100.

[0061] Figure 2B It is a response to an input signal according to one or more embodiments of this disclosure. Figure 2A The voltage curves at each node of the bandwidth extension circuit 202 in the diagram. Specifically, Figure 2B Explain the voltage V during various transitions. d and V g Specifically, Figure 2B Specify the bit pattern (i.e., bit pattern), where V dFor a number of repeating bits, it is high (range 204), for a number of repeating bits, it is low (range 206), and then for a single bit, it is high (range 208). Figure 2B Further explanation when V d and V g Both are driven high (e.g., in the case of repeating bits) V d The inductor peaking voltage 210 (e.g., the difference between the peak voltage value 212 and the equilibrium voltage value 214).

[0062] The feedback loop of the active inductor 110 is connected back to the output node (V) of the driver 102. d The driver 102 generates a weaker, inverted, and delayed version of the data at its output. This is in Figure 2B The term V is defined as the transition from low to high and from high to low. g With V d The time delay between them. V g and V d The value then reaches equilibrium after a settling time, which can be achieved in the case of repeated bits.

[0063] As previously described, two significant sources of MOSFET transistor aging include high-current interference (HCI) and bottom-tier oscillation (BTI). HCI typically occurs when a transistor experiences a large current associated with simultaneously driving both the drain and gate voltages of an NMOS device high (or low for a PMOS device). Under these HCI aging conditions, charge can become trapped in the transistor's gate, resulting in reduced carrier mobility and current capacity. BTI is typically induced when the gate voltage is driven high for an NMOS device (or low for a PMOS device) for an extended period, especially at relatively high temperatures, leading to trapped charge and an increased operating voltage threshold. In many cases, the structural effects of BTI diminish once the BTI aging conditions are no longer present. In contrast, the structural effects of HCI typically do not diminish and accumulate slowly with increasing exposure to HCI aging conditions.

[0064] This article has been considered, Figure 2A The bandwidth extension circuit 202 described herein is susceptible to both HCI and BTI aging conditions.

[0065] For example, simultaneously V during the extended duration g and V d The drive is high, corresponding to the HCI aging condition in inverter 106, which shortens the operating lifetime of bandwidth extension circuit 202. Specifically, it simultaneously increases V... g and V d Both are driven by transistor M, which corresponds to inverter 106. pa and Mna High gate and drain voltages. Exposure to these conditions induces HCI, which increases the threshold voltage of these transistors and reduces current flow. Figure 2B As explained in the paper, these HCl aging conditions include V d This is most evident in the range of 204 where repeating bits are driven high (e.g., relatively low-frequency data patterns [e.g., bit patterns]).

[0066] This paper considers that the values ​​and / or sizes of various components in the bandwidth extension circuit 202 can affect both the duration of HCI aging conditions and inductor peaking performance. For example, the relatively large value of resistor 104 and / or the size ratio (S) of inverter 106 to driver 102... act / S main A relatively large value of the inductance provides relatively high inductance peaking and slower aging. In most cases, the inverter 106 is smaller than the driver 102 to provide feedback without overpowering the driver 102. Therefore, there may be a trade-off between the amount of peaking introduced by the active inductor 112 and how fast it ages. However, in most cases, the required amount of peaking is predetermined by the communication channel conditions and cannot be adjusted to improve other circuit aspects such as aging.

[0067] Furthermore, increasing the size of inverter 106 (S act This will increase the inductor peaking voltage 210 and also reduce the duration of HCI aging conditions and the predicted aging effects. However, the size of inverter 106 cannot be increased without limitation to completely mitigate aging. For example, the size ratio of inverter 106 to driver 102 can be selected to provide the desired amount of inductor peaking (e.g., the desired inductor peaking voltage 210) for the desired bandwidth improvement without otherwise degrading performance. As an illustration, at the high V for the repetitive bit d In the case of values ​​(e.g., range 204), inductor peaking causes a decrease in the equilibrium voltage value 214 relative to the peak voltage value 212, but when V d When a single bit is driven high (e.g., range 208), the variation is relatively small. Therefore, excessive inductance peaking can result in significantly lower V for repeating high bits relative to a single high bit. d Level, which may negatively affect noise and / or transmission performance metrics.

[0068] Therefore, the existence of HCI aging conditions is a direct result of using the active inductor 110 design to provide inductance peaking. Furthermore, when no data is input to the bandwidth extension circuit 202 (e.g., the constant V), in ), making V d and V g When constant over a prolonged period of time, especially when Vd and V g Aging is likely to be most severe when the level is maintained at a high level for an extended period of time.

[0069] In some scenarios, Figure 2A The bandwidth extension circuit 202 described herein is further susceptible to BTI aging conditions. For example, whenever V in When kept constant, the transistors within driver 102 and / or inverter 106 may be exposed to BTI aging conditions because regardless of V in Regardless of the specific value, the gate voltage of either driver 102 or inverter 106 will be high. Since BTI aging is largely reversible, it can be mitigated by frequently switching the input signal V. in To alleviate Figure 2A BTI aging in the bandwidth extension circuit 202.

[0070] However, it should be noted that the bandwidth extension circuit 202 is not conducive to simultaneously mitigating both HCI and BTI.

[0071] This paper considers that bandwidth extension circuits (e.g., bandwidth extension circuit 202, bandwidth extension circuit 100, driver circuits, etc.) can typically operate under at least two conditions, referred to herein as runtime conditions and downtime conditions. Under runtime conditions, the input node (V... in The signal can typically be modulated using data (e.g., high and low bit patterns, or other bit patterns), and the bandwidth is extended at the output node (V). out The signal provided at the input node (V) can be supplied to and utilized by external devices or systems. During downtime, the bandwidth extension circuit can be connected to the power supply, but the signal applied to the input node (V) remains constant. in The signal may not typically contain meaningful data, and is extended by bandwidth expansion circuitry at the output node (V). out The signal provided at the input node (V) is typically unusable by external devices or systems. Under this downtime condition, the signal applied to the input node (V) in Signals can typically have any value, including (but not limited to) fixed or floating values. For example, in communication systems, downtime conditions may occur between data streams or when the device is in standby mode.

[0072] As a note related to the bandwidth extension circuit 202, BTI aging can typically be achieved via the input signal V. in To alleviate the frequent switching when V in When a signal is modulated with data for transmission, this can occur naturally during runtime (or runtime conditions). Furthermore, when V... inWhen the input signal V does not contain a signal modulated for transmission (referred to herein as downtime or downtime condition), the input signal V may be intentionally switched. in However, whenever V d and V g When both NMOS devices are simultaneously high or both PMOS devices are simultaneously low, the bandwidth extension circuit 202 suffers from HCI aging. For example... Figure 2B As explained in the text, when V d When a single bit is driven high or low (e.g., range 208), or when V d This can occur at least briefly when multiple repeating bits are driven high or low (e.g., ranges 204 and 206). Therefore, when V in When the signal does not contain data (or at least meaningful data) modulated for transmission, the input signal V is switched during the downtime. in It can alleviate BTI but not HCI. Alternatively, V can be used during downtime. in Forced to a low or high value, while V g Forcing the feedback resistor 104 to the same value and disconnecting it via an external power-off switch can mitigate the HCI in the inverter 106, but the driver 102 may experience BTI.

[0073] Current general reference Figure 1A , 1B The aging characteristics of the bandwidth extension circuit 100 including switch 106 are described in more detail according to one or more embodiments of this disclosure, 2A, 2B, and 3A to 4B. It has been considered that the bandwidth extension circuit 100 including switch 106, as disclosed herein, can achieve operation of the bandwidth extension circuit 100 in a manner that mitigates the aging of constituent components (e.g., inverter 106). For example, the circuits, systems, and methods disclosed herein implement control over the frequency and / or duration of operation of transistors within the bandwidth extension circuit 100 under aging conditions (e.g., but not limited to, HCI or BTI aging conditions). Therefore, the operating lifetime of the bandwidth extension circuit 100 disclosed herein can be significantly longer than that of alternative bandwidth extension circuits (e.g., but not limited to...). Figure 2A The operating life of the design described herein.

[0074] Specifically, Figure 1A and 1B The switch 106 in the bandwidth extension circuit 100 described herein enables the bandwidth extension circuit 100 to operate in two modes: an active mode in which switch 106 is in the closed state (see example...). Figure 1B The power-off mode (see example, left panel 112) and its switch 106 are in the off state. Figure 1B(Right panel 114). HCI and / or BTI can be alleviated in each of these modes.

[0075] For example, when the input signal V in When modulation data is not included, the power-off mode is suitable for (but not limited to) operation during downtime. In this configuration, such as Figure 1B As illustrated in the right panel 114, the switch 106 in the open state interrupts the feedback across the inverter 106. Specifically, the output of the inverter 106 is connected to the first node (n) of the switch 106. a ), and V d (also V) out ) connected to the second node (n) of switch 106 b In this configuration, driver 102 and inverter 106 are simply two cascaded inverters, such that V d and V g By avoiding simultaneous high or low values, this mitigates HCI aging in both NMOS and PMOS device types. Although the feedback interrupt does not provide inductor peaking in this power-down mode, when the input signal V... in Inductor peaking is not required when no modulation data is included. Furthermore, the input signal V can be artificially modulated in power-off mode. in This mitigates BTI. Therefore, in this power-down mode, both HCI and BTI are mitigated. It should be noted that any suitable mode (e.g., bit mode) can be used to modulate the input signal (V). in ), including (but not limited to) alternating high and low bits, high and low bits of random series, high and low bits of pseudo-random series, or high and low bits of preselected series.

[0076] As another example, when the input signal V in When using data modulation, the activity mode can be adapted to (but is not limited to) operation during runtime. In this case, the input signal (V) in BTI can be largely mitigated by using the inherent modulation of the data. Furthermore, this is achieved by the transistor M across inverter 106. na and M pa The voltage drop of the series-connected switch 106 (e.g., in n) a With V d (between) can be in V d When driven high, transistor M decreases na The drain voltage (or in V) d When driven low, transistor M decreases pa This reduces the severity and / or duration of HCI aging conditions for the transistor, even during operating time conditions, relative to, for example (but not limited to) Figure 2AIn the alternative design described herein, HCI can also be partially mitigated. Furthermore, since switch 106 is connected in series with resistor 104 and directly contributes to inductance peaking, this voltage drop across switch 106 (e.g., associated with the resistance of switch 106) can not be considered parasitic. Additionally, in the case of a transistor implementation of this resistor, this switch can be systematically implemented as a segment of feedback resistor 104 by utilizing finger partitions.

[0077] In summary, both active and power-off operation modes can provide anti-aging operation for the bandwidth extension circuit 100, thereby extending the operating life of the bandwidth extension circuit 100.

[0078] Now for reference Figures 3A to 4B ,Compare Figure 1B The simulated aging performance of the bandwidth extension circuit 100 in the middle and Figure 2A The bandwidth extension circuit 202 in the middle.

[0079] Figure 2A The conventional bandwidth extension circuit 202 in the circuit exhibits the most severe aging under downtime conditions, while Figure 1B The anti-aging bandwidth extension circuit 100 in the circuit did not exhibit detectable aging effects (or were negligible) under the same conditions. Furthermore, although... Figure 1B The anti-aging bandwidth extension circuit 100 exhibits some detectable aging in runtime mode, but compared to Figure 2A The effect is significantly reduced by the conventional bandwidth extension circuit 202 in the circuit.

[0080] Figures 3A to 4B Depicting Figure 1B The bandwidth expansion circuit 100 and Figure 2A The analog eye diagram of the bandwidth extension circuit 202 before and after aging. Figure 3A It is a state of newness (e.g., before aging) according to one or more embodiments of this disclosure. Figure 1B Eye diagram of bandwidth extension circuit 100 in the circuit. Figure 3B According to one or more embodiments of this disclosure Figure 1B The eye diagram of the bandwidth extension circuit 100 after 10 years of aging. Figure 4A It is a state of newness (e.g., before aging) according to one or more embodiments of this disclosure. Figure 2A Eye diagram of bandwidth extension circuit 202 in the circuit.

[0081] Figure 4B According to one or more embodiments of this disclosure Figure 2A The eye diagram of the bandwidth extension circuit 202 after 10 years of aging.

[0082] like Figure 3A and3B As explained in the text, Figure 1B The eye diagram of the anti-aging bandwidth extension circuit 100 in the simulation showed only minor changes after 10 years of aging, indicating that the operating characteristics and associated noise metrics remained relatively unchanged. Conversely, as... Figure 4A and 4B As explained in the text, Figure 2A The eye diagram of the conventional bandwidth extension circuit 202 in the simulation showed significant degradation after 10 years of aging. For example, Figure 4B The eye diagram revealed a significant decrease in signal-to-noise ratio and a significant increase in time variation.

[0083] Now for reference Figure 5 , Figure 5 This is a block diagram of a system 502 including bandwidth extension circuitry 100 according to one or more embodiments of this disclosure. It is contemplated herein that bandwidth extension circuitry 100 can be implemented in any communication system, including (but not limited to) high-speed transceiver systems (e.g., wired transceiver systems). For example, bandwidth extension circuitry 100 can be implemented in systems such as (but not limited to) SERDES systems (e.g., backplane SERDES systems), physical layer transceivers (PHYs) (e.g., Ethernet PHYs), optical communication modules (e.g., pluggable optical communication modules), or coherent communication circuitry. In this way, system 502 is generally suitable for a wide variety of applications and services, such as (but not limited to) network switches, data center interconnects, coherent telecommunications solutions, high-speed PHY devices, or wireless base stations.

[0084] In some embodiments, system 502 includes one or more bandwidth expansion circuits 100 and a controller 504 for controlling the operating state of the bandwidth expansion circuits 100. For example, controller 504 may be communicatively coupled to the bandwidth expansion circuits 100 to control (e.g., via drive signals) whether the bandwidth expansion circuits are in an active mode or a power-off mode. In some embodiments, controller 504 provides individual control over each of the bandwidth expansion circuits 100. In this way, some bandwidth expansion circuits 100 may be in an active mode while others may be in a power-off mode. In some embodiments, controller 504 controls all bandwidth expansion circuits 100 together such that each of the bandwidth expansion circuits 100 operates in the same mode.

[0085] The bandwidth extension circuit 100 can be arranged in any suitable configuration. In some embodiments, two or more bandwidth extension circuits 100 are arranged along the transmission path to facilitate data integrity along the transmission path within the desired transmission distance. In some embodiments, two or more bandwidth extension circuits 100 are arranged along different transmission paths corresponding to different communication channels. In this way, system 502 can provide or facilitate multi-channel communication. It should be understood that these examples are merely illustrative and not intended to limit the scope of this disclosure.

[0086] As a response Figure 1B The description of the bandwidth expansion circuit 100 is non-limiting, and the controller 504 can be connected to the switch 106 of the bandwidth expansion circuit 100. In this way, the controller 504 can direct a specific bandwidth expansion circuit 100 to operate in an active mode (e.g., as shown) by directing the switch 106 to a closed state. Figure 1B (as depicted in the left panel 112) and / or by directing the component switch 106 to be in the closed state to guide the specific bandwidth extension circuit 100 to operate in power-off mode (e.g., as shown ... Figure 1B (As depicted in the right panel 114).

[0087] The controller 504 may have any architecture suitable for selectively modifying the state of the bandwidth extension circuit 100 or the switch 106. In some embodiments, the controller 504 includes one or more processors configured to execute program instructions. Further, the program instructions may be stored on a memory device, such as (but not limited to) read-only memory (ROM), random access memory (RAM), or a solid-state drive. For example, the controller 504 may include any type of processing or logic circuitry system, such as (but not limited to) a microprocessor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a digital signal processor (DSP).

[0088] In some embodiments, system 502 further includes providing one or more signals (e.g., input signal V) to bandwidth extension circuit 100. in Source 506. Source 506 may provide the same signal to each bandwidth extension circuit 100, or provide different signals to different bandwidth extension circuits 100. In some embodiments, one or more signals are received from an external system or device. For example, a signal containing modulated data may be received from any location containing source 506 or an external system.

[0089] In some embodiments, when the signal directed to the bandwidth extension circuit 100 contains data, the controller 504 directs the bandwidth extension circuit 100 to operate in an active mode (e.g., as...). Figure 1B(As depicted in the left panel 112). As previously described herein, such a scenario may be referred to as a runtime condition. For example, such a signal may contain high and low bits (e.g., high and low voltage values) associated with data encoded using any technique known in the art. This signal can then be transmitted to an external device or system.

[0090] In some embodiments, when the signal directed to the bandwidth extension circuit 100 does not contain data, the controller 504 directs the bandwidth extension circuit 100 to operate in a power-off mode (e.g., as...). Figure 1B (As depicted in the right panel 114). As previously described herein, such a scenario may be referred to as a downtime condition. Under this condition, power may be supplied to the bandwidth extension circuit 100 (e.g., via one or more power sources not explicitly stated), but the signals supplied to the bandwidth extension circuit 100 may not have any meaningful data for transmission. Therefore, operation in the power-down mode can mitigate HCI, as previously described herein.

[0091] In some embodiments, source 506 provides an arbitrary signal to bandwidth extension circuit 100 in a power-down mode, wherein the arbitrary signal comprises multiple transitions between high and low values ​​to mitigate bandwidth transition in bandwidth extension circuit 100, as previously described herein. This arbitrary signal may have any pattern of high and low bits (e.g., high and low voltages), including (but not limited to) alternating patterns of high and low bits at any frequency and / or duty cycle, random series of high and low bits, pseudo-random series of high and low bits, or predefined series of high and low bits.

[0092] Figure 6 This is a flowchart illustrating the steps performed in method 600 for designing a circuit (e.g., a bandwidth extension circuit) according to one or more embodiments of this disclosure. The applicant notes that the embodiments and enabling techniques previously described herein in the context of bandwidth extension circuit 100 should be interpreted as extending to method 600. However, it should be further noted that method 600 is not limited to the architecture of bandwidth extension circuit 100.

[0093] It should be understood that Method 600 is not limited to Figure 6 The specific steps depicted. In some embodiments, method 600 includes additional steps that may be performed before, after, and / or between any of the depicted steps. In some embodiments, no additional steps are performed. Figure 6 All the steps described in the document.

[0094] In some embodiments, method 600 includes step 602 of designing a circuit (e.g., a bandwidth extension circuit, a driver circuit, a device, etc.) to include a driver 102 having a first bandwidth, an inverter 106, and a resistor 104 connected between the output node of the driver 102 and the input node of the inverter 106. In this configuration, the input node of the driver 102 may correspond to the input node of the circuit, and the output node of the driver may correspond to the output node of the circuit. Bandwidth may be the maximum transmission rate of an electronic signal (e.g., data or current). In this way, a larger (e.g., extended) bandwidth (e.g., provided by bandwidth extension) may refer to a larger maximum transmission rate of the electronic signal.

[0095] Resistor 104 may have any design suitable for the selected manufacturing process. In some embodiments, resistor 104 includes two or more transistors (e.g., MOSFET transistors or any other suitable transistors) having a common gate electrode. For example, resistor 104 may include multi-finger gate electrodes distributed throughout one or more doped semiconductor regions.

[0096] As an explanation, the circuit associated with step 602 may correspond to Figure 2A The bandwidth extension circuit 202 is depicted in the figure. Figure 7A This is a simplified schematic diagram of an active inductor 110 according to one or more embodiments of the present disclosure, which is formed as shown below. Figure 2A The inverter 106 and resistor 104 are depicted in the bandwidth extension circuit 202. For example, Figure 7A The configuration of resistor 104 having four transistor pairs 702a to d is described, each of which is formed as a MOSFET transistor arranged to provide current flow having a specified resistance (e.g., a level opposite to the current flow). For illustration, the four transistor pairs 702a to d may be formed by a common gate electrode having multiple series fingers (e.g., as a multi-finger device).

[0097] In some embodiments, method 600 includes step 604 of selecting at least one of the values ​​of resistor 104, the size of driver 102, or the size of inverter 106 in the design of the circuit such that the circuit has a second bandwidth greater than the first bandwidth.

[0098] Figure 7B This is a graph of curve 704 showing the voltage at the output node of a bandwidth extension circuit for a series of bits, according to one or more embodiments of this disclosure. Specifically, Figure 7B Corresponding to high digit, low digit, high digit, low digit, high digit of repeating series, low digit of repeating series, and high digit.

[0099] Inductance peaking Figure 7BThis is evident in the curve, especially in the repeating high points of the series. For example, the transition to the high point of the series shows a peak voltage value of 706, which decays to a balance voltage value of 708.

[0100] This document considers that in step 602, inductor peaking can be characterized by any suitable metric, such as (but not limited to) the inductor peaking voltage 710 associated with the difference between the peak voltage value 706 and the equilibrium voltage value 708.

[0101] In some embodiments, method 600 includes a step 606 of converting at least one of two or more transistors in resistor 104 into switch 106 in the circuit design, wherein a first node of switch 106 is connected to the output node of inverter 106, a second node of switch 106 is connected to the output node of driver 102, and the circuit has a third bandwidth less than a second bandwidth. For example, this can be achieved by isolating the gate electrode of the transistor forming switch 106 from the other transistors forming resistor 104 and connecting the output node (V) of active inductor 110. out From node n a Move to the output node provided to drive 102 (e.g.) Figure 1B V in d The nodes connected to ) b This is to perform the conversion of at least one of two or more transistors in resistor 104 into switch 106. As an illustration in the case where resistor 104 is formed as a multi-finger device, step 606 can be performed by supplying power to the output node (V) of driver 102. d The output node (V) of the connection out Move one finger to the left to execute.

[0102] Figure 8A According to one or more embodiments of this disclosure Figure 7A A simplified schematic diagram of the active inductor 110, in which a transistor pair 702a of resistor 104 is converted into a switch 106. For example, Figure 8A This explains how to output the node (V) out Move one finger to the left to connect to the output (V) of driver 102. d ) and modified gate node 802 (described as pd and pd) b To provide control over the state of switch 106 (e.g., via such as Figure 5 The controller 504 depicted converts the transistor pair 702a into a switch 106. In this way, the switch 106 can be operated in an open or closed state based on the control signal provided to the gate node 802.

[0103] Figure 8BIt is included according to one or more embodiments of this disclosure. Figure 7B Add explanation based on Figure 8A The output node of the bandwidth extension circuit of the active inductor 110 in the design (e.g., Figure 1B V in out The additional voltage curve at point ) is plotted as curve 804. Figure 8B As explained, converting at least one of the transistors in resistor 104 into switch 106 can reduce the inductance peak voltage 210.

[0104] In some embodiments, method 600 includes step 608 of adding one or more additional transistors to resistor 104 in the circuit design. For example, this could be done at the output (V) of the circuit connected to driver 102. d ) output node (V out ) and the input node (V) of inverter 106 g Add one or more additional transistors between nodes n. This can provide recovery of some of the lost peaking from step 606. As an illustration in the case where resistor 104 is formed as a multi-finger device, step 606 can be achieved by adding one or more additional fingers in series to node n. b With V g The resistor 104 is used to perform this action.

[0105] Figure 9 It is included according to one or more embodiments of this disclosure. Figure 8B Add explanation based on Figure 9 The output node of the bandwidth extension circuit of the active inductor 110 in the design (e.g., Figure 1B V in out The additional curve 902 of the voltage at point ) is shown in the graph. Figure 9 As explained in the paper, a portion of the inductor peak voltage 710 is recovered by adding transistor pair 702e.

[0106] In some embodiments, method 600 includes step 610 of increasing the size of switch 106 in the circuit design to provide the circuit with a second bandwidth. The size of switch 106 may be increased by any amount suitable for recovering additional inductance peaking. In some embodiments, step 610 includes doubling the size of switch 106. In some embodiments, step 610 includes increasing the number of fins of one or more transistors in switch 106. For example, switch 106 may include one or more finned FET transistors, wherein the doped semiconductor region is formed to be at least partially surrounded by one or more fins of a gate electrode. The width of a finned FET transistor depends on the number of its fins and is generally expressed in the format n×m, where n represents the number of fingers and m represents the number of fins per finger. As an illustration, if transistor pairs 702a to e (e.g., associated with steps 602 to 608) are formed as 1x3 finned devices, then step 610 may include converting transistor pair 702a associated with switch 106 into a 2x3 finned device. In this configuration, the inverter 106 can be any suitable size and includes (but is not limited to) a 2x3 finned device. Figure 10 It is included according to one or more embodiments of this disclosure. Figure 9 Add an additional curve 1002 showing the voltage at the output node of the bandwidth extension circuit based on the active inductor 110 design after increasing the size of switch 106. (See also...) Figure 10 As explained, the inductance peaking is restored (e.g., as measured by the inductance peaking voltage 710). Therefore, the designed circuit including switch 106 (e.g., Figure 1B The bandwidth extension circuit 100 described herein may have the same or substantially the same inductance peaking performance as a conventional bandwidth extension circuit 202 without switch 106, while providing anti-aging operation and corresponding longer operating life without causing any considerable bandwidth loss.

[0107] In some embodiments, although not explicitly shown, method 600 includes steps of designing and manufacturing a circuit based on circuitry. The circuitry and its components can be manufactured using any technology or manufacturing process known in the art. In this manner, the constituent transistors may include (but are not limited to) CMOS transistors, FET transistors, or BJT transistors.

[0108] It should be noted that the figures described herein (e.g., Figure 7B , 8B None of the figures (9 and 10) directly state a bandwidth value. Instead, the figures illustrate inductance peaking, which can affect bandwidth and is used as a bandwidth extension technique.

[0109] The objects described herein sometimes refer to different components contained within or connected to other components. It should be understood that such depicted architectures are merely exemplary, and many other architectures can in fact be implemented to achieve the same functionality. Conceptually, any arrangement of components that achieve the same functionality is effectively “associated” to achieve the desired functionality. Therefore, any two components combined herein to achieve a particular function can be considered “associated” with each other to achieve the desired functionality, regardless of the architecture or intermediate components. Similarly, any two such associated components can also be considered “connected” or “coupled” to each other to achieve the desired functionality, and any two components that can be suchly associated can also be considered “coupled” to each other to achieve the desired functionality. Specific examples of coupling include (but are not limited to) physically interactive and / or physically interactive components and / or wirelessly interactive and / or logically interactive and / or logically interactive components.

[0110] It is believed that this disclosure and many of its accompanying advantages will be understood from the foregoing description, and it will be apparent that various changes can be made to the form, construction, and arrangement of the components without departing from the subject matter of the disclosure or sacrificing all its significant advantages. The forms described are merely illustrative, and the following claims are intended to cover and encompass such changes. Furthermore, it should be understood that the invention is defined by the appended claims.

Claims

1. A circuit comprising: drive; Inverter; A resistor is located between the output node of the driver and the input node of the inverter, wherein a first node of the resistor is connected to the output node of the driver, and a second node of the resistor is connected to the input node of the inverter; and A switch, located between the output node of the inverter and the first node of the resistor, wherein the input node of the driver corresponds to the input node of the circuit, and wherein the output node of the driver corresponds to the output node of the circuit; The closed state of the switch enables feedback across the inverter, in which the inverter and the resistor operate as an active inductor configured to provide high-frequency gain associated with the inductance peaking of the active inductor.

2. The circuit of claim 1, wherein operation of the switch in the closed state couples the output node of the inverter to the output node of the driver.

3. The circuit of claim 2, wherein operation of the switch in the closed state provides bandwidth extension for the signal provided to the input node of the circuit.

4. The circuit of claim 3, wherein at least one of the sizes of one or more transistors in the driver, one or more transistors in the inverter, or the resistance of the resistor is selected to provide the bandwidth extension.

5. The circuit of claim 1, wherein operation of the switch in the open state decouples the output node of the inverter from the output node of the driver.

6. The circuit of claim 1, wherein the resistor is formed as one or more transistors, and wherein the switch is formed as one or more additional transistors connected in series with the resistor.

7. The circuit of claim 1, wherein at least one of the driver, the inverter, the resistor, or the switch comprises at least one of a field-effect transistor (FET), a metal-oxide-semiconductor (MOSFET) transistor, a fin FET transistor, a bipolar junction transistor (BJT), a junction field-effect transistor (JFET), an insulated gate bipolar transistor (IGBT), a high electron mobility transistor (HEMT), a tunneling field-effect transistor (TFET), a carbon nanotube FET (CNTFET), or a junctionless nanowire transistor (JLNT).

8. A system comprising: One or more circuits, each of which includes: drive; Inverter; A resistor connected between the output node of the driver and the input node of the inverter, wherein a first node of the resistor is connected to the output node of the driver, and a second node of the resistor is connected to the input node of the inverter; and A switch, located between the output node of the inverter and the first node of the resistor, wherein the input node of the driver corresponds to the input node of the circuit, and wherein the output node of the driver corresponds to the output node of the circuit; and A controller coupled to one or more circuits, wherein the controller causes the switch in each of the one or more circuits to operate in either an open or closed state. The closed state of the switch enables feedback across the inverter, in which the inverter and the resistor operate as an active inductor configured to provide high-frequency gain associated with the inductance peaking of the active inductor.

9. The system of claim 8, wherein when a signal applied to the input node of a particular one of the one or more circuits is modulated by data, the controller causes the switch of the particular one of the one or more circuits to operate in the closed state, wherein the controller directs the switch of the particular one of the one or more circuits to operate in the open state in other ways.

10. The system of claim 9, wherein operation of the switch of the particular one of the one or more circuits in the closed state couples the output node of the inverter to the output node of the driver.

11. The system of claim 9, wherein the operation of the switch of the particular one of the one or more circuits in the closed state provides bandwidth extension for the signal applied to the input node of the particular one of the one or more circuits.

12. The system of claim 9, wherein operation of the switch in the off state decouples the output node of the inverter from the output node of the driver.

13. The system of claim 9, further comprising: A source, communicatively coupled to the controller, wherein when the switch of one of the circuits is in the open state, the controller directs the source to provide a signal having a selected bit pattern to the one of the circuits.

14. The system of claim 13, wherein the selected bit mode comprises: At least one of alternating high and low digits, high and low digits of a random series, or high and low digits of a pseudo-random series.

15. The system of claim 9, wherein at least one of the driver, the inverter, the resistor, or the switch of the particular one of the one or more circuits comprises at least one of a field-effect transistor (FET), a metal-oxide-semiconductor (MOSFET) transistor, a finned FET transistor, a bipolar junction transistor (BJT), a junction field-effect transistor (JFET), an insulated gate bipolar transistor (IGBT), a high electron mobility transistor (HEMT), a tunneling field-effect transistor (TFET), a carbon nanotube FET (CNTFET), or a junctionless nanowire transistor (JLNT).

16. The system of claim 9, wherein the resistor is formed as one or more transistors, and wherein the switch is formed as one or more additional transistors connected in series with the resistor.

17. A circuit comprising: drive; Inverter; A resistor is located between the output node of the driver and the input node of the inverter, wherein a first node of the resistor is connected to the output node of the driver, and a second node of the resistor is connected to the input node of the inverter; and A switch, located between the output node of the inverter and the first node of the resistor, wherein the input node of the driver corresponds to the input node of the circuit, and wherein the output node of the driver corresponds to the output node of the circuit; The closed state of the switch enables feedback across the inverter, in which the inverter and the resistor operate as an active inductor configured to provide high-frequency gain associated with the inductance peaking of the active inductor. The open state of the switch decouples the output of the inverter from the driver, and in the open state, the inverter and the driver operate as cascaded inverters without feedback.

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