Display panel and display device
By setting up multiple transmission channels between the level conversion circuit and the scan drive circuit and switching the clock signal transmission path, the problem of heat generation and damage when the display panel transmits clock signals is solved, and the protection capability of the circuit is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HKC CORP LTD
- Filing Date
- 2023-12-07
- Publication Date
- 2026-05-01
AI Technical Summary
Existing display panels are prone to overheating and circuit damage when transmitting clock signals, especially under high current conditions.
First and second transmission channels are set between the level conversion circuit and the scan drive circuit, and the clock signal is switched between different transmission channels by the control unit to avoid overload of a single channel.
It effectively avoids heat generation when transmitting clock signals and prevents damage to the circuit from high current, thus improving the circuit's protection capabilities.
Smart Images
Figure CN117524071B_ABST
Abstract
Description
Display panel and display device Technical Field
[0001] This application relates to the field of display technology, and more particularly to display panels and display devices. Background Technology
[0002] Display panels typically include an array substrate and a counter substrate, which are positioned opposite each other to control the light emitted by the pixel units on the array substrate for image display. By placing the scanning drive circuitry used to control the image display of the pixel units on the array substrate, the space occupied by the control circuit board is reduced.
[0003] However, when the scanning drive circuit receives the clock signal to control the pixel units for image display, the clock signal current is relatively large, causing the lines transmitting the clock signal to often overheat. If a short circuit occurs in any part of the line, resulting in a large current, it can easily damage the circuit. Therefore, how to effectively prevent the lines transmitting the clock signal from overheating and burning out is an urgent problem to be solved. Summary of the Invention
[0004] In view of the shortcomings of the prior art, this application provides a display panel and display device that can effectively avoid circuit overheating.
[0005] This application provides a display panel, including a level conversion circuit, a first scan driving circuit, and multiple pixel units. The level conversion circuit is electrically connected to the first scan driving circuit to output a clock signal. The first scan driving circuit controls the pixel units to receive data signals for image display based on the clock signal to perform image display. The display panel also includes a first control unit, a first transmission channel, and a second transmission channel. The level conversion circuit is connected to the first scan driving circuit through the first control unit and the first transmission channel, and is also connected to the first scan driving circuit through the first control unit and the second transmission channel. The first control unit controls the clock signal output by the level conversion circuit to prevent it from being simultaneously transmitted to the first scan driving circuit via the first transmission channel and the second transmission channel.
[0006] Optionally, the first control unit is connected to the control signal terminal. When the control signal terminal outputs a first control signal, the first control unit controls the clock signal to be transmitted to the first scan drive circuit via the first transmission channel. When the control signal terminal outputs a second control signal, the first control unit controls the clock signal to be transmitted to the first scan drive circuit via the second transmission channel.
[0007] Optionally, during any adjacent first frame image display period and second frame image display period, the control signal terminal outputs a first control signal during the first frame image display period and outputs a second control signal during the second frame image display period.
[0008] Optionally, in any adjacent first time period and second time period, in the first time period, the control signal terminal outputs a first control signal, and in the second time period, the control signal terminal outputs a second control signal. The duration of the first time period is the duration of displaying m frames of images, and the duration of the second time period is the duration of displaying n frames of images, where m>1 and n>1.
[0009] Optionally, the first control unit includes a first switching transistor and a second switching transistor. The gate of the first switching transistor is connected to a control signal terminal, the source of the first switching transistor is connected to a level conversion circuit via a first transmission channel, and the drain of the first switching transistor is connected to a first scan driving circuit via the first transmission channel. The first switching transistor is turned on when a first control signal is received, so as to control the clock signal to be transmitted to the first scan driving circuit via the first transmission channel. The gate of the second switching transistor is connected to a control signal terminal, the source of the second switching transistor is connected to a level conversion circuit via a second transmission channel, and the drain of the second switching transistor is connected to the first scan driving circuit via the second transmission channel. The second switching transistor is turned on when a second control signal is received, so as to control the clock signal to be transmitted to the first scan driving circuit via the second transmission channel.
[0010] Optionally, the display panel further includes a second scan driving circuit, a second control unit, a third transmission channel, and a fourth transmission channel. The level conversion circuit is connected to the second scan driving circuit through the second control unit and the third transmission channel. The level conversion circuit is also connected to the second scan driving circuit through the second control unit and the fourth transmission channel. The second control unit is used to control the clock signal output by the level conversion circuit to not be transmitted to the second scan driving circuit simultaneously through the first transmission channel and the second transmission channel.
[0011] Optionally, when the control signal terminal outputs the first control signal, the control clock signal of the second control unit is transmitted to the second scan drive circuit via the third transmission channel; when the control signal terminal outputs the second control signal, the control clock signal of the second control unit is transmitted to the second scan drive circuit via the fourth transmission channel.
[0012] Optionally, when the scanning drive circuit or the second scanning drive circuit controls the pixel unit to display an image, during any adjacent first frame image display period and second frame image display period, the control signal terminal outputs a first control signal during the first frame image display period and outputs a second control signal during the second frame image display period.
[0013] Optionally, when the scanning drive circuit and the second scanning drive circuit simultaneously control the pixel unit to display images, in the adjacent first time period and second time period, the control signal terminal outputs a first control signal in the first time period and a second control signal in the second time period; the duration of the first time period is the duration of displaying m frames of images, and the duration of the second time period is the duration of displaying n frames of images, where m>1 and n>1.
[0014] This application also provides a display device, including a power module and a display panel as described above, wherein the power module is used to provide driving power for the display panel to display images.
[0015] Compared to existing technologies, by setting a first control unit between the level conversion circuit and the scan drive circuit, and correspondingly setting a first transmission channel and a second transmission channel, the first control unit can control the clock signal to be transmitted to the scan drive circuit through the first transmission channel and the second transmission channel at the same time. This avoids the overheating situation that occurs when only one transmission channel transmits the clock signal. Furthermore, by switching the transmission channel, it can effectively prevent the circuit from being damaged by large current, thus effectively improving the circuit protection capability. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0017] Figure 1 is a schematic diagram of a display device provided in the first embodiment of this application;
[0018] Figure 2 is a schematic diagram of the side structure of the display panel in Figure 1;
[0019] Figure 3 is a schematic diagram of the planar layout of the display panel in Figure 1;
[0020] Figure 4 is a schematic diagram of the equivalent circuit connection of the level conversion circuit in Figure 3;
[0021] Figure 5 is a schematic diagram of the control signal output waveform in Figure 4;
[0022] Figure 6 is a schematic diagram of the control signal output waveform shown in Figure 4, provided by the second embodiment of this application.
[0023] Figure label:
[0024] Display device-100, display panel-10, power module-20, support frame-30, display area-10a, non-display area-10b, array substrate-10c, opposing substrate-10d, display medium layer-10e, backlight module-11, first scan drive circuit-12A, second scan drive circuit-12B, flip-chip film-13, data drive circuit-14, control circuit board-15, level conversion circuit-16, first control circuit-171, second control unit-172, first transmission channel-181, second transmission channel-182, third transmission channel-183, fourth transmission channel-184, first switch-M1, second switch-M2, third switch-M3, fourth switch-M4, control signal terminal-EN, first time period-T1, second time period-T2, third time period-T3, first control signal-V1, second control signal-V2. Detailed Implementation
[0025] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.
[0026] The following descriptions of the embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments in which this application can be implemented. The component designations used herein, such as "first," "second," etc., are merely for distinguishing the described objects and do not have any sequential or technical meaning. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages). Directional terms used in this application, such as "up," "down," "front," "rear," "left," "right," "inner," "outer," "side," etc., are merely for reference to the accompanying drawings. Therefore, the use of directional terms is for better and clearer explanation and understanding of this application, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on this application.
[0027] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish different objects, not to describe a specific order.
[0028] Furthermore, the terms "comprising," "may include," "include," or "may include" used in this application indicate the presence of the corresponding functions, operations, elements, etc., disclosed, but do not limit the inclusion of one or more other functions, operations, elements, etc. Additionally, the terms "comprising" or "include" indicate the presence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusion. Furthermore, when describing embodiments of this application, "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.
[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.
[0030] Please refer to Figure 1, which is a schematic diagram of the structure of a display device provided in the first embodiment of this application. As shown in Figure 1, the display device 100 includes a display panel 10, a power module 20, and a support frame 30. The display panel 10 and the power module 20 are fixed to the support frame 30. The power module 20 is disposed on the back of the display panel 10, that is, the non-display surface of the display panel 10. The power module 20 is used to provide power voltage for the display panel 10 to display images. The support frame 30 provides fixation and protection for the display panel 10 and the power module 20. In other embodiments of this application, the display device 100 may not require the support frame 30, for example, it may be a portable electronic device, such as a mobile phone or tablet computer.
[0031] Please refer to Figure 2, which is a schematic diagram of the side structure of the display panel in Figure 1.
[0032] As shown in Figure 2, the display panel 10 includes an image display area 10a and a non-display area 10b. The display area 10a is used for image display, and the non-display area 10b is disposed around the display area 10a to house other auxiliary components or modules. Specifically, the display panel 10 includes an array substrate 10c and a counter substrate 10d, and a display medium layer 10e sandwiched between the array substrate 10c and the counter substrate 10d. Driving elements are disposed on the array substrate 10c and the counter substrate 10d to generate corresponding electric fields according to data signals, thereby driving the display medium layer 10e to emit light of corresponding brightness to perform image display. In this embodiment, the display medium in the display medium layer 10e can be materials such as liquid crystal molecules, Micro LED, Mini LED, and LED.
[0033] Taking a liquid crystal display panel as an example, the display medium layer 10e contains liquid crystal molecules. These liquid crystal molecules deflect and transmit light of a preset brightness to display images. The display panel 10 also includes a backlight module 11 (BM), which provides light for display to the display area 10a of the display panel 10. The display panel 10 emits corresponding light according to the image signal to be displayed to perform image display. The display panel 10 also includes other components or modules, such as a signal processor module and a signal sensing module.
[0034] Please refer to Figure 3, which is a schematic diagram of the planar layout of the display panel in Figure 1.
[0035] As shown in Figure 3, the display panel 10 also includes a first scan driving circuit 12A, multiple chip-on-flex (COF) films 13, a data driving circuit 14, a control circuit board 15, and a level conversion circuit 16. The scan driving circuit 12A and the multiple COF films 13 are located in the non-display area of the display panel 10, i.e., at the edge of the display panel 10. The first scan driving circuit 12A outputs scan signals to the display area 10a to control the pixel units (not shown) within the display area 10a to receive data signals for image display. The COF films 13 fix the data driving circuit 14, which outputs data signals to the pixel units in the display area 10a to control the pixel units to perform image display.
[0036] The control circuit board 15 is used to temporarily store and decode the image data to be displayed into a drive signal. The data drive circuit 14, fixed on the flip-chip film 13, is used to receive the drive signal from the control circuit board 15 and drive the pixel unit P in the display area 10a to display the image according to the drive signal.
[0037] The level conversion circuit 16 is disposed on the control circuit board 15 and is used to output a clock signal to the first scan drive circuit 12A. The first scan drive circuit 12A outputs a scan signal to the pixel unit according to the clock signal.
[0038] In an exemplary embodiment, the display panel 10 further includes a second scan driving circuit 12B, which is electrically connected to the level conversion circuit 16. The second scan driving circuit 12B is used to receive a clock signal from the level conversion circuit 16 and output a scan signal according to the clock signal. The first scan driving circuit 12A or the second scan driving circuit 12B can be selected to control the pixel unit for image display. The second scan driving circuit 12B can be used as a backup circuit for the first scan driving circuit 12A.
[0039] It can also control the first scan drive circuit 12A and the second scan drive circuit 12B to simultaneously receive clock signals from the level conversion circuit 16 and output scan signals according to the clock signals, thereby making the first scan drive circuit 12A and the second scan drive circuit 12B share the load and reduce the risk of circuit overheating.
[0040] Please refer to Figure 4, which is a schematic diagram of the equivalent circuit connection of the level conversion circuit in Figure 3.
[0041] As shown in Figure 4, the display panel 10 also includes a first control unit 171, a first transmission channel 181, and a second transmission channel 182. The first control unit 171, the first transmission channel 181, and the second transmission channel 182 are disposed between the first scan drive circuit 12A and the level conversion circuit 16. The level conversion circuit 16 is connected to the first scan drive circuit 12A through the first control unit 171 and the first transmission channel 181. The level conversion circuit 16 can also be connected to the first scan drive circuit 12A through the first control unit 171 and the second transmission channel 182. The first control unit 171 is connected to the control signal terminal EN and is used to receive control signals from the control signal terminal EN. When a first control signal is received, the first control unit 171 controls the first transmission channel 181 to conduct, and the clock signal output by the level conversion circuit 16 is transmitted to the first scan drive circuit 12A through the first transmission channel 181. When a second control signal is received, the first control unit 171 controls the second transmission channel 182 to conduct, and the clock signal output by the level conversion circuit 16 is transmitted to the first scan drive circuit 12A through the second transmission channel 182.
[0042] By setting a first control unit 171 between the level conversion circuit 16 and the scan drive circuit 12, and correspondingly setting a first transmission channel 181 and a second transmission channel 182, the first control unit 171 can control the clock signal to not be transmitted to the scan drive circuit 12 through the first transmission channel 181 and the second transmission channel 182 at the same time. This avoids the heat generation that occurs when only one transmission channel transmits the clock signal. Furthermore, by switching the transmission channels, it is possible to effectively prevent large currents from passing through, thereby preventing circuit damage and effectively improving the circuit protection capability.
[0043] Specifically, the first control unit 171 includes a first switching transistor M1 and a second switching transistor M2. The gate of the first switching transistor M1 is connected to the control signal terminal EN for receiving a first control signal from the control signal terminal EN. The source of the first switching transistor M1 is connected to the level conversion circuit 16, and the drain of the first switching transistor M1 is connected to the first scan drive circuit 12A for conducting when the first control signal is received, so as to transmit the clock signal to the first scan drive circuit 12A.
[0044] The gate of the second switch M2 is connected to the control signal terminal EN, and is used to receive the second control signal from the control signal terminal EN. The source of the second switch M2 is connected to the level conversion circuit 16, and the drain of the second switch M2 is connected to the first scan drive circuit 12A, and is used to turn on when the second control signal is received, so as to transmit the clock signal to the first scan drive circuit 12A.
[0045] In this circuit, the first switch M1 is an N-type switch, which is turned on when a high-level signal or a positive polarity signal is received. The second switch M2 is a P-type switch, which is turned on when a low-level signal or a negative polarity signal is received. That is, when the first control signal is a high-level signal or a positive polarity signal, the second control signal is a low-level signal or a negative polarity signal. Specifically, when the control signal terminal EN outputs a high-level signal, the first switch M1 is turned on and the second switch M2 is turned off, so that the first transmission channel 181 transmits the clock signal. When the control signal terminal EN outputs a low-level signal, the first switch M1 is turned off and the second switch M2 is turned on, so that the second transmission channel 182 transmits the clock signal.
[0046] Of course, the first switching transistor M1 can also be set as a P-type switching transistor, and the second switching transistor M2 can be set as an N-type switching transistor. Correspondingly, the first control signal is a low-level signal or a negative polarity signal, and the second control signal is a high-level signal or a positive polarity signal.
[0047] In an exemplary embodiment, the display panel 10 further includes a second scan driving circuit 12B, a second control unit 172, a third transmission channel 183, and a fourth transmission channel 184. The second scan driving circuit 12B, the second control unit 172, the third transmission channel 183, and the fourth transmission channel 184 are disposed between the scan driving circuit 12B and the level conversion circuit 16. That is, the level conversion circuit 16 is connected to the second scan driving circuit 12B through the second control unit 172 and the third transmission channel 183. The level conversion circuit 16 can also be connected to the second scan driving circuit 12B through the second control unit 172 and the fourth transmission channel 184. The second control unit 172 is connected to the control signal terminal EN and is used to receive control signals from the control signal terminal EN. When the first control signal is received, the second control unit 172 controls the third transmission channel 183 to be turned on. The clock signal output by the level conversion circuit 16 is transmitted to the scan drive circuit 12 through the third transmission channel 183. When the second control signal is received, the second control unit 172 controls the fourth transmission channel 184 to be turned on. The clock signal output by the level conversion circuit 16 is transmitted to the scan drive circuit 12 through the fourth transmission channel 184.
[0048] Specifically, the second control unit 172 includes a third switch M3 and a fourth switch M4. The gate of the third switch M3 is connected to the control signal terminal EN for receiving a first control signal from the control signal terminal EN. The source of the third switch M3 is connected to the level conversion circuit 16, and the drain of the third switch M3 is connected to the second scan drive circuit 12B for conducting when the first control signal is received, so as to transmit the clock signal to the second scan drive circuit 12B.
[0049] The gate of the fourth switch M4 is connected to the control signal terminal EN, and is used to receive the second control signal from the control signal terminal EN. The source of the fourth switch M4 is connected to the level conversion circuit 16, and the drain of the fourth switch M4 is connected to the second scan drive circuit 12B, and is used to turn on when the second control signal is received, so as to transmit the clock signal to the second scan drive circuit 12B.
[0050] Among them, the third switch M3 is an N-type switch, which is turned on when a high-level signal is received, and the fourth switch M4 is a P-type switch, which is turned on when a low-level signal is received. That is, when the first control signal is a high-level signal and the second control signal is a low-level signal, the third switch M3 is turned on and the fourth switch M4 is turned off, so that the first transmission channel 181 transmits the clock signal. When the control signal terminal EN outputs a low-level signal, the third switch M3 is turned off and the fourth switch M4 is turned on, so that the second transmission channel 182 transmits the clock signal.
[0051] Please refer to Figure 5, which is a schematic diagram of the control signal output waveform in Figure 4.
[0052] As shown in Figure 5, when the first scanning drive circuit 12A or the second scanning drive circuit 12B controls the pixel unit to display an image, the control signal terminal EN alternately outputs the first control signal V1 and the second control signal V2 in multiple consecutive time periods. For example, the first control signal is output in the first time period T1 and the second control signal is output in the second time period T2. The first time period T1 is the duration of displaying m frames of images, and the second time period T2 is the duration of displaying at least n frames of images, where 1 < m and 1 < n.
[0053] For example, when the first scan driving circuit 12A controls the pixel unit to perform image display, the control clock signal is transmitted to the scan driving circuit 12 via the first transmission channel 181 during the first time period T1, and the control clock signal is transmitted to the scan driving circuit 12 via the second transmission channel 182 during the second time period T2.
[0054] For example, m = 10, meaning the first time period T1 is the duration of continuously displaying 10 frames of images; n = 20, meaning the second time period T2 is the duration of continuously displaying 20 frames of images. During the first time period T1, the first switch M1 is turned on, and the clock signal is continuously transmitted to the scan drive circuit 12 via the first transmission channel 181. During the second time period T2, the second switch M2 is turned on, and the clock signal is continuously transmitted to the scan drive circuit 12 via the second transmission channel 182. The first time period T1 and the second time period T2 alternate. The second scan drive circuit 12B controls the pixel units to perform image display in a similar manner to the first scan drive circuit 12A, and will not be described in detail here.
[0055] In an exemplary embodiment, the duration of the first time period T1 and the second time period T2 can be set according to specific needs. For example, the first time period T1 can be set to the duration of displaying 5 frames of images, and the second time period T2 can be set to the duration of displaying 5 frames of images. This application does not limit this.
[0056] When either the first scan drive circuit 12A or the second scan drive circuit 12B drives the pixel unit to perform image display, the load on a single scan drive circuit is relatively large. Therefore, controlling the first time period T1 and the second time period T2 to be the duration of at least two image frames can effectively alleviate the problem of circuit overheating and burnout. Alternatively, the first time period T1 and the second time period T2 can be controlled to be the duration of one image frame, and this application does not impose any limitations on this.
[0057] Please refer to Figure 6, which is a schematic diagram of the control signal output waveform shown in Figure 4, provided by the second embodiment of this application.
[0058] As shown in Figure 6, when the first scanning drive circuit 12A and the second scanning drive circuit 12B simultaneously control the pixel unit to display an image, the control signal terminal EN alternately outputs the first control signal V1 and the second control signal V2 in multiple consecutive frame images. For example, in any adjacent first time period T1 and second time period T2, during the first time period T1, the control signal terminal EN outputs the first control signal V1, driving the first switch M1 to turn on. The clock signal is transmitted to the first scanning drive circuit 12A through the first transmission channel 181, and at the same time, the clock signal is transmitted to the second scanning drive circuit 12B through the third transmission channel 183. During the second time period T2, the control signal terminal EN outputs the second control signal V2, driving the second switch M2 to turn on. The clock signal is transmitted to the first scanning drive circuit 12A through the second transmission channel 182, and at the same time, the clock signal is transmitted to the second scanning drive circuit 12B through the fourth transmission channel 184. The duration of the first time period T1 and the second time period T2 is the duration of one frame image display.
[0059] In an exemplary embodiment, when the first scanning drive circuit 12A and the second scanning drive circuit 12B simultaneously control the pixel unit to display images, the duration of the first time period T1 and / or the second time period T2 can be set to the duration of at least two frames of image display. This application does not impose any limitations on this.
[0060] By controlling the first scanning drive circuit 12A and the second scanning drive circuit 12B to simultaneously control the pixel unit to display the image, the load on the first scanning drive circuit 12A and the second scanning drive circuit 12B is reduced. At the same time, the first control signal and the second control signal are alternately output within two consecutive frames, which can further reduce the heat generation of the circuit. Furthermore, since the control signal is switched once after one frame of image display is completed, it can effectively prevent damage to the circuit from high current.
[0061] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.
Claims
1. A display panel, comprising a level conversion circuit, a first scan driving circuit, and a plurality of pixel units, wherein the level conversion circuit is electrically connected to the first scan driving circuit for outputting a clock signal, the first scan driving circuit outputting a scan signal to the pixel units according to the clock signal, and the scan signal controlling the pixel units to receive data signals for image display and perform image display; characterized in that, The display panel further includes a first control unit, a first transmission channel, and a second transmission channel. The level conversion circuit is connected to the first control unit. The control unit is connected to the same first scan drive circuit through two parallel first transmission channels and the second transmission channel. The level conversion circuit is connected to the first scan drive circuit through the first control unit and the first transmission channel, and also through the first control unit and the second transmission channel. The first control unit is used to control the clock signal output by the level conversion circuit to not be transmitted to the first scan drive circuit simultaneously through the first transmission channel and the second transmission channel, so as to switch the clock signal to be provided to the same first scan drive circuit between the first transmission channel and the second transmission channel.
2. The display panel as described in claim 1, characterized in that, The first control unit is connected to the control signal terminal. When the control signal terminal outputs the first control signal, the first control unit controls the clock signal to be transmitted to the first scan drive circuit through the first transmission channel. When the control signal terminal outputs the second control signal, the first control unit controls the clock signal to be transmitted to the first scan drive circuit via the second transmission channel.
3. The display panel as described in claim 2, characterized in that, During any adjacent first frame image display period and second frame image display period, the control signal terminal outputs the first control signal during the first frame image display period, and outputs the second control signal during the second frame image display period.
4. The display panel as described in claim 2, characterized in that, In any adjacent first time period and second time period, during the first time period, the control signal terminal outputs a first control signal, and during the second time period, the control signal terminal outputs a second control signal; the duration of the first time period is the duration of displaying m frames of images, and the duration of the second time period is the duration of displaying n frames of images, where m > 1 and n > 1.
5. The display panel as described in claim 3 or 4, characterized in that, The first control unit includes a first switching transistor and a second switching transistor. The gate of the first switching transistor is connected to the control signal terminal, the source of the first switching transistor is connected to the level conversion circuit via the first transmission channel, and the drain of the first switching transistor is connected to the first scan driving circuit via the first transmission channel. The first switching transistor is used to turn on when the first control signal is received, so as to control the clock signal to be transmitted to the first scan driving circuit via the first transmission channel. The gate of the second switch is connected to the control signal terminal, the source of the second switch is connected to the level conversion circuit via the second transmission channel, and the drain of the second switch is connected to the first scan drive circuit via the second transmission channel. The switch is used to turn on when the second control signal is received, so as to control the clock signal to be transmitted to the first scan drive circuit via the second transmission channel.
6. The display panel as described in claim 5, characterized in that, The display panel further includes a second scan driving circuit, a second control unit, a third transmission channel, and a fourth transmission channel. The level conversion circuit is connected to the second scan driving circuit through the second control unit and the third transmission channel. The level conversion circuit is also connected to the second scan driving circuit through the second control unit and the fourth transmission channel. The second control unit is used to control the clock signal output by the level conversion circuit to be transmitted to the second scan drive circuit at different times via the first transmission channel and the second transmission channel.
7. The display panel as described in claim 6, characterized in that, When the control signal terminal outputs the first control signal, the second control unit controls the clock signal to be transmitted to the second scan drive circuit via the third transmission channel. When the control signal terminal outputs the second control signal, the second control unit controls the clock signal to be transmitted to the second scan drive circuit via the fourth transmission channel.
8. The display panel as described in claim 6, characterized in that, When the scanning driving circuit or the second scanning driving circuit controls the pixel unit to display an image, during any adjacent first frame image display period and second frame image display period, the control signal terminal outputs the first control signal during the first frame image display period, and the control signal terminal outputs the second control signal during the second frame image display period.
9. The display panel as described in claim 6, characterized in that, When the scanning driving circuit and the second scanning driving circuit simultaneously control the pixel unit to display images, in adjacent first and second time periods, in the first time period, the control signal terminal outputs the first control signal, and in the second time period, the control signal terminal outputs the second control signal; the duration of the first time period is the duration of m frames of image display, and the duration of the second time period is the duration of n frames of image display, where m>1 and n>1.
10. A display device, characterized in that, It includes a power module and a display panel as described in any one of claims 1-9, wherein the power module is used to provide driving power for the display panel to display images.
Citation Information
Patent Citations
Array substrate, control method thereof and display panel
CN115188341A