An intelligent information processing platform for missiles based on MPSOC

Abstract

This invention discloses an airborne intelligent information processing platform based on MPSOC, comprising a program loading module, a clock fan-out module, a memory cache module, an intelligent information processing module, and a VPX interface module. Upon power-up, the program loading module loads the signal processing program. The clock fan-out module uses an intermediate frequency input clock and two onboard differential crystal oscillators as references to output four 50MHz clock signals, three 125MHz clock signals, and twelve 156.25MHz clock signals to the intelligent information processing module. The memory cache module stores the operating system and data cache. After receiving data from the preceding stage, the intelligent information processing module performs pulse compression processing and transmits the processed data to DSP1 via the SRIO protocol to perform functions such as CFAR detection. Then, it transmits the data to DSP2 via Hyperlink to complete image preprocessing algorithms. Finally, it transmits the data back to the intelligent information processing module via the SRIO protocol for intelligent algorithm processing. The calculation results are then transmitted to the servo unit and the telemetry and control system via the VPX interface module.

Description

Technical Field

[0001] This invention belongs to the field of digital signal processing technology for missile-borne radar, and relates to an intelligent information processing platform for missiles based on MPSOC. Background Technology

[0002] MPSOC is a chip from Xilinx's Zynq UltraScale series. This chip integrates high-performance programmable logic, a high-speed GTH transmission unit, a multi-core ARM processor, and a GPU graphics processor. Compared to traditional intelligent information processing platforms that typically rely on dedicated AI chips for computing power, MPSOC integrates a GPU, high-performance programmable logic, and multiple ARM cores onto a single chip. This directly provides computing power support for the deployment of AI algorithms, making digital signal processing operations on the chip's internal programmable logic and ARM cores more convenient. Intelligent information processing platforms are crucial for the engineering application of intelligent algorithms on missile platforms, and the technology of these platforms is developing towards miniaturization, high performance, and versatility. Traditional intelligent information processing platforms are mostly based on a high-speed FPGA + DSP + dedicated AI chip architecture, which is no longer sufficient to meet the demands of small size, low power consumption, modularity, and strong real-time computing.

[0003] Hunan Nare Technology Co., Ltd. disclosed a radar signal processing system in its patent application, "A Long-Range, Multi-Target Millimeter-Wave Radar Signal Processing Platform Based on MPSOC" (Application Date: 2021.04.02, Application No.: 202120681528.5, Publication No.: CN 215180868 U). This system includes an ADC module for receiving raw radar signals from the front end; an MPSOC module for preprocessing the data converted by the ADC module; and a storage module for storing the preprocessed raw dataset, providing the necessary resources for long-range, multi-target detection. However, this system utilizes a large amount of storage, including solid-state drives, resulting in a large overall system size, poor versatility, and unsuitability for use in missile-borne environments. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and propose an airborne intelligent information processing platform based on MPSOC, which has the advantages of high computing power, low power consumption, modularity and universality.

[0005] The technical solution of the present invention is: an onboard intelligent information processing platform based on MPSOC, comprising a program loading module, a clock fan-out module, and an intelligent information processing module;

[0006] Program loading module: Utilizes a serial bus to load the signal processing program into the intelligent information processing module upon power-up;

[0007] Clock fan-out module: It takes the external intermediate frequency input clock and the onboard differential crystal output as inputs, and fans out N A clock signals, M B clock signals and P C clock signals to supply the intelligent information processing module as the working clock;

[0008] Intelligent information processing module: It reads the signal processing program from the program loading module through the serial bus, completes the power-on initialization, receives external input data and performs pulse compression processing, performs CFAR detection on the compressed data to obtain the range Doppler image; after image preprocessing of the range Doppler image, it performs image detection to obtain the target image and reports it to the corresponding external extension.

[0009] The program loading module consists of four SPI flash chips and is connected to the intelligent information processing module via a serial bus with a characteristic impedance of 50 ohms. During power-on, the program is loaded into the intelligent information processing module.

[0010] The clock fan-out module includes two differential crystal oscillators and three clock buffer chips. The external intermediate frequency input clock is AC-coupled to clock buffer1 through a differential transmission line with a transmission characteristic impedance of 100 ohms, and then fans out N A-channel clocks to supply the intelligent information processing module. One differential crystal oscillator is AC-coupled to clock buffer2 through a pair of differential transmission lines with a transmission characteristic impedance of 100 ohms, and then fans out M B-channel clocks to supply the intelligent information processing module. The other crystal oscillator is AC-coupled to clock buffer3 through a pair of differential transmission lines with a transmission characteristic impedance of 100 ohms, and then fans out P C-channel clocks to supply the intelligent information processing module.

[0011] The intelligent information processing module consists of one MPSOC chip and two DSP chips. One DSP chip is used for CFAR detection, and the other is used for image preprocessing. The two DSP chips are AC-coupled to the GTH interface of the MPSOC chip via SRIO interfaces using differential printed lines with a characteristic impedance of 100 ohms. The EMIF, GPIO, and reset ports of the two DSP chips are connected to the high-density bank of the FPGA via printed lines with a characteristic impedance of 50 ohms. The two DSP chips are connected via a 4X mode Hyperlink connection to achieve high-speed data transmission. The MPSOC chip is used for target detection. The GTH interface of the MPSOC chip and the VPX interface module are AC-coupled on the printed circuit board via two 4x mode differential transmission lines with a transmission characteristic impedance of 100 ohms. The GTH transceiver is used to exchange data with the outside world.

[0012] It also includes a memory cache module; the memory cache module includes a DDR4 chip, a memory module, a solid-state memory, and multiple DDR3 chips; the memory cache module uses one solid-state memory chip, connected to the intelligent information processing module via a serial bus with a characteristic impedance of 50 ohms, to complete the storage and booting of the operating system; it uses one memory module, connected to the intelligent information processing module via a serial bus with a characteristic impedance of 50 ohms, to provide memory operating space for the embedded operating system; it uses one DDR4 chip, connected to the intelligent information processing module via a serial bus with a characteristic impedance of 50 ohms, to complete data exchange; and it uses eight DDR3 chips, connected to the intelligent information processing module via a serial bus with a characteristic impedance of 50 ohms, to complete data caching.

[0013] It also includes a VPX interface module, which uses level conversion and communication protocol chips to transmit external data to the intelligent information processing module.

[0014] The VPX interface module and the MPSOC chip module are connected via two 16-channel level conversion chips, nine 8-channel level conversion chips, fourteen 422 protocol chips, two single-ended to differential chips, one differential to single-ended chip, and one fiber optic module, mainly to realize internal and external data exchange.

[0015] The N=4, M=3, and P=12.

[0016] The frequency of clock signal A is 50MHz, the frequency of clock signal B is 125MHz, and the frequency of clock signal C is 156.25MHz.

[0017] Compared with the prior art, the present invention has the following advantages:

[0018] This invention uses an MPSOC chip unit as its core to realize radar signal pulse compression, image processing, target detection and communication control. It overcomes the traditional use of dedicated artificial intelligence chip + FPGA + DSP processing architecture, reduces complexity and number of boards, and makes the invention structurally simple.

[0019] This invention uses the AXI4 transmission protocol to realize data transmission between high-performance programmable logic and multi-core ARM, reducing the need for high-speed transmission interfaces such as SRIO and PCIe, and making this invention have the advantages of simple design, fast data transmission, and high real-time performance.

[0020] This invention uses an MPSOC chip to deploy AI algorithms, reducing reliance on dedicated AI chips, lowering overall power consumption, and facilitating the realization of intelligent radar.

[0021] This invention uses a VPX standard interface, and all communication between the board and the outside is done through a single connector. This overcomes the disadvantages of product variability caused by using different connectors, making this invention modular and universal. Attached Figure Description

[0022] Figure 1 This is a structural principle block diagram of the present invention. Detailed Implementation

[0023] like Figure 1 As shown, the platform of the present invention includes a clock fan-out module, a program loading module, a memory caching module, and an intelligent information processing module.

[0024] The clock fan-out module is connected to the intelligent information processing module using differential signals, the program loading module is connected to the intelligent information processing module using a serial bus, the VPX interface module is connected to the MPSOC chip using single-ended and differential signals, and the memory cache module is connected to the MPSOC and DSP chip modules using a parallel bus.

[0025] Program loading module: Loads the signal processing program into the intelligent information processing module upon power-up;

[0026] Memory cache module; used to store operating system and data cache;

[0027] Clock fan-out module: It uses the intermediate frequency input clock and the output of two onboard differential crystal oscillators as references to output four 50MHz clock signals, three 125MHz clock signals and twelve 156.25MHz clock signals to supply the intelligent information processing module.

[0028] Intelligent information processing module: It reads the signal processing program from the program loading module through the serial bus, completes the power-on initialization, receives external input data and performs pulse compression processing, performs CFAR detection on the compressed data to obtain the range Doppler image; after image preprocessing of the range Doppler image, it performs image detection to obtain the target image and reports it to the corresponding external extension.

[0029] In this invention, the clock fan-out module is connected to the MPSOC chip and the DSP chip via an LVDS interface. The LVDS interface of the clock module is the clock buffer output interface of the ADCLK846BCPZ and ADCLK854BCPZ chips. The clock unit LVDS interface is AC coupled to the clock differential signal input interface of the MPSOC and DSP chips via a transmission line with a characteristic impedance of 100 ohms on the printed circuit board.

[0030] The program loading module is connected to the MPSOC and DSP chips via a serial bus interface. The program loading module mainly contains four SPI Flash chips, consisting of two MT25QU512ABB8ESF-0SIT chips and two N25Q128A11ESF40F chips, which are connected through a transmission line with a characteristic impedance of 50 ohms on the printed circuit board.

[0031] The internal cache module uses eight AS4C256M16D3C-12BIN double-rate synchronous dynamic random access memory (DDR3) chips, which are connected to the DSP1 and DSP2 chips respectively through a parallel bus interface. It adopts a fly-by topology, with the address bus, control bus, and clock bus being strictly of equal length. Each byte data line is located on the same layer of the printed circuit board and is DC coupled through a transmission line with a characteristic impedance of 50 ohms on the printed circuit board. One XYEN32BN solid-state memory chip is used, with its port connected to the MPSOC's PS terminal via a 50-ohm serial bus. One KSM26SES8_8HD memory module is used, also with a 50-ohm serial bus, connected to the MPSOC's PS terminal via the ADDR0067-P001A port. Its address bus, control bus, and clock bus are strictly equal in length, with each byte's data line located on the same layer of the printed circuit board and DC-coupled via a 50-ohm transmission line on the PCB. One MT40A256M16GE-075E double-data-rate synchronous dynamic random access memory (DDR4) chip is used, with its port connected to the MPSOC's PL terminal via a 50-ohm serial bus. Its address bus, control bus, and clock bus are strictly equal in length, with each byte's data line located on the same layer of the printed circuit board and DC-coupled via a 50-ohm transmission line on the PCB.

[0032] The intelligent information processing module consists of one XCZU9EG-FFVB1156 MPSOC chip and two TMS320C6678ACYPA25 DSP chips. The two DSP chips are AC-coupled to the MPSOC chip's GTH interface via SRIO interfaces using differential printed lines with a characteristic impedance of 100 ohms. The EMIF, GPIO, and reset ports of the two DSP chips are connected to the MPSOC's high-density bank via printed lines with a characteristic impedance of 50 ohms. The Hyperlink between the two DSP chips is AC-coupled on the printed circuit board via 4x mode, differential transmission lines with a characteristic impedance of 100 ohms, enabling high-speed data transmission. The MPSOC chip's GTH interface and VPX interface module are AC-coupled on the printed circuit board via two 4x mode, differential transmission lines with a characteristic impedance of 100 ohms. The GTH transceiver is used for signal interaction with other individual devices.

[0033] It also includes a VPX interface module, which comprises two SN74LVC16T245DGGR level conversion chips, nine SN74AXC8T245PWR level conversion chips, fourteen MAX3490ESA 422 protocol chips, two AM26LV31INS 422B chips, one AM26LV32EIDR 422B chip, and one TLA270M06G fiber optic module. The level conversion chips and connectors are connected on the printed circuit board via 104 single-ended transmission lines with a characteristic impedance of 50 ohms. The 422 protocol chips and connectors are connected on the printed circuit board via 28 pairs of differential transmission lines with a characteristic impedance of 100 ohms. The 422B chip and connectors are connected on the printed circuit board via 12 pairs of differential transmission lines with a characteristic impedance of 100 ohms.

[0034] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A missile-borne intelligent information processing platform based on MPSOC, characterized in that, It includes a program loading module, a clock fan-out module, and an intelligent information processing module; Program loading module: Utilizes a serial bus to load the signal processing program into the intelligent information processing module upon power-up; Clock fan-out module: It takes the external intermediate frequency input clock and the onboard differential crystal output as inputs, and fans out N A clock signals, M B clock signals and P C clock signals to supply the intelligent information processing module as the working clock; Intelligent information processing module: It reads the signal processing program from the program loading module using a serial bus, completes power-on initialization, receives external input data and performs pulse compression processing, and performs CFAR detection on the compressed data to obtain a distance Doppler image; After image preprocessing of the distance Doppler image, image detection is performed to obtain the target image and report it to the corresponding external extension. The program loading module consists of four SPI flash chips and is connected to the intelligent information processing module via a serial bus with a characteristic impedance of 50 ohms. During power-on, the program is loaded into the intelligent information processing module. The clock fan-out module includes two differential crystal oscillators and three clock buffer chips. An external intermediate frequency input clock is AC-coupled to clock buffer 1 via a differential transmission line with a transmission characteristic impedance of 100 ohms, and then fans out N A-channel clocks to supply the intelligent information processing module. One differential crystal oscillator is AC-coupled to clock buffer 2 via a pair of differential transmission lines with a transmission characteristic impedance of 100 ohms, and then fans out M B-channel clocks to supply the intelligent information processing module. Another crystal oscillator is AC-coupled to clock buffer 3 via a pair of differential transmission lines with a transmission characteristic impedance of 100 ohms, and then fans out P C-channel clocks to supply the intelligent information processing module. The intelligent information processing module consists of one MPSOC chip and two DSP chips. One DSP chip is used for CFAR detection, and the other is used for image preprocessing. The two DSP chips are AC-coupled to the GTH interface of the MPSOC chip via SRIO interfaces using differential printed lines with a characteristic impedance of 100 ohms. The EMIF, GPIO, and reset ports of the two DSP chips are connected to the high-density bank of the FPGA via printed lines with a characteristic impedance of 50 ohms. The two DSP chips are connected to each other via a 4X mode Hyperlink connection to achieve high-speed data transmission. The MPSOC chip is used for target detection. The GTH interface of the MPSOC chip and the VPX interface module are AC-coupled on the printed circuit board via two 4x mode differential transmission lines with a characteristic impedance of 100 ohms. The GTH transceiver is used to exchange data with the outside world. It also includes a memory cache module; the memory cache module includes a DDR4 chip, a memory module, a solid-state memory, and multiple DDR3 chips; the memory cache module uses one solid-state memory chip, connected to the intelligent information processing module via a serial bus with a characteristic impedance of 50 ohms, to complete the storage and booting of the operating system; it uses one memory module, connected to the intelligent information processing module via a serial bus with a characteristic impedance of 50 ohms, to provide memory operating space for the embedded operating system; it uses one DDR4 chip, connected to the intelligent information processing module via a serial bus with a characteristic impedance of 50 ohms, to complete data exchange; and it uses eight DDR3 chips, connected to the intelligent information processing module via a serial bus with a characteristic impedance of 50 ohms, to complete data caching; It also includes a VPX interface module, which uses level conversion and communication protocol chips to transmit external data to the intelligent information processing module; The VPX interface module and the MPSOC chip module are connected via two 16-channel level conversion chips, nine 8-channel level conversion chips, fourteen 422 protocol chips, two single-ended to differential chips, one differential to single-ended chip, and one fiber optic module to enable internal and external data exchange.

2. The missile-borne intelligent information processing platform based on MPSOC according to claim 1, characterized in that, The N=4, M=3, and P=12.

3. The missile-borne intelligent information processing platform based on MPSOC according to claim 2, characterized in that, The frequency of clock signal A is 50MHz, the frequency of clock signal B is 125MHz, and the frequency of clock signal C is 156.25MHz.

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