Control circuit and switching circuit based on upper power tube slope and delay detection

Abstract

The control circuit and the switching circuit based on the slope of the upper power tube and the delay detection are provided, the current detection module outputs a first voltage and a second voltage; the slope detection module determines a third voltage corresponding to the slope of the change amount of the conduction current of the upper power tube according to the first voltage and the second voltage; the sample and hold module samples the third voltage and outputs a fourth voltage during the conduction of the upper power tube, and holds the third voltage at the time before the opening during the conduction of the lower power tube; the overcurrent detection module outputs a first control signal according to the first voltage and a preset threshold voltage; the delay correction module determines an off delay time according to the first control signal output by the overcurrent detection module, determines a correction voltage according to the off delay time and the fourth voltage, corrects the preset threshold voltage input to the overcurrent detection module according to the correction voltage, and resets the correction voltage after the correction of the preset threshold voltage of the overcurrent detection module is completed.

Description

Technical Field

[0001] The embodiments of this disclosure relate to the field of integrated circuit technology and related technical fields, and more specifically, to a control circuit and switching circuit suitable for detecting the slope and delay of an upper power transistor. Background Technology

[0002] In switching circuits, peak current overcurrent protection for the upper power transistor is essential. By setting a comparator in the switching circuit, the upper power transistor is turned off when the on-state current of the upper power transistor exceeds a preset threshold.

[0003] In existing technologies, due to the comparator delay, when the current of the upper power transistor exceeds a set threshold, the upper power transistor will remain on during the comparator delay and drive delay until it is completely turned off after the delay ends. However, for some low-voltage, high-power drive circuits, the external inductor is very small, and the inductor current rises at a large slope. Therefore, the current of the upper power transistor can generate a large ΔI during the delay time. A large ΔI can easily cause aging of the power transistor, reduce its lifespan, or even damage it. At the same time, the delay is affected by factors such as power supply voltage, temperature, and manufacturing process, making it difficult to correct. Summary of the Invention

[0004] The embodiments described herein provide a control circuit and a switching circuit based on the detection of the slope and delay of the upper power transistor, thereby solving the problems existing in the prior art.

[0005] According to a first aspect of this disclosure, a control circuit based on the detection of the slope and delay of the upper power transistor is provided, comprising: a current detection module, a slope detection module, a sample and hold module, an overcurrent detection module, and a delay correction module;

[0006] The current detection module is configured to acquire the switching node voltage, and output a first voltage based on the switching node voltage and the input node voltage during the conduction of the upper power transistor, and output a second voltage based on the switching node voltage and the ground node voltage during the conduction of the lower power transistor.

[0007] The slope detection module is configured to determine a third voltage corresponding to the slope of the change in the on-state current of the upper power transistor based on the first voltage and the second voltage.

[0008] The sample-and-hold module is configured to sample the third voltage and output the fourth voltage during the conduction period of the upper power transistor, and to hold and output the third voltage at the moment before the lower power transistor is turned on during the conduction period of the lower power transistor.

[0009] The overcurrent detection module is configured to output a first control signal based on the first voltage and a preset threshold voltage;

[0010] The delay correction module is configured to determine a turn-off delay time based on the overcurrent detection module, determine a correction voltage based on the turn-off delay time and a fourth voltage when the first control signal is high, correct a preset threshold voltage input to the overcurrent detection module based on the correction voltage when the first control signal is low, and reset the correction voltage after the preset threshold voltage correction of the overcurrent detection module is completed.

[0011] In some embodiments of this disclosure, the delay correction module includes a delay control signal generation unit, a delay current change determination unit, a correction voltage storage and reset unit, and a threshold correction unit;

[0012] The delay control signal generation unit is configured to generate a high level to the delay current change determination unit and a low level to the correction voltage storage reset unit and the threshold correction unit when the first control signal output by the overcurrent detection module is high; generate a high level to the threshold correction unit and a low level to the delay current change determination unit and the correction voltage storage reset unit during a second time period when the first control signal output by the overcurrent detection module is low; and generate a high level to the correction voltage storage reset unit and a low level to the delay current change determination unit and the threshold correction unit during a third time period.

[0013] The delay current change determination unit is configured to determine the correction voltage based on the turn-off delay time and the fourth voltage when the first control signal output by the overcurrent detection module is high.

[0014] The correction voltage storage and reset unit is configured to store the correction voltage when the first control signal output by the overcurrent detection module is high, and to reset the correction voltage when the first control signal output by the overcurrent detection module is low and is in the third time period.

[0015] The threshold correction unit is configured to output a correction voltage to correct the preset threshold voltage input to the overcurrent detection module when the first control signal output by the overcurrent detection module is low and is in the second time period.

[0016] In some embodiments of this disclosure, the delay control signal generation unit includes a first AND gate, a first delay unit, a second AND gate, a third AND gate, a NOR gate, and an XOR gate. The first terminal of the first AND gate and the first terminal of the first delay unit are respectively electrically connected to the output terminal of the overcurrent detection module. The second terminals of the first AND gate and the second terminals of the second AND gate are respectively electrically connected to the chip startup completion indication signal terminal. The first terminal of the second AND gate is electrically connected to the second terminal of the first delay unit. The third terminal of the first AND gate is respectively electrically connected to the first terminal of the third AND gate, the first terminal of the NOR gate, and the enable terminal of the delay current change determination unit. The third terminal of the second AND gate is respectively electrically connected to the second terminal of the third AND gate, the second terminal of the NOR gate, and the second terminal of the XOR gate. The third terminal of the third AND gate is electrically connected to the first terminal of the XOR gate.

[0017] The delay current change determination unit includes a first transconductance amplifier, the first terminal of the first transconductance amplifier is electrically connected to the output terminal of the sample and hold module, the second terminal of the first transconductance amplifier is electrically connected to the ground node, and the third terminal of the first transconductance amplifier is electrically connected to the power supply voltage node.

[0018] The corrected voltage storage reset unit includes a first capacitor and a first switch. The first end of the first capacitor is electrically connected to the fourth end of the first transconductance amplifier and the first end of the first switch, respectively. The second end of the first capacitor and the second end of the first switch are electrically connected to a ground node.

[0019] The threshold correction unit includes a fifth amplifier, a second switch, a third switch, a second capacitor, and a first voltage source. The first terminal of the fifth amplifier is electrically connected to the first terminal of the first capacitor. The second terminal of the fifth amplifier is electrically connected to a ground node. The third terminal of the fifth amplifier is electrically connected to the first terminal of the second switch. The fourth terminal of the fifth amplifier is electrically connected to the second terminal of the third switch and the first voltage source, respectively. The enable terminal of the fifth amplifier and the control terminal of the second switch are electrically connected to the third terminal of the XOR gate. The second terminal of the second switch is electrically connected to the first terminal of the second capacitor and the first terminal of the third switch, respectively. The control terminal of the third switch is electrically connected to the chip startup completion enable signal terminal. The second terminal of the second capacitor is electrically connected to a ground node.

[0020] The second time period is the same as the delay time of the first delay unit in the overcurrent detection module.

[0021] In some embodiments of this disclosure, the current detection module includes a first current detection unit and a second current detection unit;

[0022] The first current detection unit includes a fourth switch, a first resistor, a second resistor, a third resistor, a third capacitor, a first amplifier, and a second voltage source. The control terminal of the fourth switch is electrically connected to the control terminal of the upper power transistor. The first terminal of the fourth switch is electrically connected to the input node. The second terminal of the fourth switch is electrically connected to the first terminals of the first resistor and the second resistor, respectively. The second terminals of the first resistor and the third resistor are electrically connected to the switch node, respectively. The second terminal of the second resistor is electrically connected to the first terminal of the third capacitor and the first terminal of the first amplifier, respectively. The second terminals of the third resistor and the third capacitor are electrically connected to the second terminal of the first amplifier, respectively. The third terminal of the first amplifier is electrically connected to the slope detection module. The fourth terminal of the first amplifier is electrically connected to the first terminal of the second voltage source, and the second terminal of the second voltage source is electrically connected to the ground node.

[0023] The second acquisition unit includes a fifth switch, a fourth resistor, a fifth resistor, a sixth resistor, a fourth capacitor, a second amplifier, and a third voltage source. The control terminal of the fifth switch is electrically connected to the control terminal of the lower power transistor. The first terminal of the fifth switch is electrically connected to a ground node. The second terminal of the fifth switch is electrically connected to the first terminals of the fourth and fifth resistors respectively. The second terminals of the fourth and sixth resistors are electrically connected to the switch node respectively. The second terminal of the fifth resistor is electrically connected to the first terminal of the fourth capacitor and the first terminal of the second amplifier respectively. The second terminals of the sixth resistor and the fourth capacitor are electrically connected to the second terminal of the second amplifier respectively. The third terminal of the second amplifier is electrically connected to the slope detection module. The fourth terminal of the second amplifier is electrically connected to the first terminal of the third voltage source. The second terminal of the third voltage source is electrically connected to a ground node.

[0024] In some embodiments of this disclosure, the slope detection module includes a sixth switch, a seventh switch, an eighth switch, a ninth switch, a fifth capacitor, a third amplifier, a sixth capacitor, a seventh resistor, and a sixth amplifier. The first terminal of the sixth switch is electrically connected to the first output terminal of the current detection module. The second terminal of the sixth switch is electrically connected to the first terminal of the fifth capacitor and the second terminal of the eighth switch, respectively. The first terminal of the eighth switch is electrically connected to the second output terminal of the current detection module. The second terminal of the fifth capacitor is electrically connected to the first terminal of the seventh switch and the first terminal of the ninth switch, respectively. The second terminal of the seventh switch is electrically connected to the first terminal of the sixth capacitor and the second terminal of the ninth switch, respectively. The first terminal of the six capacitors, the first terminal of the third amplifier, and the first terminal of the seventh resistor are electrically connected. The second terminal of the third amplifier is electrically connected to the ground node. The third terminal of the third amplifier is electrically connected to the second terminal of the seventh resistor, the second terminal of the sixth capacitor, and the first terminal of the sixth amplifier, respectively. The second terminal of the sixth amplifier is electrically connected to the ground node. The third terminal of the sixth amplifier is electrically connected to the sample-and-hold module. The control terminals of the sixth switch and the seventh switch are electrically connected to the control terminal of the upper power transistor. The control terminals of the eighth switch and the ninth switch are electrically connected to the control terminal of the lower power transistor.

[0025] In some embodiments of this disclosure, the sample-and-hold module includes a tenth switch, a seventh capacitor, an eighth capacitor, an eighth resistor, and a fourth amplifier;

[0026] The first terminal of the tenth switch is electrically connected to the slope detection module. The second terminal of the tenth switch is electrically connected to the first terminal of the seventh capacitor and the first terminal of the eighth resistor. The control terminal of the eighth switch is electrically connected to the control terminal of the upper power transistor. The second terminals of the seventh capacitor, the eighth capacitor, and the fourth amplifier are electrically connected to the ground node. The second terminal of the eighth resistor is electrically connected to the first terminal of the eighth capacitor and the second terminal of the fourth amplifier. The third terminal of the fourth amplifier is electrically connected to the delay correction module.

[0027] In some embodiments of this disclosure, the slope detection module further includes a second delay unit, a third delay unit, a fourth AND gate, and a fifth AND gate. The first terminal of the second delay unit is electrically connected to the control terminal of the upper power transistor and the first terminal of the fourth AND gate, respectively. The second terminal of the second delay unit is electrically connected to the second terminal of the fourth AND gate, and the third terminal of the fourth AND gate is electrically connected to the control terminals of the sixth switch and the seventh switch, respectively.

[0028] The first terminal of the third delay is electrically connected to the control terminal of the lower power transistor and the first terminal of the fifth AND gate, the second terminal of the third delay is electrically connected to the second terminal of the fifth AND gate, and the third terminal of the fifth AND gate is electrically connected to the control terminals of the eighth switch and the ninth switch.

[0029] In some embodiments of this disclosure, the sample-and-hold module further includes a fourth delay unit and a sixth AND gate. The first terminal of the fourth delay unit is electrically connected to the control terminal of the upper power transistor and the first terminal of the sixth AND gate, respectively. The second terminal of the fourth delay unit is electrically connected to the second terminal of the sixth AND gate, and the third terminal of the sixth AND gate is electrically connected to the control terminal of the eighth switch.

[0030] In some embodiments of this disclosure, a control module is also included;

[0031] The control module is configured to receive a first control signal output by the overcurrent detection module, output a second control signal according to the first control signal, and send the second control signal to the drive circuit so that the drive circuit generates a drive signal for the upper power transistor and a drive signal for the lower power transistor based on the second control signal.

[0032] According to a second aspect of this disclosure, a switching circuit is provided, including the control circuit described in any of the first aspects.

[0033] The control circuit and switching circuit based on the slope and delay detection of the upper power transistor provided in this embodiment of the present disclosure, by setting a slope detection module in the control circuit, the slope detection module determines a third voltage corresponding to the slope of the change in the conduction current of the upper power transistor based on the first voltage and the second voltage output by the current detection module. The delay correction module determines the correction voltage corresponding to the change in the conduction current of the upper power transistor during the turn-off delay time. The preset threshold voltage input to the overcurrent detection module in the initial state is compared with the correction voltage corresponding to the change in the conduction current of the upper power transistor during the turn-off delay time. The difference is then used to change the preset threshold voltage input to the overcurrent detection module. That is, by reducing the preset threshold voltage input to the overcurrent detection module, the overcurrent detection module outputs the first control signal in advance to control the upper power transistor to turn off. The conduction current of the upper power transistor does not exceed the designed maximum limit current. The time when the overcurrent detection module outputs the first control signal to control the upper power transistor to turn off in advance meets the turn-off delay time, avoiding problems such as power transistor aging and reduced lifespan caused by excessive conduction current of the upper power transistor during the delay. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0035] Figure 1 This is a schematic diagram of a control circuit based on the slope and delay detection of the upper power transistor provided in an embodiment of this disclosure;

[0036] Figure 2 This is a schematic diagram of the shutdown delay time provided in the embodiments of this disclosure;

[0037] Figure 3 This is a schematic diagram of the circuit structure of a delay correction module provided in an embodiment of this disclosure;

[0038] Figure 4 This is a timing diagram of the delay correction module provided in an embodiment of this disclosure;

[0039] Figure 5 This is a schematic diagram of the circuit structure of a current detection module provided in an embodiment of this disclosure;

[0040] Figure 6 This is a schematic diagram of the circuit structure of a slope detection module provided in an embodiment of this disclosure;

[0041] Figure 7 This is a schematic diagram of the circuit structure of a sample-and-hold module provided in an embodiment of this disclosure;

[0042] Figure 8 This is a schematic diagram of the circuit structure of another slope detection module provided in an embodiment of this disclosure;

[0043] Figure 9 This is a schematic diagram of the circuit structure of another sample-and-hold module provided in an embodiment of this disclosure;

[0044] Figure 10 This is a timing diagram of the control circuit provided in an embodiment of this disclosure. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0046] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0047] In all embodiments of this disclosure, since the source and drain (emitter and collector) of the transistor are symmetrical, and the conduction current directions between the source and drain (emitter and collector) of N-type and P-type transistors are opposite, the controlled intermediate terminal of the transistor is referred to as the control terminal, and the remaining two terminals of the transistor are referred to as the first terminal and the second terminal, respectively. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0048] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0049] In view of the problems existing in the prior art, the present disclosure provides a control circuit based on the detection of the slope and delay of the upper power transistor. Figure 1 This is a schematic diagram of a control circuit based on the slope and delay detection of the upper power transistor, as provided in an embodiment of this disclosure. Figure 1As shown, the control circuit includes: a current detection module 10, a slope detection module 20, a sample-and-hold module 30, an overcurrent detection module 40, and a delay correction module 50; wherein, the current detection module 10 is configured to acquire the switching node voltage and output a first voltage based on the switching node voltage and the input node voltage during the conduction of the upper power transistor, and output a second voltage based on the switching node voltage and the ground node voltage during the conduction of the lower power transistor; the slope detection module 20 is configured to determine a third voltage corresponding to the slope of the change in the conduction current of the upper power transistor based on the first voltage and the second voltage; the sample-and-hold module 30 is configured to sample the third voltage and output a fourth voltage during the conduction of the upper power transistor 01. During the conduction of the lower power transistor, the third voltage at the moment before turn-on is maintained; the overcurrent detection module 40 is configured to output a first control signal based on the first voltage and the preset threshold voltage; the delay correction module 50 is configured to determine the turn-off delay time based on the overcurrent detection module, and when the first control signal output by the overcurrent detection module 40 is high (i.e., during the first time period), determine the correction voltage based on the turn-off delay time and the fourth voltage; when the first control signal output by the overcurrent detection module 40 is low, correct the preset threshold voltage input to the overcurrent detection module 40 according to the correction voltage during the second time period; and reset the correction voltage after the correction of the preset threshold voltage of the overcurrent detection module 40 is completed during the third time period.

[0050] In this embodiment of the disclosure, a slope detection module 20 is set in the control circuit. The slope detection module 20 determines a third voltage corresponding to the slope of the change in the on-current of the upper power transistor based on the first voltage V_Rising (V_Rising represents the inductor current during the conduction of the upper power transistor, i.e., the product of the on-current of the upper power transistor, the on-resistance of the upper power transistor, and the amplification factor G1) and the second voltage V_Falling (V_Falling represents the inductor current during the conduction of the lower power transistor, i.e., the product of the on-current of the lower power transistor, the on-resistance of the lower power transistor, and the amplification factor G2) output by the current detection module 10. The sample and hold module 30 outputs a fourth voltage based on the third voltage, and the delay correction module 50 determines the turn-off delay time of the upper power transistor 01. The correction voltage corresponding to the change in the on-current of the upper power transistor is calculated by taking the difference between the preset threshold voltage input to the overcurrent detection module 40 in the initial state and the correction voltage corresponding to the change in the on-current of the upper power transistor during the turn-off delay time. This difference changes the preset threshold voltage input to the overcurrent detection module 40. In other words, by reducing the preset threshold voltage input to the overcurrent detection module 40, the overcurrent detection module 40 outputs the first control signal in advance to control the upper power transistor 01 to turn off. The time when the overcurrent detection module 40 outputs the first control signal to control the upper power transistor to turn off meets the turn-off delay time. The on-current of the upper power transistor 01 does not exceed the designed maximum limit current, thus avoiding problems such as power transistor aging and reduced lifespan caused by excessive on-current of the upper power transistor during the delay.

[0051] Specifically, when the drive signal H_DRV of the upper power transistor is high, the upper power transistor 01 is turned on. The current detection module 10 collects the switching node voltage and outputs a first voltage V_Rising based on the switching node voltage and the input node voltage. The first voltage V_Rising represents the product of the inductor current (i.e., the upper power transistor's on-state current) during the upper power transistor's on-state, the upper power transistor's on-state resistance, and the amplification factor G1. V_Rising = I_Rising × R H_ON ×G1, I_Rising represents the inductor current during the power-on period, R H_ON G1 represents the on-resistance of the upper power transistor, and G1 represents the gain of the amplifier in the first current detection unit included in the current detection module 10. That is, during the conduction period of the upper power transistor 01, the current detection module 10 converts the conduction current (i.e., inductor current) flowing through the upper power transistor 01 into a first voltage V_Rising, which is output to the slope detection module 20 and the overcurrent detection module 40 respectively.

[0052] When the drive signal L_DRV of the lower power transistor is high, the lower power transistor 02 is turned on. The acquisition module 10 acquires the switching node voltage VSW and outputs a second voltage V_Falling based on the switching node voltage VSW and the ground node voltage VGND. The second voltage V_Falling represents the product of the inductor current (i.e., the lower power transistor's on-state current) and the lower power transistor's on-state resistance during the lower power transistor's on-state, multiplied by the amplification factor G2. V_Falling = I_Falling × R L_ON ×G2, I_Falling represents the inductor current during the conduction period of the lower power transistor, R L_ON G1 represents the on-resistance of the lower power transistor, and G2 represents the gain of the amplifier in the second acquisition unit included in the acquisition module 10. That is, when the upper power transistor 01 is turned on, the acquisition module 10 converts the on-current (i.e., inductor current) flowing through the upper power transistor 01 into a first voltage V_Rising and outputs it to the slope detection module 20; when the lower power transistor 02 is turned on, the acquisition module 10 converts the on-current (i.e., inductor current) flowing through the lower power transistor 02 into a second voltage V_Falling and outputs it to the slope detection module 20.

[0053] The slope detection module 20 determines the third voltage corresponding to the slope of the change in the conduction current of the upper power transistor based on the first voltage V_Rising and the second voltage V_Falling output by the current detection module 10. That is, during the conduction period of the upper power transistor 01, if the change in the inductor current is ΔI, then the slope of the change in the inductor current satisfies: At this point, the slope SR of the change in inductor current is... I_Rising The corresponding third voltage V_SRt satisfies: V_SRt=SR I_Rising ×R H_ON ×G1×R7×C5, that is, after the slope detection module 20 receives the first voltage V_Rising and the second voltage V_Falling output by the current detection module 10, it outputs the third voltage V_SRt corresponding to the slope of the change in the conduction current of the power transistor.

[0054] The sample-and-hold module 30 outputs a voltage V_SRo = V_SRt during the conduction of the upper power transistor 01. During the conduction of the lower power transistor 02, it holds the third voltage at the moment before the transistor is turned on. That is, the sample-and-hold module holds the output fourth voltage V_SRo to satisfy: V_SRo = V_SRt.

[0055] The overcurrent detection module 40 outputs a high level to the delay correction module 50 when the first voltage V_Rising output by the current detection module 10 is greater than the preset threshold voltage V_OCP, and outputs a low level to the delay correction module 50 when the first voltage V_Rising output by the current detection module is less than the preset threshold voltage V_OCP.

[0056] When the delay correction module 50 receives a high-level first control signal from the overcurrent detection module 40, it determines the correction voltage based on the turn-off delay time and the fourth voltage V_SRo output by the sample-and-hold module 30. When the delay correction module receives a low-level first control signal from the overcurrent detection module 40, it corrects the preset threshold voltage input to the overcurrent detection module based on the correction voltage. After the correction of the preset threshold voltage of the overcurrent detection module 40 is completed, the correction voltage is reset.

[0057] In the above embodiments, combined with Figure 2 The turn-off delay time includes the delay time of the rising edge of the overcurrent detection module, the delay time of the drive circuit, the delay time of the first voltage output by the current detection module being reset to the preset threshold voltage, and the delay time of the falling edge of the overcurrent detection module. Figure 2 In the diagram, Delay1 is the delay time of the rising edge of the overcurrent detection module, Delay2 is the delay time of the drive circuit, Delay3 is the delay time of the first voltage output by the current detection module being reset to the preset threshold voltage, Delay4 is the delay time of the falling edge of the overcurrent detection module, V_H is the high-level threshold of the overcurrent detection module, V_L is the logic low-level threshold of the overcurrent detection module, and OCP refers to the first control signal output by the overcurrent detection module.

[0058] The overcurrent detection module 40 outputs a high-level duration Δt1 = Delay2 + Delay3 + Delay4. When the first voltage V_Rising is greater than the preset threshold voltage V_OCP, the additional time for the first voltage V_Rising to increase, i.e., the turn-off delay, is Δt2, where Δt2 = Delay1 + Delay2. For a faster comparator, Delay4 ≈ Delay1. For the overcurrent detection module, the V_Rising reset time is very short, i.e., Delay3 ≈ 0. Therefore, Δt1 = Delay1 + Delay2, i.e., the turn-off delay time Δt2 ≈ Δt1.

[0059] The control circuit based on the slope and delay detection of the upper power transistor provided in this embodiment includes a slope detection module. This module determines a third voltage corresponding to the slope of the change in the upper power transistor's on-state current based on the first and second voltages output by the current detection module. A sample-and-hold module outputs a fourth voltage based on the third voltage. A delay correction module determines a correction voltage corresponding to the change in the upper power transistor's on-state current during the turn-off delay. The difference between the preset threshold voltage input to the overcurrent detection module in the initial state and the correction voltage corresponding to the change in the upper power transistor's on-state current during the turn-off delay is used to change the preset threshold voltage input to the overcurrent detection module. In other words, by reducing the preset threshold voltage input to the overcurrent detection module, the overcurrent detection module outputs a first control signal earlier to control the upper power transistor to turn off. The timing of the first control signal output by the overcurrent detection module to control the upper power transistor to turn off satisfies the turn-off delay time, and the on-state current of the upper power transistor does not exceed the designed maximum limit current, thus avoiding power transistor aging and reduced lifespan due to excessive on-state current during the delay.

[0060] In a specific implementation method Figure 3 This is a circuit structure diagram of a delay correction module provided in an embodiment of this disclosure. Figure 4 This is a timing diagram of the delay correction module provided in the embodiments of this disclosure, combined with... Figure 3 and Figure 4The delay correction module 50 includes a delay control signal generation unit 51, a delay current change determination unit 52, a correction voltage storage and reset unit 53, and a threshold correction unit 54. The delay control signal generation unit 51 is configured to generate a high level signal to the delay current change determination unit 52, and a low level signal to the correction voltage storage and reset unit 53 and the threshold correction unit 54 when the first control signal output by the overcurrent detection module 40 is high; to generate a high level signal to the threshold correction unit 54, and a low level signal to the delay current change determination unit 52 and the correction voltage storage and reset unit 53 within a second time period when the first control signal output by the overcurrent detection module 40 is low; and to generate a high level signal within a third time period when the first control signal output by the overcurrent detection module 40 is low. The correction voltage storage and reset unit 53 generates a low-level delay current change determination unit 52 and a threshold correction unit 54. The delay current change determination unit 52 is configured to determine the correction voltage based on the turn-off delay time and the fourth voltage V_SRo when the first control signal output by the overcurrent detection module is high. The correction voltage storage and reset unit 53 is configured to store the correction voltage when the first control signal output by the overcurrent detection module is high, and reset the correction voltage when the first control signal output by the overcurrent detection module is low and in the third time period. The threshold correction unit 54 is configured to output the correction voltage to correct the preset threshold voltage input to the overcurrent detection module when the first control signal output by the overcurrent detection module is low and in the second time period.

[0061] The delay control signal generation unit 51 includes a first AND gate A1, a first delay unit D1, a second AND gate A2, a third AND gate A3, a NOR gate O, and an XOR gate F. The first terminals of the first AND gate A1 and the first delay unit D1 are electrically connected to the output terminals of the overcurrent detection module 40. The second terminals of the first AND gate A1 and the second AND gate A2 are electrically connected to the chip completion indicator signal terminals. The chip completion indicator signal terminals output a start completion indicator signal OK. The first terminal of the second AND gate A2 is electrically connected to the second terminal of the first delay unit D1, and the third terminal of the first AND gate A1 is electrically connected to the third AND gate A3. The first terminal of the first AND gate 3, the first terminal of the NOR gate 0, and the enable terminal Enable1 of the delay current change determination unit 52 are electrically connected. The third terminal of the second AND gate A2 is electrically connected to the second terminal of the third AND gate A3, the second terminal of the NOR gate 0, and the second terminal of the XOR gate F, respectively. The third terminal of the third AND gate A3 is electrically connected to the first terminal of the XOR gate F. The delay current change determination unit 52 includes a first transconductance amplifier GM1. The first terminal of the first transconductance amplifier GM1 is electrically connected to the output terminal of the sample and hold module 30, and the second terminal of the first transconductance amplifier GM1 is electrically connected to the ground node. The third terminal is electrically connected to the power supply voltage node VCC; the corrected voltage storage reset unit 53 includes a first capacitor C1 and a first switch S1. The first terminal of the first capacitor C1 is electrically connected to the fourth terminal of the first transconductance amplifier GM1 and the first terminal of the first switch S1, respectively. The second terminal of the first capacitor C1 and the second terminal of the first switch S1 are electrically connected to the ground node; the threshold correction unit 53 includes a fifth amplifier K5, a second switch S2, a third switch S3, a second capacitor C3, and a first voltage source V_OCP. The first terminal of the fifth amplifier K5 is electrically connected to the first terminal of the first capacitor C1. The second terminal of the fifth amplifier K5 is electrically connected to the ground node. The third terminal of the fifth amplifier K5 is electrically connected to the first terminal of the second switch S2. The fourth terminal of the fifth amplifier K5 is electrically connected to the second terminal of the third switch S3 and the first voltage source V_OCP, respectively. The enable terminal Enable2 of the fifth amplifier K5 and the control terminal of the second switch S2 are electrically connected to the third terminal of the XOR gate F. The second terminal of the second switch S2 is electrically connected to the first terminal of the second capacitor C2 and the first terminal of the third switch S3, respectively. The control terminal of the third switch S3 is electrically connected to the chip completion indicator signal terminal. The second terminal of the second capacitor C2 is electrically connected to the ground node.

[0062] Combination Figure 3 and Figure 4During the chip startup phase, the chip completion indicator signal outputs a low level. This low level is then inverted and outputs a high level to the third switch S3, turning it on. The first voltage source V_OCP charges the second capacitor C2, and the voltage across the second capacitor C2 is V_OCP. When the chip startup ends, the chip completion indicator signal outputs a high level. This high level is then inverted and outputs a low level to the third switch S3, turning it off. At this time, the second capacitor C2 maintains a preset threshold voltage V_OCP to the overcurrent detection module. The overcurrent detection module 40 compares the first voltage V_Rising with the preset threshold voltage V_OCP. When the first voltage V_Rising is greater than the preset threshold voltage V_OCP, the overcurrent detection module 40 outputs a high level; when the first voltage V_Rising is less than the preset threshold voltage V_OCP, the overcurrent detection module 40 outputs a low level.

[0063] When the overcurrent detection module outputs a high level, that is Figure 4 During the first time period T1 shown, the first AND gate A1 outputs a high level, the second AND gate A2 outputs a high level after being delayed by the first delay unit D1, the third AND gate A3 outputs a high level, the NOR gate O outputs a low level, the XOR gate F outputs a low level, the first transconductance amplifier GM1 is turned on (the first transconductance amplifier is equivalent to a voltage-controlled current source), and the sample-and-hold module holds the output of the fourth voltage V_SRo to control the current to charge the first capacitor C1. The high-level output duration of the overcurrent detection module is approximately equal to the turn-off delay, i.e., Δt1. Therefore, within Δt1, the first capacitor C1 is charged, satisfying: I × Δt1 = C1 × V C1 Where I = gm1 × V_SRo, I is the current flowing through the first transconductance amplifier, and gm1 is the gain of the first transconductance amplifier.

[0064] When the overcurrent detection module outputs a low level, that is Figure 4 During the second time period T2 shown, the first AND gate A1 outputs a low level, the second AND gate A2 outputs a high level, the third AND gate A3 outputs a low level, the NOR gate O outputs a low level, the XOR gate F outputs a high level, the fifth amplifier K5 is enabled, the second switch S2 is turned on, and the input of the fifth amplifier K5 is the voltage V of capacitor C1. C1 The fifth amplifier K5 has a gain of -1 and an output DC bias voltage of V_OCP. Therefore, the fifth amplifier K5 corrects the preset threshold voltage input to the overcurrent detection module 40 to V_OCP - V_OCP. C1 And synchronized to the second capacitor C2, that is, the voltage of the second capacitor C2 is V. C2 Above, i.e., V C2 =V_OCP-V C1 .

[0065] When the overcurrent detection module 40 outputs a low level, that is... Figure 4 During the third time period T3 shown, the first AND gate A1 outputs a low level, the second AND gate A2 outputs a low level, the third AND gate A3 outputs a low level, the NOR gate O outputs a high level, and the XOR gate F outputs a low level. At this time, the first switch S1 is turned on, and the voltage of the first capacitor C1 is reset to zero. When the H_DRV signal arrives in the next cycle, the above process is repeated.

[0066] It should be noted that in the above embodiment, the second time period T2 is the same as the delay time of the first delayer.

[0067] In a specific implementation method Figure 5 This is a schematic diagram of the circuit structure of a current detection module provided in an embodiment of this disclosure, as shown below. Figure 5 As shown, the current detection module 10 includes a first current detection unit 11 and a second current detection unit 12. The first current detection unit includes a fourth switch S4, a first resistor R1, a second resistor R2, a third resistor R3, a third capacitor C3, a first amplifier K1, and a second voltage source V2. The control terminal of the fourth switch S3 is electrically connected to the control terminal of the upper power transistor O1. The first terminal of the fourth switch S4 is electrically connected to the input node IN. The second terminal of the fourth switch S4 is electrically connected to the first terminal of the first resistor R1 and the first terminal of the second resistor R2. The second terminals of the first resistor R1 and the first terminal of the third resistor R3 are electrically connected to the switch node SW. The second terminal of the second resistor R2 is electrically connected to the first terminal of the third capacitor C3 and the first terminal of the first amplifier K1. The second terminals of the third resistor R3 and the third capacitor C3 are electrically connected to the second terminal of the first amplifier K1. The third terminal of the first amplifier K1 is electrically connected to the slope detection module. The fourth terminal of the first amplifier K1 is electrically connected to the first terminal of the second voltage source V2. The second voltage source V2 is electrically connected to the grounding node. The second acquisition unit 12 includes a fifth switch S5, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a fourth capacitor C4, and a second amplifier K2. The control terminal of the fifth switch S5 is electrically connected to the control terminal of the lower power transistor O2. The first terminal of the fifth switch S5 is electrically connected to the grounding node GND. The second terminal of the fifth switch S5 is electrically connected to the first terminals of the fourth resistor R4 and the fifth resistor R5, respectively. The second terminals of the fourth resistor R4 and the sixth resistor R6 are electrically connected to the switch node SW, respectively. The second terminal of the fifth resistor R5 is electrically connected to the first terminal of the fourth capacitor C4 and the first terminal of the second amplifier K2, respectively. The second terminals of the sixth resistor R6 and the fourth capacitor C4 are electrically connected to the second terminal of the second amplifier K2, respectively. The third terminal of the second amplifier K2 is electrically connected to the slope detection module. The fourth terminal of the second amplifier K2 is electrically connected to the third voltage source V3. The second terminal of the third voltage source V3 is electrically connected to the grounding node.

[0068] When the drive signal H_DRV of the upper power transistor is high, the upper power transistor 01 is turned on, and the first current detection unit 11 is enabled. The input node voltage of the input node IN and the switching node voltage of the switching node SW are connected to the two ends of the first resistor R1. After being filtered by the filter composed of the second resistor R2, the third resistor R3 and the third capacitor C3, the signal is sent to the first amplifier K1. After being amplified by the third amplifier K1, the signal is output. The gain of the first amplifier K1 is G1, and the signal output by the first amplifier K1 is V_Rising. The second voltage source V2 provides the DC bias voltage of the first amplifier K1.

[0069] When the drive signal L_DRV of the lower power transistor is high, the lower power transistor 02 is turned on, simultaneously enabling the second current detection unit 12. The ground node voltage of ground node GND and the switching node voltage of switching node SW are connected to the four resistors R4, then filtered by the filter composed of the fifth resistor R5, the sixth resistor R6, and the fourth capacitor C4 before being sent to the second amplifier K2. After being amplified by the second amplifier K2, the signal is output. The gain of the second amplifier K2 is G2, and the voltage signal output by the second amplifier K2 is V_Falling. The third voltage source V3 provides the DC bias voltage for the second amplifier K2. The second and third power supplies satisfy V2 = V3. The gains of the amplifiers in the first current detection unit 11 and the second current detection unit 12 need to satisfy the following relationship: G1 × R H_ON =G2×R L_ON R H_ON On-resistance of the upper power transistor, R L_ON The on-resistance of the lower power transistor ensures that the voltage across the capacitor in the slope detection module 20 does not change drastically when the upper and lower power transistors are alternately turned on.

[0070] In a specific implementation method Figure 6 This is a schematic diagram of the circuit structure of a slope detection module provided in an embodiment of this disclosure, as shown below. Figure 6As shown, the slope detection module includes a sixth switch S6, a seventh switch S7, an eighth switch S8, a ninth switch S9, a fifth capacitor C5, a third amplifier K3, a sixth capacitor C6, a seventh resistor R7, and a sixth amplifier K6. The first terminal of the sixth switch S6 is electrically connected to the first output terminal of the current detection module. The second terminal of the sixth switch S6 is electrically connected to the first terminal of the fifth capacitor C5 and the second terminal of the eighth switch S8. The first terminal of the eighth switch S8 is electrically connected to the second output terminal of the current detection module. The second terminal of the fifth capacitor C5 is electrically connected to the first terminal of the seventh switch S7 and the first terminal of the ninth switch S9. The second terminal of the seventh switch S7 is electrically connected to... The first terminal of the sixth capacitor C6, the first terminal of the third amplifier K3, and the first terminal of the seventh resistor R7 are electrically connected respectively. The second terminal of the third amplifier K3 is electrically connected to the ground node. The third terminal of the third amplifier K3 is electrically connected to the second terminal of the seventh resistor R7, the second terminal of the sixth capacitor C6, and the first terminal of the sixth amplifier K6. The second terminal of the sixth amplifier K6 is electrically connected to the ground node. The third terminal of the sixth amplifier K6 is electrically connected to the sample-and-hold module. The control terminals of the sixth switch S6 and the seventh switch S7 are electrically connected to the control terminal of the upper power transistor. The control terminals of the eighth switch S8 and the ninth switch are electrically connected to the control terminal of the lower power transistor.

[0071] Combination Figure 6 When the drive signal H_DRV of the upper power transistor is high, the sixth switch S6 and the seventh switch S7 are turned on. The V_Rising output by the current detection module 10 charges the fifth capacitor C5 through the sixth switch S6 and is sent to the third amplifier K3 through the seventh switch. The third amplifier K3, the first seven resistor R7, and the sixth capacitor C6 form a differentiating circuit. The seventh resistor R7 and the sixth capacitor C6 in the differentiating circuit have a high-frequency filtering function to shield the spike voltage generated when the upper power transistor 01 is turned on. Since the on-current of the upper power transistor gradually increases, and the slope detection module amplifies the slope detection result in reverse, the sixth amplifier K6 needs to be set. The sixth amplifier K6 amplifies the output voltage of the third amplifier K3 in reverse, and its gain is -1. The sixth amplifier K6 outputs the third voltage V_SRt corresponding to the slope of the change in the on-current of the upper power transistor.

[0072] The third voltage output by the slope detection module 20 is: V_SRt=C5×R7×SR V_Rising =C5×R7×SR I_Rising ×R H_ON ×G1.

[0073] In a specific implementation method Figure 7 This is a schematic diagram of the circuit structure of a sample-and-hold module provided in an embodiment of this disclosure, as shown below. Figure 7As shown, the system includes a tenth switch S10, a seventh capacitor C7, an eighth capacitor C8, an eighth resistor R8, and a fourth amplifier K4. The first terminal of the tenth switch S10 is electrically connected to the slope detection module. The second terminal of the tenth switch S10 is electrically connected to the first terminal of the seventh capacitor C7 and the first terminal of the eighth resistor R8. The control terminal of the tenth switch S10 is electrically connected to the control terminal of the upper power transistor O1. The second terminals of the seventh capacitor C7, the eighth capacitor C8, and the first terminal of the fourth amplifier K4 are electrically connected to the grounding node. The second terminal of the eighth resistor R8 is electrically connected to the first terminal of the eighth capacitor C8 and the second terminal of the fourth amplifier K4. The third terminal of the fourth amplifier K4 is electrically connected to the delay correction module.

[0074] like Figure 7 As shown, when the drive signal H_DRV of the upper power transistor is high, the tenth switch S10 is open, and the fourth voltage V_SRo output by the sample-and-hold module 30 is V_SRt. When the drive signal H_DRV of the upper power transistor is low, the tenth switch S10 is turned off, and the voltage V_SRo output by the sample-and-hold module 30 is the third voltage V_SRt sampled before the tenth switch S10 is turned off. That is, the fourth voltage V_SRo output by the sample-and-hold module satisfies: V_SRo = V_SRt.

[0075] Because the rising slope of the first voltage V_Rising output by the first current detection unit is Within Δt1, the change in the first voltage V_Rising Known therefore If we set C5×R7×gm1=C1, then ΔV=V C1 That is, the voltage across the first capacitor C1 is reflected in Δt1, and the change in the first voltage V_Rising is ΔV.

[0076] In a specific implementation method Figure 8 This is a schematic diagram of the circuit structure of another slope detection module provided in this embodiment of the present disclosure, as shown below. Figure 8As shown, the slope detection module also includes a second delay unit D2, a third delay unit D3, a fourth AND gate A4, and a fifth AND gate A5. The first terminal of the second delay unit D2 is electrically connected to the control terminal of the upper power transistor O1 and the first terminal of the fourth AND gate A4, respectively. The second terminal of the second delay unit D2 is electrically connected to the second terminal of the fourth AND gate A4, and the third terminal of the fourth AND gate A4 is electrically connected to the control terminals of the sixth switch S6 and the seventh switch S7, respectively. The first terminal of the third delay unit D3 is electrically connected to the control terminal of the lower power transistor O2 and the first terminal of the fifth AND gate A5, respectively. The second terminal of the third delay unit D3 is electrically connected to the second terminal of the fifth AND gate A5, and the third terminal of the fifth AND gate A5 is electrically connected to the control terminals of the eighth switch S8 and the ninth switch S9, respectively.

[0077] like Figure 8 As shown, the slope detection module 20 also includes a second delayer D2, a third delayer D3, a fourth AND gate A4, and a fifth AND gate A5. The fourth AND gate A4 receives the drive signal H_DRV of the upper power transistor and the drive signal H_DRV of the upper power transistor after being delayed by the second delayer D2 for a time t1 (the second delayer D2 is used to shield the resonant spike current generated by parasitic parameters when the upper power transistor is turned on). After the internally set shielding time t1, the fourth AND gate A4 outputs a high level to the control terminals of the sixth switch S6 and the seventh switch S7, controlling the sixth switch S6 and the seventh switch S7 to be turned on, so that V_Rising output by the first current detection unit 11 is connected to the first terminal of the fifth capacitor C5 through the sixth switch S6, and sent to the third amplifier k3 through the seventh switch S7. The fifth AND gate A5 receives the drive signal L_DRV of the lower power transistor and the drive signal L_DRV of the lower power transistor after being delayed for t2 by the third delayer D3 (the third delayer D3 is used to shield the resonant spike current generated by parasitic parameters when the lower power transistor is turned on). After the internally set shielding time t2, the fifth AND gate A5 outputs a high level to the control terminals of the eighth switch S8 and the ninth switch S9, controlling the eighth switch S8 and the ninth switch S9 to be turned on, so that the V_Falling output by the second current detection unit 12 is connected to the first terminal of the fifth capacitor C5 through the seventh switch S7.

[0078] In a specific implementation method Figure 9 This is a schematic diagram of the circuit structure of another sample-and-hold module provided in an embodiment of this disclosure, as shown below. Figure 9 As shown, the sample-and-hold module also includes a fourth delay unit D4 and a sixth AND gate A6. The first terminal of the fourth delay unit D4 is electrically connected to the control terminal of the upper power transistor O1 and the first terminal of the sixth AND gate A6, respectively. The second terminal of the fourth delay unit D4 is electrically connected to the second terminal of the sixth AND gate A6, and the third terminal of the sixth AND gate A6 is electrically connected to the control terminal of the tenth switch S10.

[0079] The sample-and-hold module also includes a fourth delay circuit D4 and a sixth AND gate A6. The sixth AND gate A6 receives the drive signal H_DRV of the upper power transistor and the drive signal H_DRV of the upper power transistor after being delayed by the fourth delay circuit D4 for a time t3. After the shielding time t3, the tenth switch S10 is turned on, thereby enabling the sampling or holding of V_SRt output by the third amplifier K3 through the sample-and-hold module. That is, when the drive signal H_DRV of the upper power transistor is high, after the shielding time t3, the tenth switch S10 is turned on, and the sample-and-hold module 30 outputs the fourth voltage V_SRo = V_SRt. When the drive signal H_DRV of the upper power transistor is low, the tenth switch S10 is turned off, and the fourth voltage V_SRo output by the sample-and-hold module 30 is the third voltage V_SRt sampled before the tenth switch S10 is turned off. By setting the shielding time, the spike generated in the V_SRt signal output by the third amplifier K3 at the slope reversal time is shielded.

[0080] Based on the above embodiments, the control circuit provided in this disclosure further includes: a control module configured to receive a first control signal output by the overcurrent detection module, output a second control signal according to the first control signal, and send the second control signal to the drive circuit so that the drive circuit generates a drive signal for the upper power transistor and a drive signal for the lower power transistor based on the second control signal.

[0081] When the first control signal output by the overcurrent detection module changes from low to high, the second control signal generated by the control module changes from high to low (that is, the control signal sent to the drive circuit changes from high to low). At this time, the drive signal H_DRV of the upper power transistor generated by the drive circuit based on the second control signal changes from high to low. After the dead time of the drive circuit, the drive signal L_DRV of the lower power transistor generated based on the second control signal changes from low to high.

[0082] Specifically, in combination Figure 10 When the drive signal H_DRV generated by the drive module for the upper power transistor is high, the upper power transistor is turned on. The drive signal H_DRV generated by the drive module enables the first current detection unit, which outputs V_Rising. The sixth switch S6 and the seventh switch S7 of the slope detection module are turned on after an internally set shielding time t1, connecting the V_Rising output from the first current detection unit to the fifth capacitor C5 through the sixth switch S6. Figure 10V_Cap represents the voltage across the fifth capacitor C5. The positive terminal of C5 is connected to the negative terminal of the third amplifier K3 via the seventh switch S7. When the drive signal H_DRV generated by the drive module for the upper power transistor is low, the first current detection unit is turned off, the sixth switch S6 of the slope detection module is turned off, and the seventh switch S7 is also turned off. The voltage in the fifth capacitor C5 remains unchanged. This stage is within the dead time of the alternation between the power transistor and the lower power transistor. When the drive signal L_DRV generated by the drive module for the lower power transistor is high, the lower power transistor is turned on. The drive signal L_DRV generated by the drive module enables the second current detection unit, which outputs V_Falling. The eighth switch S8 and the ninth switch S9 of the slope detection module are turned on after an internally set shielding time t2, connecting the V_Falling output by the second current detection unit to the positive terminal of the fifth capacitor C5 through the eighth switch S8. By setting the amplification factor G1 of the first amplifier in the first current detection unit corresponding to the upper power transistor and the amplification factor G2 of the second amplifier in the second current detection unit corresponding to the lower power transistor, the following condition is met: G1 × R H_ON =G2×R L_ON R H_ON On-resistance of the upper power transistor, R L_ON The on-resistance of the lower power transistor ensures that the voltage across the fifth capacitor C5 in the slope detection module 20 does not change drastically when the upper and lower power transistors are alternately turned on. At this time, the voltage of the fifth capacitor is the synthesis of V_Rising and V_Falling, i.e., V_Cap. The fifth capacitor C5 is input to the third amplifier K3, and together with amplifier K3 and resistor R7, they form a differentiating circuit. After being inverted and amplified by the sixth amplifier K6, the third voltage V_SRt is output. When the drive signal H_DRV of the upper power transistor generated by the drive module is high, after a shielding time t3, the sample-and-hold module sends the third voltage V_SRt output by the slope detection module to the sample-and-hold module composed of the tenth switch S10, the eighth resistor R8, the seventh capacitor C7, and the eighth capacitor C8. After being sent out by the fourth amplifier K4, V_SRt is obtained. The fourth amplifier is a unity-gain buffer.

[0083] The control circuit based on the slope and delay detection of the upper power transistor provided in this embodiment includes a slope detection module. This module determines a third voltage corresponding to the slope of the change in the upper power transistor's on-state current based on the first and second voltages output by the current detection module. A sample-and-hold module outputs a fourth voltage based on the third voltage. A delay correction module determines a correction voltage corresponding to the change in the upper power transistor's on-state current during the turn-off delay. The difference between the preset threshold voltage input to the overcurrent detection module in the initial state and the correction voltage corresponding to the change in the upper power transistor's on-state current during the turn-off delay is used to change the preset threshold voltage input to the overcurrent detection module. This reduces the preset threshold voltage, allowing the overcurrent detection module to output a first control signal earlier to control the upper power transistor's turn-off. The on-state current of the upper power transistor does not exceed the designed maximum current limit. The timing of the first control signal output by the overcurrent detection module to control the upper power transistor's turn-off satisfies the turn-off delay time, preventing power transistor aging and reduced lifespan due to excessive on-state current during the delay.

[0084] Based on the above embodiments, this disclosure also provides a switching circuit, including the control circuit described in any of the above embodiments, which has the beneficial effects described in any of the above embodiments. This disclosure will not provide specific examples of each of these features.

[0085] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0086] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A control circuit based on the slope and delay detection of the upper power transistor, characterized in that, include: The module includes a current detection module, a slope detection module, a sample and hold module, an overcurrent detection module, and a delay correction module. The current detection module is configured to acquire the switching node voltage, and output a first voltage based on the switching node voltage and the input node voltage during the conduction of the upper power transistor, and output a second voltage based on the switching node voltage and the ground node voltage during the conduction of the lower power transistor. The slope detection module is configured to determine a third voltage corresponding to the slope of the change in the on-state current of the upper power transistor based on the first voltage and the second voltage. The sample-and-hold module is configured to sample the third voltage and output the fourth voltage during the conduction period of the upper power transistor, and to hold and output the third voltage at the moment before the lower power transistor is turned on during the conduction period. The overcurrent detection module is configured to output a first control signal based on the first voltage and a preset threshold voltage; The delay correction module is configured to determine a turn-off delay time based on the overcurrent detection module, determine a correction voltage based on the turn-off delay time and a fourth voltage when the first control signal is high, correct a preset threshold voltage input to the overcurrent detection module based on the correction voltage when the first control signal is low, and reset the correction voltage after the preset threshold voltage correction of the overcurrent detection module is completed.

2. The control circuit according to claim 1, characterized in that, The delay correction module includes a delay control signal generation unit, a delay current change determination unit, a correction voltage storage and reset unit, and a threshold correction unit. The delay control signal generation unit is configured to generate a high level to the delay current change determination unit and a low level to the correction voltage storage reset unit and the threshold correction unit when the first control signal output by the overcurrent detection module is high; generate a high level to the threshold correction unit and a low level to the delay current change determination unit and the correction voltage storage reset unit during a second time period when the first control signal output by the overcurrent detection module is low; and generate a high level to the correction voltage storage reset unit and a low level to the delay current change determination unit and the threshold correction unit during a third time period. The delay current change determination unit is configured to determine the correction voltage based on the turn-off delay time and the fourth voltage when the first control signal output by the overcurrent detection module is high. The correction voltage storage and reset unit is configured to store the correction voltage when the first control signal output by the overcurrent detection module is high, and to reset the correction voltage when the first control signal output by the overcurrent detection module is low and is in the third time period. The threshold correction unit is configured to output a correction voltage to correct the preset threshold voltage input to the overcurrent detection module when the first control signal output by the overcurrent detection module is low and is in the second time period.

3. The control circuit according to claim 2, characterized in that, The delay control signal generation unit includes a first AND gate, a first delay unit, a second AND gate, a third AND gate, a NOR gate, and an XOR gate. The first terminal of the first AND gate and the first terminal of the first delay unit are electrically connected to the output terminal of the overcurrent detection module. The second terminals of the first AND gate and the second terminals of the second AND gate are electrically connected to the chip start-up completion indication signal terminal. The first terminal of the second AND gate is electrically connected to the second terminal of the first delay unit. The third terminal of the first AND gate is electrically connected to the first terminal of the third AND gate, the first terminal of the NOR gate, and the enable terminal of the delay current change determination unit. The third terminal of the second AND gate is electrically connected to the second terminal of the third AND gate, the second terminal of the NOR gate, and the second terminal of the XOR gate. The third terminal of the third AND gate is electrically connected to the first terminal of the XOR gate. The delay current change determination unit includes a first transconductance amplifier, the first terminal of the first transconductance amplifier is electrically connected to the output terminal of the sample and hold module, the second terminal of the first transconductance amplifier is electrically connected to the ground node, and the third terminal of the first transconductance amplifier is electrically connected to the power supply voltage node. The corrected voltage storage reset unit includes a first capacitor and a first switch. The first end of the first capacitor is electrically connected to the fourth end of the first transconductance amplifier and the first end of the first switch, respectively. The second end of the first capacitor and the second end of the first switch are electrically connected to a ground node. The threshold correction unit includes a fifth amplifier, a second switch, a third switch, a second capacitor, and a first voltage source. The first terminal of the fifth amplifier is electrically connected to the first terminal of the first capacitor. The second terminal of the fifth amplifier is electrically connected to a ground node. The third terminal of the fifth amplifier is electrically connected to the first terminal of the second switch. The fourth terminal of the fifth amplifier is electrically connected to the second terminal of the third switch and the first voltage source, respectively. The enable terminal of the fifth amplifier and the control terminal of the second switch are electrically connected to the third terminal of the XOR gate. The second terminal of the second switch is electrically connected to the first terminal of the second capacitor and the first terminal of the third switch, respectively. The control terminal of the third switch is electrically connected to the chip startup completion enable signal terminal. The second terminal of the second capacitor is electrically connected to a ground node. The second time period is the same as the delay time of the first delay unit in the overcurrent detection module.

4. The control circuit according to claim 1, characterized in that, The current detection module includes a first current detection unit and a second current detection unit. The first current detection unit includes a fourth switch, a first resistor, a second resistor, a third resistor, a third capacitor, a first amplifier, and a second voltage source. The control terminal of the fourth switch is electrically connected to the control terminal of the upper power transistor. The first terminal of the fourth switch is electrically connected to the input node. The second terminal of the fourth switch is electrically connected to the first terminals of the first resistor and the second resistor, respectively. The second terminals of the first resistor and the third resistor are electrically connected to the switch node, respectively. The second terminal of the second resistor is electrically connected to the first terminal of the third capacitor and the first terminal of the first amplifier, respectively. The second terminals of the third resistor and the third capacitor are electrically connected to the second terminal of the first amplifier, respectively. The third terminal of the first amplifier is electrically connected to the slope detection module. The fourth terminal of the first amplifier is electrically connected to the first terminal of the second voltage source, and the second terminal of the second voltage source is electrically connected to the ground node. The second current detection unit includes a fifth switch, a fourth resistor, a fifth resistor, a sixth resistor, a fourth capacitor, a second amplifier, and a third voltage source. The control terminal of the fifth switch is electrically connected to the control terminal of the lower power transistor. The first terminal of the fifth switch is electrically connected to a ground node. The second terminal of the fifth switch is electrically connected to the first terminals of the fourth and fifth resistors respectively. The second terminals of the fourth and sixth resistors are electrically connected to the switch node respectively. The second terminal of the fifth resistor is electrically connected to the first terminal of the fourth capacitor and the first terminal of the second amplifier respectively. The second terminals of the sixth resistor and the fourth capacitor are electrically connected to the second terminal of the second amplifier respectively. The third terminal of the second amplifier is electrically connected to the slope detection module. The fourth terminal of the second amplifier is electrically connected to the first terminal of the third voltage source. The second terminal of the third voltage source is electrically connected to a ground node.

5. The control circuit according to claim 1, characterized in that, The slope detection module includes a sixth switch, a seventh switch, an eighth switch, a ninth switch, a fifth capacitor, a third amplifier, a sixth capacitor, a seventh resistor, and a sixth amplifier. The first terminal of the sixth switch is electrically connected to the first output terminal of the current detection module. The second terminal of the sixth switch is electrically connected to the first terminal of the fifth capacitor and the second terminal of the eighth switch. The first terminal of the eighth switch is electrically connected to the second output terminal of the current detection module. The second terminal of the fifth capacitor is electrically connected to the first terminal of the seventh switch and the first terminal of the ninth switch. The second terminal of the seventh switch is electrically connected to the first terminal of the sixth capacitor, the first terminal of the third amplifier, and the first terminal of the seventh resistor. The second terminal of the third amplifier is electrically connected to a ground node. The third terminal of the third amplifier is electrically connected to the second terminal of the seventh resistor, the second terminal of the sixth capacitor, and the first terminal of the sixth amplifier. The second terminal of the sixth amplifier is electrically connected to a ground node. The third terminal of the sixth amplifier is electrically connected to the sample-and-hold module. The control terminals of the sixth and seventh switches are electrically connected to the control terminals of the upper power transistor. The control terminals of the eighth and ninth switches are electrically connected to the control terminals of the lower power transistor.

6. The control circuit according to claim 1, characterized in that, The sample-and-hold module includes a tenth switch, a seventh capacitor, an eighth capacitor, an eighth resistor, and a fourth amplifier; The first terminal of the tenth switch is electrically connected to the slope detection module. The second terminal of the tenth switch is electrically connected to the first terminal of the seventh capacitor and the first terminal of the eighth resistor. The control terminal of the tenth switch is electrically connected to the control terminal of the upper power transistor. The second terminals of the seventh capacitor, the eighth capacitor, and the fourth amplifier are electrically connected to the ground node. The second terminal of the eighth resistor is electrically connected to the first terminal of the eighth capacitor and the second terminal of the fourth amplifier. The third terminal of the fourth amplifier is electrically connected to the delay correction module.

7. The control circuit according to claim 5, characterized in that, The slope detection module further includes a second delay unit, a third delay unit, a fourth AND gate, and a fifth AND gate. The first terminal of the second delay unit is electrically connected to the control terminal of the upper power transistor and the first terminal of the fourth AND gate, respectively. The second terminal of the second delay unit is electrically connected to the second terminal of the fourth AND gate, and the third terminal of the fourth AND gate is electrically connected to the control terminals of the sixth switch and the seventh switch, respectively. The first terminal of the third delay is electrically connected to the control terminal of the lower power transistor and the first terminal of the fifth AND gate, the second terminal of the third delay is electrically connected to the second terminal of the fifth AND gate, and the third terminal of the fifth AND gate is electrically connected to the control terminals of the eighth switch and the ninth switch.

8. The control circuit according to claim 6, characterized in that, The sample-and-hold module further includes a fourth delay unit and a sixth AND gate. The first terminal of the fourth delay unit is electrically connected to the control terminal of the upper power transistor and the first terminal of the sixth AND gate, respectively. The second terminal of the fourth delay unit is electrically connected to the second terminal of the sixth AND gate, and the third terminal of the sixth AND gate is electrically connected to the control terminal of the tenth switch.

9. The control circuit according to claim 1, characterized in that, It also includes a control module; The control module is configured to receive a first control signal output by the overcurrent detection module, output a second control signal according to the first control signal, and send the second control signal to the drive circuit so that the drive circuit generates a drive signal for the upper power transistor and a drive signal for the lower power transistor based on the second control signal.

10. A switching circuit, characterized in that, Includes the control circuit described in any one of claims 1-9.

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