A time-to-digital conversion device, a time-correlated single photon counting system and a time-to-digital conversion method
By combining a time-to-digital converter with programmable logic circuits and a dedicated timing integrated circuit, the problems of low counting efficiency and poor temperature stability are solved, achieving high-precision time-to-digital conversion with uniform bin width, which is suitable for long-duration detection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIAMEN UNIV
- Filing Date
- 2023-12-29
- Publication Date
- 2026-05-19
AI Technical Summary
Existing ASIC-based time-to-digital converters suffer from low counting efficiency due to excessively large numbers of bits in the coarse time value when the measurement range is too long, and also have problems such as uneven bin width and poor temperature stability.
A combination of programmable logic circuits and dedicated timing integrated circuits is adopted. The clock module generates gate pulse signals, and the first and second counters count the start and end edges respectively. The selector selects the coarse time value according to the fine time value. Combined with a phase-locked loop, efficient communication and accurate timing are achieved.
It improves counting efficiency, achieves high precision, uniform bin width and good temperature stability, can accurately determine event time, and is suitable for long-duration detection.
Smart Images
Figure CN117590731B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of time-to-digital conversion, specifically to a time-to-digital conversion device, a time-correlated single-photon counting system, and a time-to-digital conversion method. Background Technology
[0002] A Time-to-Digital Converter (TDC) is a digital device used to identify events and obtain the precise time of their occurrence. TDCs are widely used in many fields, including precision time measurement, medical imaging, high-energy physics, quantum communication, fluorescence lifetime imaging, and time-correlated single-photon counting systems. In different applications, TDCs are typically implemented using two main methods: methods based on Field Programmable Gate Arrays (FPGAs) and methods based on Application Specific Integrated Circuits (ASICs).
[0003] FPGA-based methods include the vernier caliper method, the tapped delay line method, and the coarse + fine measurement method. These methods utilize FPGAs to achieve long-duration measurements and have the advantages of relatively simple development and easy portability. However, they also have disadvantages such as relatively low measurement accuracy, uneven bin width, poor stability, and susceptibility to factors such as power, voltage, and temperature.
[0004] ASIC-based methods typically require collaboration with FPGAs or control units (MCUs) and offer advantages such as high precision, uniform bin width, and good temperature stability. ASICs usually generate time values consisting of two parts: a coarse time value and a fine time value. The more bits in the coarse time value, the wider the measurable range (duration). However, because ASICs need to communicate with FPGAs or MCUs, an excessively large coarse time value will limit their counting efficiency. Summary of the Invention
[0005] The purpose of this application is to overcome the above-mentioned defects or problems in the background art and provide a time-to-digital conversion device, a time-correlated single-photon counting system and a time-to-digital conversion method, which can avoid the problem of low counting efficiency caused by the large number of bits of coarse time values in ASIC when the measurement range is too long, while taking advantage of the high precision, uniform bin width and good temperature stability of ASIC.
[0006] To achieve the above objectives, the following technical solution is adopted:
[0007] The first technical solution relates to a time-to-digital conversion device, comprising: a programmable logic circuit including a clock module and at least one conversion module; the clock module sends a gate pulse signal every set period, the gate pulse signal having a start edge for marking the beginning of the period and an end edge for marking half a period; the conversion module includes a first counter, a second counter, and a selector; the first counter receives the gate pulse signal and counts the start edge to form a first count value, which is output to the selector; the second counter receives the gate pulse signal and counts the end edge to form a second count value, which is output to the selector; the selector receives a first signal containing a fine time value, and selects the first count value to form a coarse time value when the fine time value is less than half a period value, and selects the second count value to form a coarse time value when the fine time value is greater than or equal to half a period value; the selector also outputs a time tag containing at least a time value, the time value being... The system includes coarse and fine time values; and a dedicated timing integrated circuit that receives the gate pulse signal and has timing modules that are equal in number and correspond one-to-one with the conversion modules. The timing module receives an event signal and sends a first signal to the selector of the corresponding conversion module. The fine time value in the first signal is the time interval between the timing module receiving the most recent start edge and the timing module receiving the event signal. The period of the clock module is configured to be greater than twice the total delay. The total delay is the sum of a first delay value, a second delay value, and a third delay value. The first delay value is the time interval between the clock module sending the gate pulse signal and the timing module receiving the gate pulse signal. The second delay value is the time interval between the timing module receiving the event signal and the timing module sending the first signal. The third delay value is the time interval between the timing module sending the first signal and the selector receiving the first signal.
[0008] The second technical solution is based on the first technical solution, wherein the clock module adopts a phase-locked loop.
[0009] The third technical solution is based on the first technical solution, wherein when the start edge of the gate pulse signal is a rising edge, the end edge is a falling edge; and when the start edge of the gate pulse signal is a falling edge, the end edge is a rising edge.
[0010] The fourth technical solution is based on the first technical solution, wherein the time tag further includes the identification information of the conversion module or the corresponding timing module.
[0011] The fifth technical solution is based on the first technical solution, wherein the conversion module further includes a time tag memory, which is used to receive and store time tags.
[0012] The sixth technical solution is based on the fifth technical solution. In this solution, the conversion module further includes a time-segmentation statistical unit and a statistical value storage unit. The time-segmentation statistical unit is used to receive time tags from the time tag storage unit and count the number of time tags in each specific time period to form a time-segmentation statistical value. The statistical value storage unit is used to receive and store the time-segmentation statistical value.
[0013] The seventh technical solution is based on the sixth technical solution, wherein the editable logic circuit further includes a first communication module, which is used to send time-segmented statistical values.
[0014] The eighth technical solution is based on the fifth technical solution, wherein the editable logic circuit further includes a second communication module, which is used to send time tags.
[0015] The ninth technical solution relates to a time-correlated single-photon counting system, which includes a photon detection device and a time-to-digital conversion device as described in any of the first to eighth technical solutions, wherein the single-photon detection device outputs an event signal to the timing module when it detects a photon.
[0016] The tenth technical solution relates to a time-to-digital conversion method, comprising: generating and transmitting gate pulse signals periodically using an editable logic circuit, the gate pulse signals having a start edge for marking the beginning of the period and an end edge for marking half a period; generating fine time values of events based on the gate pulse signals using a dedicated timing integrated circuit; receiving the fine time values by the editable logic circuit, generating a coarse time value based on counting the start edge when the fine time value is less than half a period value, and generating a coarse time value based on counting the end edge when the fine time value is greater than or equal to half a period value; and merging the coarse time value and the fine time value by the editable logic circuit to generate a time value.
[0017] Compared with existing technologies, the above solution has the following beneficial effects:
[0018] In the first technical solution, the first signal generated and transmitted by the dedicated timing integrated circuit contains only fine time values, thus requiring relatively few bits. This results in high communication efficiency with the programmable logic circuit, leading to high counting efficiency. Furthermore, since the fine time values are generated by the dedicated timing integrated circuit, it achieves advantages such as high precision, uniform bin width, and good temperature stability characteristic of dedicated timing integrated circuits.
[0019] In the first technical solution, since the time value is ultimately generated by the programmable logic circuit, and the event signal is only sent to the dedicated timing integrated circuit, the programmable logic circuit needs to determine the coarse time value based on the fine time value sent by the dedicated timing integrated circuit. However, due to the inherent communication delay between the dedicated timing integrated circuit and the programmable logic circuit, and the calculation delay between the dedicated timing integrated circuit receiving the event signal and sending the first signal, under the condition that the total delay value is less than half a cycle value, the coarse time value is determined by selecting the first count value based on the gate pulse start edge when the fine time value is less than half a cycle value, and by selecting the second count value based on the gate pulse end edge when the fine time value is greater than or equal to half a cycle value. This approach obtains an accurate coarse time value and avoids the impact of delay on the determination of the coarse time value.
[0020] In the fourth technical solution, the time tag also contains the identification information of the conversion module, which can determine the channel of event signal transmission and facilitate accurate event location.
[0021] In the sixth technical solution, the number of time tags in each time period is counted by a time-segmented statistician, which facilitates the statistical analysis of events in each time period.
[0022] In the ninth technical solution, the time-correlated single-photon counting system, by applying the aforementioned time-to-digital conversion device, can accurately determine the physical, chemical, or biological characteristics of the atmosphere, water body, or ground that change with location during long-term, wide-area detection of the atmosphere, water body, or ground, which is beneficial for wide-area, long-term detection.
[0023] The time-to-digital conversion method defined in the tenth technical solution realizes the above-mentioned time-to-digital conversion process and has the same technical effect as the first technical solution. Attached Figure Description
[0024] To more clearly illustrate the technical solutions of the embodiments, the accompanying drawings used are briefly described below:
[0025] Figure 1 This is a schematic diagram of the time-to-digital conversion device in Embodiment 1;
[0026] Figure 2 This is a schematic diagram of the time-to-digital conversion method when the fine time value is less than half a period value in Example 1;
[0027] Figure 3 This is a schematic diagram of the time-to-digital conversion method when the fine time value is greater than half a period value in Example 1;
[0028] Figure 4 This is a schematic diagram of the time-to-digital conversion device in Embodiment 2;
[0029] Figure 5This is a schematic diagram of the detection and counting section of the time-correlated single-photon counting system in Example 3.
[0030] Explanation of key figure labels:
[0031] 1. Time-to-digital converter; 2. Programmable logic circuit; 3. Dedicated timing integrated circuit; 4. Clock module; 5. Conversion module; 6. First communication module; 7. First counter; 8. Second counter; 9. Selector; 10. Time tag memory; 11. Time-segmented statistician; 12. Statistical value memory; 13. Timing module; 14. Second communication module; 15. Time-correlated single-photon counting system; 16. Single-photon detector. Detailed Implementation
[0032] Unless otherwise specified, the terms “first,” “second,” or “third,” etc., in the claims and description are used to distinguish different objects and not to describe a particular order.
[0033] Unless otherwise specified, in the claims and description, the terms “center,” “lateral,” “longitudinal,” “horizontal,” “vertical,” “top,” “bottom,” “inner,” “outer,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “clockwise,” “counterclockwise,” etc., indicate the orientation or positional relationship based on the orientation and positional relationship shown in the drawings, and are only for the purpose of simplifying the description, and do not imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation.
[0034] Unless otherwise specified in the claims and description, the terms "fixed connection" or "fixed connection" shall be interpreted broadly to mean any connection in which there is no displacement or relative rotation relationship between the two parties, including non-removable fixed connection, detachable fixed connection, integral connection, and fixed connection by other means or components.
[0035] Unless otherwise specified, the terms “comprising,” “having,” and variations thereof in the claims and description shall mean “including but not limited to.”
[0036] In the claims and description, unless otherwise specified, the term "have" means that a technical feature that follows is part of a technical feature that precedes it.
[0037] In the claims and description, unless otherwise specified, the term "cycle" refers to a period used to divide fine time, where the coarse time value is the cumulative value of the cycle when the event occurs, and the fine time value is the time interval between the time of the event occurrence and the start time of the cycle; the term "half-cycle" refers to a cycle as half of the time interval; the term "half-cycle time" refers to the time elapsed from the start time of the cycle to the half-cycle time; the term "first half-cycle" refers to the portion between the start time of the cycle and the half-cycle time; the term "second half-cycle" refers to the portion between the half-cycle time and the start time of the next cycle; and the term "half-cycle value" refers to the time interval of half a cycle.
[0038] The technical solutions in the embodiments will be clearly and completely described below with reference to the accompanying drawings.
[0039] Example 1
[0040] See Figure 1 , Figure 1 The time-to-digital conversion device 1 in Embodiment 1 is shown. For example... Figure 1 As shown, the time-to-digital converter 1 includes a programmable logic circuit 2 and a dedicated timing integrated circuit 3.
[0041] The programmable logic circuit 2 includes a clock module 4, at least one conversion module 5, and a first communication module 6.
[0042] In this embodiment, clock module 4 employs a phase-locked loop (PLL). Clock module 4 sends a gate pulse signal at set intervals. The gate pulse signal has a start edge to mark the beginning of the cycle and an end edge to mark half a cycle. When the start edge is a rising edge, the end edge is a falling edge; when the start edge is a falling edge, the end edge is a rising edge. In this embodiment, the start edge is a rising edge.
[0043] The conversion module 5 includes a first counter 7, a second counter 8, a selector 9, a time stamp memory 10, a time-segmented statistician 11, and a statistical value memory 12.
[0044] The first counter 7 receives the gate pulse signal and counts the start edge to form a first count value, which is then output to the selector 9.
[0045] The second counter 8 receives the gate pulse signal and counts the end edge to form a second count value, which is then output to the selector 9.
[0046] Selector 9 receives a first signal containing a fine time value sent by dedicated timing integrated circuit 3, and upon receiving the first signal, selects between the latest first count value output by first counter 7 and the latest second count value output by second counter 8 to determine which value is the coarse time value. Specifically, when the fine time value in the first signal is less than half a cycle value, selector 9 selects the first count value as the coarse time value; and when the fine time value in the first signal is greater than or equal to half a cycle value, selector 9 selects the second count value as the coarse time value. Selector 9 also outputs a time tag including the time value and identification information of conversion module 5, wherein the time value includes both the coarse and fine time values.
[0047] The time tag memory 10 uses a first-in-first-out (FIFO) memory for receiving, storing, and sending time tags.
[0048] The time-segmented statistical unit 11 uses a random access memory and a state machine jump method to realize time-segmented statistics. Specifically, the time-segmented statistical unit 11 is used to receive time tags from the time tag memory 10 and count the number of time tags in a specific time period to form time-segmented statistical values.
[0049] The statistical value storage 12 is a first-in-first-out (FIFO) memory, which is used to receive and store statistical values for different time periods.
[0050] The first communication module 6 is used to receive time-segmented statistical values sent by the statistical value storage 12 and output them to the outside.
[0051] In this embodiment, the dedicated timing integrated circuit 3 is model TDC-GPX2, but other chips with similar functions can also be used. The dedicated timing integrated circuit 3 receives gate pulse signals and has timing modules 13 in number and one-to-one correspondence with the conversion modules 5. The timing module 13 receives event signals and sends a first signal to the selector 9 of the corresponding conversion module 5. The first signal contains a fine time value, which is the time interval between the timing module 13 receiving the most recent start edge and the timing module 13 receiving the event signal.
[0052] In this embodiment, the period of the clock module is configured to be greater than twice the total delay. The total delay is the sum of a first delay value, a second delay value, and a third delay value. The first delay value is the time interval between the clock module 4 sending the gate pulse signal and the timing module 13 receiving the gate pulse signal; the second delay value is the time interval between the timing module 13 receiving the event signal and the timing module 13 sending the first signal; and the third delay value is the time interval between the timing module 13 sending the first signal and the selector 9 receiving the first signal.
[0053] In this embodiment, the time-to-digital converter 1 performs time-to-digital conversion by using an editable logic circuit 2 to generate and send gate pulse signals periodically. The gate pulse signals have a start edge for marking the beginning of the period and an end edge for marking half a period. A dedicated timing integrated circuit 3 generates fine time values for events based on the gate pulse signals. The editable logic circuit 2 receives the fine time values. When the fine time value is less than half a period value, a coarse time value is generated based on the count of the start edge. When the fine time value is greater than or equal to half a period value, a coarse time value is generated based on the count of the end edge. The editable logic circuit 2 then merges the coarse and fine time values to generate a time value.
[0054] Specifically, see Figure 2 and Figure 3 .like Figure 2 As shown, when the event occurs in the first half of the N+1th cycle, due to the existence of the first, second, and third delays, when selector 9 receives the first signal, the first count value of the first counter 7 is N+1, while the second count value of the second counter 8 remains N. Therefore, when the event occurs in the first half of the cycle, the first count value output by the first counter 7, which counts the starting edge, should be selected as the coarse time value. Figure 3 As shown, when the event occurs in the second half of the Nth cycle, due to the presence of the first, second, and third delays, when selector 9 receives the first signal, the first count value of the first counter 7 is N+1, while the second count value of the second counter 8 remains N. Therefore, when the event occurs in the second half of the cycle, the second count value output by the second counter 8, which counts the last edge, should be selected as the coarse time value.
[0055] In this embodiment, the first signal generated and transmitted by the dedicated timing integrated circuit 3 contains only fine time values, thus having a very limited number of bits. Its communication efficiency with the programmable logic circuit 2 is high, resulting in high counting efficiency. Simultaneously, since the fine time values are generated by the dedicated timing integrated circuit 3, advantages such as high precision, uniform bin width, and good temperature stability can be obtained.
[0056] In this embodiment, since the time value is ultimately generated by the programmable logic circuit 2, and the event signal is only sent to the dedicated timing integrated circuit 3, the programmable logic circuit 2 needs to determine the coarse time value based on the fine time value sent by the dedicated timing integrated circuit 3. At this time, since there is an objective communication delay between the dedicated timing integrated circuit 3 and the programmable logic circuit 2, and there is also a calculation delay between the dedicated timing integrated circuit 3 receiving the event signal and sending the first signal, under the condition that the total delay value is less than half a cycle value, when the fine time value is less than half a cycle value, the first count value based on the gate pulse start edge is selected to determine the coarse time value, and when the fine time value is greater than or equal to half a cycle value, the second count value based on the gate pulse end edge is selected to determine the coarse time value. This allows for the acquisition of an accurate coarse time value and avoids the influence of delay on the determination of the coarse time value.
[0057] In this embodiment, the time tag also contains identification information of the conversion module, thereby enabling the determination of the channel through which the event signal is transmitted, facilitating accurate event location.
[0058] In this embodiment, the number of time tags in each time period is counted by the time period counter 11, which facilitates the counting of events in each time period.
[0059] Example 2
[0060] See Figure 4 ,like Figure 4 As shown, the time-to-digital conversion device 1 in Embodiment 2 differs from that in Embodiment 1 in that its conversion module 5 does not include the time-segmentation statistician 11 and the statistical value memory 12, and its programmable logic circuit 2 does not include the first communication module 6 but instead includes a second communication module 14. The second communication module 14 is used to receive time tags from the time tag memory 10 and output them to the outside. Because the time-to-digital conversion device 1 in this embodiment directly outputs time tags, it enables the outside to more accurately grasp the precise time of events and perform statistics based on this.
[0061] Example 3
[0062] See Figure 5 ,like Figure 5 As shown, the time-correlated single-photon counting system 15 in Embodiment 3 includes a single-photon detector 16 and a time-to-digital converter 1 as described in Embodiment 1. The single-photon detector 16 outputs an event signal to the timing module 13 when a photon is detected. Therefore, the time-to-digital converter 1 can count photon quantities in time segments over long periods, thereby enabling the detection of physical, chemical, or biological characteristics of the atmosphere, water bodies, and the ground.
[0063] The description of the above specification and embodiments is used to explain the scope of protection of this application, but does not constitute a limitation on the scope of protection of this application.
Claims
1. A time-to-digital converter (1), characterized in that, include: An editable logic circuit (2) includes a clock module (4) and at least one conversion module (5). The clock module (4) sends a gate pulse signal at set intervals. The gate pulse signal has a start edge for marking the beginning of the cycle and an end edge for marking half a cycle. The conversion module (5) includes a first counter (7), a second counter (8), and a selector (9). The first counter (7) receives the gate pulse signal and counts the start edge to form a first count value, which is output to the selector (9). The second counter (8) receives the gate pulse signal and counts the end edge to form a second count value, which is output to the selector (9). The selector (9) receives a first signal containing a fine time value and selects the first count value to form a coarse time value when the fine time value is less than half a cycle value, and selects the second count value to form a coarse time value when the fine time value is greater than or equal to half a cycle value. The selector (9) also outputs a time tag containing at least a time value, which includes both a coarse time value and a fine time value. A dedicated timing integrated circuit (3) receives the gate pulse signal and has timing modules (13) that are equal in number and correspond one-to-one with the conversion modules (5). The timing module (13) receives the event signal and sends a first signal to the selector (9) of the corresponding conversion module (5). The fine time value in the first signal is the time interval value between the timing module receiving the nearest start edge and the timing module receiving the event signal. The period of the clock module (4) is configured to be greater than twice the total delay; the total delay is the sum of the first delay value, the second delay value and the third delay value, the first delay value is the time interval between the clock module (4) sending the gate pulse signal and the timing module (13) receiving the gate pulse signal, the second delay value is the time interval between the timing module (13) receiving the event signal and the timing module (13) sending the first signal, and the third delay value is the time interval between the timing module (13) sending the first signal and the selector (9) receiving the first signal.
2. The time-to-digital conversion device (1) as described in claim 1, characterized in that, The clock module (4) uses a phase-locked loop.
3. The time-to-digital conversion device (1) as described in claim 1, characterized in that, When the start edge of the gate pulse signal is a rising edge, the end edge is a falling edge; when the start edge of the gate pulse signal is a falling edge, the end edge is a rising edge.
4. The time-to-digital conversion device (1) as described in claim 1, characterized in that, The time tag also contains identification information of the conversion module (5) or the corresponding timing module (13).
5. The time-to-digital conversion device (1) as described in claim 1, characterized in that, The conversion module (5) also includes a time tag memory (10), which is used to receive, store and send time tags.
6. The time-to-digital conversion device (1) as described in claim 5, characterized in that, The conversion module (5) further includes a time-segmentation statistician (11) and a statistical value storage (12). The time-segmentation statistician (11) is used to receive time tags from the time tag storage (10) and count the number of time tags in a specific time period to form a time-segmentation statistical value. The statistical value storage (12) is used to receive and store the time-segmentation statistical value.
7. The time-to-digital conversion device (1) as described in claim 6, characterized in that, The editable logic circuit (2) further includes a first communication module (6), which is used to send time-segmented statistical values.
8. The time-to-digital conversion device (1) as described in claim 5, characterized in that, The editable logic circuit also includes a second communication module (14), which is used to send time tags.
9. A time-correlated single-photon counting system (15) comprising a single-photon detection device (16) and a time-to-digital converter (1) as described in any one of claims 1 to 8, wherein the single-photon detection device (16) outputs an event signal to the timing module (13) when a photon is detected.
10. A time-to-digital conversion method, applied to a time-to-digital conversion apparatus as described in any one of claims 1 to 8, characterized in that, include: A gate pulse signal is generated and sent periodically using an editable logic circuit (2), the gate pulse signal having a start edge for marking the beginning of the period and an end edge for marking half of the period; Using a dedicated timing integrated circuit (3), fine time values of events are generated based on gate pulse signals; The programmable logic circuit (2) receives the fine time value, and generates the coarse time value based on the count of the start edge when the fine time value is less than the half-cycle value, and generates the coarse time value based on the count of the end edge when the fine time value is greater than or equal to the half-cycle value. and The coarse time value and the fine time value are combined by the editable logic circuit (2) to generate the time value.