A countable pulse generation and detection system and method
By leveraging the collaborative efforts of the FPGA control module and the host computer software, and utilizing opto-isolation switches to achieve efficient communication between hardware and software, the problems of delay and inaccurate timing in pulse detection are solved, ensuring the real-time performance and accuracy of pulse generation and detection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TIANJIN JINHANG COMP TECH RES INST
- Filing Date
- 2023-12-01
- Publication Date
- 2026-06-02
AI Technical Summary
In existing technologies, direct access to hardware registers by software results in unpredictable delays and inaccurate pulse waveform timing, leading to inaccurate pulse detection results.
The FPGA control module and the host computer software have a clear division of labor. The FPGA is responsible for pulse generation and feedback of the remaining pulse count, while the host computer is responsible for calculating the total number of pulses and judging the detection results. Efficient communication between the hardware and software is achieved through opto-isolation switches.
It achieves efficient collaboration between hardware and software, ensuring the real-time performance and accuracy of pulse generation and detection, and solving the problems of delay and inaccurate timing.
Smart Images
Figure CN117590895B_ABST
Abstract
Description
Technical Field
[0001] This disclosure generally relates to the field of electronic technology, and specifically to a system and method for generating and detecting countable pulses. Background Technology
[0002] Since the pulse period and width are generally in the millisecond range, the duration is short. Software with a human-machine interface typically runs on complex operating systems, such as Windows, resulting in poor real-time performance. If such software directly accesses hardware registers, obtains the valid state of the counting enable signal, delays the timing using the `sleep()` function, and then directly accesses the hardware registers to control the on / off state of the hardware optocoupler to generate the pulse, two problems arise: First, due to the inherent delay caused by the periodic operation of the host computer software, directly reading and determining the validity of the counting enable signal before controlling the on / off state of the hardware optocoupler to output the pulse signal will inevitably result in unpredictable delays. If the control system does not receive a pulse input after the count enable signal is valid, it will shut down the counting enable signal, preventing subsequent detection. Second, the inaccurate timing of the `sleep()` function will cause inaccurate pulse waveform duration, meaning an ideal pulse waveform cannot be generated, which will also affect the control system's detection results. Summary of the Invention
[0003] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a countable pulse generation pre-detection system and detection method to solve the above problems.
[0004] The first aspect of this application provides a countable pulse generation and detection system, including: an FPGA control module, a host computer, and a photoelectric switch module;
[0005] The FPGA control module includes a pulse counting unit, a counting enable state unit, and a pulse generation unit.
[0006] The pulse counting unit is electrically connected to the host computer and is used to store the total number of pulses written by the host computer and to feed back the remaining number of pulses to the host computer. The remaining number of pulses is the difference between the total number of pulses and the number of pulses already generated.
[0007] The counting enable state unit and the pulse generation unit are electrically connected to the photoelectric switch module, respectively. The counting enable state unit is used to receive an external enable signal collected by the photoelectric switch module. The external enable signal is used to control the counting enable state unit to be in an active or inactive state. When in the active state, the pulse generation unit generates a pulse and outputs it to the outside by the photoelectric switch module. When in the inactive state, the pulse generation unit stops generating pulses. When the pulse enable state is active, the total number of pulses decreases by 1 for each pulse generated by the pulse generation unit.
[0008] According to the technical solution provided in the embodiments of this application, the photoelectric switch module includes:
[0009] A counting enable signal acquisition unit is provided, wherein the input terminal of the counting enable signal acquisition unit is electrically connected to an external power supply device, and the output terminal of the counting enable signal acquisition unit is electrically connected to the input terminal of the counting enable state unit; the counting enable signal acquisition unit is used to control the counting enable state unit to switch between the valid state and the invalid state;
[0010] A pulse signal conversion unit, wherein the input terminal of the pulse signal conversion unit is electrically connected to the output terminal of the pulse generation unit; the pulse signal conversion unit is used to output pulse signals.
[0011] According to the technical solution provided in the embodiments of this application, the counting enable signal acquisition unit adopts a first opto-isolating switch. The input side of the first opto-isolating switch includes a first connection terminal and a grounded first ground terminal. The first connection terminal is electrically connected to an external power supply device. The output side of the first opto-isolating switch includes a second connection terminal and a grounded second ground terminal. The second connection terminal is electrically connected to the counting enable state unit.
[0012] According to the technical solution provided in the embodiments of this application, the pulse signal conversion unit adopts a second opto-isolating switch. The input side of the second opto-isolating switch includes a third connection terminal and a grounded third ground terminal, and the third connection terminal is electrically connected to the pulse generation unit. The output side of the second opto-isolating switch includes a fourth connection terminal and a grounded fourth ground terminal, and the fourth connection terminal is used to output a pulse signal.
[0013] A second aspect of this application provides a method for generating and detecting countable pulses, based on the aforementioned system for generating and detecting countable pulses, comprising the following steps:
[0014] S1: When the counting enable signal acquisition unit acquires the enable signal, the counting enable state unit is placed in the valid state;
[0015] S2: When the host computer determines that the counting enable state unit is in the valid state, it writes the total number of pulses to the pulse counting unit;
[0016] S3: When the pulse generation unit determines that the counting enable state unit is in the valid state and the total number of pulses is greater than zero, it generates a pulse and outputs it to the outside by the pulse signal conversion unit;
[0017] S4: When the pulse counting unit determines that the counting enable state unit is in the valid state and the total number of pulses is greater than zero, the pulse generating unit decrements the total number of pulses by 1 after generating a pulse;
[0018] S5: Repeat S2-S4 above until the total number of pulses is reduced to zero.
[0019] According to the technical solution provided in the embodiments of this application, the following steps are further included between step S3 and step S4:
[0020] When the pulse generation unit determines that the total number of pulses is equal to zero and the counting enable state unit is in the valid state, it stops generating pulses.
[0021] When the pulse generation unit determines that the total number of pulses is greater than zero and the counting enable state unit is in the invalid state, it stops generating pulses.
[0022] According to the technical solution provided in the embodiments of this application, the following steps are further included between step S4 and step S5:
[0023] When the total number of pulses is determined to be zero and the counting enable state unit is still in the valid state, the host computer generates a fault command.
[0024] Compared with the prior art, the beneficial effects of this application are as follows: by using a hardware FPGA control module to communicate with the host computer software through a local bus or serial port, etc.; by giving full play to the advantages of the host computer software and the FPGA control module respectively, and clearly defining the functional division; the host computer software is responsible for calculating the total number of pulses to be sent, while the hardware FPGA control module is responsible for sending the pulse waveform and feeding back the remaining number of pulses to the host computer software, which then judges the rationality of the counting enable signal and the remaining number of pulses and gives the detection result. Attached Figure Description
[0025] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:
[0026] Figure 1 This is a schematic diagram of the countable pulse generation and detection system provided in Example 1;
[0027] Figure 2 This is a schematic diagram of the structure of the counting enable signal acquisition unit;
[0028] Figure 3 This is a schematic diagram of the pulse signal generation unit;
[0029] Figure 4 A flowchart showing the cycle operation of the host computer software;
[0030] Figure 5 This is a diagram of the core state machine of the host computer software.
[0031] Figure 6 The flowchart shows the steps of the countable pulse generation and detection method provided in Example 2.
[0032] Reference numerals: 100, FPGA control module; 110, pulse counting unit; 120, counting enable state unit; 130, photoelectric switch control unit; 200, host computer; 300, pulse generation device; 310, counting enable signal acquisition unit; 311, first connection terminal; 312, first ground terminal; 313, second connection terminal; 314, second ground terminal; 320, pulse signal generation unit; 321, third connection terminal; 322, third ground terminal; 323, fourth connection terminal; 324, fourth ground terminal. Detailed Implementation
[0033] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.
[0034] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.
[0035] Example 1
[0036] Please refer to Figures 1-5 This embodiment provides a countable pulse generation and detection system, including: an FPGA control module 100, a host computer 200, and a photoelectric switch module 300;
[0037] The FPGA control module 100 includes a pulse counting unit 110, a counting enable state unit 120, and a pulse generation unit 130.
[0038] The pulse counting unit 110 is electrically connected to the host computer 200 and is used to store the total number of pulses written by the host computer 200 and to feed back the remaining number of pulses to the host computer 200. The remaining number of pulses is the difference between the total number of pulses and the number of pulses generated.
[0039] The counting enable state unit 120 and the pulse generation unit 130 are electrically connected to the photoelectric switch 300, respectively. The counting enable state unit 120 is used to receive an external enable signal collected by the photoelectric switch module 300. The external enable signal is used to control the counting enable state unit 120 to be in an active or inactive state. When it is in the active state, the optical pulse generation unit 130 controls the generation of pulses and outputs them to the outside by the photoelectric switch module 300. When it is in the inactive state, the pulse generation unit 130 stops generating pulses. When the pulse enable state is in the active state, the total number of pulses decreases by 1 for each pulse generated by the pulse generation unit 130.
[0040] Specifically, the FPGA control module 100, the host computer 200, and the photoelectric switch module 300 communicate via a local bus or serial port. The host computer 200 includes a software interface where users can select the working mode by pressing buttons and view the remaining number of pulses on the display screen. When the user presses a button to enter the pulse generation and detection mode, the software of the host computer 200 begins to run.
[0041] The pulse counting unit 110 is a pulse counting register, and the total number of pulses can be written into the pulse counting unit 110. The counting enable state unit 120 is a counting enable register. When the counting enable state unit 120 receives the external enable signal, it writes 1 to enter the valid state, indicating that 1 is valid. When the counting enable state unit 120 does not receive the external enable signal, it writes 0 to enter the invalid state, indicating that 0 is invalid. The software of the host computer 200 includes FPGA input functions, core state machine functions, and FPGA output functions. The software of the host computer 200 accesses the FPGA control module 100 by calling the FPGA input functions and the FPGA output functions. The software is called with a period of 25ms. Each call first reads the state from the FPGA control module 100, then calls the internal core state machine function, and finally writes the generated data back to the FPGA control module 100 through the FPGA output function.
[0042] The logic of the core state machine function is as follows:
[0043] The current state is determined by step as a state variable. If it is the initial step=0 state, the software reads the remaining pulse count, calculates the total number of pulses to be output, and writes it into the pulse count register through a system call, while displaying it on the display interface; if it is the first time to enter the step=0 state, the remaining pulse count is processed as 50; after the operation is completed, it enters the step=1 state.
[0044] If it is in the step=1 state, read the count enable register. If its content is 1 and it is valid, enter the step=2 state; otherwise, wait in the step=1 state.
[0045] If it is in step=2 state, when the count enable register is kept at 1, the pulse counting unit 110 is read and the remaining pulse count is displayed on the display interface. When the count enable register becomes 0 and is invalid, it enters step=3 state; if the remaining pulse count of the pulse counting register is zero, the count enable register is kept at 1 and a fault prompt message is displayed on the display interface.
[0046] If it is in the step=3 state, wait for two cycles in this state before entering the step=0 state.
[0047] The photoelectric switch module 300 includes:
[0048] A counting enable signal acquisition unit 310 is provided, wherein the input terminal of the counting enable signal acquisition unit 310 is electrically connected to an external power supply device, and the output terminal of the counting enable signal acquisition unit 310 is electrically connected to the input terminal of the counting enable state unit 120; the counting enable signal acquisition unit 310 is used to control the counting enable state unit 120 to switch between the valid state and the invalid state.
[0049] A pulse signal conversion unit 320 is provided, the input terminal of which is electrically connected to the output terminal of the pulse generation unit 130; the pulse signal conversion unit 320 is used to output pulse signals.
[0050] Furthermore, the counting enable signal acquisition unit 310 adopts a first opto-isolating switch. The input side of the first opto-isolating switch includes a first connection terminal 311 and a grounded first ground terminal 312. The first connection terminal 311 is electrically connected to an external power supply device. The output side of the first opto-isolating switch includes a second connection terminal 313 and a grounded second ground terminal 314. The second connection terminal 313 is electrically connected to the counting enable state unit 120.
[0051] Furthermore, the pulse signal conversion unit 320 employs a second opto-isolating switch. The input side of the second opto-isolating switch includes a third connection terminal 321 and a grounded third ground terminal 322. The third connection terminal 321 is electrically connected to the pulse generation unit 130. The output side of the second opto-isolating switch includes a fourth connection terminal 323 and a grounded fourth ground terminal 324. The fourth connection terminal 323 is used to output a pulse signal.
[0052] Specifically, the first connection terminal 311 on the input side of the counting enable signal acquisition unit 310 is electrically connected to an external power supply device, and its input side is 28V effective and disconnected ineffective. The first ground terminal 312 on the input side of the counting enable signal acquisition unit 310 is connected to the ground on the input side. The second connection terminal 313 on the output side of the counting enable signal acquisition unit 310 is electrically connected to the input terminal of the counting enable state 120, and the second ground terminal 314 on its output side is connected to the signal ground of the FPGA control module 100. When the first connection terminal 311 receives a 28V / on input signal, the second connection terminal 313 outputs a high level. When the first connection terminal 311 is floating, the second connection terminal 313 outputs a low level, thereby inputting a standard TTL level to the counting enable state unit 120, so that the counting enable state unit 120 enters a valid 1 state. When the counting enable state unit 120 enters a valid 1 state, the pulse generation unit 130 generates a TTL level pulse according to the standard TTL level, and transmits it to the pulse signal unit 320 from the input side of the pulse signal conversion unit 320. When the input side of the pulse signal conversion unit 320 is floating, its internal voltage is 28V, and it outputs a 28V high level on the output side of the pulse signal conversion unit 320. When the input side of the pulse signal conversion unit 320 is grounded, the output side of the pulse signal conversion unit 320 outputs a low level, thereby realizing the output of a square pulse waveform generated by the mutual switching between the two states of 28V and ground.
[0053] In this embodiment, the FPGA control module 100 and the host computer 200 cooperate to give full play to their respective advantages and clearly define the functional division. The software of the host computer 200 is responsible for calculating the total number of pulses to be sent, while the hardware FPGA control module is responsible for sending the pulses and feeding back the remaining pulse count to the software of the host computer 200. The host computer 200 then judges the rationality of the counting enable signal and the remaining pulse count and gives the detection result, effectively solving the problems existing in the prior art.
[0054] Example 2
[0055] Please refer to Figure 6 This embodiment provides a countable pulse generation and detection method, based on the countable pulse generation and detection system described in Embodiment 1, including the following steps:
[0056] S1: When the counting enable signal acquisition unit 310 acquires the enable signal, the counting enable state unit 120 is placed in the valid state;
[0057] S2: When the host computer 200 determines that the counting enable state unit 120 is in the valid state, it writes the total number of pulses to the pulse counting unit 110.
[0058] S3: When the pulse generation unit 130 determines that the counting enable state unit 120 is in the valid state and the total number of pulses is greater than zero, it generates a pulse and outputs it to the outside by the pulse signal conversion unit (320);
[0059] S4: When the pulse counting unit 110 determines that the counting enable state unit 120 is in the valid state and the total number of pulses is greater than zero, the total number of pulses is decremented by 1 after the pulse generation unit 130 generates a pulse;
[0060] S5: Repeat S2-S4 above until the total number of pulses is reduced to zero.
[0061] Working process: First, the counting enable signal acquisition unit 310 acquires the external enable signal. After the counting enable signal acquisition unit 310 acquires the external enable signal, the counting enable state unit 120 is set to the valid state. When the host computer 200 determines that the counting enable state unit 120 is in the valid state, it writes the total number of pulses to the pulse counting unit 110. After the total number of pulses is written, when the pulse generation unit 130 determines that the counting enable state unit 120 is in the valid state and the total number of pulses is greater than zero, the pulse generation unit... 130 starts generating pulses, which are output by the pulse signal conversion unit 320. During pulse generation, when the pulse counting unit 110 determines that the counting enable state unit 120 is in the valid state and the total number of pulses is greater than zero, the pulse counting unit 110 decrements the total number of pulses by 1 after the pulse generation unit 130 generates a pulse. Then, the pulse counting unit 110 feeds back the remaining number of pulses to the host computer 200 and displays it on the display interface. The above steps are repeated until the total number of pulses is reduced to zero, at which point the pulse generation unit 130 stops generating pulses.
[0062] Furthermore, the following steps are included between steps S3 and S4:
[0063] When the pulse generation unit 130 determines that the total number of pulses is equal to zero and the counting enable state unit 120 is in the valid state, it stops generating pulses.
[0064] When the pulse generation unit 130 determines that the total number of pulses is greater than zero and the counting enable state unit 120 is in the invalid state, it stops generating pulses.
[0065] Specifically, when the pulse generation unit 130 determines that the total number of pulses is equal to zero and the counting enable state unit 120 is in the valid state, it proves that all the required pulses have been generated and there is no need to continue generating pulse signals. Therefore, the pulse generation unit 130 stops generating pulses until the host computer 200 rewrites the new total number of pulses.
[0066] Furthermore, the following steps are included between steps S4 and S5:
[0067] When the total number of pulses is determined to be zero and the counting enable state unit 120 is still in the valid state, the host computer 200 generates a fault command.
[0068] Specifically, under normal circumstances, when the total number of pulses is equal to zero, the counting enable state unit 120 will be placed in the invalid state. When the total number of pulses is equal to zero and the counting enable state unit 120 is still in the valid state, it indicates that the FPGA control module 100 has malfunctioned. Therefore, the host computer 200 generates a fault command.
[0069] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.
Claims
1. A countable pulse generation and detection system, characterized in that, include: FPGA control module (100), host computer (200) and photoelectric switch module (300); The FPGA control module (100) includes a pulse counting unit (110), a counting enable state unit (120), and a pulse generation unit (130): The pulse counting unit (110) is electrically connected to the host computer (200) and is used to store the total number of pulses written by the host computer (200) and to feed back the remaining number of pulses to the host computer (200). The remaining number of pulses is the difference between the total number of pulses and the number of pulses generated. The counting enable state unit (120) and the pulse generation unit (130) are electrically connected to the photoelectric switch module (300), respectively. The counting enable state unit (120) is used to receive the external enable signal collected by the photoelectric switch module (300). The external enable signal is used to control the counting enable state unit (120) to be in an active or inactive state. When it is in the active state, the pulse generation unit (130) generates a pulse and outputs it to the outside by the photoelectric switch module (300). When it is in the inactive state, the pulse generation unit (130) stops generating pulses. When the counting enable state unit (120) is in the active state, the total number of pulses decreases by 1 for each pulse generated by the pulse generation unit (130).
2. The countable pulse generation and detection system according to claim 1, characterized in that, The photoelectric switch module (300) includes: A counting enable signal acquisition unit (310) is provided, wherein the input terminal of the counting enable signal acquisition unit (310) is electrically connected to an external power supply device, and the output terminal of the counting enable signal acquisition unit (310) is electrically connected to the input terminal of the counting enable state unit (120); the counting enable signal acquisition unit (310) is used to control the counting enable state unit (120) to switch between the valid state and the invalid state; A pulse signal conversion unit (320) is provided, the input terminal of which is electrically connected to the output terminal of the pulse generation unit (130); the pulse signal conversion unit (320) is used to output pulses to the outside.
3. The countable pulse generation and detection system according to claim 2, characterized in that, The counting enable signal acquisition unit (310) adopts a first opto-isolating switch. The input side of the first opto-isolating switch includes a first connection terminal (311) and a grounded first ground terminal (312). The first connection terminal (311) is electrically connected to an external power supply device. The output side of the first opto-isolating switch includes a second connection terminal (313) and a grounded second ground terminal (314). The second connection terminal (313) is electrically connected to the counting enable state unit (120).
4. The countable pulse generation and detection system according to claim 3, characterized in that, The pulse signal conversion unit (320) adopts a second opto-isolating switch. The input side of the second opto-isolating switch includes a third connection terminal (321) and a grounded third ground terminal (322). The third connection terminal (321) is electrically connected to the pulse generation unit (130). The output side of the second opto-isolating switch includes a fourth connection terminal (323) and a grounded fourth ground terminal (324). The fourth connection terminal (323) is used to output pulse signals.
5. A method for generating and detecting countable pulses, based on the countable pulse generation and detection system described in claim 4 above, characterized in that, Includes the following steps: S1: When the counting enable signal acquisition unit (310) acquires the enable signal, the counting enable state unit (120) is placed in the valid state; S2: When the host computer (200) determines that the counting enable state unit (120) is in the valid state, it writes the total number of pulses to the pulse counting unit (110); S3: When the pulse generation unit (130) determines that the counting enable state unit (120) is in the valid state and the total number of pulses is greater than zero, it generates a pulse and outputs it to the outside by the pulse signal conversion unit (320); S4: When the pulse counting unit (110) determines that the counting enable state unit (120) is in the valid state and the total number of pulses is greater than zero, it decrements the total number of pulses by 1 after the pulse generation unit (130) generates a pulse; S5: Repeat S2-S4 above until the total number of pulses is reduced to zero.
6. The countable pulse generation and detection method according to claim 5, characterized in that, The following steps are also included between steps S3 and S4: When the pulse generation unit (130) determines that the total number of pulses is equal to zero and the counting enable state unit (120) is in the valid state, it stops generating pulses. When the pulse generation unit (130) determines that the total number of pulses is greater than zero and the counting enable state unit (120) is in the invalid state, it stops generating pulses.
7. The method for generating and detecting countable pulses according to claim 6, characterized in that, The following steps are also included between steps S4 and S5: When the total number of pulses is determined to be zero and the counting enable state unit (120) is still in the valid state, the host computer (200) generates a fault command.