Bus-powered communication system and method for measuring bus resistance

Abstract

The application belongs to the technical field of bus-powered communication and provides a bus-powered communication system and a bus resistance measurement method capable of accurately measuring bus resistance, which comprises a master device and a plurality of slave devices, the master device comprises a first processor, a first power module, a first signal transceiver circuit, a measurement current generating circuit and a signal amplification measurement circuit, the slave device comprises a second processor, a second power module, a second signal transceiver circuit and a correction short circuit, the first processor in the master device controls the measurement current generating circuit to provide a measurement current with a settable size to the bus, so that the bus resistance measurement range is large, the application range is wide, the measurement precision is high, and the automatic measurement of the bus resistance of the slave device can be realized.

Description

Technical Field

[0001] This invention relates to the field of bus-powered communication systems, and more specifically to a bus-powered communication system and a method for accurately measuring the internal resistance of the bus. Background Technology

[0002] Bus-powered communication systems are relatively simple to wire, requiring only two power cables to achieve both power supply and communication functions. They eliminate the need for laying and maintaining communication lines, resulting in low cost and simple construction. The communication performance is excellent, equivalent to wired communication, and is widely used in many fields. Existing communication devices are assigned a unique address at the factory, ensuring that devices installed on the same network will not interfere with each other's communication. However, these addresses are typically long, making recording and use cumbersome. During on-site installation, manual configuration of addresses and device mappings is required. There are generally two approaches: one is to record the device address during installation, obtaining it directly from the device via a nameplate or some communication method; the other is for the host to have an automatic device search function, acquiring all addresses and then using accompanying software to "instruct" the devices—that is, by activating a specific device address and visually observing the result—to determine the address-device mapping. If the internal resistance of the bus between the master and slave devices can be accurately measured, and different numbers can be assigned to the devices according to the distance between them, the simplest approach is for the master to assign sequential numbers to the slave devices according to their distance. This way, the device address can be determined from its location, thus avoiding complex address management.

[0003] Current methods for measuring the internal resistance of the wire from the master to the slave device rely on the slave device drawing current and detecting the bus voltage drop. Since the bus resistance is very small and the slave device's current draw is limited, the voltage drop across the bus is very small, denoted as Vsmall. However, the bus voltage at the slave end is relatively high, denoted as Vbig. Therefore, the relative voltage drop Vsmall / Vbig is very small, requiring high analog sampling accuracy from the slave device. Furthermore, a large current draw from the slave device results in a voltage drop Vdrop on the master side. The slave device cannot distinguish between the bus voltage drop Vsmall and the master-side voltage drop Vdrop, thus affecting measurement accuracy. Additionally, due to the very small bus resistance, the slave device needs to draw a large current, meaning it consumes a significant amount of power instantaneously. The master side needs to supply high power, while the slave side needs to dissipate this power without damaging the circuitry. These requirements necessitate precise constant current generation circuits for each slave device, increasing the complexity and cost of the equipment. Therefore, how to accurately measure internal resistance under low-cost conditions has become a pressing problem in this field. Summary of the Invention

[0004] To meet the practical needs of the bus power supply communication field, this invention overcomes the shortcomings of the existing technology. The technical problem to be solved is to provide a bus power supply communication system and internal resistance measurement method that can accurately measure the internal resistance of the bus, so as to realize the accurate measurement of the internal resistance of the bus power supply communication system.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: a bus power supply communication system that can accurately measure the internal resistance of the bus, characterized in that it includes a master device and multiple slave devices, wherein the master device includes a first processor, a first power supply module, a first signal transceiver circuit, a current measurement generation circuit and a signal amplification and measurement circuit;

[0006] The first power module is used for power supply, and the first signal transceiver circuit is used to modulate the power supply voltage output by the first power module under the control of the first processor to supply power to the bus and send signals; the current measurement generation circuit is used to output a set measurement current to the bus, and the signal amplification measurement circuit is used to measure the bus voltage drop at the master device end; the first processor is used to control the switching of the connection between the first signal transceiver circuit and the current measurement generation circuit and the bus, and is also used to control the output current of the current measurement generation circuit, and to receive the measurement value of the signal amplification measurement circuit to calculate the bus internal resistance from the master device to the slave device;

[0007] The slave device includes a second processor, a second power module, a second signal transceiver circuit, and a correction shorting circuit;

[0008] The second power module is used to supply power to the second processor after obtaining power from the bus through the second signal transceiver circuit. The processor is used to communicate bidirectionally with the master device through the second signal transceiver circuit. The correction short-circuit circuit is used to short-circuit the positive and negative terminals of the bus when measuring the bus resistance, and after short-circuiting, measure the voltage between the positive and negative terminals of the bus and send it to the second processor.

[0009] The correction short-circuit circuit includes field-effect transistors Q1 and Q2. The drain of field-effect transistor Q1 is connected to the positive terminal of the bus, the gate of field-effect transistor Q1 is connected to the control terminal CTL of the second processor, and the source is connected to the negative terminal of the bus. The drain of field-effect transistor Q2 is connected to the positive terminal of the bus, the source is connected to the input terminal of the second processor, and the gate is connected to the control terminal CTL.

[0010] The current measurement generating circuit includes a dual-channel operational amplifier D3, a field-effect transistor V10, a Zener diode TS8, a field-effect transistor V12, and several resistors and capacitors. The positive input terminal of the first channel of the dual-channel operational amplifier D3 is connected to one end of resistor R59. The other end of resistor R59 is connected to the first current signal output terminal CUR_500mA of the first processor. The other end of resistor R59 is also connected to one end of resistor R63. The other end of resistor R63 is connected to the second current signal output terminal CUR_300mA of the first processor. The other end of resistor R63 is also connected to the third current signal output terminal CUR_150mA of the first processor via resistor R63. Through these three output terminals, the first processor can control the current measurement generating circuit to output different current values. The positive input terminal of the first channel of the dual-channel operational amplifier D3 is also connected to the positive power supply terminal via a pull-up resistor R54. The negative input terminal of the first channel of the dual-channel operational amplifier D3 is connected to the positive power supply through resistors R55 and R52. The output terminal of the first channel is connected to the gate of the field-effect transistor V10 through resistor R61. The source of the field-effect transistor V10 is connected to the positive power supply through resistor R52. The drain is connected to the drain of the field-effect transistor V12 through Zener diode TS8. The gate of the field-effect transistor V12 is connected to the positive power supply, and the source is grounded through resistor R69. Capacitor C36 is connected in parallel with resistor R69. The drain of the field-effect transistor V12 is connected to the positive terminal MBUS+ of the bus. The source of the field-effect transistor V12 can output a sampling signal ADC_V. The sampling signal is amplified by the signal measurement amplifier circuit and sent to the first processor to obtain the bus voltage drop at the master device end.

[0011] The signal measurement and amplification circuit includes resistors R57 and R62, capacitor C35, and field-effect transistor V11. The sampling signal ADC_V is connected to the positive input terminal of the second channel of the dual-channel operational amplifier D3. The negative input terminal of the second channel of the dual-channel operational amplifier D3 is grounded through resistor R62. Its second channel output terminal is grounded through resistors R57 and R62. Its second channel output terminal is also connected to the drain of field-effect transistor V11. The gate of field-effect transistor V11 is connected to the positive power supply, and its source is grounded through resistor R68. Capacitor C35 is connected in parallel with resistor R68. In addition, the source of field-effect transistor V11 is connected to the input terminal ADC_VX6 of the first processor to input the measured bus voltage.

[0012] The dual-channel operational amplifier D3 is an LM2904.

[0013] The second power module includes an energy storage capacitor, which is used to obtain electrical energy from the bus terminal through the second signal transceiver circuit for storage, and then supply power to the slave device when there is no voltage on the bus.

[0014] Furthermore, the present invention also provides a method for measuring bus internal resistance, based on the aforementioned bus power supply and communication system capable of accurately measuring bus internal resistance, comprising the following steps:

[0015] Step 1: The master device sends a startup resistor measurement message to the slave device. After receiving the message, the slave device enters a silent state, minimizes power consumption, and monitors the bus voltage.

[0016] Step 2: The first processor of the master device switches the external power supply of the bus from the normal power supply to the current measurement and generation circuit, and begins to monitor the bus voltage;

[0017] Step 3: After the device detects a sharp drop in bus voltage, the second processor enables the correction short-circuit circuit to short-circuit the positive and negative ends of the bus and begins measuring the voltage U1 at the positive and negative ends of the bus on the device side; at the same time, the master device detects the voltage U2 at both ends of the bus on the master device side through the signal amplification and measurement circuit.

[0018] Step 4: The master device sends a request for calibration data message to the slave device, and the slave device replies to the master device with the measured voltage U1 of the positive and negative terminals of the bus at the slave device end;

[0019] Step 5: The master device calculates the bus voltage drop U corresponding to the slave device using the formula: U = U2 - U1, and then obtains the bus resistance corresponding to the slave device.

[0020] Step three also includes the following steps:

[0021] The slave device uses a second processor to determine if the power supply voltage is lower than the set value. If so, it disables the correction short-circuit circuit. After the master device detects a sharp rise in the bus voltage, it switches the bus power supply to the normal power supply circuit, and the slave device draws power from the bus to resume normal operation.

[0022] Compared with the prior art, the present invention has the following advantages:

[0023] 1. This invention provides a bus power supply communication system and internal resistance measurement method capable of accurately measuring bus internal resistance. The host generates various settable measurement currents, ensuring a wide measurement range and broad application scope. The slave device features a short-circuit correction circuit. During measurement, the host measures the bus voltage drop and obtains the short-circuit voltage value from the slave device for correction, thereby accurately determining the bus resistance. In this invention, the slave device circuit is simple, low-cost, and highly accurate, possessing wide applicability.

[0024] 2. This invention can achieve accurate measurement of the bus internal resistance of each slave device without manual intervention, which greatly improves measurement efficiency and accuracy. Attached Figure Description

[0025] Figure 1This is a structural block diagram of a bus power supply and communication system that can accurately measure the internal resistance of the bus, as provided in Embodiment 1 of the present invention.

[0026] Figure 2 This is a block diagram of the main device circuit in Embodiment 1 of the present invention;

[0027] Figure 3 This is a circuit block diagram of the slave device in Embodiment 1 of the present invention;

[0028] Figure 4 This is a circuit diagram of the device correction short-circuit circuit in Embodiment 1 of the present invention;

[0029] Figure 5 This is a circuit diagram of the current generation circuit and the signal amplification measurement circuit of the main device in Embodiment 1 of the present invention. Detailed Implementation

[0030] To make the technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with specific embodiments and accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments; based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] Example 1

[0032] like Figures 1-3 As shown, Embodiment 1 of the present invention provides a bus power supply and communication system capable of accurately measuring bus internal resistance, including a master device and multiple slave devices. The master device and slave devices are connected by two wires, which serve both power supply and communication functions. The master device supplies power to the slave devices, and the slave devices obtain power from the bus. The master and slave devices communicate bidirectionally via the two wires.

[0033] like Figure 2As shown, in this embodiment, the master device includes a first processor, a first power module, a first signal transceiver circuit, a current measurement generation circuit, and a signal amplification measurement circuit. The first power module is used to supply power, and the first signal transceiver circuit is used to modulate the power supply voltage output by the first power module under the control of the first processor to supply power to the bus and send signals. The current measurement generation circuit is used to output a set measurement current to the bus, and the signal amplification measurement circuit is used to measure the bus voltage drop at the master device end. The first processor is used to control the switching of the connection between the first signal transceiver circuit and the current measurement generation circuit and the bus terminals, and is also used to control the output current of the current measurement generation circuit, and to receive the measured positive and negative terminal voltage values ​​of the master device side bus from the signal amplification measurement circuit, and the measured positive and negative terminal voltage values ​​of the slave device side bus from the slave device, and calculate the bus internal resistance between the master device and the slave device.

[0034] In this embodiment, the first power module supplies power not only to the master device itself but also to the slave devices. The first processor controls the first signal transceiver circuit, sending signals to the slave devices by modulating the external power supply voltage and receiving signals from the slave devices by detecting bus voltage or current signals. The current generation circuit primarily outputs a set high current with a low output voltage to reduce the power consumption of the master device. The output current has multiple levels, such as 500mA and 300mA, which can be controlled and adjusted by the processor to generate sufficient voltage drop to meet measurement requirements. The signal amplification and measurement circuit primarily measures the voltage drop across the bus to determine the internal resistance of the wires between the slave device and a specific slave device, further determining the slave device's position on the bus.

[0035] like Figure 2 As shown, in this embodiment, the slave device includes a second processor, a second power module, a second signal transceiver circuit, and a correction short-circuit circuit. The second power module is used to supply power to the second processor after obtaining power from the bus terminal through the second signal transceiver circuit. The processor is used to communicate bidirectionally with the master device through the second signal transceiver circuit. The correction short-circuit circuit is used to short-circuit the positive and negative terminals of the bus when measuring the bus resistance, and after short-circuiting, measure the voltage between the positive and negative terminals of the bus and send it to the second processor.

[0036] Furthermore, in this embodiment, the second power module includes an energy storage capacitor, which is used to obtain electrical energy from the bus terminal through the second signal transceiver circuit for storage, and then supply power to the slave device when there is no voltage on the bus.

[0037] In this embodiment, the second power module primarily obtains electrical energy from the bus to power the slave devices and stores some energy in an energy storage capacitor to ensure the slave devices can operate normally when there is no voltage on the bus. The second processor communicates bidirectionally with the host through the second signal transceiver circuit. The correction short-circuit circuit is used to short-circuit the positive and negative terminals of the bus when measuring the bus resistance and to measure the voltage across the bus on the slave device side after the short circuit to correct the results.

[0038] Specifically, such as Figure 4 As shown, in this embodiment, the correction short-circuit circuit includes field-effect transistors Q1 and Q2. The drain of field-effect transistor Q1 is connected to the positive terminal of the bus, the gate of field-effect transistor Q1 is connected to the output terminal CTL of the second processor, and the source is connected to the negative terminal of the bus. The drain of field-effect transistor Q2 is connected to the positive terminal of the bus, the source is connected to the input terminal of the second processor, and the gate is connected to the CTL terminal. When a short circuit is required, the second processor outputs a control signal to the gate of field-effect transistor Q1, turning on field-effect transistor Q1 and short-circuiting the positive and negative terminals of the bus. Simultaneously, the source of field-effect transistor Q2 outputs a short-circuit voltage signal to the second processor. Alternatively, in this embodiment, the correction short-circuit circuit can also be implemented by controlling a relay.

[0039] Specifically, such as Figure 5The diagram shows the circuit schematic of the current generation circuit and the signal measurement amplification circuit. In this embodiment, the current generation circuit includes a dual-channel operational amplifier D3, a field-effect transistor V10, a Zener diode TS8, a field-effect transistor V12, and several resistors and capacitors. The positive input terminal of the first channel of the dual-channel operational amplifier D3 is connected to one end of resistor R59, and the other end of resistor R59 is connected to the first current signal output terminal CUR_500mA of the first processor. The other end of resistor R59 is also connected to one end of resistor R63, and the other end of resistor R63 is connected to the second current signal output terminal CUR_300mA of the first processor. The other end of resistor R63 is also connected to the third current signal output terminal CUR_150mA of the first processor via resistor R63. Through these three output terminals, the first processor can control the current generation circuit to output different current values. The positive input terminal of the first channel of the dual-channel operational amplifier D3 is also connected to the positive power supply via a pull-up resistor R54. The negative input terminal of the first channel of the dual-channel operational amplifier D3 is connected to the positive power supply through resistors R55 and R52. The output terminal of the first channel is connected to the gate of the field-effect transistor V10 through resistor R61. The source of the field-effect transistor V10 is connected to the positive power supply through resistor R52. The drain is connected to the drain of the field-effect transistor V12 through Zener diode TS8. The gate of the field-effect transistor V12 is connected to the positive power supply, and the source is grounded through resistor R69. Capacitor C36 is connected in parallel with resistor R69. The drain of the field-effect transistor V12 is connected to the positive terminal MBUS+ of the bus. The source of the field-effect transistor V12 can output a sampling signal ADC_V. The sampling signal is amplified by the signal measurement amplifier circuit and sent to the first processor to obtain the bus voltage drop at the master device end.

[0040] Specifically, such as Figure 5 As shown, the signal measurement amplification circuit includes resistors R57, R62, R62, capacitor C35, and field-effect transistor V11. The sampling signal ADC_V is connected to the positive input terminal of the second channel of the dual-channel operational amplifier D3. The negative input terminal of the second channel of the dual-channel operational amplifier D3 is grounded through resistor R62. Its second channel output terminal is grounded through resistors R57 and R62. Its second channel output terminal is also connected to the drain of field-effect transistor V11. The gate of field-effect transistor V11 is connected to the positive power supply, and its source is grounded through resistor R68. Capacitor C35 is connected in parallel with resistor R68. In addition, the source of field-effect transistor V11 is connected to the input terminal ADC_VX6 of the first processor to input the measured bus voltage.

[0041] In this embodiment, the dual-channel operational amplifier D3 is selected as LM2904.

[0042] Example 2

[0043] This embodiment provides a method for measuring bus internal resistance, implemented based on a bus power supply and communication system as described in Embodiment 1, and specifically includes the following steps:

[0044] Step 1: The master device sends a startup resistor measurement message to the slave device. After receiving the message, the slave device enters a silent state, minimizes power consumption, and monitors the bus voltage.

[0045] Step Two: The master device's first processor switches the external power supply from the normal power supply to the current measurement circuit and begins monitoring the bus voltage. Typically, the normal power supply voltage is greater than 12V, while the typical bus voltage generated by the current measurement circuit is around 3V.

[0046] Step 3: At this time, the second signal transceiver circuit of the slave device will detect a sharp drop in bus voltage. After sending the bus voltage to the second processor, the second processor enables the correction short-circuit circuit, which shorts the positive and negative ends of the bus and begins to measure the voltage U1 at the positive and negative ends of the slave device's bus. At the same time, the master device detects the voltage U2 at both ends of the master device's bus through the signal amplification and measurement circuit.

[0047] Furthermore, in this embodiment, the slave device detects a sharp drop in bus voltage and considers the measurement to begin. The slave device then enables a correction short-circuit circuit, which short-circuits the two ends of the bus by closing a relay or a MOSFET switch, simultaneously starting to measure and record the voltage across the bus. When the slave device short-circuits the two ends of the bus, the signal measurement amplification circuit in the master device detects a sharp drop in bus voltage and begins to measure and record the voltage across the master device's bus. During the master-slave measurement process, the slave device draws power from its energy storage capacitor to maintain operation.

[0048] Furthermore, in this embodiment, the master device can automatically switch from measurement mode to communication mode after the measurement is completed. During the measurement process, the slave device simultaneously monitors the bus power supply voltage. When the power supply voltage is lower than a set value, the power correction short-circuit circuit is disabled. At this time, the bus voltage rises sharply to approximately 3V. The master device detects this rise and quickly switches the bus power supply to the normal power supply circuit (first signal transceiver circuit). The slave device then draws power from the bus and resumes normal operation. The entire measurement process is then complete.

[0049] Step 4: The master device sends a request for calibration data message to the slave device, and the slave device replies to the master device with the measured voltage U1 of the positive and negative terminals of the bus at the slave device end.

[0050] Step 5: The master device calculates the bus voltage drop U corresponding to the slave device using the formula: U = U2 - U1, and then obtains the bus resistance corresponding to the slave device.

[0051] Specifically, after receiving the calibration data message, the receiving device replies to the master device with a message containing the measured voltage across the switch composed of a relay or MOSFET. The master device subtracts the bus voltage measured from device A from the voltage measured in step 2 to obtain the actual bus voltage drop and records it.

[0052] In this embodiment, since the bus measurement current output by the current generation circuit is fixed, the measured bus voltage drop U is basically proportional to the bus resistance. By measuring the bus voltage drop, the bus resistance of each slave device can be obtained.

[0053] This invention improves the master and slave device circuits. The master device provides a configurable measurement current, ensuring a wide range of bus resistance measurements and broad application. The slave device circuit has a simple structure and low cost. It can automatically correct for voltage drops introduced by short-circuit switches and accurately obtain the voltage drop caused by the internal resistance of the bus, resulting in extremely high measurement accuracy. Furthermore, this invention enables automatic and accurate measurement of bus resistance without manual intervention, is low-cost, and has a wide range of applications.

[0054] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A bus-powered communication system capable of accurately measuring the internal resistance of the bus, characterized in that, It includes a master device and multiple slave devices. The master device includes a first processor, a first power module, a first signal transceiver circuit, a current measurement generation circuit, and a signal amplification and measurement circuit. The first power module is used for power supply, and the first signal transceiver circuit is used to modulate the power supply voltage output by the first power module under the control of the first processor to supply power to the bus and send signals; the current measurement generation circuit is used to output a set measurement current to the bus, and the signal amplification measurement circuit is used to measure the bus voltage drop at the master device end; the first processor is used to control the switching of the connection between the first signal transceiver circuit and the current measurement generation circuit and the bus, and is also used to control the output current of the current measurement generation circuit, and to receive the measurement value of the signal amplification measurement circuit to calculate the bus internal resistance from the master device to the slave device; The slave device includes a second processor, a second power module, a second signal transceiver circuit, and a correction shorting circuit; The second power module is used to supply power to the second processor after obtaining power from the bus through the second signal transceiver circuit. The processor is used to communicate bidirectionally with the master device through the second signal transceiver circuit. The correction short-circuit circuit is used to short-circuit the positive and negative terminals of the bus when measuring the bus resistance, and after short-circuiting, to measure the voltage between the positive and negative terminals of the bus and send it to the second processor. The correction short-circuit circuit includes field-effect transistors Q1 and Q2. The drain of field-effect transistor Q1 is connected to the positive terminal of the bus, the gate of field-effect transistor Q1 is connected to the control terminal CTL of the second processor, and the source is connected to the negative terminal of the bus. The drain of field-effect transistor Q2 is connected to the positive terminal of the bus, the source is connected to the input terminal of the second processor, and the gate is connected to the control terminal CTL. The current measurement generating circuit includes a dual-channel operational amplifier D3, a field-effect transistor V10, a Zener diode TS8, a field-effect transistor V12, and several resistors and capacitors. The positive input terminal of the first channel of the dual-channel operational amplifier D3 is connected to one end of resistor R59. The other end of resistor R59 is connected to the first current signal output terminal CUR_500mA of the first processor. The other end of resistor R59 is also connected to one end of resistor R63. The other end of resistor R63 is connected to the second current signal output terminal CUR_300mA of the first processor. The other end of resistor R63 is also connected to the third current signal output terminal CUR_150mA of the first processor via resistor R65. Through these three output terminals, the first processor can control the current measurement generating circuit to output different current values. The positive input terminal of the first channel of D3 is also connected to the positive power supply through pull-up resistor R54; the negative input terminal of the first channel of the dual-channel operational amplifier D3 is connected to the positive power supply through resistors R55 and R52, and its first channel output terminal is connected to the gate of field-effect transistor V10 through resistor R61. The source of field-effect transistor V10 is connected to the positive power supply through resistor R52, and the drain is connected to the drain of field-effect transistor V12 through Zener diode TS8. The gate of field-effect transistor V12 is connected to the positive power supply, and the source is grounded through resistor R69. Capacitor C36 is connected in parallel with resistor R69. The drain of field-effect transistor V12 is connected to the positive terminal of the bus MBUS+. The source of field-effect transistor V12 can output a sampling signal ADC_V. The sampling signal is amplified by the signal amplification and measurement circuit and sent to the first processor to obtain the bus voltage drop at the master device end. The signal amplification and measurement circuit includes resistors R57, R62, and R68, capacitor C35, and a field-effect transistor (FET) V11. The sampling signal ADC_V is connected to the positive input terminal of the second channel of the dual-channel operational amplifier D3. The negative input terminal of the second channel of the dual-channel operational amplifier D3 is grounded through resistor R62. Its second channel output terminal is grounded through resistors R57 and R62. Its second channel output terminal is also connected to the drain of the FET V11. The gate of the FET V11 is connected to the positive power supply, and its source is grounded through resistor R68. Capacitor C35 is connected in parallel with resistor R68. In addition, the source of the FET V11 is connected to the input terminal ADC_VX6 of the first processor, which inputs the measured bus voltage.

2. The bus power supply and communication system capable of accurately measuring bus internal resistance according to claim 1, characterized in that, The dual-channel operational amplifier D3 is an LM2904.

3. A bus power supply and communication system capable of accurately measuring bus internal resistance according to claim 1, characterized in that, The second power module includes an energy storage capacitor, which is used to obtain electrical energy from the bus terminal through the second signal transceiver circuit for storage, and then supply power to the slave device when there is no voltage on the bus.

4. A method for measuring the internal resistance of a bus, characterized in that, The implementation of a bus power supply and communication system capable of accurately measuring bus internal resistance as described in claim 1 includes the following steps: Step 1: The master device sends a startup resistor measurement message to the slave device. After receiving the message, the slave device enters a silent state, minimizes power consumption, and monitors the bus voltage. Step 2: The first processor of the master device switches the external power supply of the bus from the normal power supply to the current measurement and generation circuit, and begins to monitor the bus voltage; Step 3: After the device detects a sharp drop in bus voltage, the second processor enables the correction short-circuit circuit to short-circuit the positive and negative ends of the bus and begins measuring the voltage U1 at the positive and negative ends of the bus on the device side; at the same time, the master device detects the voltage U2 at both ends of the bus on the master device side through the signal amplification and measurement circuit. Step 4: The master device sends a request for calibration data message to the slave device, and the slave device replies to the master device with the measured voltage U1 of the positive and negative terminals of the bus at the slave device end; Step 5: The master device calculates the bus voltage drop U corresponding to the slave device using the formula: U = U2 - U1, and then obtains the bus resistance corresponding to the slave device.

5. The method for measuring the internal resistance of a bus according to claim 4, characterized in that, Step three also includes the following steps: The slave device uses a second processor to determine if the power supply voltage is lower than the set value. If so, it disables the correction short-circuit circuit. After the master device detects a sharp rise in the bus voltage, it switches the bus power supply to the normal power supply circuit, and the slave device draws power from the bus to resume normal operation.

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