Display device

Abstract

The first TFT (9A) includes a first semiconductor layer (17a) of an oxide semiconductor, a first gate electrode (19a) provided over the first semiconductor layer (17a) with a first gate insulating film (18a) interposed therebetween, a first interlayer insulating film (20) of a silicon oxide film covering the first gate electrode (19a), a second interlayer insulating film (21) of a silicon nitride film over the first interlayer insulating film (20), a through-hole (M) formed in the second interlayer insulating film (21), the through-hole (M) entirely overlapping with a first channel region (17ac) of the first semiconductor layer (17a), and a metal cap layer (22e) integrally provided on a surface of the first interlayer insulating film (20) exposed from the through-hole (M) and a peripheral portion of the through-hole (M).

Description

Technical Field

[0001] This invention relates to display devices. Background Technology

[0002] In recent years, self-emissive organic EL (OLED) displays, which utilize organic electroluminescent (EL) elements, have attracted considerable attention as alternatives to liquid crystal displays (LCDs). In these OLED displays, multiple thin-film transistors (TFTs) are disposed in each sub-pixel, which serves as the smallest unit of an image. Commonly used semiconductor layers constituting TFTs include, for example, polycrystalline silicon with high mobility and oxide semiconductors such as In-Ga-Zn-O with low leakage current.

[0003] For example, Patent Document 1 discloses a display device in which a transistor with a channel formed in an oxide semiconductor layer made of oxide semiconductor is used in a pixel section and a driving circuit section.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent No. 6219562 Summary of the Invention

[0007] The technical problem to be solved by the present invention

[0008] However, in TFTs with a semiconductor layer composed of oxide semiconductors, if a silicon oxide film is used as an interlayer insulating film covering the semiconductor layer, surrounding moisture can penetrate the interlayer insulating film composed of silicon oxide film to reach the semiconductor layer, potentially causing a depletion shift in the TFT's threshold voltage towards the negative side. Furthermore, even if a moisture-resistant silicon nitride film is stacked on top of the silicon oxide film and used as an interlayer insulating film, depletion shift can still occur because hydrogen generated by the silicon nitride film can reach the semiconductor layer via the silicon oxide film, thus there is room for improvement.

[0009] The present invention was made in view of this, and its purpose is to suppress the depletion shift caused by the diffusion of moisture and hydrogen.

[0010] Solution to the problem

[0011] To achieve the above objectives, the display device of the present invention includes: a substrate layer; and a thin-film transistor layer disposed on the substrate layer. In the thin-film transistor layer, a first thin-film transistor is provided for each sub-pixel. The first thin-film transistor has a first semiconductor layer formed of oxide semiconductor. The first thin-film transistor includes: the first semiconductor layer, wherein a first conductor region and a second conductor region are defined separately, and a first channel region is defined between the first conductor region and the second conductor region; a first gate insulating film disposed on the first semiconductor layer; a first gate electrode disposed on the first gate insulating film and controlling the conduction between the first conductor region and the second conductor region; and a first interlayer insulating film. The first interlayer insulating film is composed of a silicon oxide film disposed in a manner covering the first gate electrode; the second interlayer insulating film is composed of a silicon nitride film disposed on the first interlayer insulating film; and the first terminal electrode and the second terminal electrode are disposed separately on the second interlayer insulating film and electrically connected to the first conductor region and the second conductor region respectively via a first contact hole and a second contact hole formed in the first interlayer insulating film and the second interlayer insulating film, respectively. A through hole is formed in the second interlayer insulating film, the through hole penetrating the second interlayer insulating film in a manner that overlaps with the first channel region. A metal cover layer is integrally disposed on the surface of the first interlayer insulating film exposed from the through hole and the periphery of the through hole.

[0012] Invention Effects

[0013] According to the present invention, depletion offset caused by the diffusion of moisture and hydrogen can be suppressed. Attached Figure Description

[0014] Figure 1 This is a top view showing the schematic configuration of the organic EL display device according to the first embodiment of the present invention.

[0015] Figure 2 This is a top view of the display area of ​​the organic EL display device according to the first embodiment of the present invention.

[0016] Figure 3 This is a cross-sectional view of the display area of ​​the organic EL display device according to the first embodiment of the present invention.

[0017] Figure 4 This is an equivalent circuit diagram of the thin-film transistor layer constituting the organic EL display device according to the first embodiment of the present invention.

[0018] Figure 5 This is a cross-sectional view showing the organic EL layer of the organic EL display device constituting the first embodiment of the present invention.

[0019] Figure 6 This is a first cross-sectional view illustrating a method for manufacturing an organic EL display device according to a first embodiment of the present invention.

[0020] Figure 7 This is a second cross-sectional view illustrating a method for manufacturing an organic EL display device according to a first embodiment of the present invention.

[0021] Figure 8 This is a third cross-sectional view illustrating a method for manufacturing an organic EL display device according to the first embodiment of the present invention.

[0022] Figure 9 This is a cross-sectional view showing a first modified example of the thin-film transistor layer constituting the first embodiment of the organic EL display device according to the present invention.

[0023] Figure 10 This is a cross-sectional view showing a second modified example of the thin-film transistor layer constituting the organic EL display device according to the first embodiment of the present invention.

[0024] Figure 11 This is a cross-sectional view showing a third modified example of the thin-film transistor layer constituting the organic EL display device according to the first embodiment of the present invention.

[0025] Figure 12 This is a cross-sectional view of the display area of ​​the organic EL display device according to the second embodiment of the present invention.

[0026] Figure 13 This is a first cross-sectional view illustrating a method for manufacturing an organic EL display device according to a second embodiment of the present invention.

[0027] Figure 14 This is a second cross-sectional view illustrating a method for manufacturing an organic EL display device according to a second embodiment of the present invention.

[0028] Figure 15 This is a third cross-sectional view illustrating a method for manufacturing an organic EL display device according to a second embodiment of the present invention.

[0029] Figure 16 This is a cross-sectional view of the display area of ​​the organic EL display device according to the third embodiment of the present invention.

[0030] Figure 17 This is a first cross-sectional view illustrating a method for manufacturing an organic EL display device according to a third embodiment of the present invention.

[0031] Figure 18 This is a second cross-sectional view illustrating a method for manufacturing an organic EL display device according to a third embodiment of the present invention.

[0032] Figure 19 This is a third cross-sectional view illustrating a method for manufacturing an organic EL display device according to a third embodiment of the present invention. Detailed Implementation

[0033] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below.

[0034] First Implementation Method

[0035] Figures 1 to 11 A first embodiment of the display device according to the present invention is shown. Furthermore, as a display device having a light-emitting element layer, an organic EL display device having an organic EL element is exemplified in the following embodiments. Here, Figure 1 This is a top view showing the schematic configuration of the organic EL display device 50a according to this embodiment. Additionally, Figure 2 and Figure 3 These are top and cross-sectional views of the display area D of the organic EL display device 50a. Additionally, Figure 4 This is an equivalent circuit diagram of the thin-film transistor layer 30a that constitutes the organic EL display device 50a. Additionally, Figure 5 This is a cross-sectional view of the organic EL layer 33 that constitutes the organic EL display device 50a.

[0036] like Figure 1 As shown, the organic EL display device 50a includes, for example, a display area D that is rectangular and displays images, and a border area F disposed around the display area D. Furthermore, in this embodiment, a rectangular display area D is exemplified, but this rectangle also includes, for example, shapes with rounded sides, rounded corners, or cutouts on a portion of the side, etc., generally rectangular shapes.

[0037] like Figure 2 As shown, in display area D, multiple sub-pixels P are arranged in a matrix. Additionally, in display area D, as... Figure 2 As shown, for example, a sub-pixel P having a red emitting area Er for displaying red, a sub-pixel P having a green emitting area Eg for displaying green, and a sub-pixel P having a blue emitting area Eb for displaying blue are arranged adjacent to each other. Furthermore, in the display area D, for example, one pixel is formed by three adjacent sub-pixels P having the red emitting area Er, the green emitting area Eg, and the blue emitting area Eb.

[0038] In the border area F Figure 1 A terminal T is provided at the right end of the middle part. Additionally, as... Figure 1As shown, in the border area F, between the display area D and the terminal part T, there is a bending part B that can be bent 180° (in a U-shape) along an axis that is the vertical direction in the figure, extending in one direction (vertical direction in the figure).

[0039] like Figure 3 As shown, the organic EL display device 50a includes: a resin substrate layer 10 which serves as a substrate layer, a TFT layer 30a disposed on the resin substrate layer 10, an organic EL element layer 40 disposed on the TFT layer 30a as a light-emitting element layer, and a sealing film 45 disposed to cover the organic EL element layer 40.

[0040] The resin substrate layer 10 is made of, for example, polyimide resin.

[0041] like Figure 3 As shown, the TFT layer 30a includes: a base coating film 11 disposed on the resin substrate layer 10; three first TFTs 9A, four second TFTs 9B, and one capacitor 9h disposed on the base coating film 11 for each sub-pixel P (see reference). Figure 4 ); and a first planarization film 23 disposed on each of the first TFT 9A, each of the second TFT 9B, and each capacitor 9h. Here, in the TFT layer 30a, as Figure 2 As shown, multiple gate lines 14g are arranged in a manner that extends parallel to each other in the horizontal direction shown in the attached figure. Additionally, in the TFT layer 30a, as... Figure 2 As shown, multiple light-emitting control lines 14e are arranged in a manner that extends parallel to each other in the horizontal direction shown in the attached figure. Additionally, in the TFT layer 30a, as... Figure 2 As shown, multiple source lines 22f are arranged in a manner that extends parallel to each other in the longitudinal direction shown in the attached figure. Additionally, as... Figure 2 As shown, in the TFT layer 30a, multiple power lines 22g are arranged in a manner that extends parallel to each other in the vertical direction shown in the figure. Additionally, as... Figure 2 As shown, in the TFT layer 30a, multiple initialization signal lines 22i are arranged in a manner that extends parallel to each other in the vertical direction shown in the figure. Furthermore, as... Figure 2 As shown, each source line 22f is configured to be adjacent to each power line 22g and each initialization signal line 22i. Here, as... Figure 3 As shown, in the TFT layer 30a, a base coating film 11, a second gate insulating film 13, a third interlayer insulating film 15, a first interlayer insulating film 20, a second interlayer insulating film 21, and a first planarization film 23 are sequentially stacked on the resin substrate layer 10. Furthermore, a gate line 14g and a light-emitting control line 14e are disposed on the second gate insulating film 13, and a source line 22f, a power supply line 22g, and an initialization signal line 22i are disposed on the second interlayer insulating film 21.

[0042] like Figure 3 As shown, the first TFT 9A includes: a first semiconductor layer 17a disposed on a third interlayer insulating film 15; a first conductive layer 16a and a second conductive layer 16b disposed on the resin substrate layer 10 side of the first conductor region 17aa and the second conductor region 17ab of the first semiconductor layer 17a (described later); a first gate insulating film 18a disposed on a first channel region 17ac of the first semiconductor layer 17a (described later); a first gate electrode 19a disposed on the first gate insulating film 18a; a first interlayer insulating film 20 disposed to cover the first gate electrode 19a; a second interlayer insulating film 21 disposed on the first interlayer insulating film 20; and a first terminal electrode 22a and a second terminal electrode 22b disposed on the second interlayer insulating film 21 in a mutually separated manner. Here, the base coating film 11, the second gate insulating film 13, the third interlayer insulating film 15, and the first gate insulating film 18a are composed of a single layer or a stack of inorganic insulating films such as silicon nitride, silicon oxide, and silicon oxynitride. Furthermore, at least the first semiconductor layer 17a side of the third interlayer insulating film 15 and the first gate insulating film 18a is, for example, composed of a silicon oxide film.

[0043] The first semiconductor layer 17a is formed, for example, of an oxide semiconductor such as an In-Ga-Zn-O system, such as... Figure 3The device includes a first conductor region 17aa and a second conductor region 17ab defined in a mutually separated manner, and a first channel region 17ac defined between the first conductor region 17aa and the second conductor region 17ab. Here, the In-Ga-Zn-O semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited. Furthermore, the In-Ga-Zn-O semiconductor can be amorphous or crystalline. Moreover, a crystalline In-Ga-Zn-O semiconductor with its c-axis oriented substantially perpendicular to the plane is preferred. Alternatively, other oxide semiconductors may be included instead of the In-Ga-Zn-O semiconductor. For example, an In-Sn-Zn-O semiconductor (e.g., In₂O₃-SnO₂-ZnO; InSnZnO) may also be included. Here, the In-Sn-Zn-O semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Other oxide semiconductors may also include In-Al-Zn-O semiconductors, In-Al-Sn-Zn-O semiconductors, Zn-O semiconductors, In-Zn-O semiconductors, Zn-Ti-O semiconductors, Cd-Ge-O semiconductors, Cd-Pb-O semiconductors, CdO (cadmium oxide), Mg-Zn-O semiconductors, In-Ga-Sn-O semiconductors, In-Ga-O semiconductors, Zr-In-Zn-O semiconductors, Hf-In-Zn-O semiconductors, Al-Ga-Zn-O semiconductors, Ga-Zn-O semiconductors, In-Ga-Zn-Sn-O semiconductors, InGaO3(ZnO)5, and magnesium zinc oxide (MgO). x Zn 1-x O), zinc cadmium oxide (Cd) x Zn 1-x In addition, as a Zn-O semiconductor, ZnO can be used in amorphous, polycrystalline, microcrystalline, or unadulterated states, incorporating one or more impurity elements from Group 1, Group 13, Group 14, Group 15, and Group 17 elements.

[0044] like Figure 3 As shown, the first conductive layer 16a and the second conductive layer 16b are configured to contact the resin substrate layer 10 side of the first conductor region 17aa and the second conductor region 17ab at both ends of the first semiconductor layer 17a. Here, the first conductive layer 16a and the second conductive layer 16b are formed, for example, of a metal film such as a molybdenum film.

[0045] like Figure 3As shown, the first gate insulating film 18a is configured to overlap with the first gate electrode 19a.

[0046] like Figure 3 As shown, the first gate electrode 19a is disposed via the first gate insulating film 18a in a manner that overlaps with the first channel region 17ac of the first semiconductor layer 17a, thereby controlling the conduction between the first conductor region 17aa and the second conductor region 17ab of the first semiconductor layer 17a.

[0047] like Figure 3 As shown, the first interlayer insulating film 20 is provided such that it covers the first semiconductor layer 17a exposed from the first gate electrode 19a and a portion of the first conductive layer 16a and the second conductive layer 16b. Here, the first interlayer insulating film 20 is, for example, made of an inorganic insulating film such as a silicon oxide film.

[0048] The second interlayer insulating film 21 is, for example, composed of an inorganic insulating film such as a silicon nitride film, and has moisture-proof properties. Additionally, such as... Figure 3 As shown, a through-hole M penetrating the second interlayer insulating film 21 is provided in the second interlayer insulating film 21 in a manner that overlaps with the entire first channel region 17ac. Here, as... Figure 3 As shown, a metal capping layer 22e is integrally formed on the surface of the first interlayer insulating film 20 exposed from the through-hole M and on the surface of the periphery of the through-hole M. Furthermore, the metal capping layer 22e is formed on the same layer as the source line 22f, power line 22g, initialization signal line 22i, first terminal electrode 22a, and second terminal electrode 22b. Additionally, the metal capping layer 22e is electrically levitated.

[0049] like Figure 3 As shown, the first terminal electrode 22a and the second terminal electrode 22b are electrically connected to the first conductor region 17aa and the second conductor region 17ab, respectively, via the first contact hole Ha and the second contact hole Hb formed in the laminated film of the first interlayer insulating film 20 and the second interlayer insulating film 21. Here, as... Figure 3 As shown, the first contact hole Ha and the second contact hole Hb are arranged to overlap with the first conductive layer 16a and the second conductive layer 16b respectively, forming a bottom contact structure. The first conductive layer 16a contacts the first conductor region 17aa, and the second conductive layer 16b contacts the second conductor region 17ab.

[0050] like Figure 3As shown, the second TFT9B includes: a second semiconductor layer 12a disposed on the base coating film 11; a second gate insulating film 13 disposed on the second semiconductor layer 12a; a second gate electrode 14a disposed on the second gate insulating film 13; a third interlayer insulating film 15, a first interlayer insulating film 20 and a second interlayer insulating film 21 disposed sequentially to cover the second gate electrode 14a; and a third terminal electrode 22c and a fourth terminal electrode 22d disposed on the second interlayer insulating film 21 in a mutually separated manner.

[0051] The second semiconductor layer 12a is formed, for example, from polycrystalline silicon such as LTPS (low-temperature polysilicon). Figure 3 The device includes: a third conductor region 12aa and a fourth conductor region 12ab defined in a mutually separated manner, and a second channel region 12ac defined between the third conductor region 12aa and the fourth conductor region 12ab.

[0052] like Figure 3 As shown, the second gate electrode 14a is disposed in a manner that overlaps with the second channel region 12ac of the second semiconductor layer 12a, and is configured to control the conduction between the third conductor region 12aa and the fourth conductor region 12ab of the second semiconductor layer 12a.

[0053] like Figure 3 As shown, the third terminal electrode 22c and the fourth terminal electrode 22d are electrically connected to the third conductor region 12aa and the fourth conductor region 12ab of the second semiconductor layer 12a, respectively, via the third contact hole Hc and the fourth contact hole Hd formed in the stacked film of the second gate insulating film 13, the third interlayer insulating film 15, the first interlayer insulating film 20 and the second interlayer insulating film 21.

[0054] In this embodiment, three first TFTs 9A having a first semiconductor layer 17a formed of oxide semiconductor are exemplified as initialization TFT 9a, compensation TFT 9b, and anode discharge TFT 9g (described later). Four second TFTs 9B having a second semiconductor layer 12a formed of polysilicon are exemplified as writing TFT 9c, driving TFT 9d, power supply TFT 9e, and light emission control TFT 9f (see reference 1). Figure 4 In addition, in Figure 4 In the equivalent circuit diagram, the first terminal electrode 22a and the second terminal electrode 22b of each TFT 9a, 9b, and 9g are indicated by circled numbers 1 and 2, and the third terminal electrode 22c and the fourth terminal electrode 22d of each TFT 9c, 9d, 9e, and 9f are indicated by circled numbers 3 and 4. Additionally, in Figure 4The equivalent circuit diagram shows the pixel circuit of sub-pixel P in row n and column m, and also includes a portion of the pixel circuit of sub-pixel P in row (n-1) and column m.

[0055] like Figure 4 As shown, in each sub-pixel P, the gate electrode of the initialization TFT 9a is electrically connected to the gate line 14g(n-1) of the front segment (n-1 segment), its first terminal electrode is electrically connected to the lower conductive layer 16c of the capacitor 9h (described later) and the gate electrode of the driving TFT 9d, and its second terminal electrode is electrically connected to the power line 22g.

[0056] like Figure 4 As shown, in each sub-pixel P, the gate electrode of the compensation TFT9b is electrically connected to the gate line 14g(n) of the current level (n level), its first terminal electrode is electrically connected to the gate electrode of the driving TFT9d, and its second terminal electrode is electrically connected to the third terminal electrode of the driving TFT9d.

[0057] like Figure 4 As shown, in each sub-pixel P, the gate electrode of the TFT 9c used for writing is electrically connected to the gate line 14g(n) of the same level (n level), its third terminal electrode is electrically connected to the corresponding source line 22f, and its fourth terminal electrode is electrically connected to the fourth terminal electrode of the driving TFT 9d.

[0058] like Figure 4 As shown, in each sub-pixel P, the gate electrode of the driving TFT 9d is electrically connected to the first terminal electrode of both the initialization TFT 9a and the compensation TFT 9b. Its third terminal electrode is electrically connected to the second terminal electrode of the compensation TFT 9b and the fourth terminal electrode of the power supply TFT 9e. Its fourth terminal electrode is electrically connected to the fourth terminal electrode of the writing TFT 9c and the third terminal electrode of the light emission control TFT 9f. Here, the driving TFT 9d is configured to control the current of the organic EL element 35.

[0059] like Figure 4 As shown, in each sub-pixel P, the gate electrode of the power supply TFT9e is electrically connected to the light emission control line 14e of the current level (n level), its third terminal electrode is electrically connected to the corresponding power supply line 22g, and its fourth terminal electrode is electrically connected to the third terminal electrode of the driving TFT9d.

[0060] like Figure 4 As shown, in each sub-pixel P, the gate electrode of the TFT 9f for light emission control is electrically connected to the light emission control line 14e of the current level (n level), the third terminal electrode of the TFT 9f for driving is electrically connected to the fourth terminal electrode of the TFT 9d for driving, and the fourth terminal electrode of the TFT 9f for driving is electrically connected to the first electrode 31a of the organic EL element 35 described later.

[0061] like Figure 4 As shown, in each sub-pixel P, the gate electrode of the TFT 9g used for anode discharge is electrically connected to the gate line 14g(n) of the same level (n level), its first terminal electrode is electrically connected to the first electrode 31a of the organic EL element 35, and its second terminal electrode is electrically connected to the initialization signal line 22i.

[0062] The capacitor 9h, for example, includes: a lower conductive layer (not shown) formed on the same layer as the second gate electrode 14a, a third interlayer insulating film 15 disposed to cover the lower conductive layer, and an upper conductive layer (not shown) disposed on the third interlayer insulating film 15 to overlap the lower conductive layer, wherein the upper conductive layer (not shown) is formed on the same layer as the first conductive layer 16a and the second conductive layer 16b. Figure 4 As shown, in each sub-pixel P, the lower conductive layer of capacitor 9h is electrically connected to the gate electrode of driving TFT 9d, initialization TFT 9a and compensation TFT 9b, and the upper conductive layer is electrically connected to the first terminal electrode of anode discharge TFT 9g, the fourth terminal electrode of light emission control TFT 9f and the first electrode 31a of organic EL element 35.

[0063] The first planarization film 23 has a flat surface in the display area D, for example, it is made of organic resin materials such as polyimide resin and acrylic resin, or polysiloxane-based SOG (spin on glass) materials.

[0064] like Figure 3 As shown, the organic EL element layer 40 includes a plurality of first electrodes 31a disposed sequentially on the TFT layer 30a corresponding to a plurality of sub-pixels P, a common edge mask 32, a plurality of organic EL layers 33, and a common second electrode 34. Here, as Figure 3 As shown, the organic EL element 35 is composed of a first electrode 31a, an organic EL layer 33 and a second electrode 34 sequentially stacked on the first planarization film 23 of the TFT layer 30a.

[0065] The first electrode 31a is electrically connected to the fourth terminal electrode of the TFT 9f for light emission control of each sub-pixel P via a contact hole formed in the first planarization film 23. Furthermore, the first electrode 31a has the function of injecting holes (positive holes) into the organic EL layer 33. In order to improve the hole injection efficiency into the organic EL layer 33, the first electrode 31a is more preferably formed of a material with a high work function. Examples of materials constituting the first electrode 31a include, for example, metallic materials such as silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), and tin (Sn). Alternatively, the material constituting the first electrode 31a may also be an alloy such as astatine (At) / atamine oxide (AtO2). Furthermore, the material constituting the first electrode 31a can be, for example, a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). Additionally, the first electrode 31a can be formed by stacking multiple layers composed of the aforementioned materials. Furthermore, compound materials with high work functions can be, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

[0066] like Figure 3 As shown, the edge cover 32 is arranged in a grid pattern to cover the periphery of each first electrode 31a. Here, the edge cover 32 is made of organic resin materials such as polyimide resin and acrylic resin, or SOG material based on polysiloxane.

[0067] like Figure 5 As shown, the organic EL layer 33 is configured as a light-emitting functional layer, which includes a hole injection layer 1, a hole transport layer 2, a light-emitting layer 3, an electron transport layer 4 and an electron injection layer 5 sequentially disposed on the first electrode 31a.

[0068] Hole injection layer 1, also known as anodic buffer layer, brings the energy levels of the first electrode 31a and the organic EL layer 33 closer together, thereby improving the efficiency of hole injection from the first electrode 31a to the organic EL layer 33. Examples of materials constituting hole injection layer 1 include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkyl derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrene-anthracene derivatives, fluorenone derivatives, hydrazone derivatives, and stilbene derivatives.

[0069] The hole transport layer 2 functions to improve the transport efficiency of holes from the first electrode 31a to the organic EL layer 33. Examples of materials constituting the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, phenylethylamine derivatives, polyvinylcarbazole, poly-p-phenylacetylene, polysilanes, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkyl derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, aromatic amine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrene-anthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, zinc sulfide, and zinc selenide.

[0070] The light-emitting layer 3 is a region in which holes and electrons are injected from the first electrode 31a and the second electrode 34 respectively when a voltage is applied to the first electrode 31a and the second electrode 34, and the holes and electrons recombine. Here, the light-emitting layer 3 is formed of a material with high luminous efficiency. Moreover, examples of materials constituting the light-emitting layer 3 include metal hydroxyquinoline compounds [8-hydroxyquinoline metal complex], naphthalene derivatives, anthracene derivatives, stilbene derivatives, vinyl acetone derivatives, triphenylamine derivatives, butadiene derivatives, coumarin derivatives, benzoxazole derivatives, oxadiazole derivatives, oxazole derivatives, benzimidazole derivatives, thiadiazole derivatives, benzothiazazole derivatives, styryl derivatives, styrylamine derivatives, stilbeneylbenzene derivatives, tristyrylbenzene derivatives, perylene derivatives, pyrene derivatives, aminopyrene derivatives, pyridine derivatives, rhodamine derivatives, acridine derivatives, phenoxazinone, quinacridone derivatives, rubrene, poly(p-phenylenevinylene), polysilane, etc.

[0071] The electron transport layer 4 has the function of enabling electrons to migrate to the light-emitting layer 3 with high efficiency. Here, the materials constituting the electron transport layer 4 can be, for example, organic compounds such as diazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinone dimethane derivatives, biphenylquinone derivatives, fluorenone derivatives, thiophene derivatives, and metal hydroxyquinoline compounds.

[0072] The electron injection layer 5 is close to the energy levels of the second electrode 34 and the organic EL layer 33, and has the function of improving the efficiency of electron injection from the second electrode 34 to the organic EL layer 33. Through this function, the driving voltage of the organic EL element 35 can be reduced. In addition, the electron injection layer 5 is also referred to as the cathode buffer layer. Here, the materials constituting the electron injection layer 5 include, for example, inorganic alkali compounds such as lithium fluoride (LiF), magnesium fluoride (MgF2), calcium fluoride (CaF2), strontium fluoride (SrF2), and barium fluoride (BaF2), as well as alumina (Al2O3) and strontium oxide (SrO).

[0073] like Figure 3As shown, the second electrode 34 is configured to be shared across all sub-pixels P in a manner that covers each organic EL layer 33 and the edge mask 32. Furthermore, the second electrode 34 has the function of injecting electrons into each organic EL layer 33. In order to improve the electron injection efficiency into the organic EL layer 33, the second electrode 34 is more preferably made of a material with a low work function. Examples of materials constituting the second electrode 34 include silver (Ag), aluminum (Al), vanadium (V), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), and lithium fluoride (LiF). Alternatively, the second electrode 34 may also be formed of alloys such as magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), astatine (At) / astatine oxide (AtO2), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), and lithium fluoride (LiF) / calcium (Ca) / aluminum (Al). Alternatively, the second electrode 34 may also be formed of conductive oxides such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO). Furthermore, the second electrode 34 may also be formed by stacking multiple layers composed of the above materials. In addition, materials with low work functions include, for example, magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), lithium fluoride (LiF) / calcium (Ca) / aluminum (Al), etc.

[0074] like Figure 3 As shown, the sealing film 45 includes a first inorganic sealing film 41, an organic sealing film 42, and a second inorganic sealing film 43 arranged in a manner covering the second electrode 34 and sequentially disposed on the second electrode 34, and has the function of protecting the organic EL layer 33 of the organic EL element 35 from the influence of moisture and oxygen.

[0075] The first inorganic sealing membrane 41 and the second inorganic sealing membrane 43 are, for example, composed of inorganic insulating membranes such as silicon nitride membrane, silicon oxide membrane, and silicon oxynitride membrane.

[0076] Organic sealing film 42 is composed of organic resin materials such as acrylic resin, epoxy resin, silicone resin, polyurea resin, parylene resin, polyimide resin, and polyamide resin.

[0077] In the organic EL display device 50a configured as described above, in each sub-pixel P, first, when the light emission control line 14e is selected and becomes inactive, the organic EL element 35 becomes non-light-emitting. In this non-light-emitting state, the previous gate line 14g(n - 1) is selected, and a gate signal is input to the initialization TFT 9a via this gate line 14g(n - 1). As a result, the initialization TFT 9a becomes conductive, the high power supply voltage ELVDD of the power supply line 22g is applied to the capacitor 9h, and the driving TFT 9d becomes conductive. Thereby, the charge of the capacitor 9h is discharged, and the voltage applied to the gate electrode of the driving TFT 9d is initialized. Next, the current-stage gate line 14(n) is selected and becomes active, whereby the compensation TFT 9b and the writing TFT 9c become conductive, and a prescribed voltage corresponding to the source signal transmitted via the corresponding source line 22f is written into the capacitor 9h via the driving TFT 9d in a diode-connected state, and the anode discharge TFT 9g becomes conductive. The initialization signal is applied to the first electrode 31a of the organic EL element 35 via the initialization signal line 22i, so that the charge accumulated in the first electrode 31a is reset. After that, the light emission control line 14e is selected, the power supply TFT 9e and the light emission control TFT 9f become conductive, and a driving current corresponding to the voltage applied to the gate electrode of the driving TFT 9d is supplied from the power supply line 22g to the organic EL element 35. Thus, in the organic EL display device 50a, in each sub-pixel P, the organic EL element 35 emits light with a brightness corresponding to the driving current, and image display is performed.

[0078] Next, a manufacturing method of the organic EL display device 50a of the present embodiment will be described. In addition, the manufacturing method of the organic EL display device 50a includes a TFT layer formation process, an organic EL element layer formation process, and a sealing film formation process. Here, Figure 6 、 Figure 7 and Figure 8 are the first, second, and third cross-sectional views showing the manufacturing method of the organic EL display device 50a.

[0079] <TFT layer formation process>

[0080] First, for example, by using the plasma CVD (Chemical Vapor Deposition) method, a silicon nitride film (thickness: about 50 nm) and a silicon oxide film (thickness: about 250 nm) are sequentially formed on the resin substrate layer 10 formed on the glass substrate, thereby forming the undercoat film 11.

[0081] Next, on the surface of the substrate on which the base coating film 11 is formed, an amorphous silicon film (approximately 50 nm thick) is formed, for example, by plasma CVD. The amorphous silicon film is then crystallized by laser annealing or the like to form a polycrystalline silicon film. Afterward, the polycrystalline silicon film is patterned to form a second semiconductor layer 12a, etc.

[0082] Furthermore, on the surface of the substrate where the second semiconductor layer 12a is formed, a silicon oxide film (approximately 100 nm thick) is deposited using, for example, plasma CVD to form a second gate insulating film 13. Then, a metal film, such as a molybdenum film (approximately 200 nm thick), is formed using, for example, sputtering. This metal film is then patterned to form a second gate electrode 14a, gate lines 14g, light-emitting control lines 14e, etc.

[0083] Next, by using the second gate electrode 14a as a mask to dope impurity ions such as phosphorus in the second semiconductor layer 12a, a third conductor region 12aa, a fourth conductor region 12ab, and a second channel region 12ac are formed in the second semiconductor layer 12a.

[0084] Furthermore, by forming a third conductor region 12aa on the substrate surface of the second semiconductor layer 12a, for example, by forming a single layer of silicon oxide film (approximately 150 nm thick) or a stacked film consisting of a silicon nitride film (approximately 150 nm thick) and a silicon oxide film (approximately 50 nm thick) sequentially stacked using plasma CVD, a third interlayer insulating film 15 is formed. Then, a metal film such as a molybdenum film (approximately 200 nm thick) is formed, for example, by sputtering. This metal film is then patterned to form a first conductive layer 16a and a second conductive layer 16b, etc.

[0085] Next, on the substrate surface where the first conductive layer 16a is formed, an oxide semiconductor film such as InGaZnO4 (with a thickness of about 30 nm) is formed by sputtering, the oxide semiconductor film is patterned to form the first semiconductor layer 17a.

[0086] Furthermore, by forming a silicon oxide film (thickness of about 100 nm) on the surface of a substrate on which the first semiconductor layer 17a is formed, for example by plasma CVD, a metal film is formed by sputtering a single layer of molybdenum film (thickness of about 200 nm), a stacked film of aluminum film (thickness of about 300 nm) and titanium film (thickness of about 50 nm) stacked sequentially, or a stacked film of titanium film (thickness of about 50 nm), aluminum film (thickness of about 300 nm) and titanium film (thickness of about 50 nm) stacked sequentially. By patterning the above metal film, the first gate insulating film 18a and the first gate electrode 19a are formed.

[0087] Next, on the surface of the substrate where the first gate electrode 19a is formed, for example, a silicon oxide film (approximately 400 nm thick) and a silicon nitride film (approximately 200 nm thick) are sequentially formed using plasma CVD to form a first interlayer insulating film 20 and a second interlayer insulating film 21. Then, the second gate insulating film 13, the third interlayer insulating film 15, the first interlayer insulating film 20, and the second interlayer insulating film 21 are appropriately patterned, such as... Figure 6 As shown, a first contact hole Ha, a second contact hole Hb, a third contact hole Hc, and a fourth contact hole Hd are formed.

[0088] Furthermore, such as Figure 7 As shown, after a resist pattern R is formed on the surface of a substrate with a first contact hole Ha, the second interlayer insulating film 21 exposed from the resist pattern R is etched, as shown. Figure 8 As shown, this forms a through hole M in the second interlayer insulating film 21.

[0089] Subsequently, a substrate surface with through holes M is formed in the second interlayer insulating film 21. For example, a titanium film (thickness of about 50 nm), an aluminum film (thickness of about 600 nm), and another titanium film (thickness of about 50 nm) are sequentially formed by sputtering. Then, the metal stacked film is patterned to form a first terminal electrode 22a, a second terminal electrode 22b, a third terminal electrode 22c, a fourth terminal electrode 22d, a metal capping layer 22e, a source line 22f, a power line 22g, and an initialization signal line 22i.

[0090] Finally, after coating a polyimide-based photosensitive resin film (approximately 2 μm thick) onto the surface of a substrate on which the first terminal electrode 22a is formed, for example by spin coating or slot coating, the first planarization film 23 is formed by pre-baking, exposing, developing and post-baking the coated film.

[0091] As described above, a TFT layer 30a can be formed.

[0092] <Organic EL Component Layer Formation Process>

[0093] An organic EL element layer 40 is formed by forming a first electrode 31a, an edge mask 32, an organic EL layer 33 (hole injection layer 1, hole transport layer 2, light emission layer 3, electron transport layer 4, electron injection layer 5) and a second electrode 34 on the first planarization film 23 of the TFT layer 30a formed in the above-mentioned TFT layer formation process using known methods.

[0094] <Sealing film formation process>

[0095] First, on the substrate surface formed by the organic EL element layer 40 formed in the above-mentioned organic EL element layer formation process, an inorganic insulating film such as silicon nitride film, silicon oxide film, or silicon oxynitride film is formed by plasma CVD using a mask, thereby forming a first inorganic sealing film 41.

[0096] Next, an organic sealing film 42 is formed on the surface of the substrate on which the first inorganic sealing film 41 is formed, for example, using an organic resin material such as an acrylic resin formed by inkjet printing.

[0097] Subsequently, a second inorganic sealing film 43 is formed on the surface of the substrate on which the organic sealing film 42 is formed, by using a mask, for example by plasma CVD, to form an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film, thereby forming a sealing film 45.

[0098] Finally, after a protective sheet (not shown) is attached to the substrate surface on which the sealing film 45 is formed, the glass substrate is peeled off from the lower surface of the resin substrate layer 10 by irradiating a laser from the glass substrate side of the resin substrate layer 10, and a protective sheet (not shown) is attached to the lower surface of the resin substrate layer 10 after the glass substrate has been peeled off.

[0099] As described above, the organic EL display device 50a of this embodiment can be manufactured.

[0100] Furthermore, in this embodiment, an organic EL display device 50a having a TFT layer 30a is illustrated, but it could also be an organic EL display device having thin-film transistor layers 30aa, 30ab, and 30ac as shown below. Here, Figure 9 , Figure 10 and Figure 11 This is a cross-sectional view showing the first, second and third modified examples of the thin-film transistor layer 30aa, 30ab and 30ac.

[0101] In TFT layer 30aa, such as Figure 9 As shown, in the first TFT 9A, a lower gate electrode 14b is provided on the resin substrate layer 10 side of the first semiconductor layer 17a, separated by a third interlayer insulating film 15. Here, the lower gate electrode 14b, like the first gate electrode 19a, is configured to control the conduction between the first conductor region 17aa and the second conductor region 17ab of the first semiconductor layer 17a. Furthermore, the lower gate electrode 14b is formed on the same layer as the second gate electrode 14a using the same material. Based on this TFT layer 30aa, the first TFT 9A has a dual-gate structure, thus improving the driving capability of the first TFT 9A. Additionally, since the potential of the interface on the lower side of the first semiconductor layer 17a is fixed, the stability and reliability of the characteristics of the first TFT 9A can be improved.

[0102] like Figure 10 As shown, in TFT layer 30ab, in the first TFT 9A, similar to TFT layer 30aa, a lower gate electrode 14b is provided, and the metal capping layer 22eb, which corresponds to the metal capping layer 22e, is electrically connected to the first gate electrode 19a. According to this TFT layer 30ab, since the metal capping layer 22eb is electrically connected to the first gate electrode 19a, the formation of parasitic capacitance caused by the metal capping layer 22eb can be suppressed.

[0103] In TFT layer 30ac, such as Figure 11 As shown, in the first TFT 9A, the first contact hole Ha and the second contact hole Hb are arranged to overlap with the first conductor region 17ba and the second conductor region 17bb, which will be described later, respectively, forming a top contact structure. Here, the first semiconductor layer 17b, which corresponds to the first semiconductor layer 17a, includes: the first conductor region 17ba and the second conductor region 17bb, which are defined in a mutually separated manner, and a first channel region 17bc defined between the first conductor region 17ba and the second conductor region 17bb. According to this TFT layer 30ac, the first conductive layer 16a and the second conductive layer 16b in the TFT layer 30a can be omitted, thus simplifying the manufacturing process.

[0104] As described above, in the organic EL display device 50a according to this embodiment, a through-hole M is formed in the second interlayer insulating film 21, which is composed of a silicon nitride film. This through-hole M penetrates the second interlayer insulating film 21 in a manner that completely overlaps with the first channel region 17ac of the first semiconductor layer 17a. Therefore, the diffusion of hydrogen from the silicon nitride film of the second interlayer insulating film 21 to the first channel region 17ac can be suppressed. Furthermore, since a moisture-resistant metal capping layer 22e is integrally provided on the surface of the first interlayer insulating film 20 exposed by the through-hole M of the moisture-resistant second interlayer insulating film 21 and on the surface of the periphery of the through-hole M, the diffusion of moisture from the first planarization film 23 to the first channel region 17ac can be suppressed. Therefore, in the first TFT 9A, the diffusion of moisture and hydrogen to the first channel region 17ac of the first semiconductor layer 17a is suppressed, thereby suppressing depletion shift caused by the diffusion of moisture and hydrogen. Furthermore, by suppressing depletion offset caused by the diffusion of moisture and hydrogen, the manufacturing yield and reliability of the organic EL display device 50a can be reduced.

[0105] Second Implementation Method

[0106] Figures 12 to 15 A second embodiment of the display device according to the present invention is shown. Here, Figure 12 This is a cross-sectional view of the display area D of the organic EL display device 50b according to this embodiment. Additionally, Figure 13 , Figure 14 and Figure 15 These are first, second, and third cross-sectional views illustrating a method for manufacturing an organic EL display device 50b. Furthermore, in the following embodiments, [the following text refers to...]. Figures 1 to 11 Identical parts are labeled with the same reference numerals, and their detailed descriptions are omitted.

[0107] In the first embodiment described above, an organic EL display device 50a is shown with a metal cover layer 22e disposed on the same layer as the first terminal electrode 22a, but in this embodiment, an organic EL display device 50b is shown with a metal cover layer 24b disposed on the same layer as the power line 24a.

[0108] Similar to the organic EL display device 50a of the first embodiment described above, the organic EL display device 50b includes, for example, a display area D that is configured in a rectangular shape and a border area F that is configured around the display area D.

[0109] In addition, such as Figure 12 As shown, the organic EL display device 50b includes: a resin substrate layer 10, a TFT layer 30b disposed on the resin substrate layer 10, an organic EL element layer 40 disposed on the TFT layer 30b, and a sealing film 45 disposed to cover the organic EL element layer 40.

[0110] like Figure 12 As shown, the TFT layer 30b includes: a base coating film 11 disposed on the resin substrate layer 10; three first TFTs 9A, four second TFTs 9B, and one capacitor 9h disposed on the base coating film 11 for each sub-pixel P (see reference). Figure 4 ); and a first planarization film 23 and a second planarization film 25 are sequentially disposed on each of the first TFT 9A, each of the second TFT 9B, and each capacitor 9h. Here, in the TFT layer 30b, similarly to the TFT layer 30a of the first embodiment described above, multiple gate lines 14g, multiple light-emitting control lines 14e, multiple source lines 22f, and multiple initialization signal lines 22i are disposed. In addition, as Figure 12 As shown, in the TFT layer 30b, instead of the power lines 22g in the TFT layer 30a of the first embodiment described above, power lines 24a are provided in a grid pattern between the first planarization film 23 and the second planarization film 25 as a wiring layer. Here, as... Figure 12 As shown, in the TFT layer 30b, a base coating film 11, a second gate insulating film 13, a third interlayer insulating film 15, a first interlayer insulating film 20, a second interlayer insulating film 21, a first planarization film 23, and a second planarization film 25 are sequentially stacked on the resin substrate layer 10.

[0111] like Figure 12As shown, the first TFT 9A includes: a first semiconductor layer 17b disposed on a third interlayer insulating film 15; a first gate insulating film 18a disposed on a first channel region 17bc of the first semiconductor layer 17b; a first gate electrode 19a disposed on the first gate insulating film 18a; a first interlayer insulating film 20 disposed to cover the first gate electrode 19a; a second interlayer insulating film 21 disposed on the first interlayer insulating film 20; and a first terminal electrode 22a and a second terminal electrode 22b disposed separately on the second interlayer insulating film 21. Here, at least the first semiconductor layer 17b side of the third interlayer insulating film 15 and the first gate insulating film 18a are, for example, made of silicon oxide film. Furthermore, in this embodiment, a first TFT 9A with a single-gate structure is illustrated, but the first TFT 9A may also have a dual-gate structure as in the first variation of the first embodiment described above. Additionally, in this embodiment, a first TFT 9A with a top contact structure is illustrated, but the first TFT 9A may also have a bottom contact structure as in the first embodiment described above.

[0112] like Figure 12 As shown, a first through hole Ma is provided in the second interlayer insulating film 21 in such a way that it overlaps with the entire first channel region 17bc.

[0113] The first planarization film 23 has a flat surface in the display area D, and is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG (spin-on-glass) material. Here, as... Figure 12 As shown, a second through-hole Mb is provided in the first planarization film 23 in a manner that overlaps with the entire first channel region 17bc, penetrating the first planarization film 23. Furthermore, as... Figure 12 As shown, the periphery of the second through hole Mb is positioned further outward than the periphery of the first through hole Ma. Furthermore, as... Figure 12 As shown, a metal capping layer 24b is integrally formed on the surface of the first interlayer insulating film 20 exposed from the first through-hole Ma, the surface of the periphery of the first through-hole Ma, and the surface of the periphery of the second through-hole Mb. Here, the metal capping layer 24b is formed in the same layer as the power line 24a. Furthermore, the metal capping layer 24b is electrically floating. Additionally, the metal capping layer 24b can also be electrically connected to the first gate electrode 19a, as in the second variation of the first embodiment described above.

[0114] The second planarization film 25 has a flat surface in the display area D, and is made of, for example, organic resin materials such as polyimide resin and acrylic resin, or polysiloxane-based SOG (spin on glass) materials. Additionally, as... Figure 12As shown, the second planarization film 25 is provided so as to cover the power line 24a and the metal covering layer 24b provided on the first planarization film 23.

[0115] Similar to the organic EL display device 50a of the above-described first embodiment, in each sub-pixel P of the organic EL display device 50b configured as described above, the organic EL element 35 emits light with a luminance corresponding to the driving current to perform image display.

[0116] Next, a method for manufacturing the organic EL display device 50b of the present embodiment will be described. In addition, the method for manufacturing the organic EL display device 50b includes a TFT layer formation step, an organic EL element layer formation step, and a sealing film formation step.

[0117] <TFT layer formation step>

[0118] First, in the TFT layer formation step of the method for manufacturing the organic EL display device 50a of the above-described first embodiment, after forming an oxide semiconductor film such as InGaZnO4 (with a thickness of about 30 nm) on the surface of the substrate on which the third interlayer insulating film 15 is formed, for example, by sputtering, the oxide semiconductor film is patterned to form the first semiconductor layer 17b and the like.

[0119] Next, after forming a silicon oxide film (with a thickness of about 100 nm) or the like on the surface of the substrate on which the first semiconductor layer 17b and the like are formed, for example, by plasma CVD, a metal film such as a single-layer molybdenum film (with a thickness of about 200 nm), a stacked film in which an aluminum film (with a thickness of about 300 nm) and a titanium film (with a thickness of about 50 nm) are sequentially stacked, or a stacked film in which a titanium film (with a thickness of about 50 nm), an aluminum film (with a thickness of about 300 nm), and a titanium film (with a thickness of about 50 nm) are sequentially stacked is formed by sputtering. By patterning the above metal film, the first gate insulating film 18a and the first gate electrode 19a and the like are formed.

[0120] Furthermore, on the surface of the substrate on which the first gate electrode 19a and the like are formed, a silicon oxide film (with a thickness of about 400 nm) and a silicon nitride film (with a thickness of about 200 nm) are sequentially formed, for example, by plasma CVD, to form the first interlayer insulating film 20 and the second interlayer insulating film 21.

[0121] After that, similar to the TFT layer formation step of the above-described first embodiment, the second gate insulating film 13, the third interlayer insulating film 15, the first interlayer insulating film 20, and the second interlayer insulating film 21 are appropriately patterned to form the first contact hole Ha, the second contact hole Hb, the third contact hole Hc, the fourth contact hole Hd, the first through hole Ma, etc. (refer to Figure 13 ).

[0122] Next, on the substrate surface where the first through-hole Ma is formed in the second interlayer insulating film 21, for example, titanium film (thickness about 50 nm), aluminum film (thickness about 600 nm), and titanium film (thickness about 50 nm) are sequentially formed by sputtering, the metal stacked film is patterned, such as... Figure 14 As shown, a first terminal electrode 22a, a second terminal electrode 22b, a third terminal electrode 22c, a fourth terminal electrode 22d, a source line 22f, and an initialization signal line 22i are formed.

[0123] Furthermore, after coating a polyimide-based photosensitive resin film (approximately 2 μm thick) onto the surface of a substrate on which the first terminal electrode 22a is formed, for example using spin coating or slot coating, the coated film is pre-baked, exposed, developed, and then post-baked, as follows: Figure 15 As shown, a first planarization film 23 with a second through hole Mb is thus formed.

[0124] Then, on the substrate surface where the first planarization film 23 is formed, for example by sputtering, titanium film (thickness of about 50 nm), aluminum film (thickness of about 600 nm) and titanium film (thickness of about 50 nm) are sequentially formed, and the metal stacked film is patterned to form power lines 24a and metal cover layer 24b.

[0125] Finally, after coating a polyimide-based photosensitive resin film (approximately 2 μm thick) onto the surface of a substrate on which power lines 24a are formed, for example by spin coating or slot coating, the coated film is pre-baked, exposed, developed, and then post-baked to form a second planarization film 25.

[0126] As described above, a TFT layer 30b can be formed. Then, similarly to the manufacturing method of the organic EL display device 50a of the first embodiment described above, the organic EL element layer formation step and the sealing film formation step are performed to manufacture the organic EL display device 50b of this embodiment.

[0127] As described above, in the organic EL display device 50b according to this embodiment, a first through-hole Ma is formed in the second interlayer insulating film 21 composed of a silicon nitride film. This first through-hole Ma penetrates the second interlayer insulating film 21 in a manner that completely overlaps with the first channel region 17bc of the first semiconductor layer 17b. Therefore, the diffusion of hydrogen from the silicon nitride film of the second interlayer insulating film 21 to the first channel region 17bc can be suppressed. Furthermore, since a moisture-resistant metal capping layer 24b is integrally provided on the surface of the first interlayer insulating film 20 exposed by the first through-hole Ma (where the moisture-resistant second interlayer insulating film 21 is never provided), the surface of the periphery of the first through-hole Ma, and the surface of the periphery of the second through-hole Mb, the diffusion of moisture from the second planarization film 25 to the first channel region 17bc can be suppressed. Therefore, in the first TFT 9A, the diffusion of moisture and hydrogen to the first channel region 17bc of the first semiconductor layer 17b is suppressed, thereby suppressing depletion shift caused by the diffusion of moisture and hydrogen. Furthermore, by suppressing depletion offset caused by the diffusion of moisture and hydrogen, the manufacturing yield and reliability of the organic EL display device 50b can be reduced.

[0128] Third Implementation Method

[0129] Figures 16 to 19 A third embodiment of the display device according to the present invention is shown. Here, Figure 16 This is a cross-sectional view of the display area D of the organic EL display device 50c according to this embodiment. Additionally, Figure 17 , Figure 18 and Figure 19 These are first, second, and third cross-sectional views illustrating a method for manufacturing an organic EL display device 50c.

[0130] In the first embodiment described above, an organic EL display device 50a is shown with a metal cover layer 22e disposed on the same layer as the first terminal electrode 22a, but in this embodiment, an organic EL display device 50c is shown with a metal cover layer 31b disposed on the same layer as the first electrode 31a.

[0131] Similar to the organic EL display device 50a of the first embodiment described above, the organic EL display device 50c includes, for example, a display area D that is configured in a rectangular shape and a border area F that is configured around the display area D.

[0132] In addition, such as Figure 16 As shown, the organic EL display device 50c includes: a resin substrate layer 10, a TFT layer 30c disposed on the resin substrate layer 10, an organic EL element layer 40 disposed on the TFT layer 30c, and a sealing film 45 disposed in a manner that covers the organic EL element layer 40.

[0133] like Figure 16 As shown, the TFT layer 30c includes: a base coating film 11 disposed on the resin substrate layer 10; three first TFTs 9A, four second TFTs 9B, and one capacitor 9h disposed on the base coating film 11 for each sub-pixel P (see [reference]). Figure 4 ); and a first planarization film 23 and a second planarization film 25 are sequentially disposed on each of the first TFT 9A, each of the second TFT 9B, and each capacitor 9h. Here, in the TFT layer 30c, similarly to the TFT layer 30a of the first embodiment described above, multiple gate lines 14g, multiple light-emitting control lines 14e, multiple source lines 22f, and multiple initialization signal lines 22i are disposed. In addition, as Figure 16 As shown, in the TFT layer 30c, instead of the power lines 22g in the TFT layer 30a of the first embodiment described above, power lines 24a are provided in a grid pattern between the first planarization film 23 and the second planarization film 25 as a wiring layer. Here, as... Figure 16 As shown, in the TFT layer 30c, a base coating film 11, a second gate insulating film 13, a third interlayer insulating film 15, a first interlayer insulating film 20, a second interlayer insulating film 21, a first planarization film 23, and a second planarization film 25 are sequentially stacked on the resin substrate layer 10.

[0134] The first TFT 9A, like the second embodiment described above, includes: a first semiconductor layer 17b disposed on the third interlayer insulating film 15; a first gate insulating film 18a disposed on the first channel region 17bc of the first semiconductor layer 17b; a first gate electrode 19a disposed on the first gate insulating film 18a; a first interlayer insulating film 20 disposed to cover the first gate electrode 19a; a second interlayer insulating film 21 disposed on the first interlayer insulating film 20; and a first terminal electrode 22a and a second terminal electrode 22b disposed separately on the second interlayer insulating film 21. Furthermore, while this embodiment illustrates a first TFT 9A with a single-gate structure, the first TFT 9A may also have a dual-gate structure as in the first variation of the first embodiment described above. Additionally, while this embodiment illustrates a first TFT 9A with a top contact structure, the first TFT 9A may also have a bottom contact structure as in the first embodiment described above.

[0135] like Figure 16 As shown, a first through hole Ma is provided in the second interlayer insulating film 21 in such a way that it overlaps with the entire first channel region 17bc.

[0136] The first planarization film 23 has a flat surface in the display region D and is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a spin-on glass (SOG) material of a polysiloxane series. Here, as Figure 16 shown, a second through-hole Mb penetrating the first planarization film 23 is provided in the first planarization film 23 so as to overlap the entire first channel region 17bc. Further, as Figure 16 shown, the periphery of the second through-hole Mb is disposed at a position outside the periphery of the first through-hole Ma.

[0137] The second planarization film 25 has a flat surface in the display region D and is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a spin-on glass (SOG) material of a polysiloxane series. Here, as Figure 16 shown, a third through-hole Mc penetrating the second planarization film 25 is provided in the second planarization film 25 so as to overlap the entire first channel region 17bc. Further, as Figure 16 shown, the periphery of the third through-hole Mc is disposed at a position outside the periphery of the second through-hole Mb. Moreover, as Figure 16 shown, a metal covering layer 31b is integrally provided on the surface of the first interlayer insulating film 20 exposed from the first through-hole Ma, the surface of the peripheral portion of the first through-hole Ma, the surface of the peripheral portion of the second through-hole Mb, and the surface of the peripheral portion of the third through-hole Mc. Here, the metal covering layer 31b is formed of the same material as the first electrode 31a in the same layer. In addition, the metal covering layer 31b is electrically floating. Further, the metal covering layer 31b may be electrically connected to the first gate electrode 19a as in the second modification of the first embodiment.

[0138] Similar to the organic EL display device 50a of the first embodiment, in each sub-pixel P of the organic EL display device 50c configured as described above, the organic EL element 35 emits light with a luminance corresponding to the drive current to perform image display.

[0139] Next, a method for manufacturing the organic EL display device 50c of the present embodiment will be described. In addition, the method for manufacturing the organic EL display device 50c includes a TFT layer formation process, an organic EL element layer formation process, and a sealing film formation process.

[0140] <TFT layer formation process>

[0141] First, similar to the TFT layer formation process of the method for manufacturing the organic EL display device 50b of the second embodiment, a first planarization film 23 having a second through-hole Mb is formed (see Figure 17 ).

[0142] Next, on the surface of the substrate on which the first planarization film 23 is formed, after sequentially forming a titanium film (approximately 50 nm thick), an aluminum film (approximately 600 nm thick), and another titanium film (approximately 50 nm thick) using a sputtering method, the metal laminate is patterned, such as... Figure 18 As shown, power lines 24a, etc. are formed.

[0143] Finally, after coating a polyimide-based photosensitive resin film (approximately 2 μm thick) onto the surface of a substrate on which power lines 24a are formed, for example using spin coating or slot coating, this coated film is pre-baked, exposed, developed, and then post-baked. Thus, as... Figure 19 As shown, a second planarization film 25 with a third through hole Mc is formed.

[0144] As described above, a TFT layer 30c can be formed. Subsequently, in the organic EL element layer formation step of the manufacturing method of the organic EL display device 50a of the first embodiment, when forming the first electrode 31a, a metal cover layer 31b is formed, and the sealing film formation step of the manufacturing method of the organic EL display device 50a of the first embodiment is performed, thereby enabling the manufacturing of the organic EL display device 50c of this embodiment.

[0145] As described above, in the organic EL display device 50c according to this embodiment, a first through-hole Ma is formed in the second interlayer insulating film 21 composed of a silicon nitride film. This first through-hole Ma penetrates the second interlayer insulating film 21 in a manner that completely overlaps with the first channel region 17bc of the first semiconductor layer 17b. Therefore, the diffusion of hydrogen from the silicon nitride film of the second interlayer insulating film 21 to the first channel region 17bc can be suppressed. Furthermore, since a moisture-resistant metal cover layer 31b is integrally provided on the surface of the first interlayer insulating film 20 exposed by the first through-hole Ma (where the moisture-resistant second interlayer insulating film 21 is never provided), the surface of the peripheral portion of the first through-hole Ma, the surface of the second through-hole Mb, and the surface of the peripheral portions of the third through-hole Mc, the diffusion of moisture from the edge cover 32 to the first channel region 17bc can be suppressed. Therefore, in the first TFT 9A, the diffusion of moisture and hydrogen to the first channel region 17bc of the first semiconductor layer 17b is suppressed, thereby suppressing depletion shift caused by the diffusion of moisture and hydrogen. Furthermore, by suppressing the depletion offset caused by the diffusion of moisture and hydrogen, the reduction in manufacturing yield and reliability of the organic EL display device 50c can be suppressed.

[0146] Other Implementation Methods

[0147] In the above embodiments, an organic EL display device with a hybrid structure having a TFT with a semiconductor layer made of polysilicon in the sub-pixel and a TFT with a semiconductor layer made of oxide semiconductor is illustrated. However, the present invention can also be applied to an organic EL display device having a TFT with a semiconductor layer made of oxide semiconductor but not a TFT with a semiconductor layer made of polysilicon in the sub-pixel.

[0148] Furthermore, in the above embodiments, an organic EL layer with a five-layer stacked structure of a hole injection layer, a hole transport layer, a light emission layer, an electron transport layer, and an electron injection layer is exemplified. However, the organic EL layer may also be a three-layer stacked structure of a hole injection layer that also serves as a hole transport layer, a light emission layer, and an electron transport layer that also serves as an electron injection layer.

[0149] Furthermore, in the above embodiments, an organic EL display device is illustrated in which the first electrode is set as the anode and the second electrode is set as the cathode. However, the present invention can also be applied to an organic EL display device in which the stacked structure of the organic EL layer is reversed and the first electrode is set as the cathode and the second electrode is set as the anode.

[0150] Furthermore, in the above embodiments, an organic EL display device was described as an example of a display device, but the present invention can be applied to display devices having multiple light-emitting elements driven by current, such as a display device having a QLED (Quantum-dot Light Emitting Diode), which is a light-emitting element using a quantum dot layer.

[0151] Practicality in industry

[0152] As described above, the present invention can be used in flexible EL display devices.

[0153] Explanation of reference numerals in the attached figures

[0154] Ha First contact hole

[0155] Hb second contact hole

[0156] Hc Third Contact Hole

[0157] Hd Fourth Contact Hole

[0158] M through hole

[0159] Ma First Through Hole

[0160] P sub-pixel

[0161] 9a Initialization TFT (First Thin Film Transistor)

[0162] 9b Compensation TFT (First Thin Film Transistor)

[0163] 9c Write-in TFT (Second Thin Film Transistor)

[0164] 9d driving TFT (second thin-film transistor)

[0165] 9e Power supply TFT (second thin-film transistor)

[0166] 9f TFT (Second Thin Film Transistor) for Light Emitting Control

[0167] 9g TFT (First Thin Film Transistor) for Anode Discharge

[0168] 9A First TFT (First Thin Film Transistor)

[0169] 9B Second TFT (Second Thin Film Transistor)

[0170] 10. Resin substrate layer (base substrate layer)

[0171] 12a Second semiconductor layer

[0172] 12aa Third conductor region

[0173] 12ab Fourth conductor region

[0174] 13 Second gate insulating film

[0175] 14a Second gate electrode

[0176] 14b Lower gate electrode

[0177] 15 Third interlayer insulating film

[0178] 16a First conductive layer

[0179] 16b Second conductive layer

[0180] 17a, 17b First semiconductor layer

[0181] 17aa, 17ba First Conductor Region

[0182] 17ab, 17bb Second conductor region

[0183] 17ac, 17bc First Channel Area

[0184] 18a First gate insulating film

[0185] 19a First gate electrode

[0186] 20 First interlayer insulating film

[0187] 21 Second interlayer insulating film

[0188] 22a First terminal electrode

[0189] 22b Second terminal electrode

[0190] 22c Third terminal electrode

[0191] 22d Fourth terminal electrode

[0192] 22e, 22eb metallic coating

[0193] 23 Planarization film, first planarization film

[0194] 24A power cable (wiring layer)

[0195] 24b Metallic coating

[0196] 25 Second planarization film

[0197] 30a, 30aa, 30ab, 30ac, 30b, 30c TFT layers (thin-film transistor layers)

[0198] 31a First electrode

[0199] 31b Metallic coating

[0200] 33 Organic EL layer (organic electroluminescent layer, light-emitting functional layer)

[0201] 34 Second electrode

[0202] 40 Organic EL element layer (light-emitting element layer)

[0203] 45 Sealing film

[0204] 50a, 50b, 50c Organic EL Display Devices

Claims

1. A display device, characterized in that, include: Substrate layer; as well as A thin-film transistor layer is disposed on the substrate layer. In the thin-film transistor layer, a first thin-film transistor is provided for each sub-pixel, and the first thin-film transistor has a first semiconductor layer formed of oxide semiconductor. The first thin-film transistor includes: The first semiconductor layer includes a first conductor region and a second conductor region that are separated from each other, and a first channel region is defined between the first conductor region and the second conductor region. A first gate insulating film is disposed on the first semiconductor layer; A first gate electrode is disposed on the first gate insulating film and controls the conduction between the first conductor region and the second conductor region; The first interlayer insulating film is composed of a silicon oxide film disposed in such a way as to cover the first gate electrode; The second interlayer insulating film is composed of a silicon nitride film disposed on the first interlayer insulating film; and The first terminal electrode and the second terminal electrode are configured to be separated from each other on the second interlayer insulating film, and are electrically connected to the first conductor region and the second conductor region respectively via a first contact hole and a second contact hole formed in the first interlayer insulating film and the second interlayer insulating film. A through-hole is formed in the second interlayer insulating film, the through-hole penetrating the second interlayer insulating film in a manner that completely overlaps with the first channel region. A metal covering layer is integrally formed on the surface of the first interlayer insulating film exposed from the through hole and the periphery of the through hole.

2. The display device according to claim 1, characterized in that, The metal overlay is formed in the same layer as the first terminal electrode and the second terminal electrode.

3. The display device according to claim 1, characterized in that, The thin-film transistor layer includes: A first planarization film is disposed such that it covers the first terminal electrode and the second terminal electrode; A wiring layer is disposed on the first planarization film; as well as A second planarization film is disposed in such a manner that it covers the wiring layer. The metal overlay is formed in the same layer as the wiring layer using the same material.

4. The display device according to claim 1, characterized in that, include: A light-emitting element layer is disposed on the thin-film transistor layer, and a plurality of first electrodes, a plurality of light-emitting functional layers and a common second electrode are sequentially stacked in relation to the plurality of sub-pixels; as well as A sealing film is provided to cover the light-emitting element layer. The metal capping layer is formed in the same layer from the same material as each of the first electrodes.

5. The display device according to any one of claims 1 to 4, characterized in that, The metal capping layer is electrically connected to the first gate electrode.

6. The display device according to any one of claims 1 to 4, characterized in that, The metal overlay is electrically levitated.

7. The display device according to any one of claims 1 to 6, characterized in that, A lower gate electrode is disposed on the substrate layer side of the first channel region, separated by a third interlayer insulating film, and the lower gate electrode controls the conduction between the first conductor region and the second conductor region.

8. The display device according to any one of claims 1 to 7, characterized in that, A first conductive layer and a second conductive layer, which are in contact with the first conductor region and the second conductor region, are respectively disposed on the substrate layer side of the first conductor region and the second conductor region. The first contact hole and the second contact hole are formed in a manner that overlaps with the first conductive layer and the second conductive layer, respectively.

9. The display device according to any one of claims 1 to 7, characterized in that, The first contact hole and the second contact hole are formed in a manner that overlaps with the first conductor region and the second conductor region, respectively.

10. The display device according to any one of claims 1 to 9, characterized in that, In the thin-film transistor layer, in addition to the first thin-film transistor, each of the sub-pixels also has a second thin-film transistor with a second semiconductor layer formed of polycrystalline silicon. The second thin-film transistor includes: The second semiconductor layer includes mutually separated third conductor regions and fourth conductor regions; A second gate insulating film is disposed on the second semiconductor layer; A second gate electrode is disposed on the second gate insulating film and controls the conduction between the third conductor region and the fourth conductor region; A third interlayer insulating film, a first interlayer insulating film, and a second interlayer insulating film are sequentially disposed in a manner that covers the second gate electrode; as well as The third terminal electrode and the fourth terminal electrode are disposed separately on the second interlayer insulating film and are electrically connected to the third conductor region and the fourth conductor region respectively via the third contact hole and the fourth contact hole formed on the second gate insulating film, the third interlayer insulating film, the first interlayer insulating film and the second interlayer insulating film.

11. The display device according to claim 10, characterized in that, The first semiconductor layer is disposed on the third interlayer insulating film.

12. The display device according to claim 4, characterized in that, Each of the light-emitting functional layers is an organic electroluminescent layer.

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