Light-emitting substrate and display device

Abstract

The embodiments of the present disclosure disclose a light-emitting substrate and a display device, comprising: a substrate; a first conductive layer on the substrate; the first conductive layer comprises a plurality of common voltage lines and a plurality of first connection lines arranged at intervals; the plurality of common voltage lines extend along a first direction and are arranged along a second direction; a first insulating layer on a side of the first conductive layer away from the substrate; a second conductive layer on a side of the first insulating layer away from the substrate; the second conductive layer comprises a plurality of first bridge portions arranged at intervals; at least one of the plurality of common voltage lines comprises a plurality of signal line segments arranged at intervals; in the same common voltage line, two adjacent signal line segments are electrically connected by the first bridge portion, and at least one first connection line is arranged at a line gap between the two adjacent signal line segments; in the common voltage line, the line gap between the two adjacent signal line segments, the first bridge portion and the first connection line overlap on the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to light-emitting substrates and display devices. Background Technology

[0002] With the development of LED technology, backlights using LEDs at the sub-millimeter or even micrometer scale have been widely adopted. This allows backlights that utilize transmissive displays to achieve the same contrast ratio as OLED displays, while retaining the technological advantages of liquid crystal displays (LCDs), thus enhancing the display effect and providing users with a superior visual experience. Summary of the Invention

[0003] The light-emitting substrate provided in this embodiment includes:

[0004] Substrate;

[0005] A first conductive layer is located on the substrate; wherein the first conductive layer includes a plurality of common voltage lines and a plurality of first connection lines arranged at intervals between each other; the plurality of common voltage lines extend along a first direction and are arranged along a second direction;

[0006] The first insulating layer is located on the side of the first conductive layer that is away from the substrate.

[0007] A second conductive layer is located on the side of the first insulating layer away from the substrate; wherein the second conductive layer includes a plurality of first bridging portions spaced apart from each other;

[0008] Among them, at least one of the multiple common voltage lines includes multiple signal segments arranged at intervals; in the same common voltage line, two adjacent signal segments are electrically connected through the first bridging part and at least one first connecting line is provided at the segment gap between two adjacent signal segments;

[0009] At the gap between two adjacent signal segments in the common voltage line, the first bridging portion overlaps with the orthographic projection of the first connecting line on the substrate.

[0010] In some examples, an electric field exists between the first bridging portion and the first connecting line where the orthographic projections of the substrate overlap, and the direction of the electric field is from the first conductive layer to the second conductive layer.

[0011] In some examples, the second conductive layer further includes a first connection portion and a second connection portion disposed at intervals from each other;

[0012] The first end of the first connecting line is electrically connected to the first connecting part through the first via, and the second end of the first connecting line is electrically connected to the second connecting part through the second via; wherein the first via and the second via penetrate the first insulating layer.

[0013] In some examples, the orthographic projection of the first connecting line onto the substrate covers the orthographic projection of the first via onto the substrate, and the orthographic projection of the first connecting portion onto the substrate covers the orthographic projection of the first via onto the substrate.

[0014] The orthographic projection of the first connecting line on the substrate covers the orthographic projection of the second via on the substrate, and the orthographic projection of the second connecting portion on the substrate covers the orthographic projection of the second via on the substrate.

[0015] In some examples, the width of the area of ​​the first connection portion covering the first via in the first direction is greater than the width of the first connection line in the first direction;

[0016] The width of the area of ​​the second connecting portion covering the second via in the first direction is greater than the width of the first connecting line in the first direction.

[0017] In some examples, the width of the first bridging portion in the first direction ranges from 100 micrometers to 250 micrometers, and the width of the first connecting line in the first direction ranges from 0.6 micrometers to 2.5 micrometers.

[0018] In some examples, the length of the first connecting line in the second direction is greater than the length of the first bridging portion in the second direction.

[0019] In some examples, the first bridging portion extends to one side of the first connecting portion and has a first gap with the first connecting portion, and the first bridging portion extends to one side of the second connecting portion and has a second gap with the second connecting portion;

[0020] The width of the first gap and the width of the second gap are both in the range of 20 micrometers to 50 micrometers.

[0021] In some examples, the gap between the first connecting line and the signal segment has a width ranging from 20 micrometers to 50 micrometers in the first direction.

[0022] In some examples, in a direction perpendicular to the plane of the substrate, the thickness of the first bridging portion is greater than or equal to the thickness of the first connecting portion and the second connecting portion in the second conductive layer.

[0023] In some examples, the second conductive layer further includes a plurality of pads;

[0024] One end of the first connection portion is electrically connected to one of the pads, and the other end is electrically connected to the first end of the first connection line;

[0025] The other end of the second connection portion is electrically connected to another one of the pads, and the other end is electrically connected to the second end of the first connection line.

[0026] In some examples, the plurality of common voltage lines are located in the display area; the display area further includes a plurality of light-emitting units, and the light-emitting unit includes a driving circuit and a plurality of light-emitting elements; wherein, the driving circuit includes a common voltage terminal and an output terminal; the plurality of light-emitting elements are sequentially connected in series between the driving voltage terminal and the output terminal; the common voltage terminal is electrically connected to the common voltage line; the pad is electrically connected to at least one of the light-emitting elements and the driving circuit;

[0027] The plurality of light-emitting elements in the light-emitting unit are divided into M element groups, and each element group includes N light-emitting elements arranged along the first direction; the M element groups are arranged along the second direction; N is an integer greater than 0, and M is an integer greater than 0;

[0028] In the order from the driving voltage terminal to the output terminal, the plurality of element groups are sequentially numbered;

[0029] The first light-emitting element in the element group numbered 1 is electrically connected to the driving voltage terminal;

[0030] The first light-emitting element in the element group numbered k is electrically connected to the first light-emitting element in the element group numbered k + 1 through the first connection line; wherein, 1 < k < M and k is an integer;

[0031] The last first light-emitting element in the element group numbered M is electrically connected to the output terminal;

[0032] One column of light-emitting units corresponds to one of the common voltage lines, and the common voltage line is located between the element group numbered k and the element group numbered k + 1 in the corresponding column of light-emitting units.

[0033] In some examples, the second conductive layer further includes a plurality of series traces arranged at intervals; the light-emitting elements in the same element group are connected in series through the series traces, and the last light-emitting element in the element group numbered k - 1 is electrically connected to the last light-emitting element in the element group numbered k through the series traces;

[0034] The projection of the common voltage line onto the substrate does not overlap with the projection of the series trace onto the substrate.

[0035] In some examples, the light-emitting substrate further includes a fan-out region;

[0036] The first conductive layer further includes multiple first fan-out lines and multiple second connecting lines located in the fan-out area; wherein, one of the common voltage lines is electrically connected to one of the first fan-out lines; the first fan-out line includes a first sub-fan-out line and a second sub-fan-out line; the first sub-fan-out line extends along the first direction, and the second sub-fan-out line extends along the second direction;

[0037] The second conductive layer further includes a plurality of second bridging portions located in the fan-out region;

[0038] The first sub-fan-out line includes a plurality of first fan-out line segments arranged at intervals; in the same first sub-fan-out line, two adjacent first fan-out line segments are electrically connected through the second bridging part and at least one second connecting line is provided in the gap between two adjacent first fan-out line segments.

[0039] At the gap between two adjacent first fan-out line segments in the first sub-fan-out line, the second bridging portion overlaps with the orthographic projection of the second connecting line on the substrate.

[0040] In some examples, the first conductive layer also includes multiple third connecting lines;

[0041] The second conductive layer also includes a plurality of third bridging portions located in the fan-out region;

[0042] The second sub-fan-out line includes a plurality of spaced second fan-out line segments; in the same second sub-fan-out line, two adjacent second fan-out line segments are electrically connected through the third bridging part and at least one third connecting line is provided in the gap between two adjacent second fan-out line segments;

[0043] At the gap between two adjacent second fan-out line segments in the second sub-fan-out line, the third bridging portion overlaps with the orthographic projection of the third connecting line on the substrate.

[0044] In some examples, the fan-out area includes multiple light-emitting units, each light-emitting unit including a driving circuit and multiple light-emitting elements; wherein, the driving circuit includes a common voltage terminal and an output terminal; the multiple light-emitting elements are connected in series between the driving voltage terminal and the output terminal.

[0045] The common voltage terminal is electrically connected to the first fan-out line;

[0046] In at least one of the light-emitting units, at least two of the light-emitting elements are electrically connected via the second connecting line; and / or, at least two of the light-emitting elements are electrically connected via the third connecting line.

[0047] The display device provided in this disclosure includes the above-described light-emitting substrate. Attached Figure Description

[0048] Figure 1a This is a schematic diagram of the structure of a light-emitting substrate in related technologies;

[0049] Figure 1b This is a schematic diagram of a partial layout of a light-emitting substrate in a related technology;

[0050] Figure 2 This is a schematic diagram of the structure of the light-emitting substrate in the embodiments of this disclosure;

[0051] Figure 3 This is a partial structural schematic diagram of the light-emitting substrate in an embodiment of this disclosure;

[0052] Figure 4 A waveform diagram of the second input signal in the driving circuit provided in an embodiment of this disclosure;

[0053] Figure 5 Signal timing diagram of the driving circuit provided in the embodiments of this disclosure;

[0054] Figure 6 This is a partial layout diagram of the light-emitting substrate in an embodiment of this disclosure;

[0055] Figure 7 for Figure 6 Enlarged layout diagram of the central FB area;

[0056] Figure 8a for Figure 7 A schematic diagram of the cross-sectional structure along the AA' direction;

[0057] Figure 8b for Figure 7 A schematic diagram of the cross-sectional structure along the BB' direction;

[0058] Figure 9 This is a schematic diagram of a partial layout of the fan-out area in an embodiment of this disclosure. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0060] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0061] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0062] Combination Figure 1a and Figure 1bA first conductive layer 02, an insulating layer 03, and a second conductive layer 04 are sequentially disposed on the substrate 01. The first conductive layer 02 has a driving voltage line 220 and a common voltage line 210. The second conductive layer 04 has metal connecting lines. Taking a light-emitting unit with nine light-emitting elements as an example, these nine light-emitting elements are connected in series via the metal connecting lines. The metal connecting lines between these nine light-emitting elements are divided into eight segments: segment A, segment B, segment C, segment D, segment E, segment F, and segment G. For example, the driving voltage line 220 transmits a voltage of 27V, the common voltage line 210 transmits a voltage of 0V, the metal connection line in segment A transmits a voltage of 24V, the metal connection line in segment B transmits a voltage of 21V, the metal connection line in segment C transmits a voltage of 18V, the metal connection line in segment D transmits a voltage of 15V, the metal connection line in segment E transmits a voltage of 12V, the metal connection line in segment F transmits a voltage of 9V, the metal connection line in segment G transmits a voltage of 6V, and the metal connection line in segment H transmits a voltage of 3V. Furthermore, the projection of the metal connection line in segment C onto the substrate overlaps with the projection of the driving voltage line 220 onto the substrate, and the projection of the metal connection line in segment F onto the substrate overlaps with the projection of the common voltage line 210 onto the substrate.

[0063] Because the voltage transmitted by the metal connection line in segment F is greater than the voltage transmitted by the common voltage line 210, the direction of the electric field between the overlapping area of ​​the metal connection line in segment F and the common voltage line 210 is from the second conductive layer to the first conductive layer. Since the second conductive layer is easily exposed and prone to introducing water and oxygen, and the materials of the first conductive layer 02 and the second conductive layer 04 are typically made of low-resistance Cu, Cu is relatively reactive and therefore prone to metal corrosion under the influence of an electric field. A potential difference exists between the metal connection line in segment F and the common voltage line 210, forming the anode and cathode for electrochemical corrosion. The metal connection line in segment F acts as the positive electrode undergoing oxidation, while the common voltage line 210 acts as the cathode undergoing reduction. The continuous electrochemical corrosion eventually leads to a short circuit between the metal connection line in segment F and the common voltage line 210. However, the presence of electrochemical corrosion in the light-emitting substrate will affect the light-emitting stability of the substrate.

[0064] Furthermore, since the voltage transmitted by the metal connection line in segment C is less than the voltage transmitted by the driving voltage line 220, the direction of the electric field between the overlapping area of ​​the metal connection line in segment C and the driving voltage line 220 is from the first conductive layer to the second conductive layer. The driving voltage line 220 is also protected by an insulating layer 03, and the intrusion path of water and oxygen is relatively long, thus reducing the likelihood of electrochemical corrosion. In view of this, at least one embodiment of this disclosure provides a light-emitting substrate and a display device that reduces the impact of electrochemical corrosion on the light-emitting substrate and improves light emission stability.

[0065] In some embodiments, such as Figure 2 As shown, the light-emitting substrate provided in at least one embodiment of this disclosure may include a substrate 10. The substrate 10 may include a display area and a fan-out area FO. Exemplarily, the material of the substrate 10 may be selected from plastic, polyimide, silicon, ceramic, glass, quartz, etc., and the embodiments of this disclosure are not limited thereto.

[0066] In some embodiments, such as Figure 2 As shown, the display area may include multiple light-emitting units (PXs) arranged in an array. For example, the multiple light-emitting units (PXs) are arranged in multiple rows and columns. In practical applications, the number of light-emitting units (PXs) can be determined according to actual needs, such as the size of the light-emitting substrate and the required brightness. Figure 2 Only 6 rows and 5 columns of light-emitting units PX are shown in the image, but it should be understood that the number of light-emitting units PX is not limited to this.

[0067] In some embodiments, such as Figure 2 As shown, in the display area, the light-emitting units PX can be arranged in multiple rows and columns along the first direction F1 and the second direction F2. For example, the light-emitting substrate is rectangular, the first direction F1 can be parallel to the long side of the light-emitting substrate, and the second direction F2 can be parallel to the short side of the light-emitting substrate. Alternatively, the first direction F1 can also be parallel to the short side of the light-emitting substrate, and the second direction F2 can also be parallel to the long side of the light-emitting substrate. Of course, the embodiments of this disclosure are not limited to this; the first direction F1 and the second direction F2 can be any direction, as long as they intersect. Furthermore, the multiple light-emitting units PX are not limited to being arranged in a straight line; they can also be arranged along a broken line, in a ring, or in any other manner, depending on actual needs. The embodiments of this disclosure do not impose any limitations on this.

[0068] In some embodiments, such as Figure 2 and Figure 3 As shown, each light-emitting unit PX may include a driving circuit QD0 and multiple light-emitting elements QD1. Exemplarily, the driving circuit QD0 may include a first input terminal Di, a second input terminal Pwr, an output terminal OT, and a common voltage terminal GND. Furthermore, the multiple light-emitting elements QD1 in the light-emitting unit PX are connected in series and electrically connected between the driving voltage terminal Vled and the output terminal OT of the driving circuit QD0. Alternatively, the multiple light-emitting elements QD1 in the light-emitting unit PX may be connected in parallel first, and then in series, to electrically connect the driving voltage terminal Vled and the output terminal OT of the driving circuit QD0. In practical applications, the design can be determined according to actual needs, and no limitation is made here.

[0069] In some examples, in specific implementations, the driving circuit QD0 can be configured to output a relay signal through the output terminal OT during a first time period based on a first input signal received at the first input terminal Di and a second input signal received at the second input terminal Pwr, and to form a current path with the series-connected light-emitting element QD1 through the output terminal OT during a second time period. Exemplarily, the first input terminal Di receives a first input signal, such as an address signal, to select the driving circuit QD0 corresponding to the specified address. For example, the addresses of different driving circuits QD0 may be the same or different. The first input signal can be an 8-bit address signal, and the address to be transmitted can be determined by parsing this address signal. The second input terminal Pwr receives a second input signal, such as a power line carrier communication signal. For example, the second input signal not only provides power to the driving circuit QD0 but also transmits communication data to the driving circuit QD0. This communication data can be used to control the light-emitting duration of the corresponding light-emitting unit PX, thereby controlling its visual brightness. The output terminal OT can output different signals during different time periods, such as a relay signal and a driving signal respectively. For example, the relay signal is an address signal provided to other driving circuits QD0. That is, the first input terminal Di of other driving circuits QD0 receives this relay signal as its first input signal, thereby obtaining the address signal. For example, the driving signal can be a driving current used to drive the light-emitting element QD1 to emit light. The common voltage terminal GND receives a common voltage signal, such as a ground signal.

[0070] Furthermore, the driving circuit QD0 is configured to output a relay signal through the output terminal OT during a first time period based on the first input signal received at the first input terminal Di and the second input signal received at the second input terminal Pwr, and to provide a driving signal through the output terminal OT to a plurality of sequentially connected light-emitting elements QD1 during a second time period. Specifically, during the first time period, the output terminal OT outputs a relay signal, which is provided to other driving circuits QD0 to provide address signals. During the second time period, the output terminal OT outputs a driving signal, which is provided to the plurality of sequentially connected light-emitting elements QD1, causing the light-emitting elements QD1 to emit light during the second time period. For example, the first time period and the second time period are different time periods; the first time period may, for example, be earlier than the second time period. The first time period may be consecutively connected to the second time period, with the end time of the first time period being the start time of the second time period; alternatively, there may be other time periods between the first and second time periods, which can be used to implement other required functions, or these other time periods may only be used to separate the first and second time periods to avoid interference between the signals from the output terminal OT during the first and second time periods.

[0071] It should be noted that when the driving signal is a driving current, the driving current can flow from the output terminal OT to the light-emitting element QD1, or it can flow from the light-emitting element QD1 into the output terminal OT. The direction of the driving current flow can be determined according to actual needs, and the embodiments disclosed herein do not impose any restrictions on this. In this document, "output terminal OT outputs driving signal" means that the output terminal OT provides a driving signal, and the direction of the driving signal can be either from the output terminal OT or into the output terminal OT.

[0072] Mini-LEDs (or micro-LEDs) are small in size and high in brightness, making them widely applicable in display devices or their backlight modules. By finely adjusting the backlight, they enable the display of high-dynamic-range (HDR) images. For example, the typical size (e.g., length) of a Micro-LED is less than 100 micrometers, such as 10 to 80 micrometers; the typical size (e.g., length) of a Mini-LED is 80 to 350 micrometers, such as 80 to 120 micrometers. Exemplarily, the light-emitting element QD1 can be a Micro-LED or a Mini-LED.

[0073] For example, each light-emitting element QD1 includes a positive (+) and a negative (-) electrode (or, alternatively, an anode and a cathode). The positive and negative electrodes of multiple light-emitting elements QD1 are connected in series, forming a current flow path between the driving voltage terminal Vled and the output terminal OT. Furthermore, the driving voltage terminal Vled can provide a driving voltage, for example, a high voltage during the period when the light-emitting elements QD1 need to emit light (the second time period), and a low voltage during other periods. Thus, during the second time period, the driving signal (e.g., driving current) flows sequentially from the driving voltage terminal Vled through the multiple light-emitting elements QD1, and then into the output terminal OT of the driving circuit QD0. The multiple light-emitting elements QD1 emit light when the driving current flows. By controlling the duration of the driving current, the duration of light emission of the light-emitting elements QD1 can be controlled, thereby controlling the visual brightness of the light emission.

[0074] In some examples, such as Figure 2 and Figure 3As shown, the light-emitting unit PX may include nine light-emitting elements QD1, arranged in a 3x3 row and 3x3 column. For example, when these nine light-emitting elements QD1 are connected in series, the starting point is the QD1 electrically connected to the driving voltage terminal Vled, and the ending point is the QD1 electrically connected to the output terminal OT of the driving circuit QD0. Furthermore, the driving voltage terminal Vled can be electrically connected to the positive terminal of the light-emitting element QD1, and the output terminal OT of the driving circuit QD0 can be electrically connected to the negative terminal of the light-emitting element QD1. This distribution and series connection effectively avoids overlapping traces, facilitating design and fabrication. Moreover, the length of the signal connection between any two adjacent light-emitting elements QD1 in the series circuit can be set to approximately the same, resulting in a more balanced resistance of the signal connection itself, improving load balancing and circuit stability.

[0075] It should be noted that, in the embodiments of this disclosure, the number of light-emitting elements QD1 in each light-emitting unit PX is not limited, and can be any number such as 6, 8, or 12, but is not limited to 9. Multiple light-emitting elements QD1 can be arranged in any manner, such as according to a desired pattern, and are not limited to a matrix arrangement. Furthermore, the placement of the driving circuit QD0 is not limited; it can be placed in any gap between the light-emitting elements QD1, depending on actual needs. The embodiments of this disclosure do not impose any limitations on this.

[0076] In some examples, in specific implementation, combined with Figure 2 and Figure 3 As shown, the relative positions of the driving circuit QD0 within the light-emitting unit PX can be different, or the positions of the driving circuit QD0 within the light-emitting unit PX can be the same. Furthermore, the relative positional relationship of the light-emitting elements QD1 in each light-emitting unit PX can be made the same. For example, the relative positional relationship of the light-emitting elements QD1 in a light-emitting unit PX can be used as a reference, and they can be periodically repeated along the first direction F1 and the second direction F2. For example, in a plurality of light-emitting units PX arranged in the first direction F1, the light-emitting elements QD1 located at the same position in each light-emitting unit PX can be arranged approximately along the same straight line along the first direction F1. In a plurality of light-emitting units PX arranged in the second direction F2, the light-emitting elements QD1 located at the same position in each light-emitting unit PX can be arranged approximately along the same straight line along the second direction F2.

[0077] In some examples, the driver circuit QD0 may include a demodulation circuit, a physical layer interface circuit, a data processing control circuit, a pulse width modulation circuit, a driver signal generation circuit, a relay signal generation circuit, and a power supply circuit.

[0078] Exemplarily, the demodulation circuit is electrically connected to the second input terminal Pwr and the physical layer interface circuit, and is configured to demodulate the second input signal to obtain communication data and transmit the communication data to the physical layer interface circuit. For example, the second input signal input to the second input terminal Pwr is a power line carrier communication signal, and the power line carrier communication signal contains information corresponding to the communication data. For example, the communication data is data reflecting the light-emitting duration, and thus represents the required light-emitting brightness. Compared with the conventional Serial Peripheral Interface (SPI) protocol, in the embodiments of the present disclosure, by adopting the Power Line Carrier Communication (PLC) protocol, the communication data is superimposed on the power supply signal, thereby effectively reducing the number of signal lines.

[0079] As Figure 4 shown, the dashed ellipse represents an enlarged view of the corresponding waveform. When the second input signal is at a high level, the amplitude of its high level fluctuates near the threshold amplitude Vth. For example, it varies between the first amplitude V1 and the second amplitude V2, where V2 < Vth < V1. By modulating the variation law of the first amplitude V1 and the second amplitude V2, the communication data can be modulated into the second input signal, so that the second input signal transmits the information corresponding to the communication data while transmitting electrical energy. For example, the demodulation circuit filters out the DC power component of the second input signal, and thus the communication data can be obtained. For a detailed description of the second input signal, reference can be made to the conventional power line carrier communication signal, which will not be elaborated here. Correspondingly, for a detailed description of the demodulation circuit, reference can also be made to the demodulation circuit of the conventional power line carrier communication signal, which will not be elaborated here.

[0080] Exemplarily, the physical layer interface circuit is also electrically connected to the data processing and control circuit, and is configured to process the communication data to obtain a data frame (such as frame frequency data) and transmit the data frame to the data processing and control circuit. The data frame obtained by the physical layer interface circuit contains the information to be transmitted to the driving circuit QD0, such as information related to the light-emitting time (such as the specific duration of the light-emitting time). For example, the physical layer interface circuit can be a conventional port physical layer (Physical, PHY), and for a detailed description, reference can be made to the conventional design, which will not be elaborated here.

[0081] For example, the data processing control circuit is also electrically connected to the first input terminal Di, the pulse width modulation circuit, and the relay signal generation circuit. The data processing control circuit is configured to generate a pulse width control signal based on a data frame and transmit the pulse width control signal to the pulse width modulation circuit, and to generate a relay control signal based on the first input signal and transmit the relay control signal to the relay signal generation circuit. For example, the required light-emitting duration of the light-emitting element QD1 connected to the driving circuit QD0 can be determined from the data frame, and a corresponding pulse width control signal is generated based on this light-emitting duration. For example, the relay control signal is a signal generated by the data processing control circuit after processing the first input signal. By processing the first input signal (e.g., parsing, latching, decoding, etc.), the address signal corresponding to the driving circuit QD0 can be determined, and a relay control signal corresponding to a subsequent address, which corresponds to another driving circuit QD0, will be generated. For example, the data processing control circuit can be implemented as a microcontroller, a central processing unit (CPU), a digital signal processor, etc.

[0082] Exemplarily, the pulse width modulation circuit is also electrically connected to the drive signal generation circuit and is configured to generate a pulse width modulation signal in response to a pulse width control signal, and transmit the pulse width modulation signal to the drive signal generation circuit. For example, the pulse width modulation signal generated by the pulse width modulation circuit corresponds to the light emission duration required by the light-emitting element QD1, such as the effective pulse width duration being equal to the light emission duration required by the light-emitting element QD1. For example, a detailed description of the pulse width modulation circuit can be found in conventional pulse width modulation circuits, and will not be detailed here.

[0083] For example, the drive signal generation circuit is also electrically connected to the output terminal OT and is configured to generate a drive signal in response to a pulse width modulation signal and output the drive signal from the output terminal OT. Here, outputting the drive signal from the output terminal OT can mean that the drive signal (e.g., drive current) flows from the output terminal OT to the light-emitting element QD1, or it can mean that the drive signal (e.g., drive current) flows from the light-emitting element QD1 into the output terminal OT; the specific direction of the current is not limited.

[0084] For example, in some examples, when the drive signal is a drive current, the drive signal generation circuit may include a current source and a metal-oxide-semiconductor (MOS) field-effect transistor (FET), referred to as a MOS transistor. The control terminal of the MOS transistor receives a pulse-width modulation (PWM) signal transmitted by the pulse-width modulation (PWM) circuit, thereby turning it on or off under the control of the PWM signal. The first terminal of the MOS transistor is connected to the output terminal OT, and the second terminal of the MOS transistor is connected to the first terminal of the current source. The second terminal of the current source is connected to the common voltage terminal GND to receive the common voltage. For example, the current source may be a constant current source.

[0085] When the pulse width modulation signal is at an active level, the MOSFET is turned on, and the current source provides drive current through the output terminal OT. When the pulse width modulation signal is at an inactive level, the MOSFET is turned off, and the output terminal OT does not provide drive current. The duration of the active level of the pulse width modulation signal is equal to the conduction duration of the MOSFET, and the conduction duration of the MOSFET is equal to the duration for which the output terminal OT provides drive current. Therefore, the emission duration of the light-emitting element QD1 can be further controlled, thereby controlling the visual brightness. For example, in some examples, when the MOSFET is turned on, the drive current flows from the OT terminal into the drive circuit QD0, and then sequentially through the MOSFET and the current source, before flowing into the ground terminal (e.g., the common voltage terminal GND). It should be noted that in the embodiments of this disclosure, the drive signal generation circuit can also adopt other circuit structures, and the embodiments of this disclosure are not limited in this regard.

[0086] Exemplarily, the relay signal generation circuit is also electrically connected to the output terminal OT and is configured to generate a relay signal based on a relay control signal and output the relay signal from the output terminal OT. For example, the relay control signal corresponds to a subsequent address, and the relay signal generated based on the relay control signal contains the subsequent address, which corresponds to another driving circuit QD0. After the relay signal is output from the output terminal OT, it is provided to the first input terminal Di of the separately provided driving circuit QD0. The relay signal is input to the separately provided driving circuit QD0 as a first input signal, thereby enabling the separately provided driving circuit QD0 to obtain the corresponding address signal. The relay signal generation circuit can be implemented by a latch, decoder, encoder, etc., and the embodiments of this disclosure are not limited thereto.

[0087] It should be noted that, in the embodiments of this disclosure, although both the drive signal generation circuit and the relay signal generation circuit are electrically connected to the output terminal OT, the drive signal generation circuit and the relay signal generation circuit output drive signals and relay signals at different time periods. The drive signals and relay signals are transmitted through the output terminal OT in a time-division manner, so they will not affect each other.

[0088] Exemplarily, the power supply circuit is electrically connected to both the demodulation circuit and the data processing control circuit, and is configured to receive electrical energy and supply power to the data processing control circuit. For example, if the second input signal is a power line carrier communication signal, after demodulation by the demodulation circuit, the DC power component (i.e., electrical energy) in the second input signal is transmitted to the power supply circuit, which then supplies power to the data processing control circuit. Of course, the embodiments of this disclosure are not limited to this; the power supply circuit can also be electrically connected to other circuits in the drive circuit QD0 to provide electrical energy. The power supply circuit can be implemented using a switching circuit, a voltage conversion circuit, a voltage regulator circuit, etc., and the embodiments of this disclosure do not limit this.

[0089] It should be noted that in the embodiments of this disclosure, the driving circuit QD0 may also include more circuits and components, not limited to the demodulation circuit, physical layer interface circuit, data processing control circuit, pulse width modulation circuit, driving signal generation circuit, relay signal generation circuit and power supply circuit mentioned above. This can be determined according to the functions to be implemented, and the embodiments of this disclosure do not limit this.

[0090] like Figure 5 As shown, when the drive circuit QD0 is working, it first powers on (i.e., is powered on) to complete initialization. Then, it performs an address write operation during time period S1. That is, during time period S1, the first input signal Di_1 is input to the drive circuit QD0 through the first input terminal Di, thereby writing the address. For example, the first input signal Di_1 is sent through a separately provided transmitter.

[0091] Next, during time period S2, drive configuration is performed, and a relay signal Di_2 is output through the output terminal OT. For example, the relay signal Di_2 is input as the first input signal to the first input terminal Di of the separately provided drive circuit QD0. For example, the aforementioned first time period is time period S2.

[0092] Then, during period S3, the drive voltage terminal Vled is energized. For example, after multiple drive circuits QD0 have acquired their corresponding addresses, period S3 begins approximately 10 microseconds later. At this time, the drive voltage provided by the drive voltage terminal Vled becomes high.

[0093] Next, during time period S4, the driving circuit QD0 is in normal operating mode, and the output terminal OT provides a driving signal (e.g., driving current) according to the required duration, so that the light-emitting element QD1 connected to the driving circuit QD0 emits light for the required duration. For example, the aforementioned second time period is time period S4. For example, in the case of a backlight unit of a display device, the light-emitting substrate using the driving circuit QD0 can achieve a high dynamic range effect by operating in local dimming mode.

[0094] Finally, during period S5, the system shuts down, that is, the drive circuit QD0 is de-energized, and the drive voltage provided by the drive voltage terminal Vled becomes low, and the light-emitting element QD1 stops emitting light.

[0095] It should be noted that the above workflow is merely illustrative and not restrictive. The actual workflow of the drive circuit QD0 can be determined according to actual needs, and the embodiments disclosed herein do not impose any limitations on it. Figure 5 In this diagram, VREG, POR, Vreg_1.8, OSC, and Re_B are all internal signals of the driver circuit QD0 and will not be input or output through the first input terminal Di, the second input terminal Pwr, the output terminal OT, or the common voltage terminal GND. Di_1 is the first input signal received by the driver circuit QD0, Di_2 is the relay signal output by the driver circuit QD0 (that is, the first input signal received by the next connected driver circuit QD0), and Di_n is the first input signal received by the nth driver circuit QD0 among multiple sequentially connected driver circuits QD0.

[0096] For example, in a specific implementation, the driving circuit QD0 can be configured as a chip. The chip size (e.g., length) can be tens of micrometers, and the chip area is approximately several hundred square micrometers or even smaller, similar in size to a Mini-LED. This miniaturization feature facilitates integration into the light-emitting substrate (e.g., bonding it to the surface of the light-emitting substrate), saving space on the printed circuit board, simplifying the structure, and contributing to a thinner and lighter design. Each driving circuit QD0 directly drives one light-emitting unit PX, avoiding the problems of complex operation and flickering inherent in line scanning control methods. Furthermore, the driving circuit QD0 has fewer ports, requires fewer signals, has a simple control method, simple wiring, and low cost.

[0097] In specific implementation, as described in the embodiments of this disclosure, Figures 6 to 8b As shown, a buffer layer 400 is disposed on the substrate 10 to improve the adhesion of the first conductive layer. The first conductive layer is located on the side of the buffer layer 400 facing away from the substrate 10. Exemplarily, the first conductive layer may include: a plurality of common voltage lines 210, a plurality of driving voltage lines 220, a plurality of source voltage lines 230, and a plurality of first connection lines 110 disposed at intervals between each other. Exemplarily, a column of light-emitting units PX may correspond to one common voltage line 210, one source voltage line 230, and one driving voltage line 220. Wherein, for a column of light-emitting units PX, the common voltage line 210, the source voltage line 230, and the driving voltage line 220 correspond, and the orthographic projection of the common voltage line 210 onto the substrate 10 is located between the driving voltage line 220 and the source voltage line 230.

[0098] For example, multiple driving voltage lines 220 extend along a first direction F1 and are arranged along a second direction F2. One column of light-emitting units PX can correspond to one driving voltage line 220, so that the driving voltage terminal Vled of that column of light-emitting units PX is electrically connected to the corresponding driving voltage line 220. For example, as... Figure 3 As shown, when these 9 light-emitting elements QD1 are connected in series, the light-emitting element QD1 that is electrically connected to the driving voltage line 220 is taken as the starting point for the series connection of these 9 light-emitting elements QD1.

[0099] For example, multiple source voltage lines 230 extend along a first direction F1 and are arranged along a second direction F2. The source voltage lines 230 can be electrically connected to the second input terminal Pwr of the drive circuit QD0. This allows the second input signal to be transmitted to the second input terminal Pwr of the drive circuit QD0 via the source voltage lines 230.

[0100] For example, multiple common voltage lines 210 extend along a first direction F1 and are arranged along a second direction F2. In some examples, a common voltage terminal can be electrically connected to the common voltage line 210 to provide voltage to the common voltage terminal of the drive circuit QD0 through the common voltage line 210.

[0101] It should be noted that by aligning the extension directions of most signal lines in the first conductive layer, wiring space can be rationally designed, reducing signal interference.

[0102] For example, a row of light-emitting units PX corresponds to a common voltage line 210 and a driving voltage line 220. That is, the common voltage terminal GND of the driving circuit QD0 in a row of light-emitting units PX is electrically connected to the same common voltage line 210, and the driving voltage terminal Vled in a row of light-emitting units PX is electrically connected to the same driving voltage line 220.

[0103] In some examples, in specific implementations, such as Figure 6 and Figure 7 As shown, for a column of light-emitting units PX, the common voltage line 210, driving voltage line 220, and source voltage line 230 are located between the driving voltage line 220 and the source voltage line 230. For example, the width of the common voltage line 210 in the second direction F2 is greater than the width of the driving voltage line 220 in the second direction F2. The width of the driving voltage line 220 in the second direction F2 is greater than the width of the source voltage line 230 in the second direction F2. The width of the source voltage line 230 in the second direction F2 is greater than the width of the cascaded trace 240 in the second direction F2.

[0104] In some examples, the first conductive layer may be a single-layer structure made of a metallic material. Alternatively, the first conductive layer may also be a multilayer structure made of a metallic material. For example, two first conductive layers made of metallic materials may be used, such as the first conductive layer having a C-1 layer and a C-2 layer. Exemplarily, the metallic material may include, but is not limited to, Cu.

[0105] In a specific implementation, in this embodiment of the disclosure, a first insulating layer 310 is formed on the first conductive layer, that is, the first insulating layer 310 is located on the side of the first conductive layer opposite to the substrate 10. Furthermore, the first insulating layer 310 is provided with a first via GK1, a second via GK2, a third via GK3, and a fourth via GK4. Exemplarily, the first insulating layer 310 can be formed as a single-layer structure using inorganic, organic, or organic-inorganic composite materials. Alternatively, the first insulating layer 310 can also be a multilayer structure formed using at least one of inorganic, organic, or organic-inorganic composite materials. For example, the first insulating layer 310 can be formed using multiple layers of organic materials. The first insulating layer 310 can also be formed using multiple layers of inorganic materials. The first insulating layer 310 can also be formed by stacking organic and inorganic materials. Exemplarily, such as... Figure 8a and Figure 8b As shown, the first insulating layer 310 may include an insulating layer 311 and an insulating layer 312. The insulating layer 312 may be made of an organic material, while the insulating layer 311 may be made of an inorganic material.

[0106] For example, the inorganic material may be selected from at least one of silicon nitride (SiNx), silicon oxide (SiOX), silicon oxynitride (SiON), etc. The organic material may be polyimide (PI), etc.

[0107] In some examples, in specific implementations, such as Figures 6 to 8bAs shown, a second conductive layer is formed on the first insulating layer 310, that is, the second conductive layer is located on the side of the first insulating layer 310 facing away from the substrate 10. Exemplarily, the second conductive layer may include: multiple pads (such as PD1, PD2, PD3, PD4) and multiple cascaded traces 240 spaced apart from each other. Exemplarily, the multiple cascaded traces 240 extend along a first direction F1. For example, along the first direction F1, the driving circuits QD0 in a column of light-emitting units PX can be coupled to each other, and in a column, the driving circuits QD0 in adjacent light-emitting units PX are coupled through the cascaded traces 240. For example, the first row to the sixth row are defined along the direction indicated by the arrow in the first direction F1. The first column to the fifth column are defined along the direction indicated by the arrow in the second direction F2. Taking the first column as an example, the output terminal of the driving circuit QD0 in the first row of light-emitting units PX is coupled to the first input terminal Di of the driving circuit QD0 in the second row of light-emitting units PX through a cascaded trace 240. The output of the driver circuit QD0 in the second row of LED units PX is coupled to the first input terminal Di of the driver circuit QD0 in the third row of LED units PX via a cascaded trace 240. The output of the driver circuit QD0 in the third row of LED units PX is coupled to the first input terminal Di of the driver circuit QD0 in the fourth row of LED units PX via a cascaded trace 240. The output of the driver circuit QD0 in the fourth row of LED units PX is coupled to the first input terminal Di of the driver circuit QD0 in the fifth row of LED units PX via a cascaded trace 240. The output of the driver circuit QD0 in the fifth row of LED units PX is coupled to the first input terminal Di of the driver circuit QD0 in the sixth row of LED units PX via a cascaded trace 240. The output of the driver circuit QD0 in the sixth row of LED units PX is coupled to the cascaded output terminal via a cascaded output trace. This ensures that the cascaded trace 240 and the cascaded driver circuit QD0 are aligned in direction, reducing signal overlap and interference.

[0108] In specific implementations, in the embodiments of this disclosure, the pads can be electrically connected to the driving circuit. For example, the pads can be electrically connected to corresponding pins in the driving circuit for signal transmission.

[0109] In specific implementation, as described in the embodiments of this disclosure, Figure 6 and Figure 7 As shown, pads can also be electrically connected to the light-emitting elements. For example, each electrode of the light-emitting element is electrically connected to a corresponding pad. For instance, pad PD3 is electrically connected to the positive electrode of light-emitting element QD1, and pad PD1 is electrically connected to the negative electrode of light-emitting element QD1. Pad PD2 is electrically connected to the positive electrode of light-emitting element QD1, and pad PD4 is electrically connected to the negative electrode of light-emitting element QD1. The rest follow the same principle and will not be elaborated further here.

[0110] In specific implementations, in this embodiment of the disclosure, a second insulating layer 320 is formed on the second conductive layer, that is, the second insulating layer 320 is located on the side of the second conductive layer facing away from the substrate 10. Exemplarily, the second insulating layer 320 can be formed as a single-layer structure using inorganic, organic, or organic-inorganic composite materials. Alternatively, the second insulating layer 320 can also be a multilayer structure formed using at least one of inorganic, organic, or organic-inorganic composite materials. For example, the second insulating layer 320 can be formed using multiple layers of organic materials. The second insulating layer 320 can also be formed using multiple layers of inorganic materials. The second insulating layer 320 can also be formed by stacking organic and inorganic materials. Exemplarily, such as... Figure 8a and Figure 8b As shown, the second insulating layer 320 may include an insulating layer 321 and an insulating layer 322. The insulating layer 322 may be made of an organic material, while the insulating layer 321 may be made of an inorganic material.

[0111] For example, the inorganic material may be selected from at least one of silicon nitride (SiNx), silicon oxide (SiOX), silicon oxynitride (SiON), etc. The organic material may be polyimide (PI), etc.

[0112] In some examples, in specific implementations, such as Figures 6 to 8b As shown, at least one of the multiple common voltage lines 210 may include multiple signal segments spaced apart. For example, each common voltage line 210 may include multiple signal segments spaced apart. For instance, a common voltage line 210 may include signal segments 211-1 and 211-2. For instance, within the same common voltage line 210, there is a segment gap between adjacent signal segments, and one segment gap may be located within a light-emitting unit PX.

[0113] In some examples, in specific implementations, such as Figures 6 to 8b As shown, the second conductive layer also includes a plurality of first bridging portions QB1 spaced apart from each other. In the same common voltage line 210, two adjacent signal segments can be electrically connected through the first bridging portions QB1, allowing the signal segments to be electrically connected and transmit signals. For example, signal segments 211-1 and 211-2 can be electrically connected through the first bridging portions QB1. Signal segment 211-2 is electrically connected to the first bridging portion QB1 through a third via GK3, and signal segment 211-1 is electrically connected to the first bridging portion QB1 through a fourth via GK4. Exemplarily, in the same common voltage line 210, two adjacent signal segments can be electrically connected through one, two, three, or more first bridging portions QB1. Of course, the number of first bridging portions QB1 connecting two adjacent signal segments can be designed and determined according to the actual environment, and is not limited here.

[0114] In some examples, in specific implementations, such as Figures 6 to 8b As shown, in the same common voltage line 210, at least one first connecting line 110 is provided at the gap between two adjacent signal line segments. For example, one first connecting line 110 can be provided at the gap between two adjacent signal line segments in the same common voltage line 210. For instance, one first connecting line 110 can be provided at the gap between signal line segments 211-1 and 211-2. Of course, two, three, or more first connecting lines 110 can also be provided at the gap between two adjacent signal line segments in the same common voltage line 210, which can be designed and determined according to the actual environment and is not limited here.

[0115] In some examples, in specific implementations, such as Figures 6 to 8b As shown, at the gap between two adjacent signal segments in the common voltage line 210, the orthographic projection of the first bridging portion QB1 on the substrate 10 overlaps with the orthographic projection of the first connecting line 110 on the substrate 10. This allows the first bridging portion QB1 and the first connecting line 110 to have an overlapping area in a direction perpendicular to the plane of the substrate 10, thereby reducing the amount of extra space occupied by the first connecting line 110.

[0116] In some examples, in specific implementations, such as Figures 6 to 8b As shown, the voltage transmitted on the first bridging section QB1 can be less than the voltage transmitted on the first connecting line 110. For example, if the voltage of the common voltage line 210 can be ground voltage, then the first bridging section QB1 can be ground voltage, for example, 0V. The voltage of the first connecting line 110 can be a positive value, for example, 9V. Of course, in practical applications, the voltages of the common voltage line 210 and the first connecting line 110 can be designed and determined according to the actual application environment, and are not limited here.

[0117] In this embodiment of the disclosure, such as Figure 8a As shown, if the voltage applied to the first connecting line 110 is greater than the voltage applied to the first bridging portion QB1, an electric field exists between the first bridging portion and the first connecting line, which overlap in the orthographic projection of the substrate 10. The direction of this electric field, F02, is from the first conductive layer to the second conductive layer. This prevents the first connecting line 110 from undergoing a reduction reaction as a cathode and also prevents the first bridging portion QB1 from undergoing an oxidation reaction as a positive electrode. Furthermore, the first bridging portion QB1 is protected by a second insulating layer 320, and the intrusion path of water and oxygen is relatively long. Therefore, electrochemical corrosion can be effectively reduced. Especially for... Figure 1b The metal connection wire in segment F shown can effectively reduce electrochemical corrosion.

[0118] In practical applications, the thickness and number of layers of the first insulating layer 310 can be increased to reduce electrochemical corrosion. However, in this embodiment, if the voltage applied to the first connecting line 110 is greater than the voltage applied to the first bridging portion QB1, the electric field direction generated between the first connecting line 110 and the first bridging portion QB1 is F02, pointing from the first connecting line 110 to the first bridging portion QB1, which can effectively reduce electrochemical corrosion. Therefore, it is not necessary to further increase the thickness and number of insulating layers, thus saving production capacity.

[0119] In some examples, in specific implementations, such as Figure 6 and Figure 7 As shown, the first connecting line 110 can extend along the second direction F2. The second conductive layer may further include a first connecting portion BL1 and a second connecting portion BL2 disposed at intervals from each other; wherein, the first end of the first connecting line 110 is electrically connected to the first connecting portion BL1 through a first via GK1, and the second end of the first connecting line 110 is electrically connected to the second connecting portion BL2 through a second via GK2. The first via GK1 and the second via GK2 penetrate the first insulating layer 310. Exemplarily, the orthographic projection of the first connecting portion BL1 on the substrate 10 is located within the orthographic projection of the line segment gap on the substrate 10, and the orthographic projection of the first connecting portion BL1 on the substrate 10 is located at the first end of the orthographic projection of the line segment gap on the substrate 10, and the orthographic projection of the first connecting portion BL1 on the substrate 10 does not overlap with the orthographic projection of the first bridging portion QB1 on the substrate 10. The orthographic projection of the second connecting portion BL2 on the substrate 10 is located within the orthographic projection of the line segment gap on the substrate 10, and the orthographic projection of the second connecting portion BL2 on the substrate 10 is located at the second end of the orthographic projection of the line segment gap on the substrate 10, and the orthographic projection of the second connecting portion BL2 on the substrate 10 does not overlap with the orthographic projection of the first bridging portion QB1 on the substrate 10.

[0120] In some examples, in specific implementations, such as Figure 6 and Figure 7 As shown, the first connection portion BL1 is also electrically connected to one of the plurality of pads (e.g., PD1), and the second connection portion BL2 is also electrically connected to another of the plurality of pads (e.g., PD2). That is, one end of the first connection portion BL1 is electrically connected to one pad (e.g., PD1), and the other end is electrically connected to the first end of the first connecting line. The other end of the second connection portion BL2 is electrically connected to another pad (e.g., PD2), and the other end is electrically connected to the second end of the first connecting line. This allows the light-emitting element QD1 to be connected in series with another light-emitting element QD1 via pad PD1, the first connection portion BL1, the first connecting line 110, the second connection portion BL2, and pad PD2.

[0121] In some examples, in specific implementations, such as Figure 6 and Figure 7 As shown, the orthographic projection of the first connecting line 110 onto the substrate 10 covers the orthographic projection of the first via GK1 onto the substrate 10, and the orthographic projection of the first connecting portion BL1 onto the substrate 10 also covers the orthographic projection of the first via GK1 onto the substrate 10. That is, the size of the first via GK1 cannot exceed the size of the first connecting line 110 where the overlapping area is located, and the size of the first via GK1 also cannot exceed the size of the first connecting portion BL1 where the overlapping area is located. This allows the first connecting line 110 and the first connecting portion BL1 to make contact as close as possible through the first via GK1, thereby improving the reliability of the electrical connection.

[0122] In some examples, in specific implementations, such as Figure 6 and Figure 7 As shown, the width W11 of the area where the first connecting part BL1 covers the first via GK1 in the first direction F1 can be greater than the width W12 of the first connecting line 110 in the first direction F1. This allows the area where the first connecting part BL1 covers the first via GK1 to be not only larger than the area where the first via GK1 is located, but also larger than the area where the first connecting line 110 covers the first via GK1. This ensures that the first connecting part BL1 can make contact with the first connecting line through the first via as much as possible, thereby improving the reliability of the electrical connection.

[0123] In some examples, in specific implementations, such as Figure 7 As shown, the width W30 of the first bridging portion QB1 in the first direction F1 can range from 100 micrometers to 250 micrometers. For example, the width W30 of the first bridging portion QB1 in the first direction F1 can be 100 micrometers. The width W30 of the first bridging portion QB1 in the first direction F1 can also be 150 micrometers. The width W30 of the first bridging portion QB1 in the first direction F1 can also be 200 micrometers. The width W30 of the first bridging portion QB1 in the first direction F1 can also be 250 micrometers. Of course, the specific value of the width W30 of the first bridging portion QB1 in the first direction F1 can be designed and determined according to the actual application environment, and is not limited here.

[0124] In some examples, in specific implementations, such as Figure 7As shown, the width W0 of the first connecting line 110 in the first direction F1 can range from 0.6 micrometers to 2.5 micrometers. For example, the width W0 of the first connecting line 110 in the first direction F1 can be 0.6 micrometers. The width W0 of the first connecting line 110 in the first direction F1 can also be 0.8 micrometers. The width W0 of the first connecting line 110 in the first direction F1 can also be 1.0 micrometer. The width W0 of the first connecting line 110 in the first direction F1 can also be 1.6 micrometers. The width W0 of the first connecting line 110 in the first direction F1 can also be 2.0 micrometers. The width W0 of the first connecting line 110 in the first direction F1 can also be 2.5 micrometers. Of course, the specific value of the width W0 of the first connecting line 110 in the first direction F1 can be designed and determined according to the actual application environment, and is not limited here.

[0125] In some examples, in specific implementations, such as Figure 7 As shown, the width W40 of the gap between the first connecting line 110 and the signal line segment in the first direction F1 can range from 20 micrometers to 50 micrometers. For example, the width W40 of the gap between the first connecting line 110 and the signal line segment in the first direction F1 can be 20 micrometers. The width W40 of the gap between the first connecting line 110 and the signal line segment in the first direction F1 can also be 25 micrometers. The width W40 of the gap between the first connecting line 110 and the signal line segment in the first direction F1 can also be 30 micrometers. The width W40 of the gap between the first connecting line 110 and the signal line segment in the first direction F1 can also be 35 micrometers. The width W40 of the gap between the first connecting line 110 and the signal line segment in the first direction F1 can also be 40 micrometers. The width W40 of the gap between the first connecting line 110 and the signal line segment in the first direction F1 can also be 50 micrometers. Of course, the specific value of the width of the gap between the first connecting line 110 and the signal line segment in the first direction F1 can be designed and determined according to the actual application environment, and is not limited here.

[0126] In some examples, in specific implementations, such as Figures 6 to 8a As shown, the orthographic projection of the first connecting line 110 onto the substrate 10 overlaps the orthographic projection of the second via GK2 onto the substrate 10, and the orthographic projection of the second connecting portion BL2 onto the substrate 10 overlaps the orthographic projection of the second via GK2 onto the substrate 10. That is, the size of the second via GK2 cannot exceed the size of the first connecting line 110 where the overlapping area is located, and the size of the second via GK2 cannot exceed the size of the second connecting portion BL2 where the overlapping area is located. This allows the first connecting line 110 and the second connecting portion BL2 to make contact as close as possible through the second via GK2, thereby improving the reliability of the electrical connection.

[0127] In some examples, in specific implementations, such as Figures 6 to 8a As shown, the width W21 of the area where the second connecting part BL2 covers the second via GK2 in the first direction F1 is greater than the width of the first connecting line 110 in the first direction F1. This allows the area where the second connecting part BL2 covers the second via GK2 to be not only larger than the area where the second via GK2 is located, but also larger than the area where the first connecting line 110 covers the second via GK2. This allows the second connecting part BL2 to contact the first connecting line through the second via as much as possible, thereby improving the reliability of the electrical connection.

[0128] In some examples, in specific implementations, such as Figure 7 and Figure 8b As shown, the length of the first connecting line 110 in the second direction F2 can be greater than the length of the first bridging portion QB1 in the second direction F2. This allows the first via GK1 and the second via GK2 to be located on both sides of the first bridging portion QB1, and the first via GK1 and the second via GK2 do not overlap with the first bridging portion QB1, reducing the possibility that the first bridging portion QB1 is short-circuited to the first connecting line 110 through the first via GK1 and the second via GK2.

[0129] In some examples, as shown in Figure 7, the first bridging portion QB1 has a planar structure, and a first gap exists between the first bridging portion QB1 and the first connecting portion BL1 on one side. The width X1 of the first gap can range from 20 micrometers to 50 micrometers. For example, the width X1 of the first gap can be 20 micrometers. The width X1 of the first gap can also be 30 micrometers. The width X1 of the first gap can also be 40 micrometers. The width X1 of the first gap can also be 50 micrometers. Of course, in practical applications, the specific value of the width X1 of the first gap can be designed and determined according to the actual application environment, and is not limited here.

[0130] In some examples, as shown in Figure 7, the first bridging portion QB1 has a planar structure, and a second gap exists between the first bridging portion QB1 and the second connecting portion BL2 on one side. The width X2 of the second gap can range from 20 micrometers to 50 micrometers. For example, the width X2 of the second gap can be 20 micrometers. The width X2 of the second gap can also be 30 micrometers. The width X2 of the second gap can also be 40 micrometers. The width X2 of the second gap can also be 50 micrometers. Of course, in practical applications, the specific value of the width X2 of the second gap can be designed and determined according to the actual application environment, and is not limited here.

[0131] In some examples, in practice, the width X1 of the first gap and the width X2 of the second gap can be made approximately equal.

[0132] In some examples, in specific implementations, the thickness of the first bridging portion QB1 can be equal to the thickness of other structures in the second conductive layer in the direction perpendicular to the plane of the substrate 10. For example, the thickness of the first bridging portion QB1 can be equal to the thickness of the first connection portion and the second connection portion. Exemplarily, the thickness of the first bridging portion QB1 can be equal to the thickness of the first connection portion BL1 and the thickness of the second connection portion BL2. In this way, when fabricating the second conductive layer, a Cu film layer can be coated on the entire surface of the substrate 10, and then the Cu film layer can be patterned by a patterning process, which can simultaneously form the patterns of the first bridging portion QB1, the first connection portion BL1, the second connection portion BL2, the cascaded traces 240, and other structures in the second conductive layer.

[0133] In some examples, in specific implementations, the thickness of the first bridging portion QB1 can be greater than the thickness of other structures in the second conductive layer in the direction perpendicular to the plane of the substrate 10. By increasing the thickness of the first bridging portion QB1, the resistance of the first bridging portion QB1 can be reduced. For example, the thickness of the first bridging portion QB1 is greater than the thickness of the first connection portion and the second connection portion. Exemplarily, when preparing the second conductive layer, a Cu film layer can be coated on the entire surface of the substrate 10, and then the Cu film layer can be patterned by a patterning process to simultaneously form the first film layer of the first bridging portion QB1, the first connection portion BL1, the second connection portion BL2, the cascaded trace 240, and the patterns of other structures in the second conductive layer. Then, one or more film layers are formed on the first film layer of the first bridging portion QB1 using a patterning process so that these film layers form the first bridging portion QB1. Alternatively, a Cu film layer can be coated on the entire surface of the substrate 10, and then the Cu film layer can be patterned using a patterning process on a grayscale mask. This can simultaneously form the first bridging portion QB1, the first connecting portion BL1, the second connecting portion BL2, the cascaded trace 240, and other structures in the second conductive layer, and make the thickness of the first bridging portion QB1 greater than the thickness of the other structures in the second conductive layer.

[0134] In some examples, in specific implementations, at least two light-emitting elements QD1 in the same light-emitting unit PX are electrically connected via a first connecting line 110. Exemplarily, one light-emitting element QD1 is electrically connected to another light-emitting element QD1 via a first connecting portion BL1. For example, the first connecting portion BL1 is electrically connected to the negative electrode of one light-emitting element QD1 and to the first end of the first connecting line 110. A second connecting portion BL2 is electrically connected to the positive electrode of the other light-emitting element QD1 and to the second end of the first connecting line 110. This allows one light-emitting element QD1 to be connected in series with another light-emitting element QD1 via the first connecting portion BL1.

[0135] In some examples, during specific implementation, such as Figure 3 shown, multiple light-emitting elements QD1 in the light-emitting unit PX can be divided into M element groups, and each element group includes N light-emitting elements QD1 arranged along the first direction F1; the M element groups are arranged along the second direction F2. Here, N is an integer greater than 0, and M is an integer greater than 0. Exemplarily, taking the light-emitting unit PX including 9 light-emitting elements QD1 as an example, M = 3 and N = 3 can be set. That is, these 9 light-emitting elements QD1 are divided into 3 element groups Z-1, Z-2, and Z-3. The element groups Z-1, Z-2, and Z-3 are arranged along the second direction F2. Moreover, there are 3 light-emitting elements QD1 arranged along the first direction F1 in the element group Z-1, 3 light-emitting elements QD1 arranged along the first direction F1 in the element group Z-2, and 3 light-emitting elements QD1 arranged along the first direction F1 in the element group Z-3.

[0136] In some examples, during specific implementation, such as Figure 3 As with Figure 6 and Figure 7 shown, in the same light-emitting unit PX, at least two element groups are electrically connected through the first connection line 110. Exemplarily, in the order from the drive voltage terminal to the output terminal, the multiple element groups are numbered in sequence; the first light-emitting element QD1 in the element group numbered 1 is electrically connected to the drive voltage terminal; the first light-emitting element QD1 in the element group numbered k is electrically connected to the first light-emitting element QD1 in the element group numbered k + 1 through the first connection line 110; the last first light-emitting element QD1 in the element group numbered M is electrically connected to the output terminal; 1 < k < M and k is an integer. For example, taking the light-emitting unit PX including 9 light-emitting elements QD1 as an example, M = 3, N = 3, and k = 2 can be set. The element group numbered 1 is Z-1, the element group numbered 2 is Z-2, and the element group numbered 3 is Z-3. The first light-emitting element QD1 in the element group numbered 1 is electrically connected to the drive voltage terminal, and the last light-emitting element QD1 in the element group numbered 1 is electrically connected to the last light-emitting element QD1 in the element group Z-2 numbered 2. The first light-emitting element QD1 in the element group Z-2 numbered 2 is electrically connected to the first light-emitting element QD1 in the element group Z-3 numbered 3 through the first connection line 110. The last first light-emitting element QD1 in the element group Z-3 numbered 3 is electrically connected to the output terminal.

[0137] In some examples, during specific implementation, such as Figure 3 As with Figure 6As shown, the second conductive layer may further include multiple series traces 250 spaced apart; the light-emitting elements QD1 in the same element group are connected in series through the series traces 250. Exemplarily, the light-emitting element QD1 is electrically connected to the pad, and the pad is electrically connected to the series trace 250, so that the light-emitting elements QD1 in the same element group are electrically connected through the pad and the series trace 250.

[0138] In some examples, in specific implementations, such as Figure 3 and Figure 6 As shown, the last light-emitting element QD1 in element group k-1 is electrically connected to the last light-emitting element QD1 in element group k via the first connecting line 110. For example, taking a light-emitting unit PX comprising 9 light-emitting elements QD1, M=3, N=3, and k=2. In element group Z-1 (numbered 1), the first light-emitting element QD1 and the second light-emitting element QD1 are connected in series via a series trace 250, and the second light-emitting element QD1 and the third light-emitting element QD1 are connected in series via a series trace 250. In element group Z-2 (numbered 2), the first light-emitting element QD1 and the second light-emitting element QD1 are connected in series via a series trace 250, and the second light-emitting element QD1 and the third light-emitting element QD1 are connected in series via a series trace 250. In component group Z-3 (numbered 3), the first and second light-emitting elements QD1 are connected in series via a series trace 250, and the second and third light-emitting elements QD1 are also connected in series via a series trace 250. The last light-emitting element QD1 in component group Z-1 (numbered 1) is connected in series with the last light-emitting element QD1 in component group Z-2 (numbered 2) via a series trace 250.

[0139] In some examples, in specific implementations, such as Figure 6 As shown, the orthographic projection of the common voltage line 210 onto the substrate 10 does not overlap with the orthographic projection of the series trace 250 onto the substrate 10. This avoids the formation of a direct electric field between the common voltage line 210 and the series trace 250.

[0140] In some examples, in specific implementations, such as Figure 3 and Figure 6 As shown, for a column of light-emitting units PX, there are: a common voltage line 210, a source voltage line 230, and a driving voltage line 220. A driving voltage line 220 is set between component group Z-1 (numbered 1) and component group Z-2 (numbered 2). A common voltage line 210 is set between component group Z-2 (numbered 2) and component group Z-3 (numbered 3). A source voltage line 230 is set between component group Z-3 (numbered 3) and component group Z-1 (numbered 1) in the adjacent light-emitting unit PX.

[0141] In specific implementation, as described in the embodiments of this disclosure, Figure 6 and Figure 7 As shown, the orthographic projection of the pad on the substrate does not overlap with the orthographic projection of the common voltage line 210 on the substrate.

[0142] In some examples, in specific implementations, such as Figure 3 and Figure 6 As shown, the common voltage line 210 has avoidance areas on both sides, and the pads on both sides of the common voltage line 210 are located within these avoidance areas. For example, the pads for the electrical connection of the light-emitting element QD1 in component group Z-2 (numbered 2) are located in the avoidance area on the side of the common voltage line 210 facing the driving voltage line 220, while the pads for the electrical connection of the light-emitting element QD1 in component group Z-3 (numbered 3) are located in the avoidance area on the side of the common voltage line 210 away from the driving voltage line 220. In other words, the orthographic projection of the common voltage line 210 onto the substrate does not overlap with the orthographic projections of the pads for the electrical connection of the light-emitting element QD1 in component group Z-2 and component group Z-3 (numbered 3).

[0143] In some examples, in specific implementations, such as Figure 9 As shown, the fan-out area FO can also include multiple light-emitting units PX to increase the light-emitting area. It should be noted that the common voltage terminal in the light-emitting unit PX is electrically connected to the first fan-out line, and the implementation of the light-emitting unit PX in the fan-out area FO can be basically the same as the implementation of the light-emitting unit PX in the display area. That is, the specific implementation of the light-emitting unit PX in the fan-out area FO can be found in the above-mentioned implementation of the light-emitting unit PX in the display area, and will not be repeated here.

[0144] In some examples, in specific implementations, such as Figure 9 As shown, the first conductive layer may further include a plurality of first fan-out lines and a plurality of second connecting lines 112 spaced apart, the plurality of first fan-out lines and the plurality of second connecting lines 112 being located in the fan-out region FO. A common voltage line 210 is electrically connected to one of the first fan-out lines. Furthermore, at least one first fan-out line includes a first sub-fan-out line 511 and a second sub-fan-out line 512. The first sub-fan-out line 511 extends along a first direction F1, and the second sub-fan-out line 512 extends along a second direction F2. The first sub-fan-out line 511 and the second sub-fan-out line 512 are electrically connected to each other to form a first fan-out line. That is, the first fan-out line has a right-angled portion.

[0145] In some examples, in specific implementations, such as Figure 9As shown, the second conductive layer may further include a plurality of second bridging portions QB2 arranged at intervals. Furthermore, the plurality of second bridging portions QB2 are located in the fan-out region FO. The first sub-fan-out line 511 includes a plurality of first fan-out line segments arranged at intervals. In the same first sub-fan-out line 511, two adjacent first fan-out line segments are electrically connected through the second bridging portions QB2. For example, first fan-out line segments 511-1 and 511-2 are electrically connected through the second bridging portions QB2. Furthermore, in the same first sub-fan-out line 511, at least one second connecting line 112 is provided at the gap between two adjacent first fan-out line segments. And, at the gap between two adjacent first fan-out line segments in the first sub-fan-out line 511, the orthographic projection of the second bridging portion QB2 on the substrate 10 overlaps with the orthographic projection of the second connecting line 112 on the substrate 10. Exemplarily, in at least one light-emitting unit PX, at least two light-emitting elements QD1 are electrically connected through the second connecting line 112.

[0146] It should be noted that both the first sub-fan output line 511 and the common voltage line 210 extend along the first direction F1. The implementation principle of the second connecting line 112 and the second bridging part QB2 is basically the same as that of the first connecting line 110 and the first bridging part QB1. Therefore, the implementation of the second connecting line 112 and the second bridging part QB2 can be basically the same as that of the first connecting line 110 and the first bridging part QB1. That is, the specific implementation of the second connecting line 112 and the second bridging part QB2 can be found in the above-described implementation of the first connecting line 110 and the first bridging part QB1, and will not be elaborated here.

[0147] In some examples, in specific implementations, such as Figure 9 As shown, the first conductive layer may further include multiple third connecting lines 113. In at least one light-emitting unit PX, at least two light-emitting elements QD1 are electrically connected via the third connecting lines 113. Exemplarily, some light-emitting elements QD1 in the same element group are connected in series via the third connecting lines 113. For example, the second light-emitting element QD1 in element group Z-1 (numbered 1) is connected in series with the third light-emitting element QD1 via a third connecting line 113. The second light-emitting element QD1 in element group Z-2 (numbered 2) is connected in series with the third light-emitting element QD1 via a third connecting line 113.

[0148] In some examples, in specific implementations, such as Figure 9As shown, the second conductive layer also includes a plurality of third bridging portions QB3 located in the fan-out region FO. The second sub-fan-out line 512 includes a plurality of spaced-apart second fan-out line segments. In the same second sub-fan-out line 512, two adjacent second fan-out line segments are electrically connected by the third bridging portions QB3, and in the same second sub-fan-out line 512, at least one third connecting line 113 is provided at the gap between two adjacent second fan-out line segments. And at the gap between two adjacent second fan-out line segments in the second sub-fan-out line 512, the orthographic projection of the third bridging portion QB3 on the substrate 10 overlaps with the orthographic projection of the third connecting line 113 on the substrate 10.

[0149] It should be noted that the second sub-fan output line 512 is arranged perpendicularly to the common voltage line 210. Therefore, the implementation principle after rotating the first connecting line 110 and the first bridging part QB1 by 90 degrees is basically the same as the implementation principle of the third connecting line 113 and the third bridging part QB3. Therefore, the implementation of the third connecting line 113 and the third bridging part QB3 can be implemented by rotating the first connecting line 110 and the first bridging part QB1 by 90 degrees. That is, the specific implementation of the third connecting line 113 and the third bridging part QB3 can also refer to the above-described implementation of the first connecting line 110 and the first bridging part QB1, and will not be repeated here.

[0150] Based on the same disclosed concept, this disclosure also provides a display device, including the light-emitting substrate described above. The principle by which this display device solves the problem is similar to that of the aforementioned light-emitting substrate; therefore, the implementation of this display device can refer to the implementation of the aforementioned light-emitting substrate, and the repetitions will not be repeated here.

[0151] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0152] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A light-emitting substrate, comprising: Substrate; A first conductive layer is located on the substrate; wherein the first conductive layer includes a plurality of common voltage lines and a plurality of first connection lines arranged at intervals between each other; the plurality of common voltage lines extend along a first direction and are arranged along a second direction; The first insulating layer is located on the side of the first conductive layer that is away from the substrate. A second conductive layer is located on the side of the first insulating layer away from the substrate; wherein the second conductive layer includes a plurality of first bridging portions spaced apart from each other; Among them, at least one of the multiple common voltage lines includes multiple signal segments arranged at intervals; in the same common voltage line, two adjacent signal segments are electrically connected through the first bridging part and at least one first connecting line is provided at the segment gap between two adjacent signal segments; At the gap between two adjacent signal segments in the common voltage line, the first bridging portion overlaps with the orthographic projection of the first connecting line on the substrate.

2. The light emitting substrate of claim 1, wherein, An electric field exists between the first bridging portion and the first connecting line, where the orthographic projections of the substrate overlap, and the direction of the electric field is from the first conductive layer to the second conductive layer.

3. The light emitting substrate of claim 1, wherein, The second conductive layer further includes a first connecting portion and a second connecting portion that are spaced apart from each other; The first end of the first connecting line is electrically connected to the first connecting part through the first via, and the second end of the first connecting line is electrically connected to the second connecting part through the second via; wherein the first via and the second via penetrate the first insulating layer.

4. The light emitting substrate of claim 3, wherein, The orthographic projection of the first connecting line on the substrate covers the orthographic projection of the first via on the substrate, and the orthographic projection of the first connecting portion on the substrate covers the orthographic projection of the first via on the substrate. The orthographic projection of the first connecting line on the substrate covers the orthographic projection of the second via on the substrate, and the orthographic projection of the second connecting portion on the substrate covers the orthographic projection of the second via on the substrate.

5. The light emitting substrate of claim 4, wherein, The width of the area of ​​the first connecting portion covering the first via in the first direction is greater than the width of the first connecting line in the first direction; The width of the area of ​​the second connecting portion covering the second via in the first direction is greater than the width of the first connecting line in the first direction.

6. The light emitting substrate of claim 5, wherein, The width of the first bridging portion in the first direction ranges from 100 micrometers to 250 micrometers, and the width of the first connecting line in the first direction ranges from 0.6 micrometers to 2.5 micrometers.

7. The light emitting substrate of claim 3, wherein, The length of the first connecting line in the second direction is greater than the length of the first bridging portion in the second direction.

8. The light emitting substrate of claim 7, wherein, The first bridging portion extends to one side of the first connecting portion and has a first gap with the first connecting portion, and the first bridging portion extends to one side of the second connecting portion and has a second gap with the second connecting portion; The width of the first gap and the width of the second gap are both in the range of 20 micrometers to 50 micrometers.

9. The light emitting substrate of claim 3, wherein, The width of the gap between the first connection line and the signal line segment in the first direction ranges from 20 micrometers to 50 micrometers.

10. The light emitting substrate of any of claims 1-9, wherein, In a direction perpendicular to the plane of the substrate, the thickness of the first bridging portion is greater than or equal to the thicknesses of the first connection portion and the second connection portion in the second conductive layer.

11. The light emitting substrate of any of claims 3-9, wherein, The second conductive layer further includes a plurality of pads; One end of the first connection portion is electrically connected to one of the pads, and the other end is electrically connected to the first end of the first connection line; The other end of the second connection portion is electrically connected to another one of the pads, and the other end is electrically connected to the second end of the first connection line.

12. The light emitting substrate of claim 11, wherein, The plurality of common voltage lines are located in the display area; the display area further includes a plurality of light-emitting units, and each light-emitting unit includes a driving circuit and a plurality of light-emitting elements; wherein, the driving circuit includes a common voltage terminal and an output terminal; the plurality of light-emitting elements are sequentially connected in series between the driving voltage terminal and the output terminal; the common voltage terminal is electrically connected to the common voltage line; the pad is electrically connected to at least one of the light-emitting elements and the driving circuit; The plurality of light-emitting elements in the light-emitting unit are divided into M element groups, and each element group includes N light-emitting elements arranged along the first direction; the M element groups are arranged along the second direction; N is an integer greater than 0, and M is an integer greater than 0; In the order from the driving voltage terminal to the output terminal, the plurality of element groups are sequentially numbered; The first light-emitting element in the element group numbered 1 is electrically connected to the driving voltage terminal; The first light-emitting element in the element group numbered k is electrically connected to the first light-emitting element in the element group numbered k + 1 through the first connection line; wherein, 1 < k < M and k is an integer; The last first light-emitting element in the element group numbered M is electrically connected to the output terminal; One column of light-emitting units corresponds to one common voltage line, and the common voltage line is located between the element group numbered k and the element group numbered k + 1 in the corresponding column of light-emitting units.

13. The light-emitting substrate as claimed in claim 12, wherein, The second conductive layer further includes a plurality of series traces arranged at intervals; the light-emitting elements in the same element group are connected in series through the series traces, and the last light-emitting element in the element group numbered k - 1 is electrically connected to the last light-emitting element in the element group numbered k through the series traces; The orthographic projection of the common voltage line on the substrate does not overlap with the orthographic projection of the series trace on the substrate.

14. The light-emitting substrate according to any one of claims 1-9, wherein, The light-emitting substrate further includes a fan-out area; The first conductive layer further includes a plurality of first fan-out lines and a plurality of second connection lines located in the fan-out area; wherein, one common voltage line is electrically connected to one first fan-out line; the first fan-out line includes a first sub-fan-out line and a second sub-fan-out line; the first sub-fan-out line extends along the first direction, and the second sub-fan-out line extends along the second direction; The second conductive layer further includes a plurality of second bridging portions located in the fan-out area; The first sub-fan-out line includes a plurality of first fan-out line segments arranged at intervals; in the same first sub-fan-out line, two adjacent first fan-out line segments are electrically connected through the second bridging part and at least one second connecting line is provided in the gap between two adjacent first fan-out line segments. At the gap between two adjacent first fan-out line segments in the first sub-fan-out line, the second bridging portion overlaps with the orthographic projection of the second connecting line on the substrate.

15. The light-emitting substrate as claimed in claim 14, wherein, The first conductive layer also includes multiple third connecting lines; The second conductive layer also includes a plurality of third bridging portions located in the fan-out region; The second sub-fan-out line includes a plurality of spaced second fan-out line segments; in the same second sub-fan-out line, two adjacent second fan-out line segments are electrically connected through the third bridging part and at least one third connecting line is provided in the gap between two adjacent second fan-out line segments; At the gap between two adjacent second fan-out line segments in the second sub-fan-out line, the third bridging portion overlaps with the orthographic projection of the third connecting line on the substrate.

16. The light-emitting substrate as claimed in claim 15, wherein, The fan-out area includes multiple light-emitting units, each light-emitting unit including a driving circuit and multiple light-emitting elements; wherein, the driving circuit includes a common voltage terminal and an output terminal; the multiple light-emitting elements are connected in series between the driving voltage terminal and the output terminal. The common voltage terminal is electrically connected to the first fan-out line; In at least one of the light-emitting units, at least two of the light-emitting elements are electrically connected via the second connecting line; and / or, at least two of the light-emitting elements are electrically connected via the third connecting line.

17. A display device comprising a light-emitting substrate as described in any one of claims 1-16.

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