A dependency detection method and device for a RISC-V matrix operation instruction

Abstract

Embodiments of the present application disclose a method and device for dependency detection of RISC-V matrix operation instructions. Embodiments of the present application obtain a to-be-transmitted instruction, the to-be-transmitted instruction being used for operating a first slice of a two-dimensional register corresponding to the to-be-transmitted instruction; obtain entry information of the to-be-transmitted instruction in a dependency detection queue; obtain entry information of other instructions arranged in front of the entry information in the dependency detection queue, wherein the other instructions are used for operating a second slice of a two-dimensional register corresponding to the other instructions; and determine, according to the entry information and the entry information, that the first slice and the second slice are irrelevant, and instruct to transmit the to-be-transmitted instruction. Through the above method, the data dependency of the two-dimensional register can be reduced, the waiting time of the matrix operation instruction can be reduced, and the performance of the CPU can be improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and specifically to a method and apparatus for dependency detection of RISC-V matrix operation instructions. Background Technology

[0002] The fifth-generation Reduced Instruction Set Computer (RISC-V) combines the advantages of x86 and ARM instruction sets. RISC-V features simple instructions, fewer instruction lines, smaller code size, and lower power consumption. As a result, RISC-V is becoming increasingly widely used. Under these circumstances, the pipeline design of the CPU will affect the processing efficiency of RISC-V.

[0003] In existing technologies, CPU pipeline design can encounter structural hazards, data hazards, and control hazards. Data hazards arise when multiple concurrently executed instructions have data dependencies. These instructions can be scalar operation instructions, vector operation instructions, or matrix operation instructions. Scalar operation instructions correspond to scalar registers, vector operation instructions to vector registers, and matrix operation instructions to two-dimensional registers. The pipelines for these instructions can be merged. When data hazards exist, a pipeline pause is typically used, inserting a No-Operation (NOP) operation before the execution of the next instruction. The two-dimensional register comprises multiple rows and columns, storing a large amount of data. Some rows or columns may not have data dependencies on other instructions, while others may. Therefore, if the two-dimensional register is treated as a whole for data dependency detection, multiple pipeline pauses may be required to resolve the data dependencies, leading to longer waiting times, impacting the execution efficiency of matrix operation instructions, and ultimately affecting CPU performance.

[0004] In summary, how to resolve the data dependency of two-dimensional registers, reduce the waiting time of matrix operation instructions, and improve CPU performance are the problems that need to be solved. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a dependency detection method and apparatus for RISC-V matrix operation instructions, which can reduce data dependencies of two-dimensional registers, reduce the waiting time of matrix operation instructions, and improve CPU performance.

[0006] In a first aspect, embodiments of the present invention provide a dependency detection method for RISC-V matrix operation instructions, the method comprising:

[0007] Obtain the instruction to be transmitted, which is used to operate on the first slice of the two-dimensional register corresponding to the instruction to be transmitted;

[0008] The entry information of the instruction to be launched is obtained from the dependency detection queue, wherein the entry information of the instruction to be launched includes the register information of the two-dimensional register corresponding to the instruction to be launched and the slice information of the first slice;

[0009] The entry information of other instructions ordered before the entry information of the instruction to be issued is obtained from the dependency detection queue. The other instructions are used to operate on the second slice of the two-dimensional register corresponding to the other instructions. The entry information of the other instructions includes the register information of the two-dimensional register corresponding to the other instructions and the slice information of the second slice.

[0010] Based on the entry information of the command to be launched and the entry information of the other commands, it is determined that the first slice and the second slice are unrelated, and the command to be launched is instructed to be launched.

[0011] Optionally, determining that the first slice and the second slice are unrelated specifically includes:

[0012] Based on the register information of the two-dimensional registers corresponding to the instruction to be transmitted and the other instructions, the source register information of the instruction to be transmitted and the destination register information of the other instructions are determined.

[0013] In response to the fact that the source register information of the instruction to be transmitted is the same as the destination register information of the other instructions, it is determined that the slice information of the first slice is different from the slice information of the second slice.

[0014] Optionally, determining that the first slice and the second slice are unrelated specifically includes:

[0015] Based on the register information of the two-dimensional registers corresponding to the instruction to be transmitted and the other instructions, the destination register information of the instruction to be transmitted, as well as the source register information and destination register information of the other instructions, are determined.

[0016] In response to the fact that the destination register information of the instruction to be transmitted is the same as the source register information or destination register information of the other instructions, it is determined that the slice information of the first slice is different from the slice information of the second slice.

[0017] Optionally, the slicing information includes: slicing operation direction and slicing range;

[0018] Determining that the slice information of the first slice is different from the slice information of the second slice includes:

[0019] It is determined that the slicing operation directions of the first slice and the second slice are the same, and the slice intervals do not overlap.

[0020] Optionally, the slice interval includes: the slice starting index and the number of slice rows or columns.

[0021] Optionally, before obtaining the entry information of the instruction to be emitted from the dependency detection queue, the method further includes:

[0022] The command to be launched is decoded;

[0023] In response to the source register or destination register of the instruction to be transmitted being a two-dimensional register, the entry information of the instruction to be transmitted is written to the tail of the dependency detection queue.

[0024] Optionally, the entry information of the command to be launched may also include the sequence number of the command to be launched, and the method may further include:

[0025] Add the serial number from the entry information of the command to be launched to the command to be launched.

[0026] Optionally, the method further includes:

[0027] When the instruction to be issued is moved to the head of the reorder cache ROB, the entry information of the instruction to be issued is deleted from the dependency detection queue.

[0028] Optionally, the method further includes:

[0029] Delete all file entries in the dependency detection queue whose sequence number is less than the sequence number corresponding to the instruction to be launched.

[0030] Optionally, the method further includes:

[0031] In response to receiving a pipeline refresh command, all file entries in the dependency detection queue with sequence numbers greater than the sequence number corresponding to the command to be launched are deleted.

[0032] In a second aspect, embodiments of the present invention provide a dependency detection device for RISC-V matrix operation instructions, the device comprising a dependency detection queue, a correlation detection module, and at least one emitter slot;

[0033] The dependency detection queue is used to store entry information of the instruction to be launched and other instructions; the entry information of the other instructions is ordered in the dependency detection queue before the entry information of the instruction to be launched; the instruction to be launched is used to operate on the first slice of the two-dimensional register corresponding to the instruction to be launched, and the other instructions are used to operate on the second slice of the two-dimensional register corresponding to the other instructions; the entry information of the instruction to be launched includes the register information of the two-dimensional register corresponding to the instruction to be launched and the slice information of the first slice, and the entry information of the other instructions includes the register information of the two-dimensional register corresponding to the other instructions and the slice information of the second slice;

[0034] The at least one launch slot is used to store the command to be launched and the other commands;

[0035] The correlation detection module is used to determine the correlation between the first slice and the second slice based on the entry information of the instruction to be launched and the entry information of the other instructions.

[0036] Thirdly, embodiments of the present invention provide computer program instructions that, when executed by a processor, implement the method as described in the first aspect or any one of the possible methods described in the first aspect.

[0037] Fourthly, embodiments of the present invention provide a computer-readable storage medium having storage thereon.

[0038] The computer program instructions, when executed by a processor, implement the method as described in the first aspect or any one of the possibilities of the first aspect.

[0039] Fifthly, embodiments of the present invention provide a chip including a memory and a processing core, the memory being used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processing core to implement the method as described in the first aspect or any one of the possible methods of the first aspect.

[0040] Sixthly, embodiments of the present invention provide a board card, the board card including the chip described in the fifth aspect.

[0041] In a seventh aspect, embodiments of the present invention provide a server, the server including the board from the sixth aspect.

[0042] This invention, through its embodiments, acquires a pending instruction, which operates on a first slice of a two-dimensional register corresponding to the pending instruction; retrieves entry information of the pending instruction from a dependency detection queue, wherein the entry information of the pending instruction includes register information of the two-dimensional register corresponding to the pending instruction and slice information of the first slice; retrieves entry information of other instructions ordered before the entry information of the pending instruction from the dependency detection queue, wherein the other instructions operate on a second slice of a two-dimensional register corresponding to the other instructions, and the entry information of the other instructions includes register information of the two-dimensional register corresponding to the other instructions and slice information of the second slice; based on the entry information of the pending instruction and the entry information of the other instructions, it is determined that the first slice and the second slice are unrelated, and the pending instruction is instructed to be launched. This method reduces the data dependency of the two-dimensional register, reduces the waiting time of matrix operation instructions, and improves CPU performance. Attached Figure Description

[0043] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0044] Figure 1 This is a schematic diagram of an existing production line.

[0045] Figure 2 This is a flowchart of a dependency detection method for RISC-V matrix operation instructions according to an embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of a two-dimensional register according to an embodiment of the present invention;

[0047] Figure 4 This is another schematic diagram of a two-dimensional register according to an embodiment of the present invention;

[0048] Figure 5 This is another schematic diagram of a two-dimensional register according to an embodiment of the present invention;

[0049] Figure 6 This is another schematic diagram of a two-dimensional register according to an embodiment of the present invention;

[0050] Figure 7 This is a schematic diagram of a two-dimensional register according to an embodiment of the present invention;

[0051] Figure 8 This is another schematic diagram of a two-dimensional register according to an embodiment of the present invention;

[0052] Figure 9 This is another schematic diagram of a two-dimensional register according to an embodiment of the present invention;

[0053] Figure 10 This is another schematic diagram of a two-dimensional register according to an embodiment of the present invention;

[0054] Figure 11 This is a schematic diagram of a two-dimensional register according to an embodiment of the present invention;

[0055] Figure 12 This is another schematic diagram of a two-dimensional register according to an embodiment of the present invention;

[0056] Figure 13 This is another schematic diagram of a two-dimensional register according to an embodiment of the present invention;

[0057] Figure 14 This is another schematic diagram of a two-dimensional register according to an embodiment of the present invention;

[0058] Figure 15 This is a flowchart of another dependency detection method for RISC-V matrix operation instructions according to an embodiment of the present invention;

[0059] Figure 16 This is a schematic diagram of an assembly line according to an embodiment of the present invention;

[0060] Figure 17 This is a schematic diagram of a dependency detection device for RISC-V matrix operation instructions according to an embodiment of the present invention. Detailed Implementation

[0061] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0062] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0063] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0064] In the description disclosed in this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description disclosed in this invention, unless otherwise stated, "a plurality of" means two or more.

[0065] In the prior art, there are structural hazards, data hazards, and control hazards in the pipeline design of CPUs. Among them, the data hazards are the data dependencies between multiple instructions that are executed at the same time. The data dependencies are divided into three cases: read-after-write (RAW), read-after-write (WAR), and write-after-write (WAW).

[0066] Specifically, a concrete example of RAW is as follows:

[0067] Load R2, (R1)

[0068] Add R3, R4, R2

[0069] The above-mentioned load instruction loads data from address (R1) and writes it to register R2. Then the add instruction reads data from register R4 and register R2, adds them together, and writes them to register R3. The source registers R2 and R4 of the above-mentioned add instruction include the destination register R2 of the load instruction. The load instruction and the add instruction have a data dependency relationship, that is, the add instruction must wait for the load instruction to complete before it can be executed.

[0070] A specific example of the WAR is as follows:

[0071] Add R3, R4, R2

[0072] Load R2, (R1)

[0073] In this instruction, the add instruction reads data from registers R4 and R2, adds them together, and writes the sum to register R3. Then, the load instruction loads data from address (R1) and writes it to register R2. The destination register R2 of the load instruction is the same as the source register R2 of the add instruction. If the load instruction is executed before the add instruction, the result of the operation will be incorrect. Therefore, there is a data dependency between the add and load instructions. The load instruction must wait for the add instruction to complete before it can be executed.

[0074] A specific example of the WAW is as follows:

[0075] sub R3, R5, R4

[0076] Add R3, R4, R2

[0077] The above-mentioned sub instruction reads the values ​​from registers R5 and R4, then subtracts the read values ​​and writes the result to register R3; the add instruction reads data from registers R4 and R2, adds them, and writes the result to register R3; the destination register R3 of the above-mentioned add instruction is the same as the destination register R3 of the sub instruction. If the sub instruction and the above-mentioned add instruction are executed out of order, if the add instruction may be executed before the sub instruction, it will cause the final result in register R3 to be incorrect, that is, a data conflict will occur.

[0078] In existing technology, the instructions can be scalar operation instructions, vector operation instructions, and matrix operation instructions. The scalar operation instructions correspond to scalar registers, the vector operation instructions correspond to vector registers, and the matrix operation instructions correspond to two-dimensional registers. The pipelines of these scalar operation instructions, vector operation instructions, and matrix operation instructions can be integrated. When a data hazard exists, a pipeline pause is generally used, inserting a No-Operation (NOP) operation before the execution of the next instruction. This NOP is a no-op, meaning it does nothing. After the NOP operation, it is ensured that the previous instruction has completed execution before the next instruction can begin execution. For example, as... Figure 1 The illustrated 5-stage pipeline's instruction processing stages include fetch (IF), decode (ID), execute (EX), memory access (MEM), and write-back (WB). To resolve data hazards, a no-op (NOP) is inserted before the execution (EX) of the third instruction, and two NOPs are inserted before the execution (EX) of the pipeline corresponding to the fourth instruction. The two-dimensional register comprises multiple rows and columns, storing a large amount of data. Some rows or columns may not have data dependencies on other instructions, while others may. Therefore, performing data dependency detection on the two-dimensional register as a whole may require multiple pipeline pauses to resolve inter-instruction data dependencies, leading to longer waiting times, impacting the execution efficiency of matrix operation instructions, and consequently affecting CPU performance.

[0079] In summary, how to resolve the data dependency of two-dimensional registers, reduce the waiting time of matrix operation instructions, and improve CPU performance are the problems that need to be solved.

[0080] In this embodiment of the invention, the two-dimensional register may be the ZA tile register of ARM's SME, and this embodiment of the invention does not limit it.

[0081] In this embodiment of the invention, to address the aforementioned issues of resolving data dependencies in two-dimensional registers, reducing latency for matrix operation instructions, and improving CPU performance, a dependency detection method for RISC-V matrix operation instructions is proposed, specifically as follows: Figure 2 As shown, Figure 2This is a flowchart of a dependency detection method for RISC-V matrix operation instructions according to an embodiment of the present invention. Specifically, it includes:

[0082] Step S200: Obtain the instruction to be transmitted, which is used to operate on the first slice of the two-dimensional register corresponding to the instruction to be transmitted.

[0083] Specifically, a two-dimensional register consists of multiple rows and columns. A slice of a two-dimensional register includes row slices and column slices. A row slice consists of any one or more rows of the two-dimensional register, while a column slice consists of any one or more columns. The instruction to be issued is used to operate on the two-dimensional register, that is, to read or write data to any one or more row slices (or column slices) of the two-dimensional register.

[0084] For example, such as Figure 3 The two-dimensional register shown includes 4 rows and 4 columns. Assume that dir = 0 represents the row of the two-dimensional register and dir = 1 represents the column of the two-dimensional register. For example, the second row of the two-dimensional register is represented as: dir = 0, sliceIdx (slice start index) = 1; the third row of the two-dimensional register is represented as: dir = 0, sliceIdx = 2; and the second column of the two-dimensional register is represented as dir = 1, sliceIdx = 1.

[0085] Suppose a pre-issue instruction is `load tr0, (rs1)`. If `lmul` (number of slice rows or columns) = 2, `dir` = 0, and `sliceIdx` = 1, then this pre-issue instruction loads two rows of data from the address in register `rs1` and writes them into the second and third rows of the 4x4 two-dimensional register `tr0`. Specifically, as shown below... Figure 4 As shown, the second and third rows of the two-dimensional register tr0 are the first slice corresponding to the instruction to be transmitted. This is only an illustrative example. Any row, any column, multiple rows or columns of the two-dimensional register can be the first slice corresponding to the instruction to be transmitted. The specific determination depends on the actual situation. This embodiment of the invention does not limit it.

[0086] Step S201: Obtain the entry information of the instruction to be launched from the dependency detection queue.

[0087] The entry information for the instruction to be transmitted includes register information of the two-dimensional register corresponding to the instruction and slice information of the first slice. Register information refers to information used to identify the two-dimensional register, such as the register's name and number. Slice information refers to information used to indicate the slice, such as the row or column direction of the slice, and which rows or columns of the two-dimensional register the slice corresponds to.

[0088] In one possible implementation, the register information includes a destination register list (dest reg) and a source register list (src reg). The destination register list includes one or more destination registers for the instruction to be issued, and the source register list includes one or more source registers for the instruction to be issued. Both the destination register information and the source register information are obtained from parsing the instruction machine code. The slice information includes a slice operation direction (dir) and a slice interval. Specifically, the slice operation direction includes a row direction and a column direction, and the slice interval includes a slice start index (sliceIdx) and the number of rows or columns (lmul). The slice operation direction is obtained from parsing the instruction machine code, the slice start index is read from the slice csr register, and the number of slice rows or columns is read from the lmul csr register.

[0089] In one possible implementation, the entry information of the instruction to be issued also includes the sequence number of the instruction to be issued, wherein each instruction has a unique sequence number generated during the decoding stage; the entry information of the instruction to be issued also includes an execution flag (executed), used to mark whether the instruction has been executed. Specifically, the executed flag is initially set to false and set to true after the instruction is executed.

[0090] Step S202: Obtain the entry information of other instructions that are sorted before the entry information of the instruction to be emitted from the dependency detection queue.

[0091] The other instructions are used to operate on the second slice of the two-dimensional register corresponding to the other instructions. The entry information of the other instructions includes the register information of the two-dimensional register corresponding to the other instructions and the slice information of the second slice. All instructions that operate on the two-dimensional register, i.e., matrix operation instructions, will generate entry information for them and store it in the dependency detection queue during the decoding stage. That is, the dependency detection queue only stores the entry information of matrix operation instructions. And, when storing the entry information in the dependency detection queue, it is stored in the order from front to back. Therefore, the entry information of other instructions that are ordered before the entry information of the instruction to be issued in the dependency detection queue are stored in the dependency detection queue first and will be executed first. Step S202 is to determine whether there is a data dependency between the instructions that are ordered before the instruction to be issued but have not yet been executed. If there is, it is necessary to wait for the other instructions to be executed before arranging the execution of the instruction to be issued. If there is no dependency, the instruction can be issued to the execution unit for execution immediately.

[0092] Step S203: Based on the entry information of the instruction to be transmitted and the entry information of other instructions, determine that the first slice and the second slice are unrelated, and instruct the transmission of the instruction to be transmitted. Specifically, based on the register information in the entry information, it can be determined whether the first slice and the second slice belong to the same two-dimensional register. If they do not belong to the same two-dimensional register, there will definitely be no overlap or intersection between the first slice and the second slice, indicating that the first slice and the second slice are unrelated. If they belong to the same two-dimensional register, further determine whether there is any overlap or intersection between the first slice and the second slice based on the slice information in the entry information; if there is overlap or intersection, it indicates that the first slice and the second slice are related; if there is no overlap or intersection, it indicates that the first slice and the second slice are unrelated.

[0093] In an optional embodiment, the first slice and the second slice being unrelated includes the following three cases:

[0094] Scenario 1

[0095] Based on the register information of the two-dimensional registers corresponding to the instruction to be transmitted and the other instructions, the source register information of the instruction to be transmitted and the destination register information of the other instructions are determined; in response to the fact that the source register information of the instruction to be transmitted is the same as the destination register information of the other instructions, the slice information of the first slice is determined to be different from the slice information of the second slice.

[0096] The step of determining that the slice information of the first slice is different from that of the second slice includes: determining that the slice operation directions of the first slice and the second slice are the same and that the slice intervals do not overlap.

[0097] For example, suppose the instruction to be transmitted is instruction A, the source register corresponding to instruction A is a two-dimensional register, the number of which is 1, and the slice information corresponding to instruction A is dir=0, sliceIdx=1, lmul=2, as detailed below. Figure 5 As shown; the other instruction is instruction B, which indicates that the destination register corresponding to instruction B is a two-dimensional register, the number of which is 1. The slice information corresponding to instruction B is dir=0, sliceIdx=3, lmul=1, as detailed below. Figure 6 As shown; by Figure 5 and Figure 6 It can be seen that the slice corresponding to instruction A and the slice corresponding to instruction B have the same operation direction and the slice intervals do not overlap.

[0098] Scenario 2

[0099] Based on the register information of the two-dimensional registers corresponding to the instruction to be transmitted and the other instructions, the destination register information of the instruction to be transmitted, as well as the source register information and destination register information of the other instructions, are determined; in response to the fact that the destination register information of the instruction to be transmitted is the same as the source register information or the destination register information of the other instructions, the slice information of the first slice is determined to be different from the slice information of the second slice.

[0100] Specifically, determining that the slice information of the first slice is different from that of the second slice includes: determining that the slice operation directions of the first slice and the second slice are the same, and that the slice intervals do not overlap.

[0101] For example, suppose the instruction to be transmitted is instruction A, the destination register corresponding to instruction A is a two-dimensional register, the number of which is 2, and the slice information corresponding to instruction A is dir=1, sliceIdx=0, lmul=1, as detailed below. Figure 7 As shown; the other instruction is instruction B, which indicates that the destination or source register corresponding to B is a two-dimensional register, the number of which is 2. The slice information corresponding to instruction B is dir=1, sliceIdx=2, lmul=1, as detailed below. Figure 8 As shown; by Figure 7 and Figure 8 It can be seen that the slice corresponding to instruction A and the slice corresponding to instruction B have the same operation direction and the slice intervals do not overlap.

[0102] Scenario 3

[0103] Based on the register information of the two-dimensional registers corresponding to the instruction to be transmitted and the other instructions, the destination register information of the instruction to be transmitted, as well as the source register information and destination register information of the other instructions, are determined. If the destination register information of the instruction to be transmitted is different from the source register information or destination register information of the other instructions, and based on the register information in the entry information, it is determined that the first slice and the second slice do not belong to the same two-dimensional register, then there is definitely no overlap or intersection between the first slice and the second slice, indicating that the first slice and the second slice are unrelated.

[0104] As can be seen from the above three cases, the first slice and the second slice are unrelated, that is, they do not overlap or intersect, and there is no data dependency. Therefore, the transmission of the transmission command can be indicated.

[0105] In one possible implementation, when the first slice is associated with the second slice, the transmission of the command to be transmitted needs to be blocked. Specifically, the association of the first slice with the second slice also includes two cases:

[0106] Scenario 1

[0107] The first slice overlaps with the second slice.

[0108] For example, in Example 1, suppose the instruction to be transmitted is instruction A, the destination register corresponding to instruction A is a two-dimensional register, the number of the two-dimensional register is 3, and the slice information corresponding to instruction A is dir=0, sliceIdx=1, lmul=2, as detailed below. Figure 9 As shown; the other instruction is instruction B, which indicates that the destination or source register corresponding to B is a two-dimensional register, the number of which is 3. The slice information corresponding to instruction B is dir=0, sliceIdx=1, lmul=2, as detailed below. Figure 10 As shown; by Figure 9 and Figure 10 It can be seen that the slices corresponding to instruction A and instruction B operate in the same direction, and their slice intervals overlap. In this example, the slice intervals of the slices corresponding to instruction A and instruction B completely overlap.

[0109] Example 2: Assume the instruction to be transmitted is instruction A, the destination register corresponding to instruction A is a two-dimensional register, the number of the two-dimensional register is 4, and the slice information corresponding to instruction A is dir=0, sliceIdx=1, lmul=2, as detailed below. Figure 11 As shown; the other instruction is instruction B, which means that the destination register or source register corresponding to B is a two-dimensional register, the number of the two-dimensional register is 4, and the slice information corresponding to instruction B is dir=0, sliceIdx=1, lmul=1, as detailed below. Figure 12 As shown; by Figure 11 and Figure 12 It can be seen that the slices corresponding to instruction A and instruction B operate in the same direction, and their slice intervals overlap. In this example, the slice intervals of the slices corresponding to instruction A and instruction B partially overlap.

[0110] Scenario 2

[0111] The first slice intersects with the second slice.

[0112] For example, suppose the instruction to be transmitted is instruction A, the destination register corresponding to instruction A is a two-dimensional register, the number of the two-dimensional register is 5, and the slice information corresponding to instruction A is dir=1, sliceIdx=0, lmul=1, as detailed below. Figure 13 As shown; the other instruction is instruction B, which indicates that the destination or source register corresponding to B is a two-dimensional register, the two-dimensional register number is 5, and the slice information corresponding to instruction B is dir=0, sliceIdx=1, lmul=1, as detailed below.Figure 14 As shown; by Figure 13 and Figure 14 It can be seen that the slices corresponding to instruction A and the slices corresponding to instruction B have different operation directions and their slice intervals intersect.

[0113] In one possible implementation, before obtaining the entry information of the instruction to be launched from the dependency detection queue, the method further includes steps S204 and S205, specifically as follows: Figure 15 As shown, Figure 15 This is a flowchart of a dependency detection method for RISC-V matrix operation instructions according to an embodiment of the present invention. Specifically, it includes:

[0114] Step S204: Decode the command to be transmitted.

[0115] Specifically, the fetch stage retrieves instruction data from the instruction cache (I-Cache) and then sends it to the decode stage for decoding.

[0116] Step S205: In response to the source register or destination register of the instruction to be transmitted being a two-dimensional register, the entry information of the instruction to be transmitted is written to the tail of the dependency detection queue.

[0117] Specifically, if a two-dimensional register is found in the destination or source register of the instruction to be issued during the decoding process, a file entry is allocated in the Dependency Check Queue (DCQ), and a unique sequence number (seqNum) is generated. Simultaneously, the dest reg, src reg, dir, sliceIdx, and lmul are obtained and filled into the entry. Finally, the entry is pushed to the end of the DCQ, and the execution is marked as not executed (executed = false). A schematic diagram of the file entry information is shown below. Figure 16 As shown.

[0118] In one possible implementation, the method further includes:

[0119] Add the serial number from the entry information of the command to be launched to the command to be launched.

[0120] In one possible implementation, the method further includes:

[0121] When the instruction to be issued is moved to the head of the reorder cache ROB, the entry information of the instruction to be issued is deleted from the dependency detection queue.

[0122] In one possible implementation, the method further includes:

[0123] Delete all file entries in the dependency detection queue whose sequence number is less than the sequence number corresponding to the instruction to be launched.

[0124] In one possible implementation, the method further includes:

[0125] In response to receiving a pipeline refresh command, all file entries in the dependency detection queue with sequence numbers greater than the sequence number corresponding to the command to be launched are deleted.

[0126] The following is a detailed description of the embodiments of the present invention through a complete example:

[0127] The instruction processing pipeline includes the Fetch Stage, Decode Stage, Rename Stage, Dispatch Stage, Issue Stage, Execute Stage, Write-back Stage, and Commit Stage. This embodiment of the invention primarily focuses on the Decode Stage, Issue Stage, Execute Stage, and Commit Stage. A detailed pipeline diagram is shown below. Figure 16 As shown in the schematic diagram, the embodiments of the present invention will be described.

[0128] First, if a two-dimensional register is found in the destination or source register of the instruction to be issued during the decoding process, a file entry is allocated in the Dependency Check Queue (DCQ), and a unique sequence number (seqNum) is generated. Simultaneously, the dest register, src register, dir, sliceIdx, and lmul are obtained and filled into the entry. Finally, the entry is pushed onto the end of the DCQ, and the execution is marked as not executed (executed = false). Figure 16In the code, instructions 2, 3, 4, 5, and 6 each have corresponding two-dimensional registers. Therefore, the decoded DCQ contains 5 entries. Then, after decoding, the instruction is allocated to the corresponding entry in the Reorder Buffer (ROB) and the instruction information is recorded. The Dispatch Stage distributes the instruction to different instruction slots (Issue Slots) according to the instruction type. Next, the Issue Stage retrieves an instruction from the Issue Slot and issues it. If the destination or source register of this instruction is a two-dimensional register, the seqNum of this instruction is used to find the position of the corresponding entry in the DCQ. Then, each entry is traversed sequentially from this position towards the head of the DCQ. It is determined whether the slice of the two-dimensional register in the entry overlaps or intersects with the slice of the two-dimensional register of this instruction. If there is overlap or intersection and execute is false, the issuance of this instruction is blocked. Otherwise, the traversal of entries towards the head of the DCQ continues. If the last entry in the head has been traversed and no situation has been encountered that blocks the issuance of this instruction, then this instruction is issued to the execution unit for execution. For example, Figure 16 In instruction 4, the destination register is the two-dimensional register tr2, and the source registers are the two-dimensional registers tr0 and tr1; it corresponds to entry 3 in the DCQ. Therefore, it is necessary to traverse entries 2 and 1 to check for data dependencies. Since neither the destination nor source register tr2 exists in instructions 2 and 3, there are no WAR or WAW cases. However, the source registers of instruction 4 are the destination registers of instructions 2 and 3, so there is a RAW case between instruction 4 and instructions 2 and 3. Finally, it is necessary to determine whether the slices in entries 2 and 1 overlap or intersect with the slice of entry 3. If they overlap or intersect with both entries 2 and 1, then instruction 4 must wait for instructions 2 and 3 to complete before it can be issued to the execution unit for execution. If an instruction with two-dimensional registers completes its execution, the executed property of the corresponding entry in the DCQ must be set to true. For example, Figure 16 Instruction 2 in the code must set `executed` in entry 1 to `true` after execution in the execute stage. If an instruction with a two-dimensional register reaches the ROB header and is successfully committed, the corresponding entry in the DCQ must be deleted. For example, Figure 16 Command 2 has reached the header of the ROB and has been successfully committed. Now, entry1 should be deleted from the DCQ.

[0129] Figure 17This is a schematic diagram of a dependency detection device for RISC-V matrix operation instructions according to an embodiment of the present invention. Figure 17 As shown, the apparatus of this embodiment includes a dependency detection queue 1701, a correlation detection module 1702, and at least one emission slot 1703;

[0130] The dependency detection queue 1701 is used to store entry information of the instruction to be launched and other instructions. The entry information of the other instructions is ordered in the dependency detection queue before the entry information of the instruction to be launched. The instruction to be launched is used to operate on a first slice of the two-dimensional register corresponding to the instruction to be launched, and the other instructions are used to operate on a second slice of the two-dimensional register corresponding to the other instructions. The entry information of the instruction to be launched includes the register information of the two-dimensional register corresponding to the instruction to be launched and the slice information of the first slice. The entry information of the other instructions includes the register information of the two-dimensional register corresponding to the other instructions and the slice information of the second slice.

[0131] The at least one launch slot 1703 is used to store the launch command and the other commands;

[0132] The correlation detection module 1702 is used to determine the correlation between the first slice and the second slice based on the entry information of the instruction to be launched and the other instruction entry information.

[0133] In one possible implementation, the method further includes a front-end pipeline module 1704 and an execution module 1705.

[0134] In one possible implementation, such as Figure 17 As shown, the issue slot 1703 includes an A-type issue slot and a B-type issue slot. The A-type issue slot stores instructions of type A, and the B-type issue slot stores instructions of type B. The A-type and B-type classifications are merely illustrative; the specific type classification is determined based on actual circumstances, and this embodiment of the invention does not limit its application. Furthermore, in addition to storing instructions for operating two-dimensional registers (i.e., matrix operation instructions), the issue slot can also store scalar operation instructions or vector operation instructions. However, the dependency detection queue does not contain corresponding entry information for scalar operation instructions or vector operation instructions. That is, the dependency detection queue only stores entry information for matrix operation instructions.

[0135] The front-end pipeline module is the processing procedure of instructions from the fetch stage to the dispatch stage in the CPU pipeline. The front-end pipeline module detects that the destination register or source register of the instruction has a two-dimensional register and stores the file entry information of the instruction in the DCQ; and sends different types of instructions to different instruction slots; the DCQ is used to store the file entry information of instructions with two-dimensional registers; the instruction execution module is used to execute type A instructions and type B instructions.

[0136] In one possible implementation, the DCQ mentioned above can be replaced by ROB, thereby reducing the chip area.

[0137] In this embodiment of the invention, a computer program instruction is also provided, which, when executed by a processor, implements the method described in any one of the above embodiments.

[0138] In this embodiment of the invention, a computer-readable storage medium is also provided, on which computer program instructions are stored, which, when executed by a processor, implement the method described in any one of the above embodiments.

[0139] This invention provides a chip including a memory and a processing core. The memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processing core to implement the method described in any of the above embodiments.

[0140] This invention provides a board card that includes the chip.

[0141] This invention provides a server, which includes the aforementioned board.

[0142] As those skilled in the art will recognize, various aspects of the embodiments of the present invention can be implemented as a system, method, or computer program product. Therefore, various aspects of the embodiments of the present invention can take the form of a completely hardware implementation, a completely software implementation (including firmware, resident software, microcode, etc.), or an implementation combining software and hardware aspects, which may generally be referred to herein as a "circuit," "module," or "system." Furthermore, various aspects of the embodiments of the present invention can take the form of a computer program product implemented in one or more computer-readable media having computer-readable program code implemented thereon.

[0143] Any combination of one or more computer-readable media can be used. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example, (but not limited to) an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination thereof. More specific examples (not an exhaustive list) of computer-readable storage media will include: an electrical connection having one or more wires, a portable computer floppy disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable optical disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In the context of embodiments of the present invention, a computer-readable storage medium can be any tangible medium capable of containing or storing a program used by or in conjunction with an instruction execution system, device, or apparatus.

[0144] Computer-readable signal media may include propagated data signals having computer-readable program code implemented therein, such as in baseband or as part of a carrier wave. Such propagated signals may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination thereof. A computer-readable signal medium may be any computer-readable medium that is not a computer-readable storage medium and can communicate, propagate, or transmit a program used by or in conjunction with an instruction execution system, device, or apparatus.

[0145] Program code implemented on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, fiber optic cable, RF, or any suitable combination thereof.

[0146] Computer program code for performing operations relating to various aspects of embodiments of the present invention can be written in any combination of one or more programming languages, including: object-oriented programming languages ​​such as Java, Smalltalk, C++, etc.; and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. The program code can be executed as a standalone software package entirely on the user's computer, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet provided by an Internet service provider).

[0147] The flowchart illustrations and / or block diagrams of the methods, apparatus (systems), and computer program products according to embodiments of the present invention describe various aspects of the embodiments of the present invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine such that the instructions (executed via the processor of the computer or other programmable data processing apparatus) create means for implementing the functions / actions specified in the flowchart and / or block diagram blocks or blocks.

[0148] These computer program instructions may also be stored in a computer-readable medium that can direct a computer, other programmable data processing apparatus or other means to operate in a particular manner, such that the instructions stored in the computer-readable medium produce an article of writing that includes instructions that implement the functions / actions specified in flowchart and / or block diagram blocks or blocks.

[0149] Computer program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operable steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide for implementing the functions / actions specified in flowchart and / or block diagram blocks or blocks.

[0150] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A dependency detection method for RISC-V matrix operation instructions, characterized in that, The method includes: Obtain the instruction to be transmitted, which is used to operate on the first slice of the two-dimensional register corresponding to the instruction to be transmitted; The entry information of the instruction to be launched is obtained from the dependency detection queue, wherein the entry information of the instruction to be launched includes the register information of the two-dimensional register corresponding to the instruction to be launched and the slice information of the first slice; The entry information of other instructions ordered before the entry information of the instruction to be issued is obtained from the dependency detection queue. The other instructions are used to operate on the second slice of the two-dimensional register corresponding to the other instructions. The entry information of the other instructions includes the register information of the two-dimensional register corresponding to the other instructions and the slice information of the second slice. Based on the entry information of the command to be launched and the entry information of the other commands, it is determined that the first slice and the second slice are unrelated, and the command to be launched is instructed to be launched.

2. The method as described in claim 1, characterized in that, The determination that the first slice and the second slice are unrelated specifically includes: Based on the register information of the two-dimensional registers corresponding to the instruction to be transmitted and the other instructions, the source register information of the instruction to be transmitted and the destination register information of the other instructions are determined. In response to the fact that the source register information of the instruction to be transmitted is the same as the destination register information of the other instructions, it is determined that the slice information of the first slice is different from the slice information of the second slice.

3. The method according to any one of claims 1-2, characterized in that, The determination that the first slice and the second slice are unrelated specifically includes: Based on the register information of the two-dimensional registers corresponding to the instruction to be transmitted and the other instructions, the destination register information of the instruction to be transmitted, as well as the source register information and destination register information of the other instructions, are determined. In response to the fact that the destination register information of the instruction to be transmitted is the same as the source register information or destination register information of the other instructions, it is determined that the slice information of the first slice is different from the slice information of the second slice.

4. The method according to any one of claims 2-3, characterized in that, The slicing information includes: slicing operation direction and slicing range; Determining that the slice information of the first slice is different from the slice information of the second slice includes: It is determined that the slicing operation directions of the first slice and the second slice are the same, and the slice intervals do not overlap.

5. The method as described in claim 4, characterized in that, The slice range includes: the starting index of the slice and the number of rows or columns in the slice.

6. The method according to any one of claims 1-5, characterized in that, Before retrieving the entry information of the instruction to be emitted from the dependency detection queue, the method further includes: The command to be launched is decoded; In response to the source register or destination register of the instruction to be transmitted being a two-dimensional register, the entry information of the instruction to be transmitted is written to the tail of the dependency detection queue.

7. The method as described in claim 6, characterized in that, The entry information for the command to be launched also includes the sequence number of the command to be launched, and the method further includes: Add the serial number from the entry information of the command to be launched to the command to be launched.

8. The method according to any one of claims 1-7, characterized in that, The method also includes: When the instruction to be issued is moved to the head of the reorder cache ROB, the entry information of the instruction to be issued is deleted from the dependency detection queue.

9. A dependency detection device for RISC-V matrix operation instructions, characterized in that, The device includes a dependency detection queue, a correlation detection module, and at least one emission slot; The dependency detection queue is used to store entry information of the instruction to be launched and other instructions; the entry information of the other instructions is ordered in the dependency detection queue before the entry information of the instruction to be launched. The instruction to be launched is used to operate on the first slice of the two-dimensional register corresponding to the instruction to be launched, and the other instructions are used to operate on the second slice of the two-dimensional register corresponding to the other instructions; the entry information of the instruction to be launched includes the register information of the two-dimensional register corresponding to the instruction to be launched and the slice information of the first slice, and the entry information of the other instructions includes the register information of the two-dimensional register corresponding to the other instructions and the slice information of the second slice. The at least one launch slot is used to store the command to be launched and the other commands; The correlation detection module is used to determine the correlation between the first slice and the second slice based on the entry information of the instruction to be launched and the entry information of the other instructions.

10. A computer program product comprising computer program instructions, characterized in that, The computer program instructions, when executed by a processor, implement the method as described in any one of claims 1-8.

Images