Semiconductor structure, method of manufacturing a semiconductor structure, and semiconductor device

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a semiconductor structure, a manufacturing method of the semiconductor structure and a semiconductor device, the semiconductor structure comprising: a logic chip having a power supply port; a storage module located on the upper surface of the logic chip, the storage module comprising a plurality of storage chips stacked in a first direction, the first direction being parallel to the upper surface of the logic chip; each of the storage chips has a power supply signal line, at least one of the plurality of storage chips has a power supply wiring layer, and the power supply wiring layer is electrically connected with the power supply signal line; the power supply wiring layer is exposed towards or away from the end surface of the logic chip by the storage chip; and the exposed end surface of the power supply wiring layer is electrically connected with the power supply port. The embodiment of the present disclosure can at least unify the communication delay of the plurality of storage chips, improve the operation rate, and also be beneficial to improving the stability of power supply.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductors, specifically relating to a semiconductor structure, a method for manufacturing the semiconductor structure, and a semiconductor device. Background Technology

[0002] To improve the integration of semiconductor structures, more than one memory chip can be placed within the same package. HBM (High Bandwidth Memory) is a new type of memory. Memory chip stacking technology, represented by HBM, extends the original one-dimensional memory layout to three dimensions, that is, stacking many memory chips together and packaging them, thereby significantly increasing the density of memory chips and achieving large capacity and high bandwidth.

[0003] However, HBM's performance needs improvement as the number of stacking layers increases. Summary of the Invention

[0004] This disclosure provides a semiconductor structure, a method for manufacturing the semiconductor structure, and a semiconductor device, which at least help improve the performance of the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, wherein the semiconductor structure includes: a logic chip having a power supply port; a memory module located on the upper surface of the logic chip, the memory module including a plurality of memory chips stacked in a first direction, the first direction being parallel to the upper surface of the logic chip; each memory chip having a power supply signal line, at least one of the plurality of memory chips having a power supply wiring layer, and the power supply wiring layer being electrically connected to the power supply signal line; the end face of the power supply wiring layer facing or away from the logic chip being exposed by the memory chip; the exposed end face of the power supply wiring layer being electrically connected to the power supply port.

[0006] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a semiconductor structure, wherein the manufacturing method includes: providing a logic chip having a power supply port; providing a memory module including a plurality of memory chips stacked in a first direction; each memory chip having a power supply signal line, at least one of the plurality of memory chips having a power supply wiring layer, and the power supply wiring layer being electrically connected to the power supply signal line; the end face of the power supply wiring layer facing or away from the logic chip being exposed by the memory chip; soldering the memory module onto the logic chip such that the first direction is parallel to the upper surface of the logic chip, and the exposed end face of the power supply wiring layer is electrically connected to the power supply port.

[0007] According to some embodiments of this disclosure, another aspect of this disclosure also provides a semiconductor device, including: a substrate; a logic chip disposed on the substrate and having a power supply port; a memory module located on the upper surface of the logic chip, the memory module including a plurality of memory chips stacked in a first direction, the first direction being parallel to the upper surface of the logic chip; each memory chip having a power supply signal line, at least one of the plurality of memory chips having a power supply wiring layer, and the power supply wiring layer being electrically connected to the power supply signal line; the end face of the power supply wiring layer facing or away from the logic chip being exposed by the memory chip; the exposed end face of the power supply wiring layer being electrically connected to the power supply port.

[0008] The technical solution provided in this disclosure has at least the following advantages: the stacking direction of multiple memory chips is parallel to the upper surface of the logic chip, meaning that the distance between the multiple memory chips and the logic chip is the same. Therefore, the communication delay of the multiple memory chips is consistent, which is beneficial to improving the operating speed. Furthermore, the power supply wiring layer within the memory chip can lead the power supply signal lines out of the memory chip and connect them to the power supply port through solder bumps, thereby achieving wired power supply and improving power supply stability. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0010] Figure 1 A schematic diagram of a semiconductor structure is shown;

[0011] Figure 2 , Figure 9 , Figure 11 , Figure 13 , Figure 15 Different cross-sectional views of a semiconductor structure provided in an embodiment of this disclosure are shown respectively;

[0012] Figures 4-5 , Figures 7-8 Schematic diagrams of different active surfaces of a memory chip provided in an embodiment of this disclosure are shown respectively;

[0013] Figure 3 , Figure 6 , Figure 10 , Figure 12 , Figure 14 Different bottom views of a storage module provided in one embodiment of this disclosure are shown;

[0014] Figures 16-17This invention discloses a schematic diagram of the structure corresponding to each step in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure.

[0015] Figure 18 A schematic diagram of a semiconductor device provided in yet another embodiment of this disclosure is shown. Detailed Implementation

[0016] refer to Figure 1 As the background technology indicates, the performance of HBM needs improvement. Analysis revealed that the main reason is that the arrangement of the multiple memory chips 200 in the HBM is perpendicular to the upper surface of the logic chip 300. The conductive vias 400 within the multiple memory chips 200 are electrically connected vias 500, thus forming a wired communication path. When the number of stacked layers is large, the communication distance between the topmost and bottommost memory chips 200 and the logic chip 300 differs significantly, resulting in substantial differences in communication latency between different memory chips 200 and the logic chip 300, thereby affecting the product's operating speed.

[0017] This disclosure provides a semiconductor structure in which multiple memory chips are stacked in a direction parallel to the upper surface of a logic chip. Therefore, the distance between the multiple memory chips and the logic chip is the same, which is beneficial for unifying communication latency and improving operating speed. Furthermore, the power supply wiring layer within the memory chips can change the layout of the power supply signal lines and lead the power supply signal lines out of the memory chips; that is, the wired power supply method can improve power supply stability.

[0018] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0019] like Figures 2-15 As shown, one embodiment of this disclosure provides a semiconductor structure, which includes: a logic chip 3 having a power supply port 3a; a storage module 100 located on the upper surface of the logic chip 3, the storage module 100 including a plurality of storage chips 1 stacked in a first direction X, the first direction X being parallel to the upper surface of the logic chip 3; each storage chip 1 having a power supply signal line 12, at least one of the plurality of storage chips 1 having a power supply wiring layer 2, and the power supply wiring layer 2 being electrically connected to the power supply signal line 12; the end face of the power supply wiring layer 2 facing or away from the logic chip 3 being exposed by the storage chip 1; the exposed end face of the power supply wiring layer 2 being electrically connected to the power supply port 3a.

[0020] That is, the memory chips 1 are stacked in a direction parallel to the upper surface of the logic chip 3, meaning that the arrangement direction of multiple memory chips 1 is parallel to the upper surface of the logic chip 3. Therefore, the distance between each memory chip 1 and the logic chip 3 is the same, which helps to reduce the difference in communication latency between different memory chips 1 and the logic chip 3. In addition, compared with vertical stacking, parallel stacking helps to reduce the distance between multiple memory chips 1 and the logic chip 3, thereby improving the communication speed. Furthermore, the power supply wiring layer 2 can lead the power supply signal line 12 out from the edge of the memory chip 1, and the power supply wiring layer 2 is electrically connected to the power supply port 3a, thereby realizing wired power supply to the memory chip 1 and improving the stability of the current.

[0021] The semiconductor structure will be described in detail below with reference to the accompanying drawings.

[0022] First, it should be noted that the semiconductor structure has a first direction X, a second direction Y, and a third direction Z. Among them, the first direction X is the stacking direction of the memory chip 1; the second direction Y is perpendicular to the first direction X and parallel to the upper surface of the logic chip 3; and the third direction Z is perpendicular to the upper surface of the logic chip 3.

[0023] The memory chip 1 has a front side and a back side, as well as a side connecting the front side and the back side. Two adjacent memory chips 1 can be stacked face-to-face, face-to-back, or back-to-back. The front side of the memory chip 1 can also be understood as the active surface 13.

[0024] The storage chip 1 can be a DRAM (Dynamic Random Access Memory) or SRAM (Static Random-Access Memory) chip.

[0025] In some embodiments, Figure 2 , Figure 9 , Figure 11 , Figure 13 The logic chip 3 has a first wireless communication unit 31; the memory chip 1 has a second wireless communication unit 11; the first wireless communication unit 31 and the second wireless communication unit 11 communicate wirelessly. In this way, communication between the memory chip 1 and the logic chip 3 can be realized.

[0026] In some embodiments, the second wireless communication unit 11 is located on the side of the memory chip 1 facing the logic chip 3. This reduces the distance between the first wireless communication unit 31 and the second wireless communication unit 11, thereby improving the quality of wireless communication. In other embodiments, the memory chip 1 can also communicate with the logic chip 3 via wired connections, which will be described in detail later.

[0027] It should be noted that the side of the memory chip 1 faces the logic chip 3 and has a small area. Since the communication between the memory chip 1 and the logic chip 3 is achieved through wireless communication, there is no need to set up a wired communication unit between the memory chip 1 and the logic chip 3. Therefore, the space between the memory chip 1 and the logic chip 3 can be used only to arrange the power supply path of the memory chip 1, thereby reducing the process difficulty.

[0028] Specifically, refer to Figure 2 , Figure 9 , Figure 11 and Figure 13 The end face of the power supply wiring layer 2 facing the logic chip 3 is exposed by the memory chip 1. For example, the end face of the power supply wiring layer 2 facing the logic chip 3 is flush with the side face of the memory chip 1 facing the logic chip 3. The memory chip 1 also has solder bumps 5, which are connected to the end face of the power supply wiring layer 2. Since no wired communication section is provided at the bottom of the memory module 100, the space for the solder bumps 5 is relatively sufficient, which helps to reduce the contact resistance between the solder bumps 5 and the power supply wiring layer 2, thereby improving the operating speed of the semiconductor structure; in addition, it also helps to increase the spacing between adjacent solder bumps 5, thereby avoiding incorrect electrical connections between adjacent solder bumps 5.

[0029] For example, the width of the solder bump 5 in the first direction X is greater than the width of the power supply wiring layer 2 in the first direction X. This helps to increase the contact area between the solder bump 5 and the power supply wiring layer 2, thereby reducing the contact resistance; in addition, it also helps to improve the soldering strength between the solder bump 5 and the logic chip 3.

[0030] Continue to refer to Figure 2 , Figure 9 , Figure 11 and Figure 13 The logic chip 3 has a solder pad 32 on its surface facing the storage module 100; the solder pad 32 is soldered to the solder bump 5. Furthermore, a solder paste layer 73 exists between the solder pad 32 and the solder bump 5. Additionally, the solder pad 32 serves as a power supply port 3a for the storage module 100, and can be electrically connected to an external power source to supply power to the storage module 100. Specifically, the logic chip 3 has a through-hole conductive via; one end of the conductive via is electrically connected to the solder pad 32, and the other end is electrically connected to a power source on the substrate 93.

[0031] In some embodiments, the solder pad 32 may protrude from the upper surface of the logic chip 3, thereby increasing the distance between the upper surface of the logic chip 3 and the lower surface of the storage module 100 to provide a heat dissipation area.

[0032] refer to Figures 3-6 , Figure 10 , Figure 12 , Figure 14The power supply wiring layer 2 includes multiple power supply lines 20. Therefore, the power supply wiring layer 2 has multiple end faces facing the logic chip 3, each end face corresponding to one power supply line 20. That is, multiple solder bumps 5 are respectively connected to the multiple power supply lines 20 of the same power supply wiring layer 2 in a one-to-one correspondence. For example, the multiple end faces of the same power supply wiring layer 2 are spaced apart in the second direction Y, and the solder bumps 5 connected to the same power supply wiring layer 2 are spaced apart in the second direction Y. Different solder bumps 5 are connected to different power supply ports 3a on the logic chip 3, thereby enabling the memory chip 1 to obtain different voltage signals.

[0033] The power supply wiring layer 2 can extend along the active surface 13 of the memory chip 1. That is, the power supply wiring layer 2 is located on the front side of the memory chip 1. Therefore, after the components inside the memory chip 1 are manufactured, the power supply wiring layer 2 can be manufactured using the existing back-end processes, making the process simpler. In addition, the power supply wiring layer 2 can extend only at the edge near the upper or lower side of the memory chip 1, without covering the entire active surface 13 of the memory chip 1. Therefore, the contact area between the power supply wiring layer 2 and the memory chip 1 is small, and the heat from the power supply wiring layer 2 has a smaller impact on the memory chip 1.

[0034] The connection relationship between the power supply signal line 12 and the power supply wiring layer 2 will be explained in detail below.

[0035] refer to Figures 4-5 and Figures 7-8 , Figures 4-5 and Figures 7-8 Different active surfaces 13 of the memory chip 1 are shown. Each memory chip 1 has multiple power supply signal lines 12 extending on the active surface 13. Different power supply signal lines 12 can provide different voltage signals, such as digital signals or analog signals, to the components within the memory chip 1. The power supply signal lines 12 can be ground signal lines 12G or power signal lines 12P. Different ground signal lines 12G have different voltage signals, and different power signal lines 12P have different voltage signals.

[0036] refer to Figure 3 , Figure 6 , Figure 9 , Figure 10 , Figure 12 , Figure 14The power supply cabling layer 2 can be a power cabling layer 2P, a ground cabling layer 2G, or a hybrid cabling layer 2PG. That is, a power supply cabling layer 2 includes multiple isolated power supply cablings 20. Based on the type of power supply cablings 20 in each power supply cabling layer 2, the power supply cabling layer 2 can be divided into the three categories mentioned above. When all the power supply cablings 20 in the power supply cabling layer 2 are power supply cablings 20P, this power supply cabling layer 2 is called a power supply cabling layer 2P; when all the power supply cablings 20 in the power supply cabling layer 2 are ground cablings 20G, this power supply cabling layer 2 is called a ground cabling layer 2G; when the power supply cabling layer 2 includes both ground cablings 20G and power cablings 20P, this power supply cabling layer 2 is called a hybrid cabling layer 2PG.

[0037] refer to Figures 4-5 and Figures 7-8 The grounding wiring 20G is electrically connected to the grounding signal line 12G, and the power wiring 20P is electrically connected to the power signal line 12P. It should be noted that the multiple power wirings 20 in the power wiring layer 2 are all mutually insulated, so that power signal lines 12 with different voltage signals can be led out separately.

[0038] If a memory chip 1 has its own power supply wiring layer 2, then at least some of the power supply signal lines 12 of this memory chip 1 can be directly connected to its own power supply wiring layer 2, that is, led out through its own power supply wiring layer 2. If a memory chip 1 does not have its own power supply wiring layer 2, then the power supply signal lines 12 of this memory chip 1 can be led out through the power supply wiring layers 2 of other memory chips 1. In other words, this memory chip 1 can establish an electrical connection with other memory chips 1 through conductive vias 41 and bonding portions 42, thereby electrically connecting its own power supply signal lines 12 to the power supply signal lines 12 of other memory chips 1, and further electrically connecting to the power supply wiring layers 2 of other memory chips 1. This will be explained in detail later.

[0039] Multiple memory chips 1 can be stacked using a hybrid bonding method. For example, the surface of memory chip 1 also has a dielectric layer 43, and the dielectric layers 43 of adjacent memory chips 1 can be connected together by forces such as molecular forces. In addition, the surface of memory chip 1 can also have bonding portions 42, and adjacent bonding portions 42 are bonded together under heating conditions. That is, the dielectric layer 43 is an insulating material, which can play an isolation role; the bonding portion 42 is a conductive material, which can play an electrical connection role. Furthermore, the dielectric layer 43 also exposes the end face of the power supply wiring layer 2 facing or away from the logic chip 3, and covers the sides of the power supply wiring layer 2 except for the end face.

[0040] The following will provide a detailed description of the position and quantity relationship between the memory chip 1 and the power supply wiring layer 2.

[0041] Example 1, for reference Figures 2-10 Each memory chip 1 has a power supply wiring layer 2, meaning the number of memory chips 1 is the same as the number of power supply wiring layers 2. Because there are many power supply wiring layers 2, sufficient lead-out locations can be provided for multiple power supply signal lines 12, simplifying the process of leading out the power supply signal lines 12. Furthermore, more power supply wiring layers 2 also help improve power supply stability, thereby improving the performance of the semiconductor structure. In addition, the power supply wiring layers 2 are uniformly arranged within multiple memory chips 1, thus facilitating the standardization of manufacturing processes for different memory chips 1 and reducing production costs.

[0042] In some embodiments, reference Figures 2-8 Two adjacent memory chips 1 constitute a chipset 10, and two power supply wiring layers 2 of the same chipset 10 are located between the two memory chips 1. The two memory chips 1 of the same chipset 10 share the two power supply wiring layers 2 located between them. For example, the two memory chips 1 of the chipset 10 are bonded face to face, that is, active surface 13 to active surface 13.

[0043] Specifically, refer to Figure 2 Each memory chip 1 has conductive vias 41, which are, for example, through-silicon vias (TSVs). Two memory chips 1 in the same chipset 10 are connected by a bonding portion 42, which connects to the conductive vias 41 of the two memory chips 1, thus electrically connecting the two memory chips 1. For example, each memory chip 1 has multiple spaced conductive vias 41, and each conductive via 41 is connected to a corresponding power supply signal line 12 within the memory chip 1. The voltage signals on the power supply signal lines 12 within the same memory chip 1 are different, and correspondingly, the voltage signals on the conductive vias 41 within the same memory chip 1 are also different. In the two memory chips 1 in the same chipset 10, conductive vias 41 with the same voltage signal are electrically connected through the bonding portion 42, thereby electrically connecting the power supply signal lines 12 with the same voltage signal in the two memory chips 1 together.

[0044] For example, the conductive via 41 includes multiple ground vias 41G and multiple power vias 41P, and the bonding portion 42 includes multiple ground bonding portions 42G and multiple power bonding portions 42P. The ground vias 41G are connected to the ground bonding portions 42G, and the power vias 41P are connected to the power bonding portions 42P.

[0045] The conductive vias 41 of each memory chip 1 can be arranged at intervals in the third direction Z. For example, ground vias 41G and power vias 41P are arranged alternately in the third direction Z to reduce electromagnetic interference between adjacent conductive vias 41.

[0046] Figure 3This is a bottom view of a storage module 100. Figures 4-5 These are schematic diagrams of the active surfaces 13 of the two memory chips 1 of the chipset 10, and Figures 3-5 Corresponding to the same semiconductor structure. (Reference) Figures 3-5 Chipset 10 includes a first memory chip 1a and a second memory chip 1b. Both memory chips 1a have a first power supply signal line group 121 and a second power supply signal line group 122; the power supply signal lines 12 of both the first and second power supply signal line groups 121 and 122 include a power signal line 12P and a ground signal line 12G. The first power supply signal line group 121 of the two memory chips 1a is led out through the power supply wiring layer 2 of the first memory chip 1a, and the second power supply signal line group 122 of the two memory chips 1a is led out through the power supply wiring layer 2 of the second memory chip 1b. That is, both power supply wiring layers 2 of the same chipset 10 are hybrid wiring layers 2PG.

[0047] Continue to refer to Figure 3 Within the hybrid wiring layer 2PG, grounding wiring 20G and power wiring 20P are arranged alternately in the second direction Y, which helps to reduce electromagnetic interference between adjacent power wiring 20.

[0048] Figure 5 This is a bottom view of a storage module 100. Figures 6-7 These are schematic diagrams of the active surfaces 13 of the two memory chips 1 of the chipset 10, and Figures 5-7 Corresponding to the same semiconductor structure; Reference Figures 5-7 In the first power supply signal line group 121, all power supply signal lines 12 are power signal lines 12P, and in the second power supply signal line group 122, all power supply signal lines 12 are ground signal lines 12G. The first power supply signal line group 121 of the two memory chips 1 is led out through the power supply wiring layer 2 of the first memory chip 1a, and the second power supply signal line group 122 of the two memory chips 1 is led out through the power supply wiring layer 2 of the second memory chip 1a. That is, the two power supply wiring layers 2 of the same chipset 10 are a power wiring layer 2P and a ground wiring layer 2G, respectively. The first power supply signal line group 121 is electrically connected to the power wiring layer 2P, and the second power supply signal line group 122 is electrically connected to the ground wiring layer 2G.

[0049] Thus, based on Figures 2-8 It is known that each memory chip 1 has a first power supply signal line group 121 and a second power supply signal line group 122; both the first power supply signal line group 121 and the second power supply signal line group 122 include multiple power supply signal lines 12; two first power supply signal line groups 121 within the same chipset 10 are electrically connected to one power supply wiring layer 2, and two second power supply signal line groups 122 within the same chipset 10 are electrically connected to another power supply wiring layer 2. That is, the power supply wiring layer 2 is shared by two power supply wiring layers 2 within the same chipset 10.

[0050] The advantages of this design are mainly as follows: First, the shared power supply wiring layer 2 is located between the two memory chips 1, which can shorten the distance between the power supply wiring layer 2 and the two memory chips 1, thereby helping to reduce the high power consumption caused by long distances; Second, only the dielectric layer 43 for insulation can be set between adjacent chipsets 10, thereby reducing the number of bonding parts 42 and simplifying the manufacturing process; Third, the power supply wiring layer 2 is shared by the two memory chips 1, and correspondingly, the number of power supply wiring 20 and the number of solder bumps 5 are reduced, which helps to provide more space for solder bumps 5 and avoid short circuits; Fourth, only two memory chips 1 in the chipset 10 share the power supply wiring layer 2, that is, the number of memory chips 1 in the chipset 10 is small, which helps to ensure the stability of power supply.

[0051] refer to Figure 3 and Figure 6 The solder bumps 5 include multiple first solder bumps 51 and multiple second solder bumps 52. The first solder bumps 51 and the second solder bumps 52 are respectively connected to different power supply wiring layers 2 within the same chipset 10. The first solder bumps 51 and the second solder bumps 52 are staggered in the first direction X. Specifically, the first solder bumps 51 connected to the same power supply wiring layer 2 are spaced apart in the second direction Y, and the second solder bumps 52 connected to the same power supply wiring layer 2 are spaced apart in the second direction Y. In the first direction X, the gaps between the first solder bumps 51 and the two second solder bumps 52 are directly opposite each other, and the gaps between the second solder bumps 52 and the two first solder bumps 51 are directly opposite each other; that is, in the first direction X, the first solder bumps 51 and the second solder bumps 52 are not directly opposite each other. This helps to increase the distance between the first solder bumps 51 and the second solder bumps 52, thereby avoiding incorrect electrical connections between the first solder bumps 51 and the second solder bumps 52. It should be noted that multiple first solder bumps 51 connect to different power supply signal lines 12 within the power supply wiring layer 2, and multiple second solder bumps 52 connect to different power supply signal lines 12 within the power supply wiring layer 2. In some other embodiments, the first solder bumps 51 and the second solder bumps 52 may also be arranged facing each other in the first direction X.

[0052] Continue to refer to Figure 3 and Figure 6In the first direction X, there is a first spacing d1 between two power supply wiring layers 2 within the same chipset 10; in the first direction X, there is a second spacing d2 between the first solder bump 51 and the second solder bump 52; the ratio of the first spacing d1 to the second spacing d2 is 1:1 to 1.2:1. It should be noted that if the second spacing d2 is too large, it may waste space between adjacent memory chips 1; if the second spacing d2 is too small, it may cause incorrect electrical connections between the first solder bump 51 and the second solder bump 52. Maintaining the first spacing d1 and the second spacing d2 within the above range helps to balance these two problems. For example, as... Figure 3 and Figure 6 As shown, the first spacing d1 can be the same as the second spacing d2, that is, the sidewalls opposite to the first welding bump 51 and the second welding bump 52 are flush with the sidewalls opposite to the two power supply wiring layers 2.

[0053] refer to Figures 9-10 , Figure 9 This is a cross-sectional view. Figure 10 for Figure 9 The diagram shows a bottom view of the storage module 100. Power supply signal lines 12 within the same storage chip 1 are connected to the power supply wiring layer 2. The power supply wiring layers 2 of different storage chips 1 are independent of each other, and the power supply signal lines 12 of different storage chips 1 are also independent. That is, the power supply signal lines 12 of multiple storage chips 1 do not need to be electrically connected together through conductive vias 41 and bonding portions 42. The power supply signal lines 12 within each storage chip 1 can be led out through the storage chip 1's own power supply wiring layer 2 without borrowing from the power supply wiring layers 2 of other storage chips 1. Since the power supply signal lines 12 of each storage chip 1 can be led out individually, it is beneficial to improve the stability of the power supply. Furthermore, the fabrication steps of the bonding portion 42 and conductive vias 41 can be eliminated, thereby reducing production costs. Adjacent storage chips 1 can be fixed by adhesive bonding or by bonding through an oxide layer (e.g., silicon oxide).

[0054] Continue to refer to Figure 10 Each memory chip 1 has a power supply wiring layer 2 that is a hybrid wiring layer 2PG, with power supply wiring 20P and ground wiring 20G alternately arranged in the second direction Y to reduce electromagnetic interference. Furthermore, multiple power supply wiring layers 2 can be formed on the same side of the memory chip 1, thereby unifying the manufacturing process of the power supply wiring layers 2.

[0055] Furthermore, the power supply wiring 20P of the multiple memory chips 1 can be arranged in a straight line in the first direction X, and the ground wiring 20G of the multiple memory chips 1 can also be arranged in a straight line in the first direction X. Alternatively, the power supply wiring 20P and the ground wiring 20G can be alternately arranged in a straight line in the first direction X. This helps to improve the uniformity of the semiconductor structure and simplifies the manufacturing process.

[0056] Example 2: The number of power supply wiring layers 2 can be greater than the number of memory chips 1. For example, refer to... Figures 11-12 , Figure 11 This is a cross-sectional view. Figure 12 for Figure 11 The diagram shows a bottom view of the storage module 100. A power supply wiring layer 2 is provided between two adjacent storage chips 1, and this layer is electrically connected to the storage chips 1 on either side of it. The storage module 100 also has a power supply wiring layer 2 at both ends, which are electrically connected to the storage chips 1 on each end. In other words, except for the two power supply wiring layers 2 at the ends which are not shared by the storage chips 1, the remaining power supply wiring layers 2 in the middle are shared by the storage chips 1 on either side. The storage chips 1 at the beginning and end of the storage module 100 can also be understood as the outermost storage chips 1 of the storage module 100. The power supply wiring layer 2 located in the middle is connected to the power supply signal lines 12 of the two storage chips 1, which helps to reduce the number of solder bumps 5 and simplifies the manufacturing process. Furthermore, the power supply wiring layers 2 are distributed relatively uniformly within the storage module 100, which further simplifies the manufacturing process.

[0057] like Figure 12 As shown, the power supply wiring layer 2 includes a power supply wiring layer 2P and a ground wiring layer 2G. The power supply wiring layer 2P includes multiple power supply lines 20P, and the ground wiring layer 2G includes multiple ground lines 20G. The power supply wiring layer 2P and the ground wiring layer 2G are arranged alternately in the first direction X. In some other embodiments, all power supply wiring layers 2 may also be hybrid wiring layers 2PG, and the voltage signals of the power supply signal lines 12 led out from two adjacent hybrid wiring layers 2PG are different.

[0058] Continue to refer to Figures 11-12 The following example illustrates the sharing method of the power supply wiring layer 2. The power supply wiring layer 2P located on the first side of the storage module 100 can be directly connected to the power signal line 12P of the first storage chip 1a. Therefore, the first storage chip 1a may not have a power via 41P and a power bonding portion 42P. The first storage chip 1a and the second storage chip 1b share the ground wiring layer 2G, meaning their ground signal lines 12G are connected together through the ground via 41G and the ground bonding portion 42G, and are led out through the ground wiring layer 2G between them. The second storage chip 1b and the third storage chip 1c share the power supply wiring layer 2P, meaning their power signal lines 12P are connected together through the power via 41P and the power bonding portion 42P, and are led out through the power wiring layer 2P between them. Since the second storage chip 1b and the third storage chip 1c do not share the ground wiring layer 2G, their ground vias 41G and ground bonding portions 42G will not have an electrical connection.

[0059] In other words, if the power supply wiring layer 2 between two adjacent memory chips 1 is a power supply wiring layer 2P, then these two memory chips 1 are electrically connected through a power via 41P and a power bonding portion 42P. Similarly, if the power supply wiring layer 2 between two adjacent memory chips 1 is a ground wiring layer 2G, then these two memory chips 1 are electrically connected through a ground via 41G and a ground bonding portion 42G.

[0060] It is worth noting that since the number of power supply wiring layers 2 is one more than the number of memory chips 1, one of the two power supply wiring layers 2 at the beginning and end does not need to extend along the active surface 13 of the memory chip 1, that is, it can be located on the back side of the memory chip 1. The remaining power supply wiring layers 2 can still be located on the active surface 13 of the memory chip 1.

[0061] Example 3: The number of power supply wiring layers 2 can also be less than the number of memory chips 1. For example, refer to... Figures 13-14 , Figure 13 This is a cross-sectional view. Figure 14 for Figure 13 The storage module 100 shown is a bottom view; at least two adjacent storage chips 1 are bonded together to form a chipset 10; there is a power supply wiring layer 2 between two adjacent chipsets 10, and the power supply wiring layer 2 is electrically connected to the storage chips 1 of the chipset 10 on both sides; the storage module 100 has a power supply wiring layer 2 at both ends, and is electrically connected to the chipset 10 at both ends respectively.

[0062] In other words, except for the two power supply wiring layers 2 at the beginning and end that are not shared by the chipset 1, all the power supply wiring layers 2 in the middle position are shared by the chipsets 10 on both sides. One power supply wiring layer 2 in the middle position is connected to the power supply signal lines 12 of the two chipsets 10. It is worth noting that the fewer the number of power supply wiring layers 2, the fewer the number of solder bumps 5. Therefore, it is beneficial to increase the distance between the solder bumps 5 and the coils in the first wireless communication unit 31 and the second wireless communication unit 11, thereby reducing electromagnetic interference generated by the solder bumps 5 and the coils and avoiding signal loss.

[0063] For example, each chipset 10 has two memory chips 1, and the power supply signal lines 12 with the same voltage signal in the two memory chips 1 are connected together through conductive vias 41 and bonding portions 42.

[0064] Continue to refer to Figures 13-14The following example illustrates the sharing method of power supply wiring layer 2. The first chipset 101 and the second chipset 102 share the ground wiring layer 2G, meaning their ground signal lines 12G are connected together through ground vias 41G and ground bonding portions 42G, and are led out through the ground wiring layer 2G between them. The first chipset 101 and the second chipset 102 do not share the power wiring layer 2P, therefore their power vias 41P and power bonding portions 42P are not electrically connected. The second chipset 102 and the third chipset 103 share the power wiring layer 2P, meaning their power signal lines 12P are connected together through power vias 41P and power bonding portions 42P, and are led out through the power wiring layer 2P between them.

[0065] refer to Figure 15 The memory chip 1 and the logic chip 3 communicate via wired connection. Specifically, the semiconductor structure also includes a wired communication unit 8, which is connected to both the memory chip 1 and the logic chip 3. Wired communication improves signal transmission quality. For example, at least one memory chip 1 has a signal wiring layer 83, which is electrically connected to the logic chip 3. The signal wiring layer 83 is located on the side of the memory chip 1 closer to the logic chip 3, meaning the wired communication unit 8 can be led out from the end face of the memory module 100 towards the logic chip 3, thereby shortening the wired communication path and reducing communication latency.

[0066] It should be noted that compared to vertical stacking, parallel stacking can reduce the number of wired communication units 8. This is because, in the third direction Z, multiple parallel-stacked memory chips 1 are located on the same layer. Therefore, the wired communication path of each memory chip 1 does not need to pass through memory chips 1 in other layers, thus reducing the area of ​​memory chips 1 occupied by the wired communication units 8. In contrast, with vertical stacking, the upper-layer memory chip needs to borrow the wired communication unit of the lower-layer memory chip; that is, the wired communication path of the upper-layer memory chip passes through the lower-layer memory chip.

[0067] Continue to refer to Figure 15 The power supply signal line 83 is located on the side of the memory chip 1 away from the logic chip 3, and the end face of the power supply wiring layer 2 away from the logic chip 3 is exposed by the memory chip 1. The semiconductor structure also includes at least one of a lead 91 and a lead frame 92; at least one of the lead 91 and the lead frame 92 is connected between the end face of the power supply wiring layer 2 and the power supply port 3a. In other words, the power supply signal line 12 can be led out from the upper side of the memory module 100, thereby avoiding occupying the space of the wired communication section 8 on the lower side of the memory module 100, so as to ensure the stability of power supply and communication and reduce the difficulty of manufacturing process.

[0068] For example, one end of lead 91 is connected to power supply wiring layer 2, and the other end is connected to lead frame 92. Lead frame 92 is connected to power supply port 3a on logic chip 3. It should be noted that if the end face of power supply wiring layer 2 away from logic chip 3 is exposed by memory chip 1, logic chip 3 may not have power supply port 3a, and power supply wiring layer 2 may be directly connected to substrate 93 (see reference). Figure 18 The power supply port on the device.

[0069] It is worth noting that, in order to more clearly illustrate the connection relationship between lead 91 and lead frame 92 and power supply wiring layer 2, Figure 15 Only one lead 91 and one lead frame 92 are shown. In reality, there can be multiple leads 91 and lead frames 92, which are connected to different power supply wiring 20.

[0070] Continue to refer to Figure 15 Two adjacent memory chips 1 are used to form a chipset 10, and the two adjacent chipsets 10 share a wired communication path. Specifically, the vias 81 of the memory chips 1 in both chipsets 10 are connected to the signal routing layer 83 through a bonding layer 82. The end face of the signal routing layer 83 facing the logic chip 3 is connected to the first solder layer 84, and the first solder layer 84 is connected to the second solder layer 86 through a solder layer 85. Since multiple memory chips 1 share a wired communication path, the number of signal routing layers 83, the first solder layer 84, and the second solder layer 86 can be reduced. In other words, even if the side area of ​​the memory module 100 facing the logic chip 3 is small, the wired communication path can be flexibly arranged. In addition, only two chipsets 10 share a wired communication path, which reduces signal transmission loss. In some other embodiments, each memory chip 1 can also communicate with the logic chip 3 through a separate wired communication unit 8.

[0071] In some embodiments, adjacent chipsets 10 may have two signal routing layers 83, located on the active surfaces 13 of the two memory chips 1, which facilitates signal transmission. In other embodiments, adjacent chipsets 10 may have only one signal routing layer 83.

[0072] In some embodiments, two signal routing layers 83 may be provided in each chipset 10. These two signal routing layers 83 can provide signals to each memory chip 1 respectively, which helps to reduce signal transmission loss.

[0073] It should be noted that the chipset 10 may have multiple wired communication units 8 for transmitting different communication signals. Figure 15 Only one complete wired communication unit 8 is shown.

[0074] In some embodiments, reference Figure 2 , Figure 9 , Figure 11 , Figure 13 , Figure 15 The storage module 100 also includes an insulating film 71, which can be located on the side of the storage module 100 facing or away from the logic chip 3. The insulating film 71 can also be located between adjacent solder bumps 5, thereby isolating the solder bumps 5. Furthermore, the insulating film 71 can be made of a material with good adhesive properties to fix the solder bumps 5. For example, the insulating film 71 can be a polyimide film. Polyimide films have excellent high and low temperature resistance, electrical insulation, and adhesion.

[0075] In some embodiments, a filler adhesive layer 72 is further provided between the logic chip 3 and the memory chip 1, and the filler adhesive layer 72 covers the solder bumps 5. In addition, the filler adhesive layer 72 may also cover the insulating film 71 and the solder pads 32. The filler adhesive layer 72 can fix the solder bumps 5 and the solder pads 32, thereby ensuring the connection strength between the memory module 100 and the logic chip 3.

[0076] In summary, in this embodiment, the distance between the multiple memory chips 1 and the logic chip 3 is the same, thereby avoiding differences in communication latency. Furthermore, a wired power supply is used to power the memory chips 1 to improve power supply stability. Additionally, when the power supply wiring layer 2 is led out from the lower side of the memory module 100, wireless communication is used to provide sufficient space for the solder bumps 5; when the power supply wiring layer 2 is led out from the upper side of the memory module 100, wired communication is used to improve signal transmission quality.

[0077] like Figures 16-17 and Figure 2 As shown, another embodiment of this disclosure also provides a method for manufacturing a semiconductor structure, which can manufacture the semiconductor structure provided in the foregoing embodiments. Detailed description of this semiconductor structure can be found in the foregoing embodiments.

[0078] Specifically, refer to Figure 16 A storage module 100 is provided, which includes a plurality of storage chips 1 stacked in a first direction X; each storage chip 1 has a power supply signal line 12, at least one of the plurality of storage chips 1 has a power supply wiring layer 2, and the power supply wiring layer 2 is electrically connected to the power supply signal line 12; the end face of the power supply wiring layer 2 facing the logic chip 3 is exposed by the storage chip 1; the storage chip 1 also has a solder bump 5, which is electrically connected to the end face.

[0079] Specifically, a power supply wiring layer 2 is first fabricated on the active surface of the memory chip 1, and then the power supply signal line 12 is led to the side edge of the memory chip 1. The material of the power supply wiring layer 2 can be aluminum. A dielectric layer 43 covering the power supply wiring layer 2 and a bonding portion 42 located within the dielectric layer 43 are formed.

[0080] After the bonding portion 42 is formed, multiple memory chips 1 are horizontally stacked and bonded using a hybrid bonding method to form a memory module 100. That is, during the stacking of memory chips 1, the memory chips 1 are placed horizontally.

[0081] refer to Figure 17 The storage module 100 is rotated 90° and a welding bump 5 is prepared on the side of the storage module 100. The welding bump 5 is connected to the power supply wiring layer 2.

[0082] refer to Figure 2 A logic chip 3 is provided, which has a power supply port 3a. A storage module 100 is soldered onto the logic chip 3 such that a first direction X is parallel to the upper surface of the logic chip 3, and a solder bump 5 is electrically connected to the power supply port 3a. For example, the solder bump 5 is soldered to the pad 32 of the logic chip 3 through a solder paste layer 73.

[0083] like Figure 18 As shown, another embodiment of this disclosure also provides a semiconductor device, which includes the semiconductor structure in the foregoing embodiments. For a detailed description of this semiconductor structure, please refer to the foregoing embodiments.

[0084] The semiconductor device includes: a substrate 93; a logic chip 3 disposed on the substrate 93 and having a power supply port 3a; a memory module 100 located on the upper surface of the logic chip 3, the memory module 100 including a plurality of memory chips 1 stacked in a first direction X, the first direction X being parallel to the upper surface of the logic chip 3; each memory chip 1 having a power supply signal line 12, at least one of the plurality of memory chips 1 having a power supply wiring layer 2, and the power supply wiring layer 2 being electrically connected to the power supply signal line 12; the end face of the power supply wiring layer 2 facing or away from the logic chip 3 being exposed by the memory chip; the exposed end face of the power supply wiring layer 2 being electrically connected to the power supply port 3a.

[0085] The substrate 93 provides electrical connection, protection, support, heat dissipation, and assembly for the logic chip 3 and the memory module 100. The logic chip 3 can be connected to the substrate 93 via solder balls 94. A power supply can be provided on the substrate 93, and the power supply port 3a of the logic chip 3 is connected to the power supply on the substrate 93 to supply power to the memory chip 1.

[0086] It should be noted that when the end face of the power supply wiring layer 2 away from the logic chip 3 is exposed, the power supply port 3a may not be located on the logic chip 3, but rather on the substrate 93. The power supply wiring layer 2 is connected to the power supply port on the substrate 93 through conductive structures such as leads 91 and lead frames 92. The power supply port on the substrate 93 is connected to the power supply.

[0087] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0088] Although embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and description of the present disclosure should fall within the scope of the patent coverage of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, include: A logic chip with a power supply port; A storage module is located on the upper surface of the logic chip. The storage module includes a plurality of storage chips stacked in a first direction, which is parallel to the upper surface of the logic chip. Each of the aforementioned memory chips has one of the aforementioned power supply wiring layers; Each of the memory chips has a power supply signal line, and at least one of the plurality of memory chips has a power supply wiring layer, and the power supply wiring layer is electrically connected to the power supply signal line; The end face of the power supply wiring layer facing or away from the logic chip is exposed by the memory chip; The exposed end face of the power supply wiring layer is electrically connected to the power supply port; The memory chip has conductive vias. Two adjacent memory chips constitute a chipset; A bonding portion is provided between two chips in the same chipset, and the bonding portion is connected to the conductive via of the two memory chips to electrically connect the two memory chips; The two power supply wiring layers of the same chipset are located between the two memory chips; Each of the memory chips has a first power supply signal line group and a second power supply signal line group; both the first power supply signal line group and the second power supply signal line group include a plurality of power supply signal lines; Two first power supply signal line groups within the same chipset are connected to one power supply wiring layer, and two second power supply signal line groups within the same chipset are connected to another power supply wiring layer.

2. The semiconductor structure according to claim 1, characterized in that, The two power supply wiring layers of the same chipset are a power wiring layer and a ground wiring layer, respectively; The power supply signal line of the first power supply signal line group is a power signal line, and the first power supply signal line group is connected to the power wiring layer; The power supply signal line of the second power supply signal line group is a ground signal line, and the second power supply signal line group is connected to the ground wiring layer.

3. The semiconductor structure according to claim 1, characterized in that, Both power supply wiring layers of the same chipset are hybrid wiring layers; the hybrid wiring layer includes ground wiring and power wiring; The power supply signal lines of both the first power supply signal line group and the second power supply signal line group include power signal lines and ground signal lines; The power signal line is connected to the power wiring, and the ground signal line is connected to the ground wiring.

4. The semiconductor structure according to claim 1, characterized in that, The power supply signal lines within the same memory chip are connected to the power supply wiring layer; The power supply wiring layers of different memory chips are independent of each other, and the power supply signal lines of different memory chips are independent of each other.

5. The semiconductor structure according to claim 1, characterized in that, A power supply wiring layer is provided between two adjacent memory chips, and the power supply wiring layer is electrically connected to the memory chips on both sides thereof; The storage module has a power supply wiring layer on both ends, and is electrically connected to the storage chips on both ends respectively.

6. The semiconductor structure according to claim 5, characterized in that, The power supply cabling layer includes a power cabling layer and a ground cabling layer. The power cabling layer includes multiple power cablings, and the ground cabling layer includes multiple ground cablings. The power wiring layer and the ground wiring layer are arranged alternately in the first direction.

7. The semiconductor structure according to claim 1, characterized in that, At least two adjacent memory chips are bonded together to form a chipset; A power supply wiring layer is provided between two adjacent chipsets, and the power supply wiring layer is electrically connected to the memory chips of the chipsets on both sides of it; The storage module has a power supply wiring layer on both ends, and is electrically connected to the chipset on both ends respectively.

8. The semiconductor structure according to claim 1, characterized in that, The end face of the power supply wiring layer facing the logic chip is exposed by the memory chip; The memory chip also has solder bumps that are connected to the end face and electrically connected to the power supply port.

9. The semiconductor structure according to claim 8, characterized in that, The logic chip has a first wireless communication unit; the memory chip has a second wireless communication unit; the first wireless communication unit and the second wireless communication unit communicate wirelessly.

10. The semiconductor structure according to claim 9, characterized in that, The second wireless communication unit is located on the side of the memory chip facing the logic chip.

11. The semiconductor structure according to claim 1, characterized in that, The end face of the power supply wiring layer away from the logic chip is exposed by the memory chip; The semiconductor structure further includes: leads and / or lead frames; the leads and / or lead frames are connected between the end face and the power supply port.

12. The semiconductor structure according to claim 11, characterized in that, At least one of the memory chips has a signal wiring layer that is electrically connected to the logic chip; the signal wiring layer is located on the side of the memory chip closer to the logic chip, and the power supply signal line is located on the side of the memory chip farther from the logic chip.

13. A method for manufacturing a semiconductor structure, characterized in that, include: A logic chip is provided, the logic chip having a power supply port; A storage module is provided, the storage module comprising a plurality of storage chips stacked in a first direction; the first direction is parallel to the upper surface of the logic chip; Each of the aforementioned memory chips has one of the aforementioned power supply wiring layers; Each of the memory chips has a power supply signal line, and at least one of the plurality of memory chips has a power supply wiring layer, and the power supply wiring layer is electrically connected to the power supply signal line; the end face of the power supply wiring layer facing or away from the logic chip is exposed by the memory chip; The storage module is soldered onto the logic chip so that the first direction is parallel to the upper surface of the logic chip, and the exposed end face of the power supply wiring layer is electrically connected to the power supply port. The memory chip has conductive vias. Two adjacent memory chips constitute a chipset; A bonding portion is provided between two chips in the same chipset, and the bonding portion is connected to the conductive via of the two memory chips to electrically connect the two memory chips; The two power supply wiring layers of the same chipset are located between the two memory chips; Each of the memory chips has a first power supply signal line group and a second power supply signal line group; both the first power supply signal line group and the second power supply signal line group include a plurality of power supply signal lines; Two first power supply signal line groups within the same chipset are connected to one power supply wiring layer, and two second power supply signal line groups within the same chipset are connected to another power supply wiring layer.

14. A semiconductor device, characterized in that, include: substrate; A logic chip, disposed on the substrate, has a power supply port; A storage module is located on the upper surface of the logic chip. The storage module includes a plurality of storage chips stacked in a first direction, which is parallel to the upper surface of the logic chip. Each of the aforementioned memory chips has one of the aforementioned power supply wiring layers; Each of the memory chips has a power supply signal line, and at least one of the plurality of memory chips has a power supply wiring layer, and the power supply wiring layer is electrically connected to the power supply signal line; The end face of the power supply wiring layer facing or away from the logic chip is exposed by the memory chip; the exposed end face of the power supply wiring layer is electrically connected to the power supply port. The memory chip has conductive vias. Two adjacent memory chips constitute a chipset; A bonding portion is provided between two chips in the same chipset, and the bonding portion is connected to the conductive via of the two memory chips to electrically connect the two memory chips; The two power supply wiring layers of the same chipset are located between the two memory chips; Each of the memory chips has a first power supply signal line group and a second power supply signal line group; both the first power supply signal line group and the second power supply signal line group include a plurality of power supply signal lines; Two first power supply signal line groups within the same chipset are connected to one power supply wiring layer, and two second power supply signal line groups within the same chipset are connected to another power supply wiring layer.

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