Dynamic scaling factor change for irregular ldpc codes

Abstract

The present disclosure provides a decoding method and a memory system that decodes data and estimates a weighted check sum of the decoded data to determine whether the decoding is successful. The weighted check sum is computed based on a first set and a second set, the first set being associated with weights of high order nodes of an irregular parity check matrix, the second set being associated with weights of low order nodes of the irregular parity check matrix.

Description

Technical Field

[0001] This invention relates to scaling of irregular low-density parity-check (LDPC) codes. Background Technology

[0002] The computing environment paradigm has shifted to ubiquitous computing systems that can be used anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased rapidly. These portable electronic devices typically use memory systems with memory devices (i.e., data storage devices). Data storage devices serve as either primary or secondary memory in portable electronic devices. Because they have no moving parts, data storage devices offer excellent stability, durability, high data access speeds, and low power consumption. Examples of data storage devices with these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces, and solid-state drives (SSDs).

[0003] An SSD may include flash memory components and a controller, the controller including electronics that bridge the flash memory components to the SSD input / output (I / O) interface. The SSD controller may include an embedded processor capable of running functional components such as firmware. SSD functional components are device-specific and, in most cases, updatable. Two main types of flash memory components are named after NAND and NOR logic gates. Each flash memory cell exhibits internal characteristics similar to its corresponding gate. NAND flash memory can be written to and read in blocks (or pages) that are typically much smaller than the entire storage space. NOR flash memory allows individual machine words (bytes) to be written to or read individually from an erased location. NAND flash memory primarily operates in memory cards, USB flash drives, solid-state drives, and similar products for general data storage and transfer.

[0004] As described in U.S. Patent No. 10,700,706 (the entire contents of which are incorporated herein by reference), NAND flash memory-based storage devices are widely adopted due to their faster read / write performance, lower power consumption, and shock resistance. However, they are generally more expensive than hard disk drives (HDDs). To reduce costs, NAND flash memory manufacturers have been pushing the limits of their manufacturing processes to 20 nanometers or even lower, which typically results in shorter lifespans and reduced data reliability. Therefore, a stronger error correction code (ECC) than the traditional Bose-Chaudhuri-Hocquenghem (BCH) code is needed to overcome associated noise and interference, thereby improving data integrity. One such ECC is the low-density parity-check (LDPC) code.

[0005] There are different iterative decoding algorithms and related decoders for LDPC codes, such as bit flipping (BF) decoding algorithm, belief propagation (BP) decoding algorithm, sum-product (SP) decoding algorithm, min-sum (MS) decoding algorithm, Min-Max decoding algorithm, etc. Multiple decoding algorithms can be used in a specific system to allow different codewords to be decoded by different decoders according to conditions such as noise level and interference. As described in U.S. Patent No. 7,337,384 (the entire content of which is incorporated herein by reference), existing methods and devices have used checksum-based error handling to provide unequal error detection (UED) for fault-tolerant applications.

[0006] As described in U.S. Patent No. 11,184,024 (the entire content of which is incorporated herein by reference), an LDPC code can be characterized by an M×N parity-check matrix H, and the column weight of the i-th column (0 ≤ i < N) of H is the number of non-zero terms in the i-th column of the parity-check matrix H. If the column weights of all columns of H are the same, the LDPC code represented by H is called a regular LDPC code. Otherwise, the LDPC code is called an irregular LDPC code. In other words, the columns of the parity-check matrix H of an irregular LDPC code have different column weights.

[0007] Irregular LDPC codes are characterized by very sparse parity-check matrices H, where the column weights can vary from column to column and the row weights can vary from row to row. The ability to flexibly allocate column and row weights provides useful design freedoms. In fact, properly designed irregular LDPC codes tend to outperform regular LDPC codes at large block lengths; a gain of up to 0.5 dB can be obtained.

[0008] Due to their flexibility and improved decoding performance, irregular LDPC codes are increasingly used in non-volatile memory systems (e.g., NAND flash memory) to ensure robust data storage and access.

[0009] In this context, embodiments of the present invention have emerged. Summary of the Invention

[0010] Some aspects of the present invention include a decoding method. According to an embodiment of the present invention, the decoding method may include decoding data and estimating a weighted checksum of the decoded data to determine whether the decoding is successful. The weighted checksum is calculated based on a first set and a second set, the first set being associated with the weights of the high-order nodes of an irregular parity-check matrix, and the second set being associated with the weights of the low-order nodes of the irregular parity-check matrix.

[0011] Other aspects of the invention include a memory system. According to embodiments of the invention, the memory system may include a storage device and a decoder, wherein the decoder is configured to decode data and estimate a weighted checksum of the decoded data to determine whether the decoding was successful. The weighted checksum is calculated based on a first set and a second set, the first set being associated with the weights of the higher-order nodes of an irregular parity check matrix, and the second set being associated with the weights of the lower-order nodes of the irregular parity check matrix.

[0012] Other aspects of the invention include a memory controller. According to embodiments of the invention, the memory controller may include a receiver for receiving data and a decoder. Attached Figure Description

[0013] Figure 1 This is a high-level block diagram illustrating an error correction system according to an embodiment of the present invention.

[0014] Figure 2 This is a block diagram schematically illustrating a memory system according to an embodiment of the present invention.

[0015] Figure 3 This is a block diagram illustrating a memory system according to an embodiment of the present invention.

[0016] Figure 4 This is a circuit diagram illustrating a memory block of a memory device according to an embodiment of the present invention.

[0017] Figure 5 This is a diagram illustrating a storage system according to an embodiment of the present invention.

[0018] Figure 6 This is a diagram illustrating the format of codewords to be stored in a storage system according to an embodiment of the present invention.

[0019] Figure 7A It is a description of an irregular low-density parity check matrix.

[0020] Figure 7B This is a description of the dynamic scaling factor change according to an embodiment of the present invention.

[0021] Figure 8 This is a flowchart illustrating dynamic error detection and termination according to an embodiment of the present invention.

[0022] Figure 9 It is a constrained irregular low-density parity check matrix according to an embodiment of the present invention.

[0023] Figure 10 This is a flowchart illustrating a decoding method according to another embodiment of the present invention. Detailed Implementation

[0024] Various embodiments will now be described in more detail with reference to the accompanying drawings. However, the invention may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in the various figures and embodiments of the invention.

[0025] This invention can be embodied in a variety of ways, including as a process; an apparatus; a system; a material component; a computer program product implemented on a computer-readable storage medium; and / or a processor, such as a processor adapted to execute instructions stored on and / or provided by memory linked to the processor. In this specification, these embodiments or any other form in which the invention may be adopted can be referred to as technology. Generally, the order of steps of the disclosed process can be varied within the scope of this invention. Unless otherwise stated, components such as processors or memory described as suitable for performing tasks can be implemented as general components temporarily adapted to perform tasks at a given time or manufactured as specific components for performing tasks. As used herein, the term "processor" refers to one or more means, circuits, and / or processing cores adapted to process data such as computer program instructions.

[0026] The following provides a detailed description of one or more embodiments of the present invention, along with accompanying drawings illustrating the principles of the invention. The invention is described in conjunction with these embodiments, but is not limited to any particular embodiment. The scope of the invention is defined only by the claims, and the invention includes many alternatives, modifications, and equivalents. Numerous specific details are set forth in the following description to provide a thorough understanding of the invention. These details are provided as examples, and the invention may be practiced according to the claims without requiring some or all of these specific details. For clarity, technical materials known in the art related to the invention have not been described in detail so as not to unnecessarily obscure the invention.

[0027] In one embodiment of the invention, as detailed below, the method of the invention imposes constraints on the construction of a parity-check matrix that facilitates error correction of irregular LDPC codes. These constraints divide the irregular LDPC matrix into regions with different weights, for example, into one or more regions with a high-density pattern (regions with high column weights) and into one or more regions with a medium-to-low-density pattern (regions with column weights lower than those of the high-density pattern).

[0028] In another embodiment of the invention, the decoding method of the invention uses a) the weights of the higher-order nodes (higher column weights) of the irregular parity check matrix and b) the weights of the lower-order nodes (lower column weights) of the irregular parity check matrix after decoding to estimate the number of remaining errors.

[0029] In another embodiment of the present invention, the decoding method of the present invention applies a scaling factor to a decoder using the above-described algorithms (LDPC decoding, BF decoding, BP decoding, SP decoding, MS decoding, Min-Max decoding, etc.), wherein the scaling factor is based on the weights of both low-order nodes and high-order nodes.

[0030] Figure 1 This is a high-level block diagram illustrating an error correction system according to an embodiment of the present invention. In the illustrated example, the error correction system may include an encoder and a decoder using an LDPC encoding and decoding algorithm. That is, the error correction system may include an LDPC encoder 5 and an LDPC decoder 15.

[0031] The LDPC encoder 5 can receive information bits including data that needs to be stored in the storage system (or memory system) 10. The LDPC encoder 5 can encode the information bits to output LDPC-encoded data. The LDPC-encoded data from the LDPC encoder 5 can be written to the storage device or memory device of the storage system 10. In various embodiments, the storage device may include various storage types or media. In some embodiments, data is transmitted and received via wired and / or wireless channels during writing to or reading from the storage device. In this case, errors may be introduced into the received codewords during codeword transmission.

[0032] When (e.g., an application or user storing data) requests or otherwise needs data stored in storage system 10, LDPC decoder 15 can perform LDPC decoding on data received from storage system 10, which may include some noise or errors. In various embodiments, LDPC decoder 15 may use decision and / or reliability information of the received data to perform LDPC decoding. The decoded bits generated by LDPC decoder 15 are sent to the appropriate entity (e.g., the user or application that requested it). Through proper encoding and decoding, the information bits are matched with the decoded bits.

[0033] Figure 2 This is a block diagram schematically illustrating a memory system 10 according to an embodiment of the present invention.

[0034] Reference Figure 2 The memory system 10 may include a memory controller 100 and a semiconductor memory device 200.

[0035] The memory controller 100 can control the overall operation of the semiconductor memory device 200.

[0036] The semiconductor memory device 200 can perform one or more erase, program, and read operations under the control of the memory controller 100. The semiconductor memory device 200 can receive commands (CMD), addresses (ADDR), and data (DATA) via input / output lines. The semiconductor memory device 200 can receive power (PWR) via power lines and control signals (CTRL) via control lines. Control signals may include command latch enable (CLE), address latch enable (ALE), chip enable (CE), write enable (WE), and read enable (RE) signals, etc.

[0037] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device. For example, the memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device such as a solid-state drive (SSD). The solid-state drive can include a storage device for storing data. When the semiconductor memory system 10 is used with an SSD, the operating speed of a host (not shown) connected to the memory system 10 can be significantly improved.

[0038] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device, such as a memory card. For example, the memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device to configure memory cards such as: PC cards of the Personal Computer Memory Card International Association (PCMCIA), Compact Flash (CF) cards, Smart Media (SM) cards, Memory Sticks, Multimedia Cards (MMC), Reduced Size Multimedia Cards (RS-MMC), Miniature Version of MMC (Micro MMC), Secure Digital (SD) cards, Mini Secure Digital (Mini SD) cards, Micro Secure Digital (Micro SD) cards, Secure Digital Mass Capacity (SDHC) cards, and Universal Flash Memory (UFS).

[0039] For example, the memory system 10 may be configured to include one of a variety of electronic devices such as: a computer, an ultra-mobile PC (UMPC), a workstation, a netbook computer, a personal digital assistant (PDA), a portable computer, a network tablet PC, a wireless telephone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable gaming device, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a 3D television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device for a data center, a device capable of receiving and transmitting information in a wireless environment, one of the electronic devices for a home network, one of the electronic devices for a computer network, one of the electronic devices for a telematics network, a radio frequency identification (RFID) device, or a computing system device.

[0040] Figure 3 This is a detailed block diagram illustrating a memory system according to an embodiment of the present invention. For example, Figure 3 The memory system can be described Figure 2 The memory system 10 shown.

[0041] Reference Figure 3 ,like Figure 2 As shown, the memory system 10 may include a memory controller 100 and a semiconductor memory device 200. The memory system 10 can operate in response to a request from a host device, and in particular, stores data to be accessed by the host device.

[0042] The host device can be implemented using any of a variety of electronic devices. In some embodiments, the host device may include electronic devices such as: desktop computers, workstations, 3D televisions, smart televisions, digital audio recorders, digital audio players, digital picture recorders, digital picture players, digital video recorders, and digital video players. In some embodiments, the host device may include portable electronic devices such as: mobile phones, smartphones, e-book readers, MP3 players, portable multimedia players (PMPs), and portable game consoles.

[0043] The memory device 200 can store data to be accessed by the host device.

[0044] The memory device 200 can be implemented using volatile memory devices such as dynamic random access memory (DRAM) and static random access memory (SRAM), or non-volatile memory devices such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric random access memory (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), and resistive RAM (RRAM).

[0045] The controller 100 can control the storage of data in the memory device 200. For example, the controller 100 can control the memory device 200 in response to a request from a host device. The controller 100 can provide the host device with data read from the memory device 200 and store the data provided by the host device into the memory device 200.

[0046] The controller 100 may include a storage unit 110, a control unit 120, an error correction code (ECC) unit 130, a host interface 140, and a memory interface 150 connected via a bus 160.

[0047] Storage unit 110 can be used as working memory for memory system 10 and controller 100, and stores data for driving memory system 10 and controller 100. When controller 100 controls the operation of memory device 200, storage unit 110 can store data for operations such as read operation, write operation, program operation and erase operation performed by controller 100 and memory device 200.

[0048] Storage unit 110 can be implemented using volatile memory. Storage unit 110 can be implemented using static random access memory (SRAM) or dynamic random access memory (DRAM). As described above, storage unit 110 can store data used by the host device in storage device 200 for read and write operations. For storing data, storage unit 110 may include program memory, data memory, write buffer, read buffer, mapping buffer, etc.

[0049] The control unit 120 can control the general operation of the memory system 10 and control write or read operations on the memory device 200 in response to write or read requests from the host device. The control unit 120 can drive firmware called a flash translation layer (FTL) to control the general operation of the memory system 10. For example, the FTL can perform operations such as logical-to-physical (L2P) mapping, wear leveling, garbage collection, and bad block handling. L2P mapping is called logical block addressing (LBA).

[0050] ECC unit 130 can detect and correct errors in data read from memory device 200 during a read operation. When the number of error bits is greater than or equal to the threshold number of correctable error bits, ECC unit 130 may not correct the error bits, but may instead output an error correction failure signal indicating that the correction of error bits has failed.

[0051] In some embodiments, ECC unit 130 may perform error correction operations based on coding modulation such as: low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, turbo product codes (TPC), Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), and block-coded modulation (BCM). ECC unit 130 may include all circuitry, systems, or means for error correction operations.

[0052] When using low-density parity-check (LDPC) codes, a bit-flip (BF) decoder can decode LDPC codewords. The BF decoder has limited correction capability and its performance has an error floor. Compared to the BF decoder, the minimum sum (MS) decoder has higher correction capability and can be used for codewords that the BF decoder cannot decode. However, in one embodiment of the invention, the decoding method of the present invention uses one or both of BF decoding and MS decoding.

[0053] like Figure 3 As shown, host interface 140 can communicate with host devices through one or more of the following interface protocols: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and Electronic Integrated Drive (IDE).

[0054] Memory interface 150 provides an interface between controller 100 and memory device 200, allowing controller 100 to control memory device 200 in response to requests from host device. Memory interface 150 can generate control signals for memory device 200 and process data under the control of CPU 120. When memory device 200 is flash memory such as NAND flash memory, memory interface 150 can generate control signals for the memory and process data under the control of CPU 120.

[0055] Memory device 200 may include memory cell array 210, control circuitry 220, voltage generation circuitry 230, row decoder 240, page buffer 250, column decoder 260, and input / output circuitry 270. Memory cell array 210 may include multiple memory blocks 211 and may store data therein. Voltage generation circuitry 230, row decoder 240, page buffer 250, column decoder 260, and input / output circuitry 270 form the peripheral circuitry of memory cell array 210. The peripheral circuitry may perform programming, reading, or erasing operations on memory cell array 210. Control circuitry 220 may control the peripheral circuitry.

[0056] The voltage generation circuit 230 can generate operating voltages with various levels. For example, in an erase operation, the voltage generation circuit 230 can generate operating voltages with various levels, such as erase voltage and pass voltage.

[0057] The row decoder 240 can be connected to the voltage generation circuit 230 and a plurality of memory blocks 211. The row decoder 240 can select at least one memory block among the plurality of memory blocks 211 in response to the row address RADD generated by the control circuit 220, and provide the operating voltage supplied from the voltage generation circuit 230 to the selected memory block among the plurality of memory blocks 211.

[0058] Page buffer 250 can be connected to memory cell array 210 via bit line BL (not shown). Page buffer 250 can precharge bit line BL with a positive voltage in response to page buffer control signal generated by control circuit 220, send data to and receive data from selected memory blocks during programming and read operations, or temporarily store the sent data.

[0059] The column decoder 260 can send data to or receive data from the page buffer 250, or send data to or receive data from the input / output circuit 270.

[0060] Input / output circuit 270 can send commands and addresses from external devices (e.g., memory controller 100) to control circuit 220, send data from external devices to column decoder 260, or output data from column decoder 260 to external devices.

[0061] The control circuit 220 can control the peripheral circuits in response to commands and addresses.

[0062] Figure 4 This is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present invention. For example, Figure 4The storage block can be Figure 3 Storage block 211 in the memory cell array 210 shown.

[0063] Reference Figure 4 The memory block 211 may include multiple cell strings 221 respectively connected to multiple bit lines BL0 to BLm-1. Each cell string may include one or more drain select transistors (DSTs) and one or more source select transistors (SSTs). Multiple memory cells or memory cell transistors may be connected in series between the select transistors DST and SST. Each of the memory cells MC0 to MCn-1 may be formed by a multilayer cell (MLC) that stores multiple bits of data information in each cell. The cell strings 221 may be electrically connected to the corresponding bit lines BL0 to BLm-1 respectively.

[0064] In some embodiments, memory block 211 may include NAND flash memory cells. However, memory block 211 is not limited to NAND flash memory, but may include NOR flash memory, hybrid flash memory combining two or more types of memory cells, and single NAND flash memory with the controller embedded inside the memory chip.

[0065] Figure 5 This is a diagram illustrating a storage system according to an embodiment of the present invention.

[0066] Reference Figure 5 The storage system may include a storage device 550 and a memory controller as a read processor 500. The read processor 500 may perform read operations on data stored in the storage device 550. During a read operation, the read processor 500 may read data from the storage device 550 that may contain some noise or errors, and perform error correction on the read data. In some embodiments, the read processor 500 may include a decoder, for example, an LDPC decoder 510 that may perform LDPC decoding. The read processor may also perform BF decoding and MS decoding. The read processor 500 may include a receiver (not shown) for receiving data from the storage device 550.

[0067] When (e.g., an application or user storing data) requests or otherwise needs the data stored in storage device 550, LDPC decoder 510 can receive data from storage device 550. The received data may include some noise or errors. LDPC decoder 510 can perform detection on the received data and output a decision and / or reliability information. LDPC decoder 510 may include one of a soft detector and a hard detector. Both soft and hard detectors can provide channel information to a decoder such as an LDPC decoder. For example, a soft detector can output reliability information and a decision for each detected bit. On the other hand, a hard detector outputs a decision for each bit without providing corresponding reliability information. As an example, a hard detector can output that a particular bit is "1" or "0" as a hard decision without indicating the degree of certainty or affirmation of that decision by the detector. In contrast, a soft detector can output a decision and the reliability information associated with the decision. Typically, the reliability information indicates the degree of certainty of the detector for a given decision. In one example, a soft detector can output a log-likelihood ratio (LLR), where the sign indicates the decision (e.g., a positive value corresponds to a decision "1" and a negative value corresponds to a decision "0"), and the size indicates how certain or certain the detector is about that decision (e.g., a larger size indicates high reliability or certainty).

[0068] Furthermore, the LDPC decoder 510 can use decision and / or reliability information to perform LDPC decoding. The LDPC decoder 510 may include one of a software decoder and a hardware decoder. The software decoder uses both decision and reliability information to decode the codeword. The hardware decoder uses only the decision value to decode the codeword. The decoded bits generated by the LDPC decoder 510 are sent to the appropriate entity (e.g., the user or application that requested it). Through correct encoding and decoding, the information bits are matched with the decoded bits.

[0069] In various embodiments, a variety of technologies, including application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and / or general-purpose processors (e.g., advanced RISC machine (ARM) cores), can be used for implementation. Figure 5 The system shown.

[0070] LDPC codes can be represented by a bipartite graph. One set of nodes (e.g., variable nodes or bit nodes) corresponds to the elements of the codeword, while another set of nodes (e.g., check nodes) corresponds to a set of parity constraints satisfied by the codeword. Typically, the edges in the bipartite graph are randomly chosen.

[0071] Figure 6 This is a diagram illustrating the format of codeword 600 to be stored in the storage system. (Refer to...) Figure 6The codeword 600 may include information data 610 and parity check 620. In some embodiments, the codeword 600 may be generated using a low-density parity check (LDPC) code. In other words, the information data 610 may be protected by an LDPC code, and the parity check 620 may be an LDPC parity check. The information data 610 may include user data 612 with data path protection (DPP), metadata 614, and cyclic redundancy check (CRC) parity bits 616. CRC codes, as error detection codes commonly used in digital networks and storage devices, can detect accidental alterations to the original data.

[0072] In a typical LDPC decoder, decoding can terminate if the LDPC checksum is zero. The CRC parity bit 616 is calculated after LDPC decoding based on the decoded user data 612 and metadata 614. If the calculated CRC parity bit matches the decoded CRC parity bit, decoding can succeed. Otherwise, a miscalibration may be declared.

[0073] In some embodiments of the present invention, it is assumed that x = [x0, x1, ..., x2]. N-1 ] is a bit vector, H = [h i，j The binary value h is located at the intersection of the i-th row and the j-th column. i，j An M×N low-density parity-check matrix is ​​formed. Each row of H then provides parity checking for x. If x is a codeword of H, then xH T =0.

[0074] Figure 7A This is a description of an example of an irregular parity check matrix H with different column weights in different regions. Figure 7A The parity check matrix H 700 shown comprises six parts: A 705, B 710, T 715, C 720, D 725, and E 730. As is known in the art, the six-part format can be generated using the Richardson-Urbanke (“RU”) algorithm. Figure 7A In the diagram, portions A 705 and C 720 have a width k 750, where k is the size of the information bits of the data to be encoded. Similarly, in the parity check matrix H 700 shown, portions T 715 and E 730 have a width k1 760, where k1 is the size of portion T 715, which can be an identity matrix, as described below. Portions B 710 and D 725 have a width nk-k1 755, where n is the size of the total codeword including information bits and parity bits. Figure 7AIn the middle, parts A 705, parts B 710 and parts T715 have a height k1770. Parts C 720, parts D 725 and parts E 730 have a height nk-k1 775. Figure 7A The parity check matrix H 700 shown is merely illustrative; other irregular parity check matrices may be used in this invention.

[0075] Since H 700 is an irregular parity check matrix, cyclic matrix permutations can be performed to make part of T 715 an identity matrix and reduce the size of the dense matrix D. Given the uneven column weights of the irregular parity check matrix, part of T 715 can be further enlarged (compared to a regular parity check matrix) to reduce the number of loops required for dense matrix computation.

[0076] If we assume that x is transmitted over a noisy channel, then there may be a corrupted channel output y = [y0, y1, ..., y2]. N-1 The hard decision is z = [z0, z1, ..., z]. N-1 The corrector for z can be obtained by passing through s = [s0, s1, ..., s]. N-1 ]=zH T The calculated binary vector, where This represents the number of unsatisfied check nodes and is also referred to as the checksum in this paper. Let z (j) =[z0,z1,…,z N-1 ] represents the hard decision of the j-th iteration, where the corrector vector of the j-th iteration is represented as Then |s| (j) In this paper, it is referred to as the checksum of the j-th iteration.

[0077] Each iteration may include, for example, the process of sending V2C messages from the variable node to the check node, the process of updating the check node's value, the process of sending C2V messages from the check node to the variable node, and the process of updating the variable node's value. When using a column-level hierarchical scheme, the first iteration may include the process of sending V2C messages from the variable node to the check node and the process of updating the check node's value. The initial LLR value of each variable node can be sent to the check node connected to the corresponding variable node.

[0078] In each iteration, the value of a variable node can be updated based on the C2V message received from the verification node. In some embodiments, updating the value of a variable node may include calculating the APP (A-posterior probability) of the variable node and determining the hard decision value of the variable node based on the calculated APP. For example, the scaled least sum (MS) algorithm can be used to calculate the APP corresponding to the variable node in the i-th iteration. When the APP has a negative value, the hard decision value of variable node n can be determined to be "1". When the APP is not negative, the hard decision value of variable node n can be determined to be "0".

[0079] Generally, irregular LDPC codes outperform regular LDPC codes. However, when the number of residual errors is small, scaling in the MS decoder can only be applied late in the decoding process. While this may be sufficiently efficient for regular LDPC codes (since the checksum is a good indicator of the number of residual errors), for irregular LDPC codes, any correlation between the checksum, representing the number of unsatisfied check nodes, and the number of residual errors may become weaker due to the irregular (high, medium, and low) connectivity in the different weights of the variable nodes.

[0080] In the case of irregular LDPC codes, even with a small number of remaining errors in higher-order variable nodes, the checksum can still be large. This makes alpha-beta scaling difficult to apply to irregular LDPC codes and may therefore lead to a high error floor. Generally, alpha-beta scaling provides a method for applying different weighting factors in different iterations. The weighting factor w can be a relatively small number at the beginning of the iteration and gradually increases with each subsequent iteration. For example, in a computation of eight iterations, w could be defined as {0.125, 0.25, 0.5, 0.75, 0.75, 0.75, 0.75, 0.75} for each iteration. This variable-weight-based alpha-beta method can provide convergence for the corrected codeword.

[0081] In one embodiment of the invention, the method of the invention, as detailed below, can apply alpha-beta scaling to irregular LDPC codes, thereby reducing the error threshold.

[0082] In MS decoders, scaling factors are typically applied to aid convergence in later iterations. Typical scaling factor schemes utilize estimators to estimate the number of residual errors. Checksums (or collimator weights) are commonly used as such indicators in regular LDPC codes. However, this invention recognizes that due to the irregularity of the order of variable nodes, checksums generally do not correlate well with the number of residual errors in irregular LDPC codes. In one embodiment of the invention, an inventive estimator (or indicator) for the number of residual errors is provided, applicable to irregular LDPC codes. With the estimator of the invention, (in one embodiment) a method is provided to apply different weighted scaling factors to irregular LDPC codes to compensate for irregular column weight balances, thereby improving convergence in determining the number of residual errors in irregular LDPC codes.

[0083] As mentioned above, the checksum of an LDPC code can be written as s = c' * H, where c' (or z as shown above) (j) =[z0,z1,…,z N-1 ]) is the current hard decision, and H is the parity check matrix.

[0084] In one embodiment of the present invention, for L V2C The message value changes using a dynamic scaling factor, such as Figure 7B As shown. Figure 7B Pseudocode 72 illustrates the Dynamic Scaling Factor Change (OSFC) method of the present invention. Figure 7B In the middle, L v2c This is the message value provided to variable nodes, such as those indicating the LLR (log-likelihood ratio). Therefore, the value in pseudocode 72 of message v2c is represented as L. v2c The value in pseudocode 72 of message C2V is represented as L. c2v .like Figure 7B As shown, L v2c It is the sum of the initial (and scaled α1) value of LLR (Lch / α1) and the subsequent values ​​of message C2V (from the check node to the variable node). For example... Figure 7B As shown, the scaling factor is α2. Figure 7B In this context, maxiter is the maximum number of iterations, and β is the scaling factor that is finally determined at the end of the iteration.

[0085] like Figure 7B As shown, the Dynamic Scaling Factor Change (OSFC) method involves an iterative convergence algorithm 74. It iterates multiple times up to maxiter-1 times by changing the scaling factor α1 based on the calculated checksum value during a single session (i.e., during one iteration), and continues iterating until maxiter times or until the checksum falls below an acceptable threshold T. cS2In this case, α1 is set to β; otherwise, α1 is set to α2.

[0086] Figure 8 This is a flowchart of dynamic error detection and termination. At 801, the cyclic matrix of the irregular low-density parity check matrix H is processed based on the initial scaling factor (or a later updated scaling factor). At 803, the CRC and LPDC checksums are updated. At 805, if the LPDC checksum is zero, decoding terminates at 807 and the successfully decoded word is output. At 805, if the LPDC checksum is not zero, the process proceeds to 809 to determine whether to end the iteration of the scaling factor. If it does not end at 809, the process returns to 801, where the cyclic matrix is ​​processed for a new decoding session. If it ends at 809, the process proceeds to the step of comparing the CRC and LPDC checksums with a threshold T. cs1 The comparison proceeds to 811. If the threshold is met, the process proceeds to 807 (as previously described) to output the successfully decoded word. If the threshold is not met at 811, the process then proceeds to 813 to check if the maximum number of iterations has been reached. If the maximum number has not been reached, the process returns to 801 to loop through and update the scaling factor for a new decoding session. If the maximum number has been reached, the process proceeds to 815 and generates a decoding failure error.

[0087] Weighted checksum as an error estimator

[0088] In irregular codes, the checksum does not correlate well with the number of remaining errors. In one embodiment of the invention, a weighted checksum is used to estimate the number of remaining errors. When constructing the parity check matrix, constraints are applied such that the check nodes are divided into two groups. The first group is connected to higher-order variable nodes (nodes with higher column weights). The second group is connected to mid- and low-order variable nodes (nodes with mid- to low-order column weights). The matrix structure is as follows: Figure 9 As shown. In Figure 9 In the constraint matrix H900, there are cyclic matrices H11, H12, H21, and H22. For example... Figure 9 As shown, the circular matrix H21 is an empty set.

[0089] The partial checksum s_high can be calculated as

[0090] s_high = c(high) * H11

[0091] And s_low can be calculated as

[0092] s_low=c(mid&low)*[H12,H22].

[0093] The weighted checksum can be calculated as

[0094] s_weighted=w_h*s_high+w_l*s_low.

[0095] In one embodiment of the invention, the weights w_h and w_l depend on the average of the column weights of the higher-order variable nodes and the mid- and low-order variable nodes. For example, if the average column weight of the higher-order variable nodes is 10 and the average column weight of the mid- and low-order variable nodes is 4, then quantizing the individual weights by setting w_h = 4 and w_low = 10 (i.e., exchanging weight values) balances the uneven contribution to the checksum due to the irregular LDPC matrix. In this type of alpha-beta scaling, the choice of w_h and w_l is not limited to the example above. Generally, weight values ​​from one or more higher-order regions are replaced with weight values ​​representing one or more regions with lower-order (or column weights), and weight values ​​from one or more lower-order regions are replaced with weight values ​​representing one or more regions with higher-order (or column weights), thereby providing a readjustment of the quantization level.

[0096] In one embodiment of the present invention, Figure 7B and Figure 8 The OSFC algorithm and flowchart in the text use weights that have been readjusted for high-order and low-order nodes, and operate through the above checksum calculations.

[0097] Extended to codes with higher irregularity

[0098] Based on the irregularity of the distribution of variable node weights, in one embodiment of the present invention, the verification nodes can be further divided into more groups, thereby better balancing the irregular contributions of the verification sums of different weight groups.

[0099] Promotion of flip decoders

[0100] Existing methods for improving the decoding operation of error correction devices involve the following steps: a) receiving a noisy codeword, such as one generated by an irregular low-density parity-check (LDPC) codeword; b) performing a first iteration of a bit-flipping algorithm on the noisy codeword (passing messages between multiple variable nodes and multiple check nodes via the bit-flipping algorithm); c) calculating a first corrector based on the output codeword of the first iteration, flipping at least one bit in the output codeword; d) a second corrector; and e) performing subsequent iterations of the bit-flipping algorithm if subsequent iterations are less than the maximum number of iterations.

[0101] In one embodiment of the invention, for the weights of ||s||, the first and second correctors can use the recalibrated weighted checksums described above, where the average column weights are used as alpha-beta scaling. Therefore, the number of residual errors can be better estimated during BF decoding compared to not using a weighted checksum. Thus, in one embodiment of the invention, the aforementioned recalibrated weighted checksum replaces the conventional checksum in the BF decoder to obtain better correction and a deeper error floor, allowing the BF decoder to determine better flip thresholds and error floor mitigation features.

[0102] In one embodiment of the present invention, a method such as... Figure 10 The decoding method is shown below. In step 1001 of this method, the data is decoded. In step 1003, the weighted checksum of the decoded data is estimated to determine whether the decoding was successful. In step 1005, the weighted checksum is calculated based on a first set and a second set. The first set is associated with the weights of the higher-order nodes of the irregular parity check matrix, and the second set is associated with the weights of the lower-order nodes of the irregular parity check matrix (different from the weights of the higher-order nodes). In this method, the weights of the higher-order nodes may depend on the average column weights of the higher-order nodes, and the weights of the lower-order nodes may depend on the average column weights of the lower-order nodes. In this method, the weights of the higher-order nodes and the weights of the lower-order nodes can be interchanged to estimate the weighted checksum.

[0103] In various embodiments of the method, the irregular parity check matrix may include high-order regions with high column weights, separated from low-order regions with low column weights lower than the high column weights. Further, the irregular parity check matrix may include a low-density parity check matrix, and the method may further include determining the LDPC checksum based on low-density parity check LDPC decoding.

[0104] In this method, LDPC decoding can be terminated if the generated CRC parity bits match the initial CRC bits and the LDPC checksum is less than a predetermined threshold. In this method, the scaling value can be adjusted for each iteration of LDPC decoding. In this method, dynamic processing of the cyclic matrix in the parity check matrix can estimate the weighted checksum.

[0105] In this method, a scaling factor based on the weights of low-order and high-order nodes can be applied to a minimum-sum decoder for decoding irregular LDPC codes. In this method, the checksum in the bit-flipped BF decoder can be replaced with an estimated weighted checksum based on the weights of high-order and low-order nodes.

[0106] In another embodiment of the invention, a memory system is provided having a memory device (e.g., a memory cell array 210) and a decoder (e.g., a control circuit 220) coupled to the memory device. Figure 3 (As shown). The decoder is configured to decode the data and estimate the weighted checksum of the decoded data to determine whether the decoding was successful. The weighted checksum is calculated based on a first set and a second set, the first set being associated with the weights of the higher-order nodes of the irregular parity check matrix, and the second set being associated with the weights of the lower-order nodes of the irregular parity check matrix (different from the weights of the higher-order nodes).

[0107] In this memory system, the weights of higher-order nodes can depend on the average column weights of higher-order nodes, while the weights of lower-order nodes can depend on the average column weights of lower-order nodes. In this memory system, the weights of higher-order nodes and lower-order nodes can be interchanged to estimate the weighted checksum.

[0108] In various embodiments of this memory system, the irregular parity check matrix may include high-order regions with high column weights, separated from low-order regions with low column weights. Further, the irregular parity check matrix may include a low-density parity check matrix, and the method may further include determining the LDPC checksum based on low-density parity check LDPC decoding.

[0109] In this memory system, LDPC decoding can be terminated if the generated CRC parity bits match the initial CRC bits and the LDPC checksum is less than a predetermined threshold. The decoder can be configured to adjust the scaling value for each iteration of LDPC decoding. The decoder can be configured to perform dynamic processing of the cyclic matrix in the parity check matrix to estimate the weighted checksum.

[0110] In this memory system, the decoder can be configured to apply a scaling factor based on the weights of both low-order and high-order nodes to a minimum-sum decoder for decoding irregular LDPC codes. The decoder can also be configured to replace the checksum in the bit-flipped BF decoder with an estimated weighted checksum based on the weights of both high-order and low-order nodes.

[0111] Although the foregoing embodiments have been described in detail for clarity of understanding, the invention is not limited to the details provided. Many alternative ways of carrying out the invention exist. The disclosed embodiments are illustrative and not restrictive. The invention is intended to include all modifications and substitutions to the disclosed embodiments. Furthermore, the disclosed embodiments may be combined to form additional embodiments.

[0112] In fact, embodiments of the subject matter and functional operation described in this patent document can be implemented in various systems, digital electronic circuits, or in computer software, firmware, or hardware including the structures disclosed in this specification and their equivalents, or in combinations thereof. Embodiments of the subject matter described in this specification can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a tangible and non-transitory computer-readable medium for execution by a data processing device or for controlling the operation of a data processing device. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a composition of substances affecting machine-readable propagation signals, or combinations thereof. The terms "data processing unit" or "data processing device" encompass all devices, apparatuses, and machines for processing data, including, for example, programmable processors, computers, or multiple processors or computers. In addition to hardware, the device may also include code that creates an operating environment for the computer program in discussion, for example, code constituting processor firmware, a protocol stack, a database management system, an operating system, or combinations thereof.

[0113] Computer programs (also known as programs, software, software applications, scripts, or code) can be written in any form of programming language, including compiled or interpreted languages, and can be deployed in any form, including as standalone programs or as modules, components, subroutines, or other units suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program may be stored as part of a file containing other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinating files (e.g., a file storing parts of one or more modules, subroutines, or code). Computer programs can be deployed to run on a single computer, located in one place, or distributed across multiple computers interconnected by a communications network.

[0114] The processes and logic flows described in this specification can be executed by one or more programmable processors that run one or more computer programs to perform functions by manipulating input data and generating output. The processes and logic flows can also be executed by dedicated logic circuitry, and the device can also be implemented as dedicated logic circuitry, such as an FPGA (Field-Programmable Gate Array) or an ASIC (Application-Specific Integrated Circuit).

[0115] Processors suitable for running computer programs include, for example, general-purpose and special-purpose microprocessors, and any one or more processors in any type of digital computer. Typically, a processor receives instructions and data from read-only memory or random access memory, or both. The fundamental elements of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer also includes one or more mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical disks, or may be operatively coupled to receive data from or send data to the aforementioned mass storage devices, or both. However, a computer does not need to have such devices. Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices. The processor and memory may be supplemented by or incorporated into dedicated logic circuitry.

[0116] Although this patent document includes numerous details, these details should not be construed as limiting the scope of any invention or potentially claimed protection, but rather as a description of features that may be specific to particular embodiments of a particular invention. Certain features described in the context of different embodiments in this patent document may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. Furthermore, although these features may be described above as functioning in certain combinations, in some cases, one or more features from a combination may be removed from that combination, and then that combination may refer to a sub-combination or a variation of a sub-combination.

[0117] Similarly, although operations are described in a specific order in the accompanying drawings, this should not be construed as requiring these operations to be performed in the specific order or sequential order shown, or to perform all of the shown operations to achieve the desired result. Furthermore, the separation of various system components in the embodiments described in this patent document should not be construed as requiring such separation in all embodiments.

[0118] Only some implementation schemes and examples are described, and other implementation schemes, enhancements and variations can be derived based on the content described and shown in this patent document.

Claims

1. A decoding method, comprising: Decode the data; and Estimate the weighted checksum of the decoded data to determine whether the decoding was successful. in, The weighted checksum is calculated based on the first group and the second group. The first group is associated with the weights of the higher-order nodes of the irregular parity check matrix, and The second group is associated with the weights of the lower-order nodes of the irregular parity check matrix.

2. The method according to claim 1, wherein, The weight of the higher-order node depends on the average column weight of the higher-order node, and The weight of a low-order node depends on the average column weight of that low-order node.

3. The method according to claim 2, wherein, The weights of the higher-order nodes are exchanged with the weights of the lower-order nodes to estimate the weighted checksum.

4. The method according to claim 1, wherein, The irregular parity check matrix includes a high-order region with high column weights, which is separated from a low-order region with low column weights that are lower than the high column weights.

5. The method according to claim 1, wherein, The irregular parity check matrix includes a low-density parity check matrix, and The method further includes determining the LDPC checksum based on low-density parity-check decoding, i.e., LDPC decoding.

6. The method of claim 5, further comprising terminating the LDPC decoding if the generated CRC parity bit matches the initial CRC bit and the LDPC checksum is less than a predetermined threshold.

7. The method of claim 5, further comprising adjusting the scaling value for each iteration of the LDPC decoding.

8. The method according to claim 1, wherein, Estimating the weighted checksum includes dynamically processing the cyclic matrix in the parity check matrix.

9. The method of claim 1, further comprising applying a scaling factor based on the weights of both the low-order node and the high-order node to a minimum-sum decoder for decoding irregular LDPC codes.

10. The method of claim 1, further comprising replacing the checksum in the bit-flipped BF decoder with an estimated weighted checksum based on the weights of the higher-order nodes and the lower-order nodes.

11. A memory system, comprising: Storage devices; as well as The decoder is connected to the storage device and: Decode the data; and Estimate the weighted checksum of the decoded data to determine whether the decoding was successful. in, The weighted checksum is calculated based on the first group and the second group. The first group is associated with the weights of the higher-order nodes of the irregular parity check matrix, and The second group is associated with the weights of the lower-order nodes of the irregular parity check matrix.

12. The memory system according to claim 11, wherein, The weight of the higher-order node depends on the average column weight of the higher-order node, and The weight of a low-order node depends on the average column weight of that low-order node.

13. The memory system according to claim 11, wherein, The weights of the higher-order nodes are exchanged with the weights of the lower-order nodes to estimate the weighted checksum.

14. The memory system according to claim 11, wherein, The irregular parity check matrix includes a high-order region with high column weights, which is separated from a low-order region with low column weights that are lower than the high column weights.

15. The memory system according to claim 11, wherein, The parity check matrix includes a low-density parity check matrix, and The decoder determines the LDPC checksum based on low-density parity-check decoding, i.e., LDPC decoding.

16. The memory system according to claim 15, wherein, If the generated CRC parity bit matches the initial CRC bit and the LDPC checksum is less than a predetermined threshold, the decoder terminates the LDPC decoding.

17. The memory system of claim 15, wherein the decoder adjusts the scaling value for each iteration of the LDPC decoding.

18. The memory system of claim 11, wherein the decoder estimates the weighted checksum by dynamically processing the cyclic matrix in the parity check matrix.

19. The memory system of claim 11, wherein the decoder applies a scaling factor based on the weights of both the low-order nodes and the high-order nodes to a minimum-sum decoder for decoding irregular LDPC codes.

20. The memory system of claim 11, wherein the decoder replaces the checksum in the bit-flipped BF decoder with an estimated weighted checksum based on the weights of the higher-order nodes and the lower-order nodes.

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