Controlling rough pixel size from stencil print buffer

Abstract

This application discloses controlling a rough pixel size from stencil print buffers. Systems, apparatuses, and methods can provide techniques to determine a stencil print value and use the stencil print value to control a rough pixel size of a graphics pipeline through a stencil print buffer. Additionally, the stencil print value can include a first bit range defining a first dimension of the rough pixel size and a second bit range defining a second dimension of the rough pixel size. In one example, the rough pixel size is controlled pixel by pixel for a plurality of pixels.

Description

[0001] This application is a divisional application of the invention patent application filed on April 9, 2018, with a priority date of April 10, 2017, application number 201810320707.9, entitled "Controlling coarse pixel size from a stencil printing buffer". Technical Field

[0002] The embodiments generally relate to graphics processing architecture. More specifically, the embodiments relate to controlling coarse pixel size from a stencil buffer within the graphics processing architecture. Background Technology

[0003] Pixel shading in graphics processing architectures is used to determine the color, brightness, and other visual parameters of pixels in an image presented on a display. To allow shading at a rate lower than once per pixel, the concept of coarse pixel shading is used. A coarse pixel (CP) can typically be a group of pixels that share a single coarse pixel shader (CPS) for evaluation. Currently, the size of a CP can be flat / constant across the entire screen or a variable vertex attribute that is interpolated and quantized. Compared to pixel shading, coarse pixel shading can have a lower shading resolution (e.g., less detail). Therefore, coarse pixel shading can achieve a trade-off between shading detail and energy efficiency (e.g., reduced power consumption). Attached Figure Description

[0004] The various advantages of the embodiments will become apparent to those skilled in the art from the following description and appended claims, and from the following drawings, in which:

[0005] Figure 1 This is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;

[0006] Figures 2A to 2D A parallel processor component according to an embodiment is shown;

[0007] Figures 3A to 3B This is a block diagram of a graphics multiprocessor according to an embodiment;

[0008] Figures 4A to 4F An exemplary architecture is shown, in which multiple GPUs are communicatively coupled to multiple multi-core processors;

[0009] Figure 5 Demonstrates a graphics processing pipeline according to an embodiment;

[0010] Figure 6 This is a demonstration of an example of determining the coarse pixel size according to an embodiment;

[0011] Figure 7This is a demonstration of an example of template printing values ​​according to an embodiment;

[0012] Figure 8 This is a flowchart illustrating an example of a method for operating a semiconductor package device according to an embodiment;

[0013] Figure 9 This is a block diagram of an example computing system according to an embodiment;

[0014] Figure 10 This is a demonstration of an example of a semiconductor package device according to an embodiment;

[0015] Figure 11 This is a diagram of an example of a head-mounted display (HMD) system according to an embodiment;

[0016] Figure 12 According to the embodiments, it includes in Figure 11 A block diagram illustrating an example of functional components in an HMD system;

[0017] Figure 13 This is a block diagram of an example of a general-purpose processing cluster included in a parallel processing unit according to an embodiment;

[0018] Figure 14 This is a conceptual diagram illustrating an example of a graphics processing pipeline that can be implemented within a parallel processing unit according to an embodiment;

[0019] Figure 15 This is a block diagram of an example of a streaming multiprocessor according to an embodiment;

[0020] Figures 16 to 18 This is a block diagram illustrating an example overview of a data processing system according to an embodiment;

[0021] Figure 19 This is a block diagram of an example of a graphics processing engine according to an embodiment;

[0022] Figures 20 to 22 This is a block diagram of an example execution unit according to an embodiment;

[0023] Figure 23 This is a block diagram illustrating an example of a graphical pipeline according to an embodiment;

[0024] Figures 24A to 24B This is a block diagram illustrating an example of a graphical pipeline according to an embodiment;

[0025] Figure 25 This is a block diagram illustrating an example of a graphical software architecture according to an embodiment;

[0026] Figure 26 This is a block diagram of an example intellectual property (IP) core development system according to an embodiment; and

[0027] Figure 27 This is a block diagram of an example of a system-on-chip integrated circuit according to an embodiment. Detailed Implementation

[0028] In the following description, numerous details are set forth to provide a more complete understanding of this disclosure. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these specific details. In other instances, well-known features have not been described so as not to hinder the invention.

[0029] System Overview

[0030] Figure 1 This is a block diagram illustrating a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104, the processors communicating with the system memory via an interconnect path that may include a memory hub 105. The memory hub 105 may be a separate component within a chipset assembly or may be integrated within one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107 that enables the computing system 100 to receive input from one or more input devices 108. Additionally, the I / O hub 107 enables a display controller to provide output to one or more display devices 110A, the display controller being included within one or more processors 102. In one embodiment, the one or more display devices 110A coupled to the I / O hub 107 may include local, internal, or embedded display devices.

[0031] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112 coupled to a memory hub 105 via a bus or other communication link 113. The communication link 113 may be any number of standards-based communication link technologies or protocols (e.g., but not limited to, PCI Fast Bus), or it may be a vendor-specific communication interface or communication architecture. In one embodiment, the one or more parallel processors 112 form a computationally centralized parallel or vector processing system comprising a large number of processing cores and / or processing clusters (e.g., integrated many-core (MIC) processors). In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one or more display devices 110A coupled via an I / O hub 107. The one or more parallel processors 112 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 110B.

[0032] Within the I / O subsystem 111, system storage unit 114 can be connected to I / O hub 107 to provide a storage mechanism for computing system 100. I / O switch 116 can be used to provide an interface mechanism for connecting I / O hub 107 to other components (e.g., network adapter 118 and / or wireless network adapter 119 that can be integrated into the platform, and various other devices that can be added via one or more plug-in devices 120). Network adapter 118 can be an Ethernet adapter or another wired network adapter. Wireless network adapter 119 can include one or more of the following: Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more radio devices.

[0033] The computing system 100 may include other components not explicitly shown, including USB or other port connectors, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 107. Figure 1 The communication paths for interconnecting the various components can be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI Fast Bus) or any other bus or point-to-point communication interface and / or protocol (e.g., NV-Link High-Speed ​​Interconnect, or interconnect protocols known in the art).

[0034] In one embodiment, one or more parallel processors 112 include circuitry optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). In another embodiment, one or more parallel processors 112 include circuitry optimized for general-purpose processing while maintaining the underlying computing architecture described in more detail herein. In yet another embodiment, components of the computing system 100 may be integrated on a single integrated circuit along with one or more other system elements. For example, one or more parallel processors 112, memory hub 105, processor 102, and I / O hub 107 may be integrated into a system-on-a-chip (SoC) integrated circuit. Alternatively, components of the computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM), which may interconnect with other multi-chip modules to a modular computing system.

[0035] It will be appreciated that the computing system 100 shown herein is illustrative, and various variations and modifications are possible. The connection topology can be modified as needed, including the number and rows of bridges, the number of processors(102), and the number of parallel processors(112). For example, in some embodiments, system memory 104 is connected directly to processors(102) rather than via bridges, while other devices communicate with system memory 104 via memory hub 105 and processors(102). In other alternative topologies, parallel processors(112) are connected to I / O hub 107 or directly to one or more processors(102), rather than to memory hub 105. In other embodiments, I / O hub 107 and memory hub 105 may be integrated into a single chip. Some embodiments may include two or more sets of processors(102) attached via multiple sockets, which may be coupled to two or more instances of parallel processors(112).

[0036] Some specific components shown in this document are optional and may not be included in all implementations of the computing system 100. For example, any number of plug-in cards or peripherals may be supported, or some components may be eliminated. Furthermore, some architectures may be adapted to... Figure 1 The components shown in the diagram use different terminology for similar components. For example, in some architectures, the memory hub 105 may be called the Northbridge, while the I / O hub 107 may be called the Southbridge.

[0037] Figure 2A A parallel processor 200 according to an embodiment is illustrated. Various components of the parallel processor 200 can be implemented using one or more integrated circuit devices, such as a programmable processor, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). According to the embodiment, the illustrated parallel processor 200 is... Figure 1 One or more variants of the parallel processor 112 shown.

[0038] In one embodiment, the parallel processor 200 includes a parallel processing unit 202. The parallel processing unit includes an I / O unit 204 that enables communication with other devices, including other instances of the parallel processing unit 202. The I / O unit 204 may be directly connected to other devices. In one embodiment, the I / O unit 204 is connected to other devices via a hub or switch interface (e.g., a memory hub 105). The connection between the memory hub 105 and the I / O unit 204 forms a communication link 113. Within the parallel processing unit 202, the I / O unit 204 is connected to a host interface 206 and a memory crossbar 216, wherein the host interface 206 receives commands relating to performing processing operations, and the memory crossbar 216 receives commands relating to performing memory operations.

[0039] When host interface 206 receives a command buffer via I / O unit 204, host interface 206 can direct work operations for executing those commands to front end 208. In one embodiment, front end 208 is coupled to scheduler 210, which is configured to distribute commands or other work items to processing cluster array 212. In one embodiment, scheduler 210 ensures that processing cluster array 212 is properly configured and active before tasks are distributed to the processing clusters of processing cluster array 212. In one embodiment, scheduler 210 is implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granular levels, enabling fast preemption and context switching of threads executing on processing array 212. In one embodiment, host software can validate workloads for scheduling on processing array 212 via one of a plurality of image processing doorbells. The workload can then be automatically distributed across processing array 212 by scheduler 210 logic within the scheduler microcontroller.

[0040] Processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, up to cluster 214N). Each cluster 214A-214N of processing cluster array 212 can execute a large number of concurrent threads. Scheduler 210 may use various scheduling and / or work distribution algorithms to allocate work to clusters 214A-214N of processing cluster array 212, and these algorithms may vary depending on the workload generated for each type of program or computation. Scheduling may be handled dynamically by scheduler 210 or may be partially assisted by compiler logic during compilation of the program logic configured for execution by processing cluster array 212. In one embodiment, different clusters 214A-214N of processing cluster array 212 may be assigned to process different types of programs or to perform different types of computations.

[0041] The processing cluster array 212 can be configured to perform various types of parallel processing operations. In one embodiment, the processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, the processing cluster array 212 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations (including physical operations), and performing data transformations.

[0042] In one embodiment, the processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where the parallel processor 200 is configured to perform graphics processing operations, the processing cluster array 212 may include additional logic for supporting the performance of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. Additionally, the processing cluster array 212 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit 202 may pass data from system memory for processing via I / O unit 204. During processing, the passed data may be stored in on-chip memory (e.g., parallel processor memory 222) and then written back to system memory.

[0043] In one embodiment, when the parallel processing unit 202 is used to perform graphics processing, the scheduler 210 can be configured to divide the processing workload into approximately equal-sized tasks to better enable the distribution of graphics processing operations across multiple clusters 214A to 214N in the processing cluster array 212. In some embodiments, multiple portions of the processing cluster array 212 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. Intermediate data generated by one or more of the clusters 214A to 214N can be stored in a buffer to allow the intermediate data to be transferred between clusters 214A to 214N for further processing.

[0044] During operation, the processing cluster array 212 may receive processing tasks to be executed via a scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, a processing task may include an index of data to be processed (e.g., surface (patch) data, primitive data, vertex data, and / or pixel data), as well as state parameters and commands defining how the data should be processed (e.g., what program to execute). The scheduler 210 may be configured to retrieve the indexes corresponding to the task, or may receive these indexes from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured to be active before initiating a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.).

[0045] Each of one or more instances of parallel processing unit 202 may be coupled to parallel processor memory 222. Parallel processor memory 222 may be accessed via memory crossbar switch 216, which receives memory requests from processing cluster array 212 and I / O unit 204. Memory crossbar switch 216 may access parallel processor memory 222 via memory interface 218. Memory interface 218 may include multiple partition units (e.g., partition unit 220A, partition unit 220B, up to partition unit 220N), each partition unit being coupled to a portion (e.g., memory cell) of parallel processor memory 222. In one implementation, the number of partition units 220A-220N is configured equal to the number of memory cells, such that a first partition unit 220A has a corresponding first memory cell 224A, a second partition unit 220B has a corresponding memory cell 224B, and the Nth partition unit 220N has a corresponding Nth memory cell 224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory devices.

[0046] In various embodiments, memory cells 224A to 224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory (e.g., synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory). In one embodiment, memory cells 224A to 224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will recognize that the specific implementation of memory cells 224A to 224N can vary and may be selected from a variety of conventional designs. Render targets (e.g., frame buffers or texture maps) may be stored across memory cells 224A to 224N, thereby allowing partitioning cells 220A to 220N to write in parallel to multiple portions of each render target to efficiently utilize the available bandwidth of parallel processor memory 222. In some embodiments, local instances of parallel processor memory 222 may be excluded to facilitate a unified memory design that utilizes system memory by incorporating local cache memory.

[0047] In one embodiment, any of the clusters 214A-214N of the processing cluster array 212 can process data to be written to any of the memory cells 224A-224N within the parallel processor memory 222. The memory crossbar switch 216 can be configured to pass the output of each cluster 214A-214N to any partition cell 220A-220N or another cluster 214A-214N on which additional processing operations can be performed. Each cluster 214A-214N can communicate with the memory interface 218 via the memory crossbar switch 216 to read from or write to various external memory devices. In one embodiment, the memory crossbar switch 216 has a connection to the memory interface 218 for communication with the I / O unit 204 and a connection to a local instance of the parallel processor memory 222, thereby enabling processing units within different processing clusters 214A-214N to communicate with system memory or other memory not local to the parallel processing unit 202. In one embodiment, the memory crossbar switch 216 may use a virtual channel to separate traffic flows between clusters 214A-214N and partition units 220A-220N.

[0048] While a single instance of the parallel processing unit 202 is shown within the parallel processor 200, any number of instances of the parallel processing unit 202 may be included. For example, multiple instances of the parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Different instances of the parallel processing unit 202 may be configured to interoperate even if these different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, and in one embodiment, some instances of the parallel processing unit 202 may include higher precision floating-point units relative to other instances. Systems including one or more instances of the parallel processing unit 202 or the parallel processor 200 may be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0049] Figure 2B This is a block diagram of partitioning unit 220 according to an embodiment. In one embodiment, partitioning unit 220 is... Figure 2AAn example of one of partition units 220A to 220N. As shown, partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from memory crossbar switch 216 and ROP 226. Read misses and urgent write-back requests are output by the L2 cache 221 to the frame buffer interface 225 for processing. Updates can also be sent to the frame buffer for processing via the frame buffer interface 225. In one embodiment, the frame buffer interface 225 intersects with one of the memory cells in the parallel processor memory (e.g., memory cells 224A to 224N of FIG. 2 (e.g., within parallel processor memory 222)).

[0050] In graphics applications, ROP 226 is a processing unit that performs raster operations such as stencil printing, z-testing, blending, etc. ROP 226 then outputs processed graphics data stored in graphics memory. In some embodiments, ROP 226 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. The compression logic can be a lossless compression logic utilizing one or more of various compression algorithms. The type of compression performed by ROP 226 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, Δcolor compression is performed on a tile-by-tile basis on both depth and color data.

[0051] In some embodiments, ROP 226 is included within each processing cluster (e.g., clusters 214A to 214N of FIG. 2) rather than within partition unit 220. In such embodiments, read and write requests for pixel data, rather than pixel fragment data, are transmitted via memory crossbar switch 216. Processed graphics data can be displayed on a display device (e.g., Figure 1 Displayed on one or more display devices 110, routed for further processing by processor(s) 102, or routed for use by Figure 2A One of the processing entities within the parallel processor 200 is further processed.

[0052] Figure 2CThis is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A to 214N of FIG. 2. The processing cluster 214 can be configured to execute a number of threads in parallel, wherein the term "thread" refers to an instance of a specific program executing on a particular set of input data. In some embodiments, a Single Instruction Multiple Data (SIMD) instruction issuance technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, a Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of generally synchronous threads, wherein the common instruction unit is configured to issue instructions to a set of processing engines within each of the processing clusters. Unlike the SIMD execution regime (where all processing engines typically execute the same instructions), SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will understand that the SIMD processing regime represents a functional subset of the SIMT processing regime.

[0053] The operation of the processing cluster 214 can be controlled via a pipeline manager 232, which distributes processing tasks to SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of FIG. 2 and manages the execution of those instructions via the graphics multiprocessor 234 and / or texture unit 236. The graphics multiprocessor 234 shown is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors with different architectures can be included within the processing cluster 214. One or more instances of the graphics multiprocessor 234 can be included within the processing cluster 214. The graphics multiprocessor 234 can process data, and the data crossover switch 240 can be used to distribute the processed data to one of several possible destinations (including other shader units). The pipeline manager 232 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossover switch 240.

[0054] Each graphics multiprocessor 234 within the processing cluster 214 can include the exact same set of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). The functional execution logic can be configured in a pipelined manner, where new instructions can be issued before previous instructions complete. The functional execution logic supports a wide variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and computation of various algebraic functions. In one embodiment, different operations can be performed using the same functional unit hardware, and any combination of functional units can exist.

[0055] Instructions transmitted to processing cluster 214 constitute threads. A group of threads executing across a set of parallel processing engines is a thread group. Thread groups execute the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 234. A thread group may include fewer threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is being processed. A thread group may also include more threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within graphics multiprocessor 234, processing can be performed on consecutive clock cycles. In one embodiment, multiple thread groups can be executed concurrently on graphics multiprocessor 234.

[0056] In one embodiment, the graphics multiprocessor 234 includes an internal cache memory for performing load and store operations. In another embodiment, the graphics multiprocessor 234 may forgo the internal cache and use a cache memory within the processing cluster 214 (e.g., L1 cache 308). Each graphics multiprocessor 234 also has access to an L2 cache within a partition unit (e.g., partition units 220A to 220N of FIG. 2) that is shared across all processing clusters 214 and can be used to transfer data between threads. The graphics multiprocessor 234 may also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. Any memory outside the parallel processing unit 202 may be used as global memory. Multiple embodiments (where the processing cluster 214 includes multiple instances of the graphics multiprocessor 234) may share common instructions and data, which may be stored in the L1 cache 308.

[0057] Each processing cluster 214 may include an MMU 245 (Memory Management Unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 245 may reside within the memory interface 218 of FIG2. The MMU 245 includes: a set of page table entries (PTEs) for mapping virtual addresses of tiles (more specifically tiling) to physical addresses; and optionally, a cache line index. The MMU 245 may include an address translation lookahead buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or the L1 cache or processing cluster 214. Physical addresses are processed to distribute surface data access locality, thereby allowing efficient request interleaving within partitioned units. The cache line index can be used to determine whether a request for a cache line is a hit or a miss.

[0058] In graphics and computing applications, processing cluster 214 may be configured such that each graphics multiprocessor 234 is coupled to texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data may be read from an internal texture L1 cache (not shown) or, in some embodiments, from an L1 cache within the graphics multiprocessor 234, and may be retrieved from an L2 cache, local parallel processor memory, or system memory, as needed. Each graphics multiprocessor 234 outputs processed tasks to data crossover switch 240 to provide the processed tasks to another processing cluster 214 for further processing or to store the processed tasks in L2 cache, local parallel processor memory, or system memory via memory crossover switch 216. PreROP 242 (e.g., pre-raster operation unit) is configured to receive data from graphics multiprocessor 234 and direct the data to ROP units, which may be located alongside partitioning units as described herein (e.g., partitioning units 220A to 220N of FIG. 2). The preROP 242 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0059] It will be appreciated that the core architecture described herein is illustrative, and various variations and modifications are possible. Any number of processing units (e.g., graphics multiprocessors 234, texture units 236, preROP 242, etc.) may be included within processing cluster 214. Furthermore, although only one processing cluster 214 is shown, parallel processing units as described herein may include any number of instances of processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0060] Figure 2D A graphics multiprocessor 234 according to one embodiment is illustrated. In such an embodiment, the graphics multiprocessor 234 is coupled to a pipeline manager 232 of a processing cluster 214. The graphics multiprocessor 234 has an execution pipeline including, but not limited to: an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general-purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0061] In one embodiment, instruction cache 252 receives a stream of instructions to be executed from pipeline manager 232. These instructions are cached in instruction cache 252 and dispatched for execution by instruction unit 254. Instruction unit 254 can dispatch instructions into thread groups (e.g., thread bundles), where each thread in the thread group is assigned to a different execution unit within GPGPU core 262. Instructions can access either the local, shared, or global address space by specifying an address within a unified address space. Address mapping unit 256 can be used to translate addresses in the unified address space into distinct memory addresses that can be accessed by load / store unit 266.

[0062] Register file 258 provides a set of registers for the functional units of graphics multiprocessor 324. Register file 258 provides temporary storage for operands on data paths connected to functional units of graphics multiprocessor 324 (e.g., GPGPU core 262, load / store unit 266). In one embodiment, register file 258 is partitioned among each of these functional units, such that each functional unit is allocated a dedicated portion of register file 258. In another embodiment, register file 258 is partitioned among different thread bundles executed by graphics multiprocessor 324.

[0063] Each GPGPU core 262 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 324. According to embodiments, the GPGPU cores 262 may be architecturally similar or architecturally different. For example, in one embodiment, a first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or may implement variable-precision floating-point arithmetic. The graphics multiprocessor 324 may additionally include one or more fixed-function or special-function units to perform specific functions (e.g., copying rectangles or pixel blending operations). In one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0064] In one embodiment, GPGPU core 262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, GPGPU core 262 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or can be automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. Multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, in one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0065] The memory and cache interconnect 268 is an interconnect network that connects each functional unit of the graphics multiprocessor 234 to the register file 258 and to the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a cross-switch interconnect that allows the load / store unit 266 to perform load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, resulting in very low latency for data transfer between the GPGPU core 262 and the register file 258. The shared memory 270 can be used to implement communication between threads executing on functional units within the graphics multiprocessor 234. The cache memory 272 can be used, for example, as a data cache to cache texture data communicated between functional units and texture units 236. The shared memory 270 can also be used as a program-managed cache. Threads executing on the GPGPU core 262 can programmatically store data in the shared memory other than the automatically cached data stored in the cache memory 272.

[0066] Figures 3A to 3B An additional graphics multiprocessor according to an embodiment is shown. The graphics multiprocessors 325 and 350 shown are... Figure 2C A variant of the graphics multiprocessor 234. The graphics multiprocessors 325 and 350 shown can be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0067] Figure 3A A graphics multiprocessor 325 according to an additional embodiment is shown. The graphics multiprocessor 325 is relative to... Figure 2DThe graphics multiprocessor 234 includes multiple additional instances of execution resource units. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A to 332B, register files 334A-334B, and texture units 344A-344B. The graphics multiprocessor 325 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A to 336B, GPGPU cores 337A to 337B, GPGPU cores 338A to 338B) and multiple sets of load / store units 340A to 340B. In one embodiment, the execution resource units have a common instruction cache 330, a texture and / or data cache memory 342, and a shared memory 346.

[0068] Various components can communicate via interconnect structure 327. In one embodiment, interconnect structure 327 includes one or more crossbar switches to enable communication between various components of the graphics multiprocessor 325. In one embodiment, interconnect structure 327 is a separate high-speed network structure layer on which each component of the graphics multiprocessor 325 is stacked. Components of the graphics multiprocessor 325 communicate with remote components via interconnect structure 327. For example, GPGPU cores 336A-336B, 337A-337B, and 338A-338B can each communicate with shared memory 346 via interconnect structure 327. Interconnect structure 327 can arbitrate communication within the graphics multiprocessor 325 to ensure fair bandwidth allocation among components.

[0069] Figure 3B A graphics multiprocessor 350 according to an additional embodiment is illustrated. The graphics processor includes multiple sets of execution resources 356A to 356D, wherein each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load memory units, such as... Figure 2D and Figure 3A As shown in the diagram. Execution resources 356A to 356D can work in harmony with texture units 360A to 360D for texture operations, while sharing instruction cache 354 and shared memory 362. In one embodiment, execution resources 356A to 356D can share multiple instances of instruction cache 354, shared memory 362, and texture and / or data cache memories 358A to 358B. Various components can be connected via a network similar to... Figure 3A The interconnection structure 327 communicates with the interconnection structure 352.

[0070] Those skilled in the art will understand that Figure 1 , Figures 2A to 2D as well as Figures 3A to 3BThe architecture described herein is descriptive and non-limiting for the purposes of this embodiment. Therefore, the techniques described herein can be implemented on any properly configured processing unit without departing from the scope of the embodiments described herein, including but not limited to one or more mobile application processors, one or more desktop computer or server central processing units (CPUs) (including multi-core CPUs), one or more parallel processing units (e.g., parallel processing unit 202 of FIG2), and one or more graphics processors or dedicated processing units.

[0071] In some embodiments, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as these cores and communicatively coupled to these cores via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0072] Technologies for GPU-to-host processor interconnect

[0073] Figure 4A An exemplary architecture is illustrated, in which multiple GPUs 410 to 413 are communicatively coupled to multiple multi-core processors 405 to 406 via high-speed links 440 to 443 (e.g., bus, point-to-point interconnect, etc.). In one embodiment, depending on the implementation, high-speed links 440 to 443 support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the basic principles of the invention are not limited to any particular communication protocol or throughput.

[0074] Additionally, in one embodiment, two or more of GPUs 410 to 413 are interconnected via high-speed links 444 to 445, which may be implemented using the same or different protocols / links as those used for high-speed links 440 to 443. Similarly, two or more of multi-core processors 405 to 406 may be connected via high-speed link 433, which may be a symmetric multiprocessor (SMP) bus operating at 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, Figure 4AAll communication between the various system components shown can be achieved using the same protocol / link (e.g., via a common interconnect structure). However, as mentioned, the basic principles of the invention are not limited to any particular type of interconnect technology.

[0075] In one embodiment, each multi-core processor 405 to 406 is communicatively coupled to processor memories 401 to 402 via memory interconnects 430 to 431, and each GPU 410 to 413 is communicatively coupled to GPU memories 420 to 423 via GPU memory interconnects 450 to 453. Memory interconnects 430 to 431 and 450 to 453 may utilize the same or different memory access technologies. By way of example and without limitation, processor memories 401 to 402 and GPU memories 420 to 423 may be volatile memories, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or may be non-volatile memories, such as 3D XPoint or nanometer random access memory. In one embodiment, a portion of the memory may be volatile memory, and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0076] As described below, although the various processors 405 to 406 and GPUs 410 to 413 can be physically coupled to specific memories 401 to 402 and 420 to 423 respectively, a unified memory architecture can be implemented, in which the same virtual system address space (also known as the “effective address” space) is distributed across all the various physical memories. For example, processor memories 401 to 402 can each include 64GB of system memory address space, and GPU memories 420 to 423 can each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0077] Figure 4B Additional details are shown regarding the interconnect between a multi-core processor 407 and a graphics acceleration module 446 according to one embodiment. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card coupled to the processor 407 via a high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0078] The processor 407 shown includes multiple cores 460A to 460D, each core having translation lookaside buffers 461A to 461D and one or more caches 462A to 462D. These cores may include various other components for executing instructions and processing data, which are not shown to avoid obscuring the fundamental principles of the invention (e.g., instruction fetch unit, branch prediction unit, decoder, execution unit, reordering buffer, etc.). Caches 462A to 462D may include Level 1 (L1) and Level 2 (L2) caches. Additionally, one or more shared caches 426 may be included in the cache hierarchy and shared by multiple sets of cores 460A to 460D. For example, one embodiment of the processor 407 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. The processor 407 and graphics accelerator integration module 446 are connected to the system memory 441, which may include processor memories 401 to 402.

[0079] The consistency of data and instructions stored in various caches 462A to 462D, 456 and system memory 441 is maintained via inter-core communication on the consistency bus 464. For example, each cache may have associated cache consistency logic / circuit to communicate via the consistency bus 464 in response to a detected read or write to a specific cache line. In one implementation, a cache snooping protocol is implemented via the consistency bus 464 to snoop on cache accesses. Cache snooping / consistency techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the basic principles of the invention.

[0080] In one embodiment, proxy circuitry 425 communicatively couples graphics acceleration module 446 to coherence bus 464, thereby allowing graphics acceleration module 446 to participate in cache coherence protocols as a peer of the core. Specifically, interface 435 provides connectivity to proxy circuitry 425 via high-speed link 440 (e.g., PCIe bus, NVLink, etc.), and interface 437 connects graphics acceleration module 446 to link 440.

[0081] In one implementation, accelerator integrated circuit 436 represents multiple graphics processing engines 431, 432, N of graphics acceleration module 446 to provide cache management, memory access, context management, and interrupt management services. Graphics processing engines 431, 432, N may each include a separate graphics processing unit (GPU). Alternatively, graphics processing engines 431, 432, N may include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and bit-block transfer engines. In other words, the graphics acceleration module may be a GPU with multiple graphics processing engines 431 to 432, N, or graphics processing engines 431 to 432, N may be individual GPUs integrated on a common package, line card, or chip.

[0082] In one embodiment, accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and memory access protocols for accessing system memory 441. MMU 439 may also include a translation back buffer (TLB) (not shown) for translating virtual / effective cache to physical / real address. In one implementation, cache 438 stores commands and data for effective access by graphics processing engines 431 to 432, N. In one embodiment, data stored in cache 438 and graphics memories 433 to 434, N are consistent with core caches 462A to 462D, 456 and system memory 411. As mentioned, this can be achieved via proxy circuitry 425, which participates in the cache coherence mechanism on behalf of cache 438 and memories 433 to 434, N (e.g., sending updates related to modifications / accesses to cache lines on processor caches 462A to 462D, 456 to cache 438, and receiving updates from cache 438).

[0083] A set of registers 445 stores context data for threads executed by graphics processing engines 431 to 432, N, and context management circuitry 448 manages the thread context. For example, context management circuitry 448 can perform save and restore operations during context switching to save and restore the context of various threads (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 448 can store the current register values ​​to a designated region in memory (e.g., identified by a context pointer). It can then restore these register values ​​upon returning to the context. In one embodiment, interrupt management circuitry 447 receives and processes interrupts received from the system device.

[0084] In one implementation, the MMU 439 translates the virtual / effective address from the graphics processing engine 431 into a real / physical address in system memory 411. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 may be dedicated to a single application executing on processor 407 or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented, in which multiple applications or virtual machines (VMs) share the resources of graphics processing engines 431 to 432, N. These resources may be further divided into "slices," which are allocated to these VMs and / or applications based on processing requirements and priorities associated with different VMs and / or applications.

[0085] Therefore, the accelerator integrated circuit acts as a bridge to the system of the graphics acceleration module 446, and provides address translation and system memory caching services. Additionally, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage the virtualization, interrupt, and memory management of the graphics processing engine.

[0086] Because the hardware resources of graphics processing engines 431 to 432, N are explicitly mapped to the real address space seen by the host processor 407, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 436 is to physically separate the graphics processing engines 431 to 432, N, so that they appear as independent units to the system.

[0087] As mentioned, in the illustrated embodiment, one or more graphics memories 433 to 434, M are coupled to each of the graphics processing engines 431 to 432, N, respectively. Graphics memories 433 to 434, M store instructions and data processed by each of the graphics processing engines 431 to 432, N. Graphics memories 433 to 434, M can be volatile memories, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memories, such as 3D XPoint or Nano-RAM.

[0088] In one embodiment, to reduce data traffic on link 440, a biasing technique is used to ensure that the data stored in graphics memories 433 to 434, M is the data that will be used most frequently by graphics processing engines 431 to 432, N and preferably not used (at least not frequently) by cores 460A to 460D. Similarly, the biasing mechanism attempts to store the data required by the cores (and preferably not by graphics processing engines 431 to 432, N) in the caches 462A to 462D, 456 of these cores and in system memory 411.

[0089] Figure 4C Another embodiment is shown, in which the accelerator integrated circuit 436 is integrated within the processor 407. In this embodiment, graphics processing engines 431 to 432, N communicate directly with the accelerator integrated circuit 436 via high-speed link 440 through interfaces 437 and 435 (again, these interfaces can utilize any form of bus or interface protocol). The accelerator integrated circuit 436 can perform operations related to... Figure 4B The operation described is the same, but it is potentially at a higher throughput due to its extremely close proximity to the coherence bus 462 and caches 462A to 462D, 426.

[0090] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter may include a programming model controlled by accelerator integrated circuit 436 and a programming model controlled by graphics acceleration module 446.

[0091] In one embodiment of the dedicated process model, graphics processing engines 431 to 432, N are dedicated to a single application or process within a single operating system. A single application can funnel requests from other applications to graphics engines 431 to 432, N, thereby providing virtualization within a VM / partition.

[0092] In a dedicated process programming model, graphics processing engines 431 to 432, N can be shared by multiple VM / application partitions. This shared model requires a hypervisor to virtualize graphics processing engines 431 to 432, N to allow access by each operating system. For single-partition systems without a hypervisor, graphics processing engines 431 to 432, N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431 to 432, N to provide access to each process or application.

[0093] For a shared programming model, the graphics acceleration module 446 or individual graphics processing engines 431 to 432, N use process handles to select process elements. In one embodiment, process elements are stored in system memory 411 and can be addressed using the effective address to real address translation techniques described herein. The process handle can be an implementation-specific value provided to the host process when registering its context with the graphics processing engines 431 to 432, N (i.e., invoking system software to add process elements to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0094] Figure 4D An exemplary accelerator integration slice 490 is shown. As used herein, a “slice” includes a designated portion of the processing resources of the accelerator integrated circuit 436. The application-effective address space 482 within system memory 411 stores process elements 483. In one embodiment, process element 483 is stored in response to a GPU call 481 from an application 480 executing on processor 407. Process element 483 contains the process state of the corresponding application 480. A job descriptor (WD) 484 contained in process element 483 may be a single job requested by the application, or may contain a pointer to a job queue. In the latter case, WD 484 is a pointer to a job request queue in the application's address space 482.

[0095] The graphics acceleration module 446 and / or individual graphics processing engines 431 to 432, N can be shared by all processes or a subset of processes in the system. Embodiments of the invention include infrastructure for setting process states and sending WD 484 to the graphics acceleration module 446 to initiate operations in a virtualized environment.

[0096] In one implementation, the dedicated process programming model is implementation-specific. In this model, a single process owns either the graphics acceleration module 446 or an individual graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, when assigning the graphics acceleration module 446, the hypervisor initializes the accelerator integrated circuit 436 for the owned partition, and the operating system initializes the accelerator integrated circuit 436 for the owned process.

[0097] In operation, the WD acquisition unit 491 in the accelerator integrated slice 490 acquires the next WD 484, which includes an indication of the work to be performed by one of the graphics processing engines of the graphics acceleration module 446. Data from the WD 484 may be stored in register 445 and used by the MMU 439, interrupt management circuitry 447, and / or context management circuitry 446 as shown. For example, one embodiment of the MMU 439 includes segment / page walk circuitry for accessing segment / page tables 486 within the OS virtual address space 485. The interrupt management circuitry 447 may handle interrupt events 492 received from the graphics acceleration module 446. When performing graphics operations, the MMU 439 translates the valid address 493 generated by the graphics processing engines 431 to 432, N into a real address.

[0098] In one embodiment, a set of identical registers 445 is copied for each graphics processing engine 431 to 432, N and / or graphics acceleration module 446, and these registers can be initialized by a hypervisor or operating system. Each of these copied registers may be included in the accelerator integration slice 490. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0099] Table 1 - Registers initialized by the management program

[0100] 1 Slice Control Register 2 Real Address (RA) Scheduled Process Region Pointer 3 Authority Mask Override Register 4 Interruption vector table entry offset 5 Interrupt vector table entry limit 6 Status Register 7 Logical partition ID 8 Real Address (RA) management accelerator utilizes record pointers 9 Storage description register

[0101] Table 2 shows exemplary registers that can be initialized by the operating system.

[0102] Table 2 - Registers for Operating System Initialization

[0103] 1 Process and thread identifiers 2 Valid Address (EA) Context Save / Restore Pointer 3 Virtual address (VA) accelerators utilize record pointers 4 Virtual address (VA) memory segment table pointer 5 Permission mask 6 Job descriptor

[0104] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engines 431 to 432, N. It contains all the information required for the graphics processing engines 431 to 432, N to complete their work, or it may be a pointer to a memory location where the application has set up a command queue of tasks to be completed.

[0105] Figure 4E Additional details of one embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 498 in which a list of process elements 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496, which virtualizes the graphics acceleration module engine of the operating system 495.

[0106] The shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 446. Two programming models exist where the graphics acceleration module 446 is shared by multiple processes and partitions: time-slice sharing and graphics-directed sharing.

[0107] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. For the graphics acceleration module 446 to support virtualization performed by the hypervisor 496, the graphics acceleration module 446 may meet the following requirements: 1) Application job requests must be autonomous (i.e., no state maintenance is required between jobs), or the graphics acceleration module 446 must provide context saving and restoration mechanisms. 2) The graphics acceleration module 446 guarantees completion of application job requests within a specified time (including any transition failures), or the graphics acceleration module 446 provides the ability to preempt job processing. 3) When operating in a directed shared programming model, fairness of the graphics acceleration module 446 among processes must be guaranteed.

[0108] In one embodiment, for the shared model, application 480 needs to make an operating system 495 system call using the graphics acceleration module 446 type, working descriptor (WD), authority mask register (AMR) value, and context save / restore region pointer (CSRP). The graphics acceleration module 446 type describes the target acceleration function used for the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can be in the form of a graphics acceleration module 446 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure describing the work to be performed by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state to be used for the current process. The value passed to the operating system is similar to the application setting the AMR. If the accelerator integrated circuit 436 and the graphics acceleration module 446 implementation do not support the User Authority Mask Override Register (UAMOR), then the operating system can apply the current UAMOR value to the AMR value and then pass the AMR in the hypervisor call. Optionally, hypervisor 496 may apply the current privilege mask overwrite register (AMOR) value and then place the AMR into process element 483. In one embodiment, CSRP is one of registers 445 that contains the effective address of a region in the application's address space 482 for use by the graphics acceleration module 446 to save and restore context state. This pointer is optional if saving state between jobs is not required or when a job is preempted. The context save / restore region may be pinned system memory.

[0109] Upon receiving a system call, the operating system 495 verifies that application 480 has been registered and granted permission to use the graphics acceleration module 446. Then, the operating system 495 uses the information shown in Table 3 to invoke the hypervisor 496.

[0110] Table 3 – OS to Hypervisor Call Parameters

[0111] 1 Working Descriptor (WD) 2 Authority Mask Register (AMR) value (potentially masked) 3 Valid Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual address (VA) accelerators utilize record pointers (AURP). 6 Virtual address of the segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0112] Upon receiving a hypervisor call, hypervisor 496 verifies that operating system 495 is registered and has been granted permission to use graphics acceleration module 446. Then, hypervisor 496 places process element 483 into a linked list of process elements corresponding to graphics acceleration module 446 type. Process elements may include the information shown in Table 4.

[0113] Table 4 - Process Element Information

[0114]

[0115]

[0116] In one embodiment, the hypervisor initializes multiple accelerator integration slice 490 registers 445.

[0117] like Figure 4F As shown, one embodiment of the invention employs a unified memory addressable via a common virtual memory address space for accessing physical processor memories 401-402 and GPU memories 420-423. In this implementation, operations performed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memories 401-402 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion to a second processor memory 402, a third portion to GPU memory 420, and so on. This allows the entire virtual / effective memory space (sometimes referred to as the effective address space) to be distributed across each of processor memories 401-402 and GPU memories 420-423, thereby allowing any processor or GPU to access any physical memory using virtual addresses mapped to said memory.

[0118] In one embodiment, bias / coherence management circuitry 494A to 494E within one or more of the MMUs 439A to 439E ensures cache coherence between the host processor (e.g., 405) and the caches of the GPUs 410 to 413, and implements biasing techniques that indicate the physical memory where certain types of data should be stored. Although Figure 4F Several instances of bias / coherence management circuitry 494A to 494E are shown, but bias / coherence circuitry can be implemented within the MMU of one or more host processors 405 and / or within the accelerator integrated circuit 436.

[0119] One embodiment allows GPU-attached memories 420 to 423 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, without suffering the typical performance drawbacks associated with full system cache coherence. This ability to access GPU-attached memories 420 to 423 as system memory without the heavy overhead of cache coherence provides a beneficial operating environment for GPU offloading. This arrangement allows host processor 405 software to set operands and access computation results without the overhead of traditional I / O DMA data copying. Such traditional copying involves driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient compared to simple memory access. Meanwhile, the ability to access GPU-attached memories 420 to 423 without cache coherence overhead can be critical to the execution time of offloaded computations. In cases with substantial streaming write memory traffic, for example, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 410 to 413. The efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation all play a role in determining the effectiveness of GPU offloading.

[0120] In one implementation, the choice between GPU bias and host processor bias is driven by a bias tracker data structure. A bias table can be used, for example, which could be a page-granular structure comprising 1 or 2 bits per GPU-attached memory page (i.e., controlled at the memory page level). The bias table can be implemented using one or more stolen memory ranges of GPU-attached memory 420-423, with or without a bias cache in GPUs 410-413 (e.g., for caching frequently used / recently used entries of the bias table). Alternatively, the entire bias table can be kept within the GPU.

[0121] In one implementation, the bias table entries associated with each access to GPU-attached memory 420-423 are accessed before the actual access to GPU memory, resulting in the following operations: First, local requests from GPUs 410-413 to locate their pages in the GPU bias (these local requests find their pages are in the GPU bias) are forwarded directly to the corresponding GPU memory 420-423. Local requests from GPUs (these local requests find their pages are in the host bias) are forwarded to processor 405 (e.g., via a high-speed link as discussed above). In one embodiment, a request from processor 405 to locate the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, requests for GPU-biased pages can be forwarded to GPUs 410-413. Then, if the GPU is not currently using the page, it can redirect the page to the host processor bias.

[0122] The page bias state can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or a purely hardware-based mechanism for a limited set of cases.

[0123] One mechanism for changing the bias state employs an API call (e.g., OpenCL) that in turn invokes the GPU's device driver, which then sends a message (or queues a command descriptor) to the GPU, instructing it to change the bias state and perform a cache flushing operation on the host for some transitions. The cache flushing operation is necessary for transitions from host processor 405 bias to GPU bias, but not for the reverse transition.

[0124] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that cannot be cached by the host processor 405. To access these pages, the processor 405 may request access from the GPU 410, depending on the implementation's ability to grant access immediately or not. Therefore, to reduce communication between the processor 405 and the GPU 410, it is advantageous to ensure that the GPU bias pages are those required by the GPU but not by the host processor 405 (and vice versa).

[0125] Graphics processing pipeline

[0126] Figure 5 A graphics processing pipeline 500 according to an embodiment is shown. In one embodiment, a graphics processor may implement the shown graphics processing pipeline 500. The graphics processor may be included within a parallel processing subsystem as described herein, such as the parallel processor 200 of FIG2, which in one embodiment is... Figure 1 Variations of the (multiple) parallel processors 112. Various parallel processing systems can implement the graphics processing pipeline 500 via one or more instances of parallel processing units as described herein (e.g., parallel processing unit 202 of FIG. 2). For example, a shader unit (e.g., graphics multiprocessor 234 of FIG. 3) can be configured to perform the functions of one or more of the vertex processing unit 504, tessellation control processing unit 508, tessellation evaluation processing unit 512, geometry processing unit 516, and fragment / pixel processing unit 524. The functions of the data assembler 502, primitive assemblers 506, 514, 518, tessellation unit 510, rasterizer 522, and raster operation unit 526 can also be performed by other processing engines and corresponding partitioning units (e.g., partitioning units 220A to 220N of FIG. 2) within a processing cluster (e.g., processing cluster 214 of FIG. 3). The graphics processing pipeline 500 can also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 500 may be executed by parallel processing logic within a general-purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., parallel processor memory 222 in FIG2) via a memory interface 528, which may be an instance of memory interface 218 of FIG2.

[0127] In one embodiment, the data assembler 502 is a processing unit that collects vertex data of surfaces and primitives. The data assembler 502 then outputs vertex data, including vertex attributes, to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes a vertex shader program to illuminate and transform the vertex data as specified by the vertex shader program. The vertex processing unit 504 reads data stored in a cache, local, or system memory for use in processing the vertex data, and the vertex processing unit 504 can be programmed to transform the vertex data from an object-based coordinate representation to world space coordinate space or normalized device coordinate space.

[0128] The first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 504. Primitive assembler 506 reads the stored vertex attributes as needed and constructs graphical primitives for processing by tessellation control processing unit 508. Graphical primitives include triangles, lines, points, patches, etc., supported by various graphics processing application programming interfaces (APIs).

[0129] The tessellation control processing unit 508 treats input vertices as control points for a geometric patch. These control points are transformed from an input representation of the patch (e.g., the patch's base) to a representation suitable for use in surface evaluation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 can also calculate tessellation factors for the edges of the geometric patch. The tessellation factors are applied to individual edges and quantize the view-dependent level of detail associated with that edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and subdivides the patch surface into multiple geometric primitives, such as lines, triangles, or quadrilaterals, which are then transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parametric coordinates of the subdivided patch to generate a surface representation and vertex attributes associated with each vertex of the geometric primitives.

[0130] A second instance of the primitive assembler 514 receives vertex attributes from the tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphical primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to transform the graphical primitives received from the primitive assembler 514 as specified by the geometry shader program. In one embodiment, the geometry processing unit 516 is programmed to further subdivide the graphical primitives into one or more new graphical primitives and calculate parameters for rasterizing the new graphical primitives.

[0131] In some embodiments, the geometry processing unit 516 may add or remove elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying new graphic primitives to the primitive assembler 518. The primitive assembler 518 receives parameters and vertices from the geometry processing unit 516 and constructs graphic primitives for processing by the viewport scaling, picking, and clipping unit 520. The geometry processing unit 516 reads data stored in parallel processor memory or system memory for use when processing geometry data. The viewport scaling, picking, and clipping unit 520 performs clipping, picking, and viewport scaling and outputs the processed graphic primitives to the rasterizer 522.

[0132] Rasterizer 522 can perform depth picking and other depth-based optimizations. Rasterizer 522 also performs scan transformations of new graphic primitives to generate fragments and outputs those fragments and associated overlay data to fragment / pixel processing unit 524. Fragment / pixel processing unit 524 is a programmable execution unit configured to execute fragment shader programs or pixel shader programs. Fragment / pixel processing unit 524 transforms fragments or pixels received from rasterizer 522 as specified by the fragment or pixel shader program. For example, fragment / pixel processing unit 524 can be programmed to perform operations that produce shaded fragments or pixels output to raster operation unit 526, including but not limited to texture mapping, shading, blending, texture correction, and perspective correction. Fragment / pixel processing unit 524 can read data stored in parallel processor memory or system memory for use when processing fragment data. Fragment or pixel shader programs can be configured to shade at samples, pixels, tiles, or other granularities depending on the sampling rate configured for the processing unit.

[0133] Raster operation unit 526 is a processing unit that performs raster operations including but not limited to stencil printing, z-testing, blending, etc., and outputs pixel data as processed graphic data for storage in a graphics memory (e.g., parallel processor memory 222 as shown in FIG2 and / or Figure 1 The data is stored in system memory 104, displayed on one or more display devices 110, or further processed by one or more processors 102 or one of parallel processors 112. In some embodiments, the raster operation unit 526 is configured to compress z-or color data written to memory and decompress z-or color data read from memory.

[0134] Control coarse pixel size from the buffer

[0135] Now go to Figure 6The diagram illustrates the determination of the coarse pixel (CP) size 600. Generally, a coarse pixel can be a group of pixels 608 sharing a single coarse pixel shader (CPS) evaluation on display 610. This group of pixels 608 can correspond to, for example, peripheral viewports, foveated rendering regions, motion-blurred regions, etc., on display 610 during the visual presentation of a scene (e.g., a still image, video frame, etc.) to one or more users. In the example shown, application 602 (e.g., an application programming interface / API) applies two-dimensional (2D) texture values ​​604 (604a, 604b, e.g., texel values) to a 2D texture memory 606 (e.g., a "texture"), which can typically be used to specify the appearance (e.g., color, pattern) of a 2D image projected onto a three-dimensional (3D) surface. In one example, the 2D texture memory 606 is a stencil printing buffer used to limit the rendering area of ​​a scene. As will be discussed in more detail, in the example shown, a first texel value 604a corresponds to a first pixel 614 on display 610, and a second texel value 604b corresponds to a second pixel 616 on display 610, wherein these two texel values ​​604 share the same call to the pixel shader (e.g., shader execution). The graphics pipeline 612 is communicatively coupled to 2D texture memory 606, and display 610 can make the shared pixel shader calls and output the results (e.g., scan output) to display 610. Using 2D texture memory 606 to control the coarse pixel size 600 allows for user-controlled variations of the coarse pixel size 600 across the pixels of display 610.

[0136] Figure 7 An example of a 2D texture memory being a stencil printing buffer is shown. In the example shown, a first stencil printing value 700 is used to control the coarse pixel size via a stencil printing buffer (not shown). The first stencil printing value 700 typically includes a first bit range 702 (e.g., the most significant "0010" bit marking the value four) defining a first dimension (e.g., the "x" dimension) of the coarse pixel size and a second bit range 704 (e.g., the least significant "0010" bit marking the value four) defining a second dimension (e.g., the "y" dimension) of the coarse pixel size. Thus, in the example shown, the coarse pixel size is a 4x4 pixel block 706, where each of the sixteen pixels in this 4x4 pixel block 706 shares a pixel shader call.

[0137] In contrast, the second pixel value 710 can also be used to control the size of coarse pixels via a stencil printing buffer, such as, for example, the stencil printing buffer 606 already discussed. Figure 6The second pixel value 710 may include a first bit range 712 (e.g., the most significant "0100" bit marking the value eight) defining a first dimension (e.g., the "x" dimension) of the coarse pixel size and a second bit range 714 (e.g., the least significant "0100" bit marking the value eight) defining a second dimension (e.g., the "y" dimension) of the coarse pixel size. Therefore, in the example shown, the coarse pixel size is an 8x8 pixel block 716, where each of the sixty-four pixels in this 8x8 pixel block 716 shares a pixel shader call. Other coarse pixel sizes may be used depending on the situation.

[0138] If a 2D texture is used to control the coarse pixel size, the coarse pixel size of a pixel patch can be specified by a single texel in the texture. Therefore, the size of the texture controlling the coarse pixel size can be significantly smaller than the screen size. For example, the coarse pixel size of an 8x8 group with sixty-four pixels can be specified by a single texel; in this case, the texture could be 1 / 8 the width and 1 / 8 the height of the screen. This approach significantly reduces the storage and bandwidth requirements for the texture.

[0139] Figure 8 A method 800 for operating a semiconductor package device is illustrated. Method 800 can be implemented as one or more modules of a set of logic instructions stored in a non-transitory machine or computer-readable storage medium such as random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc.; stored in configurable logic such as, for example, a programmable logic array (PLA), a field-programmable gate array (FPGA), a complex programmable logic device (CPLD); stored in fixed-function hardware logic using circuit technologies such as, for example, application-specific integrated circuits (ASIC), complementary metal-oxide-semiconductor (CMOS), or transistor-transistor logic (TTL); or stored in any combination of the above.

[0140] For example, the computer program code used to perform the operations shown in method 800 can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as JAVA, SMALLTALK, C++, or similar, and conventional procedural programming languages ​​such as the "C" programming language or similar. Additionally, the logic instructions can include assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, state setting data, configuration data for integrated circuit systems, state information for customizing electronic circuit systems, and / or other hardware-native structural components (e.g., host processor, central processing unit / CPU, microcontroller, etc.).

[0141] The processing frame 802 shown provides for determining 2D texture values. In the case of a stencil printing buffer, frame 802 can be performed during the initial (e.g., first) round of depth analysis of the scene to be rendered (e.g., 8 bits of the Z-buffer are allocated to the stencil printing, and the remaining 24 bits are used for depth). Frame 802 can therefore also include determining the appropriate level of detail (LOD, e.g., occlusion information) for the scene region in question. As already noted, the 2D texture values ​​can include a first bit range defining a first dimension of coarse pixel size and a second bit range defining a coarse pixel size, which can vary across multiple pixels in the scene. Therefore, a relatively small CP size can be selected for screen regions with relatively high LOD, and a relatively large CP size can be selected for screen regions with relatively low LOD.

[0142] Box 804 can use the 2D texture value to control the coarse pixel size of the graphics pipeline via a 2D texture memory. Box 804 (which can be performed during a subsequent (e.g., a second) round involving shader execution) can include applying the 2D texture value to the location in the 2D texture memory corresponding to a pixel in the scene being rendered by the graphics pipeline. Furthermore, the coarse pixel size can be controlled pixel-by-pixel for multiple pixels.

[0143] Figure 9 An enhanced computing system 900 is illustrated. In the illustrated example, the host processor 902 includes an integrated memory controller (IMC) 904 that communicates with system memory 906 (e.g., DRAM). The host processor 902 may be coupled to a graphics processor 908 and an input / output (I / O) module 910. The I / O module 910 may be coupled to a network controller 912 (e.g., wireless and / or wired), a display 914 (e.g., a fixed or head-mounted liquid crystal display / LCD, light-emitting diode / LED display, etc., for visually presenting video of 3D scenes), and mass storage 918 (e.g., flash memory, optical disc, solid-state drive / SSD). The illustrated graphics processor 908 is coupled to a graphics memory 916 (e.g., dedicated graphics RAM), which may include a stencil printing buffer 922, a depth buffer 924, etc.

[0144] System memory 906 and / or mass storage 918 may include instructions 920 that, when executed by host processor 902 and / or graphics processor 908, cause system 900 to execute method 800. Figure 8One or more aspects of ). Therefore, system 900 can be configured to determine stencil printing values ​​and use these stencil printing values ​​to control the coarse pixel size of the graphics pipeline 909 of graphics processor 908 via stencil printing buffer 922.

[0145] Figure 10 A semiconductor package device 1000 (e.g., a chip) is shown, comprising a substrate 1002 (e.g., silicon, sapphire, gallium arsenide) and logic 1004 (1004a to 1004c, e.g., transistor arrays and other integrated circuit / IC components) coupled to the substrate 1002. The logic 1004 (which may be implemented in configurable logic and / or fixed-function logic hardware) includes a graphics processor 1004a, a host processor 1004b, and an I / O module 1004c. The logic 1004 can generally implement method 800 (…). Figure 8 One or more aspects of the graphics pipeline. Therefore, logic 1004 can determine stencil print values ​​and use these stencil print values ​​to control the coarse pixel size of the graphics pipeline via a stencil print buffer. In one example, the stencil print values ​​include a first bit range defining a first dimension of the coarse pixel size and a second bit range defining a second dimension of the coarse pixel size. Alternatively, the coarse pixel size can be controlled pixel-by-pixel for multiple pixels.

[0146] Overview of Head-Mounted Display Systems

[0147] Figure 11 A head-mounted display (HMD) system 1100 is shown, worn by a user while experiencing an immersive environment such as, for example, a virtual reality (VR) environment, an augmented reality (AR) environment, or a multiplayer 3D game. In the example shown, one or more straps 1120 hold frames 1102 of the HMD system 1100 in front of the user's eyes. Accordingly, a left-eye display 1104 is placed for viewing by the user's left eye, and a right-eye display 1106 is placed for viewing by the user's right eye. In some examples, such as smartphones worn by the user, the left-eye display 1104 and the right-eye display 1106 may optionally be integrated into a single display. In the case of AR, the displays 1104, 1106 may be perspective displays, allowing the user to view the physical environment while other rendered content (e.g., virtual characters, information annotations, heads-up displays / HUDs) are presented above a real-time feed of the physical environment.

[0148] In one example, frame 1102 includes a lower-left camera 1108 to capture images from an area generally located in front of the user and below the left eye (e.g., a left-hand gesture). Additionally, a lower-right camera 1110 can capture images from an area generally located in front of the user and below the right eye (e.g., a right-hand gesture). The illustrated frame 1102 also includes a left-front camera 1112 and a right-front camera 1114 to capture images in front of the user's left and right eyes, respectively. Frame 1102 may also include a left-side camera 1116 to capture images from an area to the left of the user and a right-side camera 1118 to capture images from an area to the right of the user.

[0149] Images captured by cameras 1108, 1110, 1112, 1114, 1116, and 1118, which may have overlapping fields of view, can be used to detect user gestures and analyze the external environment and / or reproduce the external environment on displays 1104 and 1106. In one example, the detected gestures are used by (e.g., internal and / or external) graphics processing architectures to render and / or control a virtual representation of the user in a 3D game. In fact, overlapping fields of view can enable the capture of gestures made by other individuals (e.g., in multiplayer games), whose gestures can also be used to render / control the immersive experience. Overlapping fields of view also enable the HMD system 1100 to automatically detect obstructions or other damage near the user. Such an approach is particularly advantageous in Advanced Driver Assistance Systems (ADAS) applications.

[0150] In one example, the lower-left camera 1108 and the lower-right camera 1110, providing overlapping fields of view, offer a stereoscopic view with increased resolution. This increased resolution allows for the differentiation of very similar user movements (e.g., with sub-millimeter accuracy). The result can be an enhanced performance of the HMD system 1100 in terms of reliability. Indeed, the solution presented is useful in a wide variety of applications, such as coloring information in AR settings, exchanging virtual tools / devices among multiple users in a multi-user environment, rendering virtual items (e.g., weapons, swords, people), etc. The poses of other objects, limbs, and / or body parts can also be detected and used to render / control the virtual environment. For example, spinal cord imaging signals, EEG signals, eye tracking, breathing or panting, hand movements, etc., can be tracked in real time, whether from the wearer or from other individuals in a shared environment. Images captured by cameras 1108, 1110, 1112, 1114, 1116, and 1118 can also be used as contextual input. For example, it might determine that a user is indicating a specific word to be edited or a specific key to be pressed in a word processing application, or a specific weapon to be deployed or a direction of movement in a game.

[0151] Furthermore, images captured by cameras 1108, 1110, 1112, 1114, 1116, and 1118 can be used to implement shared communication or networked interaction in applications such as device operation, medical training, and / or remote / telescopic operation guidance. Task-specific pose libraries or neural network machine learning can enable tool identification and feedback to the task. For example, virtual tools can be enabled to be translated into remote, realistic movements. In yet another example, HMD system 1100 translates the manipulation of a virtual drill in a virtual scene into the remote operation of a drill on a robotic device deployed to search for collapsed buildings. Moreover, HMD system 1100 can be programmable to include, for example, protocols that allow users to add new poses to a list of identifiable poses associated with user actions.

[0152] Furthermore, the various cameras in the HMD 1100 can be configured to detect spectral frequencies beyond the visible wavelengths of the spectrum. The multispectral imaging capabilities of the input cameras allow for the tracking of the user and / or object's position by eliminating unnecessary image features (e.g., background noise). For example, in augmented reality (AR) applications such as surgery, instruments and equipment are tracked through their infrared reflectivity without the need for additional tracking aids. Moreover, the HMD 1100 can be used in low-visibility situations, where "real-time feeds" from the various cameras can be enhanced or amplified through computer analysis and displayed to the user as visual or audio cues.

[0153] HMD system 1100 can also forgo performing any type of data communication with a remote computing system or requiring a power cord (e.g., stand-alone operation mode). In this regard, HMD system 1100 can be a “cordless” device with a power unit that enables HMD system 1100 to operate independently of an external power system. Accordingly, users can play full-featured games without being tethered to another device (e.g., a game console) or power source. In a word processing example, HMD system 1100 presents a virtual keyboard and / or virtual mouse on displays 1104 and 1106 to provide a virtual desktop or word processing scene. Thus, gesture identification data captured by one or more cameras represents user typing activity on the virtual keyboard or movement of the virtual mouse. Advantages include, but are not limited to: portability and privacy of the virtual desktop from nearby individuals. The underlying graphics processing architecture can support the compression and / or decompression of video and audio signals. Moreover, providing separate images for the user's left and right eyes can aid in the rendering, generation, and / or perception of 3D scenes. The relative positions of the left-eye display 1104 and the right-eye display 1106 can also be adjusted to match the changes in interocular distance between different users.

[0154] Figure 11The number of cameras shown is for discussion purposes only. In fact, depending on the environment, the HMD system 1100 may include fewer or more than six cameras.

[0155] Functional components of the HMD system

[0156] Figure 12 The HMD system is shown in more detail. In the example shown, frame 1102 includes a power supply unit 1200 (e.g., battery power, adapter) that provides power to the HMD system. Frame 1102 also includes a motion tracking module 1220 (e.g., accelerometer, gyroscope) that provides motion tracking data, orientation data, and / or position data to the processor system 1204. The processor system 1204 may include a network adapter 1224 coupled to an I / O bridge 1206. The I / O bridge 1206 enables communication between the network adapter 1224 and various components such as, for example, an audio input module 1210, an audio output module 1208, a display device 1207, an input camera 1202, and so on.

[0157] In the example shown, the audio input module 1210 includes a right audio input 1218 and a left audio input 1216, both of which detect sounds that can be processed to identify voice commands from the user and nearby individuals. Voice commands identified in the captured audio signals can enhance gesture identification during modality switching and other applications. Furthermore, the captured audio signals can provide 3D information to enhance the immersive experience.

[0158] Audio output module 1208 may include a right audio output 1214 and a left audio output 1212. Audio output module 1208 can deliver sound to the ears of a user and / or other nearby individuals. Audio output module 1208 may be in the form of earbuds, on-ear speakers, over-ear speakers, loudspeakers, etc., or any combination thereof, and can deliver stereo and / or 3D audio content to the user (e.g., spatial positioning). The shown frame 1102 also includes a wireless module 1222 that facilitates communication between the HMD system and various other systems (e.g., computers, wearable devices, game consoles). In one example, wireless module 1222 communicates with processor system 1204 via network adapter 1224.

[0159] The displayed display device 1207 includes a left-eye display 1104 and a right-eye display 1106, wherein the virtual content presented on the displays 1104 and 1106 can be obtained from the processor system 1204 via the I / O bridge 1206. The input camera 1202 may include the left-side view camera 1116, the right-side view camera 1118, the lower-left view camera 1108, the left-front view camera 1112, the right-front view camera 1114, and the lower-right view camera 1110, which have already been discussed.

[0160] Turn now Figure 13 The diagram illustrates a General Processing Cluster (GPC) 1300. The demonstrated GPC 1300 can be incorporated into, for example, the processor system 1204 already discussed. Figure 12 In a processing system, GPC 1300 may include a pipeline manager 1302 that communicates with a scheduler. In one example, pipeline manager 1302 receives tasks from the scheduler and distributes the tasks to one or more streaming multiprocessors (SMs) 1304. Each SM 1304 may be configured to process a group of threads, where a group of threads can be viewed as multiple related threads performing the same or similar operations on different input data. Therefore, each thread in the group of threads can be assigned to a specific SM 1304. In another example, the number of threads may be greater than the number of execution units in the SM 1304. In this respect, multiple threads in a group of threads can operate in parallel. Pipeline manager 1302 may also assign the destination of processed data to a work distribution crossbar switch 1308, which communicates with a memory crossbar switch.

[0161] Therefore, when each SM 1304 sends a processed task to the work distribution cross switch 1308, the processed task can be provided to another GPC 1300 for further processing. The output of the SM 1304 can also be sent to a pre-raster operation (preROP) unit 1314, which then directs the data to one or more raster operation units or performs other operations (e.g., address translation, organizing image color data, color mixing, etc.). The SM 1304 may include an internal Level 1 (L1) cache (not shown) where data can be stored. The SM 1304 may also have access to a Level 2 (L2) cache (not shown) via a memory management unit (MMU) 1310 and a Level 1.5 (L1.5) cache 1306. The MMU 1310 can map virtual addresses to physical addresses. In this regard, the MMU 1310 may include page table entries (PTEs) used to map virtual addresses to physical addresses of tiles, memory pages, and / or cache line indices. The GPU 1300 shown includes texture units 1312.

[0162] Graphical Pipeline Architecture

[0163] Turn now Figure 14 The diagram illustrates a graphics pipeline 1400. In the example shown, the world space pipeline 1420 includes a primitive distributor (PD) 1402. PD 1402 collects vertex data associated with higher-order services, graphics primitives, triangles, etc., and sends the vertex data to a vertex attribute acquisition unit (VAF) 1404. VAF 1404 retrieves the vertex attributes associated with each incoming vertex from shared memory and stores the vertex data and associated vertex attributes together in the shared memory.

[0164] The world space pipeline 1420 shown also includes a Vertex, Tessellation, and Geometry Processing Unit (VTG) 1406. The VTG 1406 may include, for example, a vertex processing unit, a tessellation initialization processing unit, a task distributor, a task generation unit, a topology generation unit, a geometry processing unit, a tessellation processing unit, etc., or any combination thereof. In one example, the VTG 1406 is a programmable execution unit configured to execute geometry procedures, tessellation procedures, and vertex shader procedures. The programs executed by the VTG 1406 can process vertex data and vertex attributes received from the VAF 1404. Furthermore, the programs executed by the VTG 1406 can generate graphics primitives, color values, surface normalization factors, and transparency values ​​at each vertex of the graphics primitives for further processing within the graphics processing pipeline 1400.

[0165] The vertex processing unit of the VTG 1406 can be a programmable execution unit that executes vertex shader programs to illuminate and transform vertex data as specified by the vertex shader programs. For example, the vertex processing unit can be programmed to transform vertex data from an object-based coordinate representation (e.g., object space) to an alternative coordinate system such as world space or normalized device coordinates (NDC) space. Furthermore, the vertex processing unit can read vertex data and vertex attributes stored in shared memory by the VAF 1404 and process the vertex data and vertex attributes. In one example, the vertex processing unit stores the processed vertices in shared memory.

[0166] The tessellation initialization processing unit (e.g., the hull shader, tessellation control shader) executes the tessellation initialization shader program. In one example, the tessellation initialization processing unit processes the vertices generated by the vertex processing unit and generates graphical primitives sometimes called "patches". The tessellation initialization processing unit can also generate various patch attributes, where patch data and patch attributes are stored in shared memory. The VTG 1406's task generation unit retrieves the vertex and patch data and attributes from the shared memory. In one example, the task generation unit generates tasks for processing vertices and patches for later-stage processing in the graphics processing pipeline 1400.

[0167] Tasks generated by the task generation unit can be redistributed by the task distributor of the VTG 1406. For example, tasks generated by various instances of the vertex shader program and the tessellation initializer can differ significantly between one graphics pipeline 1400 and another. Accordingly, the task distributor can redistribute these tasks so that each graphics pipeline 1400 has nearly the same workload in later pipeline stages.

[0168] As already discussed, the VTG 1406 may also include a topology generation unit. In one example, the topology generation unit takes a task distributed by a task distributor, indexes vertices including those associated with patches, and computes the coordinates (UV) of the tessellation vertices and the indices connecting the tessellation vertices to form the graphics primitives. The indexed vertices may be stored in shared memory by the topology generation unit. The tessellation processing unit of the VTG 1406 may be configured to execute tessellation shader programs (e.g., domain shaders, tessellation evaluation shaders). The tessellation processing unit may read input data from shared memory and write output data to shared memory. The output data may be passed from shared memory to a geometry processing unit (e.g., the next shader level) as input data.

[0169] The geometry processing unit of the VTG 1406 executes geometry shader programs to transform graphic primitives (e.g., triangles, line segments, points, etc.). In one example, vertices are grouped to construct graphic primitives, where the geometry processing unit subdivides the graphic primitives into one or more new graphic primitives. The geometry processing unit can also compute parameters such as plane equation coefficients, which can be used, for example, to rasterize the new graphic primitives.

[0170] The world space pipeline 1420 shown also includes a viewport scaling, picking, and clipping unit (VPC) 1408 that acquires parameters and vertices of new graphic primitives from the VTG 1406. In one example, the VPC 1408 performs clipping, flanging, perspective correction, and viewport transformation to identify graphic primitives that may be potentially viewable in the final rendered image. The VPC 1408 can also identify graphic primitives that may not be viewable.

[0171] The graphics processing pipeline 1400 may also include a tiling unit 1410 coupled to the world space pipeline 1420. The tiling unit 1410 may be a graphics primitive sorting engine, where graphics primitives are processed in the world space pipeline 1420 and subsequently sent to the tiling unit 1410. In this regard, the graphics processing pipeline 1400 may also include a screen space pipeline 1422, where the screen space can be divided into cache tiles. Each cache tile may thus be associated with a portion of the screen space. For each graphics primitive, the tiling unit 1410 may identify a set of cache tiles that intersect (e.g., tile) with the graphics primitive. After tiling several graphics primitives, the tiling unit 1410 may process the graphics primitives one cache tile at a time. In one example, graphics primitives associated with a particular cache tile are sent one tile at a time to the setup unit 1412 in the screen space pipeline 1422. Graphic primitives that intersect with multiple cache tiles can be processed once in the world space pipeline 1420 and sent multiple times to the screen space pipeline 1422.

[0172] In one example, setup unit 1412 receives vertex data from VPC 1408 via chunking unit 1410 and calculates parameters associated with the graphics primitives. Parameters may include, for example, edge equations, partial plane equations, and depth plane equations. Screen space pipeline 1422 may also include rasterizer 1414 coupled to setup unit 1412. The rasterizer can scan and transform new graphics primitives and send fragment and overlay data to pixel shader unit (PS) 1416. Rasterizer 1414 may also perform Z-picking and other Z-based optimizations.

[0173] The PS1416, with access to shared memory, can execute a fragment shader program that transforms fragments received from the rasterizer 1414. More specifically, the fragment shader program can shade fragments at a pixel-level granularity (e.g., operate as a pixel shader program). In another example, the fragment shader program shades fragments at a sample-level granularity, where each pixel comprises multiple samples, and each sample represents a portion of the pixel. Moreover, depending on the environment (e.g., sampling rate), the fragment shader program can shade fragments at any other granularity. The PS1416 can perform color mixing, shading, perspective correction, texture mapping, etc., to generate shaded fragments.

[0174] The screen space pipeline 1422 shown also includes a raster operation unit (ROP) 1418, which can perform operations such as stencil printing, Z-testing, blending, etc. The ROP 1418 can then send pixel data as processed graphic data to one or more rendered targets (e.g., graphics memory). The ROP 1418 can be configured to compress Z or color data written to memory and decompress Z or color data read from memory. The location of the ROP 1418 can vary depending on the environment.

[0175] The graphics processing pipeline 1400 can be implemented by one or more processing elements. For example, VTG 1406 and / or PS1416 can be implemented in one or more SMs, and PD 1402, VAF 1408, partitioning unit 1410, setup unit 1412, rasterizer 1414, and / or ROP 1418 can be implemented in a specific GPC processing element combined with the corresponding partitioning unit. The graphics processing pipeline 1400 can also be implemented in fixed-function hardware logic. In fact, the graphics processing pipeline 1400 can be implemented in a PPU.

[0176] Therefore, the world-space pipeline 1420 demonstrates processing graphical objects in 3D space, where the position of each graphical object relative to other graphical objects and relative to the 3D coordinate system is known. Conversely, the screen-space pipeline 1422 can process graphical objects that have been projected from the 3D coordinate system onto a 2D planar surface representing the surface of the display device. Furthermore, the world-space pipeline 1420 can be divided into an alpha-stage pipeline and a beta-stage pipeline, where the alpha-stage pipeline includes pipeline stages from PD 1402 up to the task generation unit. The beta-stage pipeline includes pipeline stages from the topology generation unit up to VPC 1408. In this case, the graphics processing pipeline 1400 can perform a first set of operations (e.g., a single thread, a group of threads, or multiple groups of threads acting in concert) in the alpha-stage pipeline and a second set of operations (e.g., a single thread, a group of threads, or multiple groups of threads acting in concert) in the beta-stage pipeline.

[0177] If multiple graphics pipelines 1400 are in use, the vertex data and vertex attributes associated with a set of graphics objects can be partitioned so that each graphics processing pipeline 1400 has a similar workload throughout the alpha stage. Accordingly, alpha stage processing can substantially expand the amount of vertex data and vertex attributes, so that the amount of vertex data and vertex attributes generated by the task generation unit is significantly greater than the amount of vertex data and vertex attributes processed by PD 1402 and VAF 1404. Furthermore, task generation units associated with different graphics processing pipelines 1400 can generate vertex data and vertex attributes with different quality levels, i.e., starting the alpha stage with the same number of attributes. In such a case, the task distributor can redistribute the attributes generated by the alpha stage pipelines so that each graphics processing pipeline 1400 has approximately the same workload at the beginning of the beta stage pipeline.

[0178] Turn now Figure 15 A streaming multiprocessor (SM) 1500 is illustrated. The illustrated SM 1500 includes a K-scheduler unit 1504 coupled to an instruction cache 1502, wherein each scheduler unit 1504 receives an array of thread blocks from a pipeline manager (not shown) and manages instruction scheduling for one or more thread blocks in each active thread block array. The scheduler unit 1504 can schedule threads for execution in parallel thread groups, where each group may be referred to as a "thread warp". Thus, each thread warp may include, for example, 64 threads. Furthermore, the scheduler unit 1504 can manage multiple different thread blocks, assigning thread blocks to thread warps for execution. The scheduler unit can then schedule instructions from multiple different thread warps on various functional units during each clock cycle. Each scheduler unit 1504 may include one or more instruction dispatch units 1522, wherein each dispatch unit 1522 sends instructions to one or more functional units. The number of dispatch units 1522 may vary depending on the environment. In the example shown, scheduler unit 1504 includes two dispatch units 1522 that allow two different instructions from the same thread bundle to be dispatched during each clock cycle.

[0179] The SM 1500 may also include a register file 1506. The register file 1506 includes a set of registers that are partitioned among functional units such that each functional unit is assigned a dedicated portion of the register file 1506. The register file 1506 may also be partitioned among different thread bundles being executed by the SM 1500. In one example, the register file 1506 provides temporary storage for operands on data paths connected to functional units. The SM 1500 shown also includes L processing cores 1508, where L can be a relatively large number (e.g., 192). Each core 1508 can be a pipelined single-precision processing unit that includes floating-point arithmetic logic units (e.g., IEEE 754-2008) and integer arithmetic logic units.

[0180] The illustrated SM 1500 also includes M double-precision units (DPUs) 1510, N special function units (SFUs) 1512, and P load / store units (LSUs) 1514. Each DPU 1510 performs double-precision floating-point arithmetic, and each SFU 1512 performs special functions such as rectangular copy pixel blending. Furthermore, each LSU 1514 performs load and store operations between shared memory 1518 and register file 1506. In one example, load and store operations are performed via J texture units / L1 caches 1520 and an interconnect network 1516. In one example, the J texture units / L1 caches 1520 are also coupled to a crossbar switch (not shown). Therefore, the interconnect network 1516 can connect each function unit to register file 1506 and shared memory 1518. In one example, the interconnect network 1516 acts as a crossbar switch connecting any function unit to any register in register file 1506.

[0181] The SM 1500 can be implemented within a graphics processor (e.g., a graphics processing unit / GPU), where the texture unit / L1 cache 1520 can access texture maps from memory and sample the texture maps to produce sampled texture values ​​for use in the shader program. Texture operations performed by the texture unit / L1 cache include, but are not limited to, mip-map-based anti-aliasing.

[0182] Additional system overview example

[0183] Figure 16This is a block diagram of a processing system 1600 according to an embodiment. In various embodiments, system 1600 includes one or more processors 1602 and one or more graphics processors 1608, and may be a single-processor desktop computer system, a multiprocessor workstation system, or a server system having a large number of processors 1602 or processor cores 1607. In one embodiment, system 1600 is a processing platform included in a system-on-a-chip (SoC) for use in mobile devices, handheld devices, or embedded devices.

[0184] Embodiments of system 1600 may include or be included in the following: a server-based game platform, a game console (including game and media consoles), a mobile game console, a handheld game console, or an online game console. In some embodiments, system 1600 is a mobile phone, smartphone, tablet computing device, or mobile internet device. Data processing system 1600 may also include, be coupled to, or be integrated into the following: wearable devices, such as smartwatches, smart glasses, augmented reality devices, or virtual display devices. In some embodiments, data processing system 1600 is a television or set-top box device having one or more processors 1602 and a graphics interface generated by one or more graphics processors 1608.

[0185] In some embodiments, one or more processors 1602 each include one or more processor cores 1607 for processing instructions that, when executed, perform operations on the system and user software. In some embodiments, each of the one or more processor cores 1607 is configured to process a specific instruction set 1609. In some embodiments, the instruction set 1609 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). Multiple processor cores 1607 may each process different instruction sets 1609, which may include instructions for facilitating emulation of other instruction sets. Processor cores 1607 may also include other processing means, such as digital signal processors (DSPs).

[0186] In some embodiments, processor 1602 includes cache memory 1604. Depending on the architecture, processor 1602 may have a single internal cache or multiple levels of internal cache. In some embodiments, cache memory is shared among various components of processor 1602. In some embodiments, processor 1602 also uses external caches (e.g., Level 3 (L3) cache or Last Level Cache (LLC) (not shown), which can be shared among processor cores 1607 using known cache coherence techniques. Register file 1606 is additionally included in processor 1602, and the register file may include different types of registers for storing different types of data (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers). Some registers may be general-purpose registers, while others may be specific to the design of processor 1602.

[0187] In some embodiments, processor 1602 is coupled to processor bus 1610 to transmit communication signals (e.g., address, data, or control signals) between processor 1602 and other components in system 1600. In one embodiment, system 1600 uses an exemplary 'central' system architecture including a memory controller central hub 1616 and an input / output (I / O) controller central hub 1630. Memory controller central hub 1616 facilitates communication between memory devices and other components of system 1600, while I / O controller central hub (ICH) 1630 provides connectivity to I / O devices via a local I / O bus. In one embodiment, the logic of memory controller central hub 1616 is integrated within the processor.

[0188] Memory device 1620 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or some other memory device with suitable performance to serve as process memory. In one embodiment, memory device 1620 may operate as system memory of system 1600 to store data 1622 and instructions 1621 for use when one or more processors 1602 execute an application or process. Memory controller hub 1616 is also coupled to an optional external graphics processor 1612, which may be coupled to graphics processor 1608 in processor 1602 to perform graphics and media operations.

[0189] In some embodiments, ICH 1630 enables peripheral devices to be connected to memory device 1620 and processor 1602 via a high-speed I / O bus. I / O peripheral devices include, but are not limited to: audio controller 1646, firmware interface 1628, wireless transceiver 1626 (e.g., Wi-Fi, Bluetooth), data storage device 1624 (e.g., hard disk drive, flash memory, etc.), and a conventional I / O controller 1640 for coupling conventional (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 1642 connect input devices (e.g., a keyboard and mouse combination 1644). Network controller 1634 may also be coupled to ICH 1630. In some embodiments, a high-performance network controller (not shown) is coupled to processor bus 1610. It will be appreciated that the illustrated system 1600 is exemplary and not limiting, as other types of data processing systems configured differently may also be used. For example, the I / O controller hub 1630 may be integrated within one or more processors 1602, or the memory controller hub 1616 and the I / O controller hub 1630 may be integrated within a discrete external graphics processor (such as external graphics processor 1612).

[0190] Figure 17 This is a block diagram of an embodiment of processor 1700, which has one or more processor cores 1702A to 1702N, an integrated memory controller 1714, and an integrated graphics processor 1708. Figure 17 Those elements having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Processor 1700 may include up to and including additional cores 1702N, indicated by dashed boxes. Each of processor cores 1702A to 1702N includes one or more internal cache units 1704A to 1704N. In some embodiments, each processor core is also able to access one or more shared cache units 1706.

[0191] Internal cache units 1704A to 1704N and shared cache unit 1706 represent the cache memory hierarchy within processor 1700. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared intermediate level caches (e.g., Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache), wherein the highest-level cache preceding external memory is classified as LLC. In some embodiments, cache coherence logic maintains coherence between the various cache units 1706 and 1704A to 1704N.

[0192] In some embodiments, the processor 1700 may further include a set of one or more bus controller units 1716 and a system agent core 1710. The one or more bus controller units 1716 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Fast Bus). The system agent core 1710 provides management functions for each processor unit. In some embodiments, the system agent core 1710 includes one or more integrated memory controllers 1714 for managing access to various external memory devices (not shown).

[0193] In some embodiments, one or more of processor cores 1702A to 1702N include support for simultaneous multithreaded processing. In such an embodiment, system agent core 1710 includes components for coordinating and operating cores 1702A to 1702N during multithreaded processing. System agent core 1710 may additionally include a power control unit (PCU) including logic and components for regulating the power states of processor cores 1702A to 1702N and graphics processor 1708.

[0194] In some embodiments, processor 1700 further includes a graphics processor 1708 for performing graphics processing operations. In some embodiments, graphics processor 1708 is coupled to a set of shared cache units 1706 and system proxy core 1710, including one or more integrated memory controllers 1714. In some embodiments, display controller 1711 is coupled to graphics processor 1708 to drive graphics processor output to one or more coupled displays. In some embodiments, display controller 1711 may be a separate module coupled to graphics processor via at least one interconnect, or it may be integrated within graphics processor 1708 or system proxy core 1710.

[0195] In some embodiments, a ring-based interconnect unit 1712 is used to couple the internal components of the processor 1700. However, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, including those well known in the art, may be used. In some embodiments, the graphics processor 1708 is coupled to the ring interconnect 1712 via I / O link 1713.

[0196] Exemplary I / O link 1713 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 1718 (such as an eDRAM module). In some embodiments, each of processor cores 1702 to 1702N and graphics processor 1708 uses the embedded memory module 1718 as a shared last-level cache.

[0197] In some embodiments, processor cores 1702A to 1702N are homogeneous cores executing the same instruction set architecture. In another embodiment, processor cores 1702A to 1702N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of processor cores 1702A to 1702N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or different instruction values. In one embodiment, processor cores 1702A to 1702N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively higher power consumption are coupled to one or more power cores with lower power consumption. Additionally, processor 1700 can be implemented on one or more chips or implemented as a SoC integrated circuit having, among other components, the components shown.

[0198] Figure 18 This is a block diagram of a graphics processor 1800, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates with memory via a mapped I / O interface to registers on the graphics processor and using commands placed in processor memory. In some embodiments, the graphics processor 1800 includes a memory interface 1814 for accessing memory. The memory interface 1814 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0199] In some embodiments, the graphics processor 1800 further includes a display controller 1802 for driving display output data to a display device 1820. The display controller 1802 includes hardware for one or more overlapping planes of the display and a multilayer video or user interface element. In some embodiments, the graphics processor 1800 includes a video codec engine 1806 for encoding, decoding, or converting media codes to, from, or between one or more media encoding formats, including but not limited to: Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Decoding (AVC) formats (such as H.264 / MPEG-4 AVC), and Society of Motion Picture & Television Engineers (SMPTE) 421M / VC-1, and Joint Group of Picture Experts Group (JPEG) formats (such as JPEG and Motion JPEG (MJPEG)).

[0200] In some embodiments, the graphics processor 1800 includes a block image transfer (BLIT) engine 1804 for performing two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfer. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 1810. In some embodiments, the graphics processing engine 1810 is a computational engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0201] In some embodiments, GPE 1810 includes a 3D pipeline 1812 for performing 3D operations, such as rendering 3D images and scenes using processing functions acting on the shapes of 3D primitives (e.g., rectangles, triangles, etc.). The 3D pipeline 1812 includes programmable and fixed-function elements that perform various tasks to the 3D / media subsystem 1815 within components and / or generated execution threads. While the 3D pipeline 1812 can be used to perform media operations, embodiments of GPE 1810 also include a media pipeline 1816 specifically for performing media operations, such as video post-processing and image enhancement.

[0202] In some embodiments, the media pipeline 1816 includes fixed-function or programmable logic units for performing one or more specialized media operations, such as video decoding acceleration, video deinterleaving, and video encoding acceleration, in place of or on behalf of the video codec engine 1806. In some embodiments, the media pipeline 1816 further includes a thread generation unit to generate threads for execution on the 3D / media subsystem 1815. The generated threads perform calculations on the media operations for one or more graphics execution units included in the 3D / media subsystem 1815.

[0203] In some embodiments, the 3D / media subsystem 1815 includes logic for executing threads generated by the 3D pipeline 1812 and the media pipeline 1816. In one embodiment, the pipelines send thread execution requests to the 3D / media subsystem 1815, the 3D / media subsystem including thread dispatch logic for arbitrating and dispatching requests to available thread execution resources. Execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 1815 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) for sharing data between threads and storing output data.

[0204] 3D / Media Processing

[0205] Figure 19 This is a block diagram of a graphics processing engine 1910 of a graphics processor according to some embodiments. In one embodiment, GPE 1910 is... Figure 18 The image shows a version of GPE 1810. Figure 19 Elements having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0206] In some embodiments, GPE 1910 is coupled to command stream converter 1903, which provides command streams to the GPE's 3D pipeline 1912 and media pipeline 1916. In some embodiments, command stream converter 1903 is coupled to memory, which may be system memory, or one or more of internal cache memory and shared cache memory. In some embodiments, command stream converter 1903 receives commands from memory and sends the commands to 3D pipeline 1912 and / or media pipeline 1916. The commands are instructions obtained from a ring buffer storing instructions for 3D pipeline 1912 and media pipeline 1916. In one embodiment, the ring buffer may additionally include a batch command buffer storing multiple batches of multiple commands. 3D pipeline 1912 and media pipeline 1916 process the commands by performing operations via logic within their respective pipelines or by dispatching one or more execution threads to execution unit array 1914. In some embodiments, the execution unit array 1914 is scalable, such that the array includes a variable number of execution units based on the target power and performance level of the GPE 1910.

[0207] In some embodiments, the sampling engine 1930 is coupled to memory (e.g., cache memory or system memory) and the execution unit array 1914. In some embodiments, the sampling engine 1930 provides a memory access mechanism for the execution unit array 1914, which allows the execution array 1914 to read graphics and media data from memory. In some embodiments, the sampling engine 1930 includes logic for performing specialized image sampling operations for media.

[0208] In some embodiments, the dedicated media sampling logic in the sampling engine 1930 includes a denoising / deinterlacing module 1932, a motion estimation module 1934, and an image scaling and filtering module 1936. In some embodiments, the denoising / deinterlacing module 1932 includes logic for performing one or more of a denoising or deinterlacing algorithm on the decoded video data. The deinterlacing logic combines the alternating lengths of the interlaced video content into a single frame of video. The denoising logic reduces or removes data noise from the video and image data. In some embodiments, the denoising and deinterlacing logic is motion-adaptive and uses spatial or temporal filtering based on the amount of motion detected in the video data. In some embodiments, the denoising / deinterlacing module 1932 includes dedicated motion detection logic (e.g., within the motion estimation engine 1934).

[0209] In some embodiments, the motion estimation engine 1934 provides hardware acceleration for video operations by performing video acceleration functions (such as motion vector estimation and prediction) on the video data. The motion estimation engine determines motion vectors describing the transformation of image data between consecutive video frames. In some embodiments, the graphics processor media codec uses the video motion estimation engine 1934 to perform operations on macroblock-level video, which may be too computationally intensive to perform using a general-purpose processor. In some embodiments, the motion estimation engine 1934 is typically used in graphics processor components to assist video decoding and processing functions that are sensitive to or adaptive to the direction or magnitude of motion within the video data.

[0210] In some embodiments, the image scaling and filtering module 1936 performs image processing operations to improve the visual quality of the resulting images and videos. In some embodiments, the scaling and filtering module 1936 processes image and video data during sampling operations before providing data to the execution unit array 1914.

[0211] In some embodiments, the GPE 1910 includes a data port 1944 that provides additional mechanisms for enabling the graphics subsystem to access memory. In some embodiments, the data port 1944 facilitates memory access for operations including render target writes, constant buffer reads, temporary memory space reads / writes, and media surface access. In some embodiments, the data port 1944 includes cache memory space for cached access to memory. The cache memory may be a single data cache or may be partitioned into multiple caches (e.g., render buffer cache, constant buffer cache, etc.) for multiple subsystems accessing memory via the data port. In some embodiments, threads executing on execution units in the execution unit array 1914 communicate with the data port by exchanging messages via a data distribution interconnect coupled to each subsystem of the GPE 1910.

[0212] Execution unit

[0213] Figure 20 This is a block diagram of another embodiment of the graphics processor 2000. Figure 20 Elements having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0214] In some embodiments, the graphics processor 2000 includes a ring interconnect 2002, a pipeline front-end 2004, a media engine 2037, and graphics cores 2080A to 2080N. In some embodiments, the ring interconnect 2002 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of a plurality of processors integrated within a multi-core processing system.

[0215] In some embodiments, the graphics processor 2000 receives multiple batches of commands via a ring interconnect 2002. The incoming commands are translated by a command stream converter 2003 in the pipeline front-end 2004. In some embodiments, the graphics processor 2000 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2080A to 2080N. For 3D geometry processing commands, the command stream converter 2003 supplies commands to a geometry pipeline 2036. For at least some media processing commands, the command stream converter 2003 supplies commands to a video front-end 2034, which is coupled to a media engine 2037. In some embodiments, the media engine 2037 includes a video quality engine (VQE) 2030 for video and image post-processing and a multi-format encoding / decoding (MFX) engine 2033 for providing hardware-accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 2036 and the media engine 2037 each generate execution threads for use with thread execution resources provided by at least one graphics core 2080A.

[0216] In some embodiments, the graphics processor 2000 includes scalable thread execution resources characterized by modular cores 2080A to 2080N (sometimes referred to as core slices), each modular core having a plurality of sub-cores 2050A to 2050N, 2060A to 2060N (sometimes referred to as core sub-slices). In some embodiments, the graphics processor 2000 may have any number of graphics cores 2080A to 2080N. In some embodiments, the graphics processor 2000 includes a graphics core 2080A, which has at least a first sub-core 2050A and a second sub-core 2060A. In other embodiments, the graphics processor is a low-power processor having a single sub-core (e.g., 2050A). In some embodiments, the graphics processor 2000 includes a plurality of graphics cores 2080A to 2080N, each graphics core including a set of first sub-cores 2050A to 2050N and a set of second sub-cores 2060A to 2060N. Each of the first set of sub-cores 2050A to 2050N includes at least a first set of execution units 2052A to 2052N and media / texture samplers 2054A to 2054N. Each of the second set of sub-cores 2060A to 2060N includes at least a second set of execution units 2062A to 2062N and samplers 2064A to 2064N. In some embodiments, each sub-core 2050A to 2050N and 2060A-2060N shares a set of shared resources 2070A to 2070N. In some embodiments, these shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0217] Figure 21Threadable execution logic 2100 is shown, including an array of processing elements employed in some embodiments of GPE. Figure 21 Those elements that have the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0218] In some embodiments, thread execution logic 2100 includes a pixel shader 2102, a thread dispatcher 2104, an instruction cache 2106, a scalable execution unit array including multiple execution units 2108A to 2108N, a sampler 2110, a data cache 2112, and a data port 2114. In one embodiment, these included components are interconnected via an interconnect structure linking to each of these components. In some embodiments, thread execution logic 2100 includes one or more connections to memory (e.g., system memory or cache memory) via one of the instruction cache 2106, data port 2114, sampler 2110, and execution unit arrays 2108A to 2108N. In some embodiments, each execution unit (e.g., 2108A) is an individual vector processor capable of executing multiple concurrent threads and processing multiple data elements in parallel for each thread. In some embodiments, execution unit arrays 2108A to 2108N include any number of individual execution units.

[0219] In some embodiments, execution unit arrays 2108A to 2108N are primarily used to execute "shader" programs. In some embodiments, the execution units in arrays 2108A to 2108N execute instruction sets that include native support for many standard 3D graphics shader instructions, enabling the execution of shader programs from graphics libraries (e.g., Direct 3D and OpenGL) with minimal transformations. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., computation and media shaders).

[0220] Each execution unit in the execution unit arrays 2108A to 2108N operates on an array of data elements. The number of data elements is the "execution size" or the number of channels used for instructions. An execution channel is a logical execution unit used for data element access, masking, and flow control within instructions. The number of channels may be independent of the number of physical arithmetic logic units (ALUs) or floating-point units (FPUs) for a particular graphics processor. In some embodiments, execution units 2108A to 2108N support both integer and floating-point data types.

[0221] The execution unit instruction set includes Single Instruction Multiple Data (SIMD). Various data elements can be stored in registers as compressed data types, and the execution unit will process these elements based on their data size. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in registers, and the execution unit operates on the vector as four individual 64-bit compressed data elements (four times the word length (QW) size), eight individual 32-bit compressed data elements (double the word length (DW) size), sixteen individual 16-bit compressed data elements (word length (W) size), or thirty-two individual 8-bit data elements (byte (B) size). However, different vector widths and register sizes are possible.

[0222] One or more internal instruction caches (e.g., 2106) are included in thread execution logic 2100 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 2112) are included to cache thread data during thread execution. In some embodiments, sampler 2110 is included for providing texture sampling for 3D operations and media sampling for media operations. In some embodiments, sampler 2110 includes dedicated texture or media sampling functions to process texture or media data during the sampling process before providing sampled data to the execution unit.

[0223] During execution, the graphics pipeline and media pipeline send thread initiation requests to thread execution logic 2100 via thread generation and dispatch logic. In some embodiments, thread execution logic 2100 includes a local thread dispatcher 2104 that arbitrates thread initiation requests from the graphics pipeline and media pipeline and instantiates the requested thread on one or more execution units 2108A to 2108N. For example, the geometry pipeline (e.g., Figure 20 (2036) dispatches vertex processing, tessellation, or geometry processing threads to thread execution logic 2100. Figure 21 In some embodiments, thread dispatcher 2104 can also handle runtime thread generation requests from the shader execution program.

[0224] Once a set of geometric objects has been processed and rasterized into pixel data, pixel shader 2102 is invoked to further compute output information and cause the results to be written to an output surface (e.g., a color buffer, depth buffer, stencil buffer, etc.). In some embodiments, pixel shader 2102 computes values ​​for vertex attributes that are interpolated across the rasterized objects. In some embodiments, pixel shader 2102 then executes a pixel shader program provided by an application programming interface (API). To execute the pixel shader program, pixel shader 2102 dispatches a thread to an execution unit (e.g., 2108A) via thread dispatcher 2104. In some embodiments, pixel shader 2102 uses texture sampling logic in sampler 2110 to access texture data in a texture map stored in memory. Arithmetic operations performed on the texture data and input geometry compute pixel color data for each geometric fragment, or discard one or more pixels for further processing.

[0225] In some embodiments, data port 2114 provides a memory access mechanism for enabling thread execution logic 2100 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, data port 2114 includes or is coupled to one or more cache memories (e.g., data cache 2112) to cache data via the data port for memory access.

[0226] Figure 22 This is a block diagram illustrating a graphical processor instruction format 2200 according to some embodiments. In one or more embodiments, the graphics processor execution unit supports an instruction set having multiple instruction formats. Solid lines indicate components that are typically included in the execution unit instructions, while dashed lines include components that are optional or included only in a subset of the instructions. In some embodiments, the instruction format 2200 described and illustrated are macro instructions, as they are instructions supplied to the execution unit, as opposed to micro-operations generated from instruction decoding (once the instruction is processed).

[0227] In some embodiments, the graphics processor execution unit natively supports instructions in 128-bit format 2210. A 64-bit compact instruction format 2230 can be used for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit format 2210 provides access to all instruction options, while some options and operations are restricted in the 64-bit format 2230. The native instructions available in 64-bit format 2230 vary depending on the embodiment. In some embodiments, instructions are partially compacted using a set of index values ​​in index field 2213. The execution unit hardware references a set of compression tables based on these index values ​​and uses the output of the compression tables to reconstruct the native instructions in 128-bit format 2210.

[0228] For each format, instruction opcode 2212 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an addition instruction, the execution unit performs simultaneous addition across each color channel representing a texture element or image element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, instruction control field 2214 enables control over certain execution options, such as channel selection (e.g., prediction) and data channel ordering (e.g., blending). For 128-bit instructions 2210, execution size field 2216 limits the number of data channels to be executed in parallel. In some embodiments, execution size field 2216 is not available for 64-bit compact instruction format 2230.

[0229] Some execution unit instructions have up to three operands, including two source operands src0 2220 and src1 2222, and a destination 2218. In some embodiments, the execution unit supports dual-destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 2224), where the instruction opcode 2212 determines the number of source operands. The last source operand of the instruction may be an immediate (e.g., hard-coded) value passed through the instruction.

[0230] In some embodiments, the 128-bit instruction format 2210 includes access / address mode information 2226, which specifies, for example, whether to use direct register addressing mode or indirect register addressing mode. When using direct register addressing mode, the register addresses of one or more operands are provided directly by bits in the instruction 2210.

[0231] In some embodiments, the 128-bit instruction format 2210 includes an access / address mode field 2226 that specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode defines the data access alignment of the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction 2210 may use byte-aligned addressing for both the source and destination operands, and when in a second mode, the instruction 2210 may use 16-byte aligned addressing for all source and destination operands.

[0232] In one embodiment, the address mode portion of the access / address mode field 2226 determines whether the instruction will use direct or indirect addressing. When using direct register addressing mode, the bits in instruction 2210 directly provide the register addresses of one or more operands. When using indirect register addressing mode, the register addresses of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0233] In some embodiments, instructions are grouped based on the 2212-bit field of the opcode to simplify opcode decoding 2240. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is merely exemplary. In some embodiments, the move and logic opcode group 2242 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2242 shares five most significant bits (MSB), where move (mov) instructions are in the form of 0000xxxxb, and logic instructions are in the form of 0001xxxxb. The flow control instruction group 2244 (e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). The promiscuous instruction group 2246 includes a mixture of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). Parallel math instruction group 2248 includes component-wise arithmetic instructions (e.g., add, subtract mul) in the form 0100xxxxb (e.g., 0x40). Parallel math group 2248 performs arithmetic operations in parallel across data channels. Vector math group 2250 includes arithmetic instructions (e.g., dp4) in the form 0101xxxxb (e.g., 0x50). Vector math group performs arithmetic, such as calculating the dot product of vector operands.

[0234] Graphics Pipeline

[0235] Figure 23 This is a block diagram of another embodiment of the graphics processor 2300. Figure 23 Elements having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0236] In some embodiments, the graphics processor 2300 includes a graphics pipeline 2320, a media pipeline 2330, a display engine 2340, thread execution logic 2350, and a rendering output pipeline 2370. In some embodiments, the graphics processor 2300 is a graphics processor within a multi-core processing system including one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or by commands issued to the graphics processor 2300 via a ring interconnect 2302. In some embodiments, the ring interconnect 2302 couples the graphics processor 2300 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 2302 are translated by a command stream translator 2303, which supplies instructions to individual components of the graphics pipeline 2320 or the media pipeline 2330.

[0237] In some embodiments, command stream converter 2303 directs the operation of vertex acquirer 2305, which reads vertex data from memory and executes vertex processing commands provided by command stream converter 2303. In some embodiments, vertex acquirer 2305 provides vertex data to vertex shader 2307, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, vertex acquirer 2305 and vertex shader 2307 execute vertex processing instructions by dispatching execution threads to execution units 2352A and 2352B via thread dispatcher 2331.

[0238] In some embodiments, execution units 2352A and 2352B are arrays of vector processors having an instruction set for performing graphics and media operations. In some embodiments, execution units 2352A and 2352B have additional L1 caches 2351 specifically for each array or shared between arrays. The caches may be configured as data caches, instruction caches, or a single cache partitioned to contain data and instructions in different partitions.

[0239] In some embodiments, the graphics pipeline 2320 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable shell shader 2311 configures the tessellation operation. A programmable domain shader 2317 provides back-end evaluation of the tessellation output. A tessellation unit 2313 operates in the direction of the shell shader 2311 and includes dedicated logic for generating a detailed set of geometric objects based on a rough geometry model that is provided as input to the graphics pipeline 2320. In some embodiments, the tessellation components 2311, 2313, and 2317 can be bypassed if tessellation is not used.

[0240] In some embodiments, the complete geometry object may be processed by the geometry shader 2319 via one or more threads dispatched to execution units 2352A, 2352B, or may proceed directly to the clipper 2329. In some embodiments, the geometry shader operates on the entire geometry object (rather than vertices or vertex patches such as those in previous stages of the graphics pipeline). If tessellation is disabled, the geometry shader 2319 receives input from the vertex shader 2307. In some embodiments, the geometry shader 2319 may be programmed by a geometry shader program to perform geometric tessellation when the tessellation unit is disabled.

[0241] Prior to rasterization, clipper 2329 processes vertex data. Clipper 2329 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader capabilities. In some embodiments, rasterizer 2373 (e.g., a depth testing component) in the rendering output pipeline 2370 dispatches pixel shaders to convert geometric objects into their pixel-wise representations. In some embodiments, pixel shader logic is included in thread execution logic 2350. In some embodiments, the application can bypass rasterizer 2373 and access the unrasterized vertex data via outgoing unit 2323.

[0242] The graphics processor 2300 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be transferred among the main components of the processor. In some embodiments, execution units 2352A, 2352B and(multiple) associated caches 2351, texture and media samplers 2354, and texture / sampler cache 2358 are interconnected via data port 2356 to perform memory accesses and communicate with the processor's rendering output pipeline components. In some embodiments, samplers 2354, caches 2351, 2358, and execution units 2352A, 2352B each have a separate memory access path.

[0243] In some embodiments, the rendering output pipeline 2370 includes a rasterizer 2373 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes windower / masker units for performing fixed-function triangle and line rasterization. Associated rendering cache 2378 and depth cache 2379 are also available in some embodiments. Pixel manipulation unit 2377 performs pixel-based operations on the data; however, in some examples, pixel operations associated with 2D operations (e.g., bit-block image transfer and blending) are performed by the 2D engine 2341, or at display time by the display controller 2343 using an overlay display plane. In some embodiments, a shared L3 cache 2375 is available for all graphics components, allowing data to be shared without using main system memory.

[0244] In some embodiments, the graphics processor media pipeline 2330 includes a media engine 2337 and a video front-end 2334. In some embodiments, the video front-end 2334 receives pipeline commands from a command stream converter 2303. In some embodiments, the media pipeline 2330 includes a separate command stream converter. In some embodiments, the video front-end 2334 processes media commands before sending them to the media engine 2337. In some embodiments, the media engine 2337 includes thread generation functionality for generating threads for dispatching to thread execution logic 2350 via a thread dispatcher 2331.

[0245] In some embodiments, the graphics processor 2300 includes a display engine 2340. In some embodiments, the display engine 2340 is external to the processor 2300 and coupled to the graphics processor via a ring interconnect 2302 or some other interconnect bus or structure. In some embodiments, the display engine 2340 includes a 2D engine 2341 and a display controller 2343. In some embodiments, the display engine 2340 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 2343 is coupled to a display device (not shown), which may be a system-integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0246] In some embodiments, the graphics pipeline 2320 and media pipeline 2330 may be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, the graphics processor's driver software translates API schedules specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL) and Open Computing Language (OpenCL) from the Khronos Group, the Direct 3D library from Microsoft, or both OpenGL and D3D. Support may also be provided for the open-source computer vision library (OpenCV). If a pipeline mapping from future API calls to the graphics processor's pipeline is possible, then future APIs with compatible 3D pipelines will also be supported.

[0247] Graphical Pipeline Programming

[0248] Figure 24A This is a block diagram of a schematic processor command format 2400 according to some embodiments. Figure 24B This is a block diagram of a schematic processor command sequence 2410 according to an embodiment. Figure 24A Solid lines in the diagram represent components that are typically included in the drawing command, while dashed lines represent optional components or components that are only included in a subset of the drawing command. Figure 24A An exemplary graphics processor command format 2400 includes data fields for identifying the target client 2402 of the command, the command operation code (opcode) 2404, and the command's associated data 2406. Some commands also include a sub-opcode 2405 and a command size 2408.

[0249] In some embodiments, client 2402 specifies a client unit of a graphics device that processes command data. In some embodiments, a graphics processor command parser examines the client field of each command to adjust further processing of the command and route command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads opcode 2404 and (if present) sub-opcode 2405 to determine the operation to be performed. The client unit uses information in data field 2406 to execute the command. For some commands, an explicit command size 2408 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some commands in the command based on the command opcode. In some embodiments, commands are aligned via multiples of double word length.

[0250] Figure 24B The flowchart illustrates an exemplary graphics processor command sequence 2410. In some embodiments, software or firmware of a data processing system characterized by an embodiment of a graphics processor uses a version of the illustrated command sequence to initiate, execute, and terminate a set of graphics operations. Sample command sequences are shown and described for illustrative purposes only, as embodiments are not limited to these particular commands or this command sequence. Furthermore, the commands may be issued as a batch of commands in a command sequence, such that the graphics processor will process the command sequence in at least partially simultaneous manner.

[0251] In some embodiments, the graphics processor command sequence 2410 may be initiated by a pipeline dump clearing command 2412 to allow any active graphics pipeline to complete its currently pending commands. In some embodiments, the 3D pipeline 2422 and the media pipeline 2424 do not operate simultaneously. Pipeline dump clearing is performed to allow any pending commands from active graphics pipelines to complete. In response to pipeline dump clearing, the graphics processor's command resolver suspends command processing until the active graphics engine completes its pending operations and the associated read cache is invalidated. Optionally, any data marked 'dirty' in the render cache may be dumped to memory. In some embodiments, pipeline dump clearing command 2412 may be used for pipeline synchronization or before placing the graphics processor in a low-power state.

[0252] In some embodiments, pipeline selection command 2413 is used when a sequence of commands requires the graphics processor to make an explicit switch between pipelines. In some embodiments, pipeline selection command 2413 is only required once in an execution context before a pipeline command is issued, unless the context requires issuing commands for two pipelines. In some embodiments, pipeline dump clearing command 2412 is required immediately before pipeline switching via pipeline selection command 2413.

[0253] In some embodiments, pipeline control command 2414 configures a graphics pipeline for operation and is used to program the 3D pipeline 2422 and the media pipeline 2424. In some embodiments, pipeline control command 2414 configures the pipeline state of an active pipeline. In one embodiment, pipeline control command 2414 is used for pipeline synchronization and for clearing data from one or more cache memories within an active pipeline before processing a batch of commands.

[0254] In some embodiments, return buffer state command 2416 is used to configure a set of return buffers for causing corresponding pipelined write data. Some pipelined operations require allocating, selecting, or configuring one or more return buffers, which write intermediate data to said return buffers during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, return buffer state 2416 includes selecting the size and number of return buffers for a set of pipelined operations.

[0255] The remaining commands in the command sequence differ based on the active pipeline used for the operation. Based on pipeline determination 2420, the command sequence is customized according to the 3D pipeline 2422 and the media pipeline 2424, the 3D pipeline starting at 3D pipeline state 2430 and the media pipeline starting at media pipeline state 2440.

[0256] Commands for 3D pipeline state 2430 include 3D state setting commands for: vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that will be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, 3D pipeline state 2430 commands can also selectively disable or bypass specific pipeline components (if those components will not be used).

[0257] In some embodiments, the 3D primitive 2432 command is used to submit 3D primitives to be processed by the 3D pipeline. The command and associated parameters passed to the graphics processor via the 3D primitive 2432 are forwarded to a vertex acquisition function in the graphics pipeline. The vertex acquisition function uses the 3D primitive 2432 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, the 3D primitive 2432 command is used to perform vertex operations on the 3D primitives via a vertex shader. To process the vertex shader, the 3D pipeline 2422 dispatches shader execution threads to the graphics processor execution unit.

[0258] In some embodiments, the 3D pipeline 2422 is triggered by executing command 2434 or an event. In some embodiments, register writing triggers command execution. In some embodiments, execution is triggered by a 'go' or 'kick' command in a command sequence. In one embodiment, pipeline synchronization commands are used to trigger command execution to dump and clear the command sequence through the graphics pipeline. The 3D pipeline performs geometric processing on 3D primitives. Once the operations are complete, the resulting geometry is rasterized, and the pixel engine colors the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for those operations.

[0259] In some embodiments, when performing media operations, the graphics processor command sequence 2410 follows a path of media pipeline 2424. Generally, the specific purpose and programming of media pipeline 2424 depend on the media or computational operation to be performed. During media decoding, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed, and media decoding can be performed wholly or partially using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processing unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using computational shader programs that are not explicitly related to the rendering of graphics primitives.

[0260] In some embodiments, the media pipeline 2424 is configured in a manner similar to that of the 3D pipeline 2422. A set of media pipeline status commands 2440 is dispatched to or placed in a command queue prior to the media object command 2442. In some embodiments, the media pipeline status commands 2440 include data for configuring media pipeline elements that will be used to process media objects. This includes data for configuring video decoding and video encoding logic within the media pipeline (e.g., encoding or decoding modes). In some embodiments, the media pipeline status commands 2440 also support using one or more pointers to "indirect" status elements that contain a batch of status settings.

[0261] In some embodiments, media object command 2442 supplies pointers to media objects to be processed by the media pipeline. The media object includes a memory buffer containing video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object command 2442. Once the pipeline states are configured and media object command 2442 is queued, media pipeline 2424 is triggered via execution command 2444 or an equivalent execution event (e.g., register write). The output from media pipeline 2424 can then be post-processed by operations provided by 3D pipeline 2422 or media pipeline 2424. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0262] Graphical software architecture

[0263] Figure 25 An exemplary graphics software architecture of a data processing system 2500 according to some embodiments is shown. In some embodiments, the software architecture includes a 3D graphics application 2510, an operating system 2520, and at least one processor 2530. In some embodiments, the processor 2530 includes a graphics processor 2532 and one or more general-purpose processor cores 2534. The graphics application 2510 and the operating system 2520 each execute in the system memory 2550 of the data processing system.

[0264] In some embodiments, the 3D graphics application 2510 includes one or more shader programs, which include shader instructions 2512. The shader language instructions may be in the form of a high-level shader language, such as High-Level Shader Language (HLSL) or OpenGL Shader Language (GLSL). The application also includes executable instructions 2514 in machine language suitable for execution by a general-purpose processor core 2534. The application also includes geometric objects 2516 defined by vertex data.

[0265] In some embodiments, the operating system 2520 is from Microsoft Corporation. The operating system 2520 is a proprietary Unix-like operating system using a variant of the Linux kernel or an open-source Unix-like operating system. When the Direct3D API is in use, the operating system 2520 uses a front-end shader compiler 2524 to compile any shader instructions 2512 rendered in HLSL into a low-level shader language. This compilation can be just-in-time (JIT) compilation or pre-compilation of the application-executable shaders. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application 2510.

[0266] In some embodiments, the user-mode graphics driver 2526 includes a back-end shader compiler 2527 for translating shader instructions 2512 into a hardware-specific representation. When the OpenGL API is in use, shader instructions 2512 in GLSL high-level language are passed to the user-mode graphics driver 2526 for compilation. In some embodiments, the user-mode graphics driver 2526 uses operating system kernel-mode functions 2528 to communicate with the kernel-mode graphics driver 2529. In some embodiments, the kernel-mode graphics driver 2529 communicates with the graphics processor 2532 to dispatch commands and instructions.

[0267] IP core implementation

[0268] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit (e.g., a processor). For example, the machine-readable medium may include instructions representing various logic within the processor. When read by a machine, the instructions may cause the machine to manufacture logic for performing the techniques described herein. Such representations (referred to as “IP cores”) are reusable units of logic for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be supplied to consumers or manufacturing facilities that load the hardware model onto manufacturing machines that manufacture integrated circuits. Integrated circuits may be manufactured such that the circuits perform the operations described in association with any of the embodiments described herein.

[0269] Figure 26 This is a block diagram illustrating an IP core development system 2600 according to an embodiment, which can be used to manufacture integrated circuits to perform operations. The IP core development system 2600 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to build entire integrated circuits (e.g., SOC integrated circuits). Design facility 2630 can generate software simulation 2610 of the IP core design using a high-level programming language (e.g., C / C++). Software simulation 2610 can be used to design, test, and verify the behavior of the IP core. Register transfer level (RTL) designs can then be created or synthesized from the simulation model 2600. RTL design 2615 is an abstraction of the behavior of an integrated circuit (including associated logic performed using the modeled digital signals) that models the flow of digital signals between hardware registers. In addition to RTL design 2615, lower-level designs at logic levels or transistor levels can also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation can vary.

[0270] The RTL design 2615 or its equivalent can be further synthesized into a hardware model 2620 by the design facility. This hardware model can be in the form of a hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to validate the IP core design. The IP core design can be stored in non-volatile memory 2640 (e.g., hard disk, flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 2665. Alternatively, the IP core design can be transmitted (e.g., via the Internet) via a wired connection 2650 or a wireless connection 2660. The manufacturing facility 2665 can then manufacture an integrated circuit at least partially based on the IP core design. The manufactured integrated circuit can be configured to perform operations according to at least one embodiment described herein.

[0271] Figure 27 This is a block diagram illustrating an exemplary system-on-a-chip integrated circuit 2700 according to an embodiment, which can be fabricated using one or more IP cores. The exemplary integrated circuit includes one or more application processors 2705 (e.g., a CPU), at least one graphics processor 2710, and may additionally include an image processor 2715 and / or a video processor 2720, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit includes peripheral or bus logic, including a USB controller 2725, a UART controller 2730, an SPI / SDIO controller 2735, and I... 2 S / I 2 C controller 2740. Additionally, the integrated circuit may include a display device 2745 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 2750 and a Mobile Industry Processor Interface (MIPI) display interface 2755. Storage may be provided by a flash memory subsystem 2760 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 2765 for accessing SDRAM or SRAM memory devices. Some integrated circuits also include an embedded security engine 2770.

[0272] Additionally, other logic and circuitry may be included in the processor of the integrated circuit 2700, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0273] In one example, ROP 1418 ( Figure 14 Determine the template printing values ​​and use those values ​​to control the size of coarse pixels, as shown in the following example. Figures 6 to 10 And as described in the following examples.

[0274] Additional notes and examples

[0275] Example 1 may include a performance-enhanced computing system comprising: a display; a two-dimensional (2D) texture memory; a graphics pipeline coupled to the display; and logic for determining 2D texture values ​​and using stencil printing values ​​to control the coarse pixel size of the graphics pipeline via the 2D texture memory.

[0276] Example 2 may include a system as described in Example 1, wherein the 2D texture value includes a first bit range defining a first dimension of the coarse pixel size and a second bit range defining a second dimension of the coarse pixel size.

[0277] Example 3 may include a system as described in Example 1, wherein the coarse pixel size is controlled pixel-by-pixel for a plurality of pixels, and wherein the coarse pixel size varies across the plurality of pixels.

[0278] Example 4 may include a system as described in any one of Examples 1 to 3, wherein the 2D texture memory includes a stencil printing buffer, wherein the 2D texture value is a stencil printing value, and wherein the coarse pixel size is controlled by the stencil printing buffer.

[0279] Example 5 may include a system as described in Example 4, wherein the stencil printing value is determined during an initial round involving depth analysis, and the coarse pixel value is controlled during subsequent rounds involving shader execution.

[0280] Example 6 may include a system as described in Example 4, wherein the display is used to visually present a scene being rendered by the graphics pipeline, and wherein the logic is used to apply the stencil print value to the position in the stencil print buffer corresponding to a pixel in the scene.

[0281] Example 7 may include a semiconductor package device comprising: a substrate; and logic coupled to the substrate, wherein the logic is implemented in one or more of configurable logic or fixed-function hardware logic, the logic being configured to determine two-dimensional (2D) texture values ​​and use stencil printing values ​​to control the coarse pixel size of a graphics pipeline via a 2D texture memory.

[0282] Example 8 may include a device as described in Example 7, wherein the 2D texture value includes a first bit range defining a first dimension of the coarse pixel size and a second bit range defining a second dimension of the coarse pixel size.

[0283] Example 9 may include a device as described in Example 7, wherein the coarse pixel size is controlled pixel-by-pixel for a plurality of pixels, and wherein the coarse pixel size varies across the plurality of pixels.

[0284] Example 10 may include a device as described in any one of Examples 7 to 9, wherein the 2D texture value is a stencil printing value, and wherein the coarse pixel size is controlled by a stencil printing buffer.

[0285] Example 11 may include the device as described in Example 10, wherein the stencil printing value is determined during an initial round involving depth analysis, and the coarse pixel value is controlled during subsequent rounds involving shader execution.

[0286] Example 12 may include the device as described in Example 10, wherein the logic is used to apply the stencil print value to the position in the stencil print buffer corresponding to a pixel in the scene being rendered by the graphics pipeline.

[0287] Example 13 may include a method of operating a semiconductor package device, the method comprising: determining a two-dimensional (2D) texture value; and using the 2D texture value to control the coarse pixel size of a graphics pipeline via a 2D texture memory.

[0288] Example 14 may include the method as described in Example 13, wherein the 2D texture value includes a first bit range defining a first dimension of the coarse pixel size and a second bit range defining a second dimension of the coarse pixel size.

[0289] Example 15 may include the method as described in Example 14, wherein the coarse pixel size is controlled pixel-by-pixel for a plurality of pixels, and wherein the coarse pixel size varies across the plurality of pixels.

[0290] Example 16 may include the method as described in any one of Examples 13 to 15, wherein the 2D texture value is a stencil printing value, and wherein the coarse pixel size is controlled by a stencil printing buffer.

[0291] Example 17 may include the method as described in Example 16, wherein the stencil printing value is determined during an initial round involving depth analysis, and the coarse pixel value is controlled during subsequent rounds involving shader execution.

[0292] Example 18 may include the method as described in Example 16, wherein controlling the coarse pixel size includes: applying the stencil print value to a position in the stencil print buffer corresponding to a pixel in the scene being rendered by the graphics pipeline. Example 19 may include at least one computer-readable storage medium including a set of instructions that, when executed by a computing system, cause the computing system to: determine a two-dimensional (2D) texture value and use the 2D texture value to control the coarse pixel size of the graphics pipeline via a 2D texture memory.

[0293] Example 20 may include at least one computer-readable storage medium as described in Example 19, wherein the 2D texture value includes a first bit range defining a first dimension of the coarse pixel size and a second bit range defining a second dimension of the coarse pixel size.

[0294] Example 21 may include at least one computer-readable storage medium as described in Example 20, wherein the coarse pixel size is controlled pixel-by-pixel for a plurality of pixels, and wherein the coarse pixel size varies across the plurality of pixels.

[0295] Example 22 may include at least one computer-readable storage medium as described in any one of Examples 19 to 21, wherein the 2D texture value is a stencil printing value, and wherein the coarse pixel size is controlled by a stencil printing buffer.

[0296] Example 23 may include at least one computer-readable storage medium as described in Example 22, wherein the stencil printing value is determined during an initial round involving depth analysis, and the coarse pixel value is controlled during subsequent rounds involving shader execution.

[0297] Example 24 may include at least one computer-readable storage medium as described in Example 22, wherein, when executed, the instructions cause the computing system to apply the stencil printing value to the stencil printing buffer at the position corresponding to a pixel in the scene being rendered by the graphics pipeline.

[0298] Example 25 may include a semiconductor package device comprising: means for determining two-dimensional (2D) texture values; and means for using the 2D texture values ​​to control the coarse pixel size of a graphics pipeline via a 2D texture memory.

[0299] Example 26 may include a device as described in Example 25, wherein the 2D texture value includes a first bit range defining a first dimension of the coarse pixel size and a second bit range defining a second dimension of the coarse pixel size.

[0300] Example 27 may include a device as described in Example 26, wherein the coarse pixel size is controlled pixel-by-pixel for a plurality of pixels, and wherein the coarse pixel size varies across the plurality of pixels.

[0301] Example 28 may include a device as described in any one of Examples 25 to 27, wherein the 2D texture value is a stencil printing value, and wherein the coarse pixel size is controlled by a stencil printing buffer.

[0302] Example 29 may include the device as described in Example 28, wherein the stencil printing value is determined during an initial round involving depth analysis, and the coarse pixel value is controlled during subsequent rounds involving shader execution.

[0303] Example 30 may include a device as described in Example 28, wherein controlling the coarse pixel size includes applying the stencil print value to a position in the stencil print buffer corresponding to a pixel in the scene being rendered by the graphics pipeline. The term “coupling” may be used herein to refer to any type of direct or indirect relationship between the components under discussion and may be applied to electronic, mechanical, fluid, optical, electromagnetic, motor, or other connections. Furthermore, the terms “first,” “second,” etc., may be used herein merely to facilitate discussion and do not carry any specific temporal or chronological significance unless otherwise specified. Moreover, it should be understood that the indefinite article “a” or “an” carries the meaning of “one or more” or “at least one.”

[0304] As used in this application and claims, a list of items described by the term "one or more" may refer to any combination of the listed items. For example, the phrase "one or more of A, B, and C" may mean A, B, and C; A and B; A and C; B and C; or A, B, and C.

[0305] Various embodiments have been described above with reference to specific examples. However, those skilled in the art will understand that various modifications and changes can be made thereto without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the foregoing description and drawings are considered illustrative rather than restrictive.

Claims

1. A computing system, comprising: monitor; Two-dimensional (2D) texture memory; A graphics pipeline coupled to the display; as well as Logic, the logic being used for: The identifier is used for the first level of detail in the scene. A first 2D texture value is determined based on the first level of detail, wherein the first 2D texture value corresponds to a first pixel size, and wherein the first 2D texture value includes a first bit range and a second bit range, the first bit range defining a first dimension of the first pixel size, and the second bit range defining a second dimension of the first pixel size. A second 2D texture value is determined based on a second level of detail for the scene, wherein the second 2D texture value corresponds to a second pixel size, and wherein the second 2D texture value includes a first-order range defining a first dimension of the second pixel size. The first dimension of the first pixel size is different from the first dimension of the second pixel size.

2. The system as claimed in claim 1, wherein, The second 2D texture value includes a second bit range that defines the second dimension of the second pixel size.

3. The system as described in claim 2, wherein, The second dimension of the first pixel size is different from the second dimension of the second pixel size.

4. The system of claim 2, wherein: The first bit range of the first pixel size is different from the first bit range of the second pixel size; and The second bit range of the first pixel size is different from the second bit range of the second pixel size.

5. The system as claimed in claim 1, wherein, The logic is used for: The first 2D texture value is applied to a position in the 2D texture memory, wherein the position corresponds to a pixel in the scene.

6. The system as claimed in claim 1, wherein, The first level of detail includes occlusion information.

7. A computing device, comprising: Substrate; as well as Logic, coupled to the substrate, wherein the logic is implemented in one or more of configurable logic or fixed-function hardware logic, and the logic coupled to the substrate is used for: The identifier is used for the first level of detail in the scene. A first 2D texture value is determined based on the first level of detail, wherein the first 2D texture value corresponds to a first pixel size, and wherein the first 2D texture value includes a first bit range and a second bit range, the first bit range defining a first dimension of the first pixel size, and the second bit range defining a second dimension of the first pixel size. A second 2D texture value is determined based on a second level of detail for the scene, wherein the second 2D texture value corresponds to a second pixel size, and wherein the second 2D texture value includes a first-order range defining a first dimension of the second pixel size. The first dimension of the first pixel size is different from the first dimension of the second pixel size.

8. The apparatus of claim 7, wherein, The second 2D texture value includes a second bit range that defines the second dimension of the second pixel size.

9. The apparatus of claim 8, wherein, The second dimension of the first pixel size is different from the second dimension of the second pixel size.

10. The apparatus of claim 8, wherein: The first bit range of the first pixel size is different from the first bit range of the second pixel size; and The second bit range of the first pixel size is different from the second bit range of the second pixel size.

11. The apparatus of claim 7, wherein, The logic coupled to the substrate is used for: The first 2D texture value is applied to a position in the 2D texture memory, wherein the position corresponds to a pixel in the scene.

12. The apparatus of claim 7, wherein, The first level of detail includes occlusion information.

13. A calculation method, comprising: The processor identifies the first level of detail for the scene. The processor determines a first 2D texture value based on the first level of detail, wherein the first 2D texture value corresponds to a first pixel size, and wherein the first 2D texture value includes a first bit range and a second bit range, the first bit range defining a first dimension of the first pixel size, and the second bit range defining a second dimension of the first pixel size. The processor determines a second 2D texture value based on a second level of detail for the scene, wherein the second 2D texture value corresponds to a second pixel size, and wherein the second 2D texture value includes a first-order range defining a first dimension of the second pixel size. The first dimension of the first pixel size is different from the first dimension of the second pixel size.

14. The method of claim 13, wherein, The second 2D texture value includes a second bit range that defines the second dimension of the second pixel size.

15. The method of claim 14, wherein, The second dimension of the first pixel size is different from the second dimension of the second pixel size.

16. The method of claim 14, wherein: The first bit range of the first pixel size is different from the first bit range of the second pixel size; and The second bit range of the first pixel size is different from the second bit range of the second pixel size.

17. The method of claim 13, further comprising: The processor applies the first 2D texture value to a location in the 2D texture memory, wherein the location corresponds to a pixel in the scene.

18. The method of claim 13, wherein, The first level of detail includes occlusion information.

19. At least one non-transitory computer-readable storage medium, comprising a set of instructions, which, when executed by a computing system, cause the computing system to: The identifier is used for the first level of detail in the scene; A first 2D texture value is determined based on the first level of detail, wherein, The first 2D texture value corresponds to the first pixel size, wherein the first 2D texture value includes a first bit range and a second bit range, the first bit range defining a first dimension of the first pixel size, and the second bit range defining a second dimension of the first pixel size; and A second 2D texture value is determined based on a second level of detail for the scene, wherein the second 2D texture value corresponds to a second pixel size, and wherein the second 2D texture value includes a first-order range defining a first dimension of the second pixel size. The first dimension of the first pixel size is different from the first dimension of the second pixel size.

20. The at least one non-transitory computer-readable storage medium as described in claim 19, wherein, The second 2D texture value includes a second bit range that defines the second dimension of the second pixel size.

21. The at least one non-transitory computer-readable storage medium as described in claim 20, wherein, The second dimension of the first pixel size is different from the second dimension of the second pixel size.

22. The at least one non-transitory computer-readable storage medium as claimed in claim 20, wherein: The first bit range of the first pixel size is different from the first bit range of the second pixel size; and The second bit range of the first pixel size is different from the second bit range of the second pixel size.

23. The at least one non-transitory computer-readable storage medium as described in claim 19, wherein, When executed, the instructions further enable the computing system to: The first 2D texture value is applied to a position in the 2D texture memory, wherein the position corresponds to a pixel in the scene.

24. The at least one non-transitory computer-readable storage medium as described in claim 19, wherein, The first level of detail includes occlusion information.

Images