Target trigger point determination system for chip FPGA prototype verification

Abstract

The present invention relates to the field of chip verification technology, and more particularly to a target trigger point determination system for chip FPGA prototype verification. The system comprises an FPGA prototype verification module and a software control module, wherein the prototype verification module is connected to the software control module. The FPGA prototype verification module comprises an FPGA board, a trigger configuration table provided on the FPGA board, and a data processing module. The data processing module reads intermediate state data from a preset interface of the FPGA prototype system in real time and combines the data with the trigger configuration table to determine the target trigger point. The present invention improves the accuracy and efficiency of target trigger point determination in chip FPGA prototype verification.

Description

Technical Field

[0001] The present invention relates to the technical field of chip verification, and in particular to a target trigger point determination system for chip FPGA prototype verification. Background Art

[0002] With the continuous development of chip verification technology, the demand for more comprehensive verification of chip hardware logic in FPGA prototype systems is increasing. This inevitably requires debugging methods to be able to effectively deal with problems in various complex scenarios. FPGA prototype systems can only directly obtain data from input ports and cannot obtain changes in internal signals. Traditional debugging methods, when applied to FPGA prototype verification systems, usually only provide limited information and are only applicable to problems in simple scenarios. When the chip hardware logic is more complex, the problems that arise are difficult to reproduce, or there are some physical characteristics after board installation, traditional debugging methods have difficulty quickly finding the target trigger point. Only after the trigger point is determined can the target debug data be obtained to debug the FPGA prototype system. Therefore, how to accurately and quickly determine the target trigger point of the FPGA prototype verification system has become a technical problem that needs to be solved urgently. Summary of the Invention

[0003] The present invention aims to provide a target trigger point determination system for chip FPGA prototype verification, thereby improving the accuracy and efficiency of target trigger point determination.

[0004] According to one aspect of the present invention, a target trigger point determination system for chip FPGA prototype verification is provided, comprising an FPGA prototype verification module and a software control module, wherein the prototype verification module is connected to the software control module;

[0005] The FPGA prototype verification module includes an FPGA board, a trigger configuration table set on the FPGA board, and a data processing module, wherein the gate-level netlist corresponding to the chip to be verified is burned on the FPGA board; the trigger configuration table includes M trigger configuration information {A1, A2, ..., A m ,…,A M}, A m The mth trigger configuration information, m ranges from 1 to M, A m =(A1 m ,A2 m , A3 m ), A1 m A m The trigger bit identification information, A2 m A m Trigger constraint information, A3 m A m Trigger execution instruction; A3m Including jump to A j , determine the current moment as the target trigger point; the value range of j is 1 to M, A j ≠A m , set A1 as the initial target A m ;

[0006] The software control module is used to configure the initial state of the FPGA prototype verification module and input stimulus information to the input port of the FPGA prototype verification module;

[0007] The FPGA prototype verification module starts running from an initial state and performs FPGA prototype verification on the chip to be verified based on stimulus information received at an input port;

[0008] The data processing module is used to read the intermediate state data from the preset interface of the FPGA prototype system in real time, and when the intermediate state data read appears the current target A m Corresponding target A1 m When the intermediate state data read subsequently is determined to be consistent with the current target A m Corresponding target A2 m , when meeting target A2 m When the current target A m Corresponding target A3 m To determine the current moment as the target trigger point instruction, the current trigger point is determined as the target trigger point, otherwise, the target A3 m Corresponding A j Update to target A m , continue to read the intermediate state data from the preset interface of the FPGA prototype system for judgment until the target trigger point is determined.

[0009] Compared with the existing technology, the present invention has significant advantages and beneficial effects. Through the above technical solution, the target trigger point determination system for chip FPGA prototype verification provided by the present invention can achieve considerable technological advancement and practicality, and has wide industrial application value. It has at least the following beneficial effects:

[0010] The present invention covers various complex verification scenarios by setting a trigger configuration table on the FPGA board. The intermediate state data is read from the preset interface of the FPGA prototype system in real time by the data processing module inside the FPGA. The target trigger point is determined based on the read output data and the trigger configuration table, thereby improving the accuracy and efficiency of the target trigger point determination. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 Schematic diagram of a target trigger point determination system for chip FPGA prototype verification provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0013] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0014] The embodiment of the present invention provides a target trigger point determination system for chip FPGA (Field-Programmable Gate Array) prototype verification, such as Figure 1 As shown, it includes an FPGA prototype verification module and a software control module, wherein the prototype verification module is connected to the software control module. It should be noted that the FPGA prototype verification module is a hardware module and is implemented by hardware. The software control module is a software module generated based on SystemC.

[0015] The FPGA prototype verification module includes an FPGA board, a trigger configuration table set on the FPGA board, and a data processing module. It is understood that FPGA is a field programmable gate array. The FPGA board is burned with a gate-level netlist corresponding to the chip to be verified. It should be noted that an RTL simulation model is first constructed based on the original register transfer level (RTL) code of the chip to be verified. The chip to be verified is simulated and verified based on the RTL simulation model. Specifically, the chip to be verified can be simulated and verified using the Universal Verification Methodology (UVM) or software simulation. The original RTL code of the chip to be verified is updated based on the simulation verification results of the RTL simulation model, and simulation verification code for the chip to be verified is generated. The gate-level netlist of the chip to be verified is generated based on the simulation verification code of the chip to be verified.

[0016] The trigger configuration table includes M pieces of trigger configuration information {A1, A2, ..., Am ,…,A M}, A m The mth trigger configuration information, m ranges from 1 to M, A m =(A1 m ,A2 m ,A3 m ), A1 m A m The trigger bit identification information, A2 m A m Trigger constraint information, A3 m A m Trigger execution instruction; A3 m Including jump to A j , determine the current moment as the target trigger point; the value range of j is 1 to M, A j ≠A m , set A1 as the initial target A m By setting each A m , can be applied to various complex application scenarios, each A1 in the trigger configuration table m 、A2 m and A3 m All A3 m The corresponding jump information can determine the corresponding process, and the trigger configuration table can be specifically implemented through a finite state machine.

[0017] The software control module is used to configure the initial state of the FPGA prototype verification module and input stimulus information to the input port of the FPGA prototype verification module. It should be noted that the software control module also configures the initial state of the FPGA prototype verification module through the input port of the FPGA prototype verification module.

[0018] The FPGA prototype verification module starts running from an initial state and performs FPGA prototype verification on the chip to be verified based on stimulus information received by an input port.

[0019] The data processing module is used to read the intermediate state data from the preset interface of the FPGA prototype system in real time, and when the intermediate state data read appears the current target A m Corresponding target A1 m When the intermediate state data read subsequently is determined to be consistent with the current target A m Corresponding target A2 m , when meeting target A2 m When the current target A m Corresponding target A3 mTo determine the current moment as the target trigger point instruction, the current trigger point is determined as the target trigger point, otherwise, the target A3 m Corresponding A j Update to target A m , continue to read intermediate state data from the preset interface of the FPGA prototype system for judgment until the target trigger point is determined. It should be noted that the FPGA prototype system includes multiple interfaces, and users cannot directly read interface data. The data processing module set on the FPGA can read and combine it with the trigger configuration table to make judgments.

[0020] As an example, A3 m It also includes writing the target value to the target address and then jumping to A j If the current target A m Corresponding target A3 m To write the target value to the target address and then jump to A j , then the data processing module first converts the target A3 m The target address and target value in the target A3 are sent to the software control module, and the software control module m The target address and target value in the target address and target value are used to generate stimulus information, and the generated stimulus information is sent to the input port of the FPGA prototype verification module, and then the target A3 m Corresponding A j Update to target A m , continue to read the intermediate state data from the preset interface of the FPGA prototype system for judgment until the target trigger point is determined. It should be noted that the software control module sends stimulus data to the input port of the FPGA prototype verification module according to the preset stimulus sequence, but if the current target A m Corresponding target A3 m To write the target value to the target address and then jump to A j The software control module receives the target A3 sent by the data processing module m When the target address and target value in the preset stimulus sequence are set, the software control module will first pause sending the stimulus data in the preset stimulus sequence, and the software control module will first m The target address and target value in the target address are used to generate stimulus information, the generated stimulus information is sent to the input port of the FPGA prototype verification module, and then the stimulus data is continued to be sent to the input port of the FPGA prototype verification module according to the preset stimulus sequence.

[0021] The number of bits of the preset interface of the FPGA prototype system is fixed, for example, 64 bits. Then the intermediate state data read from the preset interface of the FPGA prototype system is always 64 bits. The data processing module does not need to process all 64 bits of data every time, but may only process some bits of data. It can be flexibly set, thus further covering a variety of complex verification scenarios. As an embodiment, A1 m Including the first judgment bit A11 m and A11 m The corresponding first judgment value A12 m , A2 m Including the second judgment bit A21 m and A21 m Corresponding constraint A22 m The data processing module is used to read the intermediate state data from the preset interface of the FPGA prototype system in real time, and determine the current target A in the intermediate state data currently read. m Corresponding target A11 m Is the value of the current target A m Corresponding target A12 m If so, then determine the target A in the intermediate state data read subsequently m Corresponding target A21 m Whether the corresponding value meets target A m Corresponding target A22 m If it meets the requirements, then execute target A m Corresponding A3 m .

[0022] Trigger constraint information can be of various types, which are described below in three specific categories:

[0023] Type 1:

[0024] As an example, A22 m Including Target A21 m The corresponding value is greater than the preset constraint value A23 m Target A21 m The corresponding value is greater than or equal to the preset constraint value A23 m Target A21 m The corresponding value is less than the preset constraint value A23 m Target A21 m The corresponding value is less than or equal to the preset constraint value A23 m Target A21 m The corresponding value is equal to the preset constraint value A23 m .

[0025] The data processing module includes a comparator, which supports comparison operations of greater than, greater than or equal to, less than, less than or equal to, and equal to.

[0026] If target A22 m Target A21 m The corresponding value is greater than the preset constraint value A23 m Target A21 m The corresponding value is greater than or equal to the preset constraint value A23 m Target A21 m The corresponding value is less than the preset constraint value A23 m Target A21 m The corresponding value is less than or equal to the preset constraint value A23 m Target A21 m The corresponding value is equal to the preset constraint value A23 m If any one of the following is true, the target A21 m Corresponding values ​​and preset constraint values ​​A23 m Input the comparator to determine the target A21 m Whether the corresponding value meets target A m Corresponding target A22 m The comparator will be based on the specific A22 m For input target A21 m Corresponding values ​​and preset constraint values ​​A23 m Compare to determine whether the target A22 is met m conclusion.

[0027] Type 2

[0028] As an example, A22 m Including Target A21 m The corresponding value appears equal to the preset value A24 m The number of times reaches the preset value A25 m ; A counter is provided in the data processing module.

[0029] If target A22 m For the current target A m Corresponding target A11 m The value is equal to the current target A m Corresponding target A12 m , then enable the counter to start recording target A21 m The corresponding value appears equal to the preset value A24 m If the number of times reaches the preset value A25 m , then it is determined to meet the target A2 m .

[0030] Type 3

[0031] As an example, A22 m Including entering target A m The time reaches the preset time length A26 m ; The data processing module includes a timer.

[0032] If target A22 m To enter target A m The time reaches the preset time length A26 m , then start the timer, from the current target A m Corresponding target A11 m The value is equal to the current target A m Corresponding target A12 m Start timing when the counted time reaches the preset time length A26 m , then it is determined to meet the target A2 m .

[0033] After determining the target trigger point, target debug data can be further obtained based on the target trigger point to debug the chip FPGA prototype verification. Specifically, this can be achieved using existing methods for obtaining target debug data based on the target trigger point. Embodiments of the present invention further propose a method for obtaining target debug data based on the target trigger point. Specifically, the system also includes a storage module, the software control module is connected to the FPGA prototype verification module and the storage module, and the storage module is connected to the FPGA prototype verification module.

[0034] The input ports of the FPGA prototype verification module are grouped according to the clock. The input stimulus data corresponding to Y clocks can be selected from the input port as the data to be transferred. The size of the data to be transferred is X. The state of the FPGA prototype verification module may always remain unchanged in the initial state, or it may change with the input of the stimulus data.

[0035] The storage module includes a first storage area, which includes N storage units (B1, B2, . . . , B n ,…,B N ), B n The nth storage unit, n ranges from 1 to N, B n The size is greater than (X+Y); the software control module controls the data to be transferred corresponding to the selected Y clocks in the input port of the FPGA prototype verification module and the selected Y clock data as the data to be stored, according to B1, B2, ..., B n ,…,B N The data to be stored is stored in the first storage area in the order ofn When storing the data to be stored in B, first determine n Is the current remaining storage space greater than or equal to (X+Y)? If so, store the data to be stored in B n Otherwise, the data to be stored is stored in B n+1 When stored in B N And B N When the storage space in is less than (X+Y), the data to be stored is stored in B1. It should be noted that the first storage area is a part of the storage area in the storage module, that is, it is only a part of the storage module. The present invention stores the input stimulus data and the corresponding clock data of the input port of the FPGA prototype verification module in the first storage area in a circular overwriting manner. The input stimulus data and the corresponding clock data of the input port of the FPGA prototype verification module occupy the space of the first storage area at most, rather than the space of the entire storage module, saving the size of the storage space occupied by the input stimulus data and the corresponding clock data of the input port of the FPGA prototype verification module. In addition, data will continue to be stored in the space of the first storage area only when no abnormality is found. Therefore, the data covered in the first storage area are all non-target debug data. The circular overwriting method ensures that the first storage area always stores data for a period of time close to the current moment.

[0036] When the FPGA prototype verification module reaches the target trigger point, the software control module retrieves the data stored in the first storage area as target debug data based on the target trigger point. It should be noted that when acquiring the target debug data, only the amount of data corresponding to the first storage area needs to be processed, significantly reducing the amount of data processing and improving the efficiency of acquiring the target debug data. The target trigger point is the point where debugging is required.

[0037] After the target trigger point is determined, data in different ranges before and after the target trigger point can be obtained according to different application requirements. As an embodiment, when the FPGA prototype verification module runs to the target trigger point, the software control module will nAs the end point, data is no longer stored in the first storage area, and the data in the current first storage area is sorted according to the storage order to obtain the target debug data. It should be noted that such a scenario is applicable to the situation where debug data before the target trigger point needs to be obtained. If the first storage area is full when the target trigger point is determined, the amount of the obtained target debug data is N×(X + Y); otherwise, the amount of the obtained target debug data is P×(X + Y), where 0 < P < N, and P is the serial number of the storage unit where the data corresponding to the target trigger point is located in the first storage area.

[0038] As an embodiment, when the FPGA prototype verification module runs to the target trigger point, the software control module takes the B corresponding to the target trigger point n As the starting point, continue to obtain (N - 1) pieces of data to be stored from the FPGA prototype verification module, and store them in the first storage area in sequence, and then sort the data in the first storage area according to the storage order to obtain the target debug data. It should be noted that such a scenario is applicable to the situation where debug data after the target trigger point needs to be obtained. In this case, the amount of the obtained target debug data is N×(X + Y).

[0039] As an embodiment, when the FPGA prototype verification module runs to the target trigger point, the software control module takes the B corresponding to the target trigger point n As the starting point, continue to obtain D×N / (C + D) pieces of data to be stored from the FPGA prototype verification module, and store them in the first storage area in sequence, and then sort the data in the first storage area according to the storage order to obtain the target debug data, where C and D are ratio parameters, and in the target debug data, the ratio of the amount of data before and at the target trigger point to the amount of data after the target trigger point is C:D. It should be noted that such a scenario is applicable to the situation where debug data before and after the target trigger point needs to be obtained in proportion. In this case, the amount of the obtained target debug data is N×(X + Y).

[0040] As an embodiment, the storage module further includes a second storage area. If the chip to be verified is a chip with a constant state, the initial state information is stored in the second storage area. When the FPGA prototype verification module runs to the target trigger point, the software control module also determines the initial state information stored in the second storage area as the target debug data.

[0041] As an embodiment, the storage module further includes a second storage area. If the chip to be verified is a state-variable chip, all state data appearing during the FPGA prototype verification process is recorded in the second storage area, and a mapping relationship between the state data and the data stored in the first storage area is established. When a state data in the second storage area is completely overwritten by the data stored in the first storage area, the state data and the corresponding mapping relationship information are deleted from the second storage area. When the FPGA prototype verification module runs to the target trigger point, the software control module obtains the state information corresponding to each data in the first storage area determined as target debug data from the second storage area, and also determines the state information corresponding to each data in the first storage area determined as target debug data as the target debug data.

[0042] As an embodiment, N storage units may also be provided in the second storage area, and the N storage units (B1, B2, ..., B n ,…,B N ) correspond one to one, each storage unit corresponds to the state data of the FPGA prototype verification system for storing the stimulus data stored in a storage unit in the first storage area.

[0043] As an embodiment, the target debug data includes (E1, E2, ..., E n ,…,E N ), E n For the nth group of target debug data, E n =(E1 n ,E2 n ,E3 n ), E1 n For E n Corresponding incentive data, E2 n E1 n Corresponding clock data, E3 n For E n The corresponding state data of the starting FPGA prototype verification system, E1, E2, ..., E n ,…,E N Sort by time. It should be noted that E1 n Includes multiple stimulus data arranged in execution order, E2 n Including multiple with E1 n The stimulus data in E3 corresponds to the clock data. n Only one group E n The corresponding starting FPGA prototype verification system status data does not need to be stored E1 nThe state data of the FPGA prototype verification system corresponding to each stimulus data in the target debug data is fed back into the RTL simulation model according to the timing to perform debugging, which specifically includes:

[0044] Step S1: Set N RTL simulation models.

[0045] Step S2: Set the starting state of the nth RTL simulation model to E3 n .

[0046] Step S3, parallelize each E1 n Input the corresponding nth RTL simulation model for simulation, according to E1 n and E2 n The corresponding relationship is set to clock data, and the signal changes in each RTL simulation model are observed in real time to determine the target abnormal point.

[0047] Among them, the clock data corresponding to the excitation data is the clock frequency, so according to E1 n and E2 n Just set the clock frequency according to the corresponding relationship.

[0048] Through steps S1 to S3, on the premise that the state of the RTL simulation model is consistent with the state of the FPGA prototype verification system, the corresponding recorded data is sent to the RTL simulation model according to the timing of the FPGA prototype verification system, so that the data of the FPGA prototype verification system is reproduced on the RTL simulation model, and then the verification of the FPGA prototype verification system is realized based on the RTL simulation model.

[0049] It should be noted that if E1, E2, ..., E n ,…,E N It will be very slow. n The stimulus data, clock data and the status data of the corresponding starting FPGA prototype verification system have been included, so each set of target debug data can be reproduced independently in the RTL simulation model, and all E n , which can greatly improve the debugging efficiency of chip FPGA prototype verification.

[0050] As an embodiment, step S3 includes:

[0051] Step S31, parallelize each E1 n During the simulation process in the nth RTL simulation model corresponding to the input, if an abnormal point appears based on the nth RTL simulation model, the simulation operation of the (n+1)th RTL simulation model to the Nth RTL simulation model is terminated. After the simulation of the N RTL simulation models is completed, the abnormal point that appears first is determined as the target abnormal point.

[0052] It should be noted that the target abnormal point is at the front position. Therefore, when an abnormal point is found, the subsequent simulation process does not need to be paid attention to. Therefore, the simulation operation from the (n+1)th RTL simulation model to the Nth RTL simulation model is ended to save computing resources.

[0053] It should be noted that, since the RTL simulation model can observe the state of each signal, the target debug data is directly fed back into the RTL simulation model in a timing sequence for debugging, thereby achieving debugging of the FPGA prototype verification system.

[0054] The embodiment of the present invention covers various complex verification scenarios by setting a trigger configuration table on the FPGA board. The intermediate state data is read from the preset interface of the FPGA prototype system in real time through the data processing module inside the FPGA. The target trigger point is determined based on the read output data and the trigger configuration table, thereby improving the accuracy and efficiency of the target trigger point determination.

[0055] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. A process can be terminated when its operation is completed, but can also have additional steps not included in the accompanying drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0056] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A target trigger point determination system for chip FPGA prototype verification, characterized in that: It includes an FPGA prototype verification module and a software control module, wherein the prototype verification module is connected to the software control module; The FPGA prototype verification module includes an FPGA board, a trigger configuration table set on the FPGA board, and a data processing module, wherein the gate-level netlist corresponding to the chip to be verified is burned on the FPGA board; the trigger configuration table includes M trigger configuration information {A1, A2, ..., A m ,…,A M }, A m The mth trigger configuration information, m ranges from 1 to M, A m =(A1 m ,A2 m ,A3 m ), A1 m A m The trigger bit identification information, A2 m A m Trigger constraint information, A3 m A m Trigger execution instruction; A3 m Including jump to A j , determine the current moment as the target trigger point; the value range of j is 1 to M, A j ≠A m , set A1 as target A m , the target trigger point is the point where debugging is required; The software control module is used to configure the initial state of the FPGA prototype verification module and input stimulus information to the input port of the FPGA prototype verification module; The FPGA prototype verification module starts running from an initial state and performs FPGA prototype verification on the chip to be verified based on stimulus information received at an input port; The data processing module is used to read the intermediate state data from the preset interface of the FPGA prototype system in real time, and when the intermediate state data read appears the current target A m Corresponding target A1 m When the intermediate state data read subsequently is determined to be consistent with the current target A m Corresponding target A2 m , when meeting target A2 m When the current target A m Corresponding target A3 m To determine the current moment as the target trigger point instruction, the current moment is determined as the target trigger point, otherwise, the target A3 m Corresponding A j Update to target A m , continue to read the intermediate state data from the preset interface of the FPGA prototype system for judgment until the target trigger point is determined.

2. The system according to claim 1, wherein: A3 m It also includes writing the target value to the target address and then jumping to A j ; If the current target A m Corresponding target A3 m To write the target value to the target address and then jump to A j , then the data processing module first converts the target A3 m The target address and target value in the target A3 are sent to the software control module, and the software control module m The target address and target value in the target address and target value are used to generate stimulus information, and the generated stimulus information is sent to the input port of the FPGA prototype verification module, and then the target A3 m Corresponding A j Update to target A m , continue to read the intermediate state data from the preset interface of the FPGA prototype system for judgment until the target trigger point is determined.

3. The system according to claim 1, wherein: Each A1 in the trigger configuration table m 、A2 m and A3 m They are all generated according to the verification requirements of the chip to be verified.

4. The system according to claim 1, wherein: A1 m Including the first judgment bit A11 m and A11 m The corresponding first judgment value A12 m , A2 m Including the second judgment bit A21 m and A21 m Corresponding constraint A22 m ; The data processing module is used to read the intermediate state data from the preset interface of the FPGA prototype system in real time, and determine the current target A in the currently read intermediate state data. m Corresponding target A11 m Is the value of the current target A m Corresponding target A12 m If so, then determine the target A in the intermediate state data read subsequently m Corresponding target A21 m Whether the corresponding value meets target A m Corresponding target A22 m If it meets the requirements, then execute target A m Corresponding A3 m .

5. The system according to claim 4, characterized in that A22 m Including Target A21 m The corresponding value is greater than the preset constraint value A23 m Target A21 m The corresponding value is greater than or equal to the preset constraint value A23 m Target A21 m The corresponding value is less than the preset constraint value A23 m Target A21 m The corresponding value is less than or equal to the preset constraint value A23 m Target A21 m The corresponding value is equal to the preset constraint value A23 m ; The data processing module includes a comparator, which supports comparison operations of greater than, greater than or equal to, less than, less than or equal to, and equal to; If target A22 m Target A21 m The corresponding value is greater than the preset constraint value A23 m Target A21 m The corresponding value is greater than or equal to the preset constraint value A23 m Target A21 m The corresponding value is less than the preset constraint value A23 m Target A21 m The corresponding value is less than or equal to the preset constraint value A23 m Target A21 m The corresponding value is equal to the preset constraint value A23 m If any one of the following is true, the target A21 m Corresponding values ​​and preset constraint values ​​A23 m Input the comparator to determine the target A21 m Whether the corresponding value meets target A m Corresponding target A22 m .

6. The system according to claim 4, characterized in that A22 m Including Target A21 m The corresponding value appears equal to the preset value A24 m The number of times reaches the preset value A25 m ; The data processing module is provided with a counter; If target A22 m For the current target A m Corresponding target A11 m The value is equal to the current target A m Corresponding target A12 m , then enable the counter to start recording target A21 m The corresponding value appears equal to the preset value A24 m If the number of times reaches the preset value A25 m , then it is determined to meet the target A2 m .

7. The system according to claim 4, wherein: A22 m Including entering target A m The time reaches the preset time length A26 m ; The data processing module includes a timer; If target A22 m To enter target A m The time reaches the preset time length A26 m , then start the timer, from the current target A m Corresponding target A11 m The value is equal to the current target A m Corresponding target A12 m Start timing when the counted time reaches the preset time length A26 m , then it is determined to meet the target A2 m .

8. The system according to claim 1, wherein: The software control module is a software module, which is generated based on the System C language, and the FPGA prototype verification module is a hardware module.

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