An operant conditioning neural network circuit with bridging and conditional reinforcement

Abstract

The application provides an operant conditioning reflex neural network circuit with bridging and conditional reinforcement, comprising a memory module, a delay module, a prefrontal cortex module, an experience module and a generalization module, the bridging function in the operant conditioning reflex is realized through the delay module and the prefrontal cortex module, the conditional reinforcement function in the operant conditioning reflex is realized by the memory module and the prefrontal cortex module, and the generalization function of the operant conditioning reflex is realized through the generalization module and the experience module. The application considers the situation that the classical conditioning reflex and the operant conditioning reflex occur simultaneously in the actual training scene, realizes the learning, forgetting and delay learning in the classical conditioning reflex and the bridging, conditional reinforcement and generalization functions in the operant conditioning reflex respectively. The circuit designed by the application is more in line with the biological characteristics and more comprehensive, and is helpful to build a more intelligent neural network circuit.

Description

Technical Field

[0001] This invention relates to the technical field of neural network circuits, and more particularly to an operational conditioned reflex neural network circuit with bridging and conditional reinforcement. Background Technology

[0002] In 1971, Chinese-American scientist Shao-Tang Tsai proposed, based on the principle of circuit symmetry, the existence of a device that could represent the relationship between charge and magnetic flux, and named it memristor. In 2008, Hewlett-Packard Laboratories created a physical memristor based on TiO2, and since then, research on memristors has become very popular. Memristors have characteristics such as small size, low power consumption, nonlinearity, non-volatility, and variable resistance, which are very similar to brain synapses. Therefore, they are widely used in the field of artificial neural networks to simulate brain functions, such as associative memory.

[0003] Classical conditioning and operant conditioning are two of the most fundamental and crucial learning mechanisms in the biological brain, collectively known as associative memory. Classical conditioning is a passive learning behavior, where organisms passively associate conditioned stimuli with unconditioned stimuli. Operant conditioning is an active learning behavior, where organisms actively learn the relationship between their own behavior and the surrounding environment, thereby repeating or avoiding this behavior in similar situations in the future. Some researchers have proposed neural network circuits to simulate classical and operant conditioning, but they have not considered the simultaneous occurrence of classical and operant conditioning in real-world scenarios. The neural network circuit proposed in this invention solves this problem.

[0004] Patent application number 202310283927.X discloses a multifunctional operant conditioning neural network circuit with blocking and competition effects. The stimulus signal is connected to the input of the hippocampus module, and both the excitation and output signals are connected to the input of the cerebellum module. The excitation signal, hippocampus module, and cerebellum module are all connected to the input of a voltage control module. The output of the voltage control module is connected to the experience module and feedback module, respectively. The output of the experience module is connected to the decision module and feedback module, respectively. The output of the feedback module is connected to the voltage control module and experience module, respectively. The output of the decision module is connected to the feedback module and obtains an output signal. This invention enables operant conditioning learning under multiple input signals, simulating the decision-making judgments made by animals in complex natural environments, thus broadening the possibilities of existing operant conditioning circuits. However, this invention only considers a single operant conditioning reflex. In actual training scenarios, classical conditioning and operant conditioning often occur simultaneously. Summary of the Invention

[0005] To address the technical problem that existing neural networks do not consider combining classical and operant conditioning, this invention proposes an operant conditioning neural network circuit with bridging and conditional reinforcement. The bridging function is achieved through a delay module and a prefrontal cortex module; the conditional reinforcement function is achieved through a memory module and a prefrontal cortex module; and the generalization of operant conditioning is achieved through a generalization module and an experience module. During the bridging and conditional reinforcement processes, both classical and operant conditioning occur simultaneously, thereby achieving a combination of classical and operant conditioning.

[0006] To achieve the above objectives, the technical solution of the present invention is implemented as follows: an operational conditioned reflex neural network circuit with bridging and conditional reinforcement, comprising input signal terminals N1-N5, a memory module, delay modules I, II, III, IV, and V, prefrontal cortex module I, II, experience module I, II, and a generalization module. The input signal terminal N1, representing a food signal, is connected to the input terminals of the memory module, prefrontal cortex module I, and prefrontal cortex module II, respectively. The input signal terminal N2, representing a whistle signal, is connected to the input terminal of the memory module. The input signal terminal N3, representing command signal I, is connected to the input terminal of delay module II. The input signal terminal N4, representing an auxiliary signal, is connected to the input terminals of delay modules III and IV via logic circuits, respectively. The input signal terminal N5, representing command signal II, is connected to the input terminal of delay module V. The output terminal of the memory module is connected to the delay modules I and II, respectively. The input terminals of cortical module I and prefrontal cortex module II are connected; the output terminal of delay module I is connected to the input terminals of memory module, prefrontal cortex module I and prefrontal cortex module II respectively; the output terminal of delay module II is connected to the input terminals of logic circuit and experience module I respectively; the output terminal of delay module III is connected to the input terminal of prefrontal cortex module I; the output terminal of delay module IV is connected to the input terminals of generalization module and prefrontal cortex module II respectively; the output terminal of delay module V is connected to the input terminals of logic circuit and experience module II respectively; the output terminal of prefrontal cortex module I is connected to the input terminals of experience module I and generalization module respectively; the output terminal of prefrontal cortex module II is connected to the input terminal of experience module II; the output terminal of generalization module is connected to the input terminal of prefrontal cortex module II; the output terminal and input signal terminal N1 of memory module are both connected to the input terminal of OR gate D9 through resistor R4; the output terminals of experience module I and experience module II are respectively connected to OR gate D9. 35 The two input terminals are connected together, or gate D 35 The output terminal is connected to the logic circuit, and the output of OR gate D9 represents the excitation signal. 35 The output represents the action signal.

[0007] Preferably, the memory module includes a first voltage control circuit, a synaptic neuron circuit, a NOT gate D6, an adder SUM1, and a first comparator. The input terminal of the first voltage control circuit is connected to the output terminal, input signal terminal N1, and input signal terminal N2 of the delay module I, respectively. The output terminal of the first voltage control circuit is connected to the positive terminal of the memristor M1 in the synaptic neuron circuit. The output terminal of the synaptic neuron circuit is connected to the input terminals of the prefrontal cortex module I and the prefrontal cortex module II, respectively, and one input terminal of the adder SUM1. The input signal terminal N2 is connected to the input terminal of the NOT gate D6. The output terminal of the NOT gate D6 is connected to the other input terminal of the adder SUM1 and the input terminal of the delay module I, respectively. The output terminal of the adder SUM1 is connected to the input terminal of the first comparator. The output terminal of the first comparator is connected to one input terminal of the OR gate D9 and outputs a signal representing the completion of memory.

[0008] Preferably, the first voltage control circuit includes a first logic unit, a second logic unit, a first voltage control unit, and a second voltage control unit. The input terminal of the first logic unit is connected to the input signal terminal N1 and the input signal terminal N2, respectively, and the output terminal of the first logic unit is connected to the input terminal of the first voltage control unit. The input terminal of the second logic unit is connected to the input signal terminal N1 and the input signal terminal N2, respectively, and the output terminal of the second logic unit is connected to the input terminal of the second voltage control unit. The output terminals of the first voltage control unit and the second voltage control unit are the output terminals of the first voltage control circuit, and both the output terminals of the first voltage control unit and the second voltage control unit are connected to the input terminal of the synaptic neuron circuit. The synaptic neuron circuit includes a first inverting amplifier circuit and a mathematical operation unit ABM1. The output terminals of the first voltage control unit and the second voltage control unit of the first voltage control circuit are respectively connected to the positive terminal of the memristor M1 of the first inverting amplifier circuit and one input terminal of the mathematical operation unit ABM1. The negative terminal of the memristor M1 is connected to the input terminal of the operational amplifier of the first inverting amplifier circuit. The output terminal of the first inverting amplifier circuit is connected to the other input terminal of the mathematical operation unit ABM1. The output terminal of the mathematical operation unit ABM1 is the output terminal of the synaptic neuron circuit and is connected to the input terminals of the prefrontal cortex module I and the prefrontal cortex module II, respectively.

[0009] Preferably, each of the delay modules I, II, III, IV, and V includes a first NOT gate, a third voltage-controlled unit, a fourth voltage-controlled unit, a second inverting amplifier circuit, a first NMOS transistor, a first PMOS transistor, and a first AND gate. The input terminal of the first NOT gate is the input terminal of each of the delay modules II, III, IV, and V. The output terminal of the first NOT gate is connected to the input terminal of the third voltage-controlled unit and one input terminal of the first AND gate, respectively. The output terminals of the third and fourth voltage-controlled units are both connected to the positive terminal of the first memristor of the second inverting amplifier circuit, and the negative terminal of the first memristor is connected to the input terminal of the operational amplifier of the second inverting amplifier circuit. The output terminal of the second inverting amplifier circuit is connected to the gate of the first NMOS transistor. The source of the first NMOS transistor is connected to the positive terminal of the first voltage source, and the negative terminal of the first voltage source is grounded. The drain of the first NMOS transistor is connected to the gate of the first PMOS transistor and one end of resistor I. The other end of resistor I is connected to the positive terminal of the second voltage source, and the negative terminal of the second voltage source is grounded. The source of the first PMOS transistor is connected to the positive terminal of the third voltage source, and the negative terminal of the third voltage source is grounded. The drain of the first PMOS transistor is connected to one end of resistor II and one input terminal of the first AND gate. The other end of resistor II is connected to the positive terminal of the fourth voltage source, and the negative terminal of the fourth voltage source is grounded.

[0010] Preferably, both the prefrontal cortex module I and the prefrontal cortex module II include a third logic unit, a fourth logic unit, a second AND gate, a second comparator, a third AND gate, a seventh pressure control unit, an eighth pressure control unit, a ninth pressure control unit, a tenth pressure control unit, and a first addition unit. The input terminal of the third logic unit is connected to the input signal terminal N1 and the output terminal of delay module III or delay module IV, respectively. The output terminal of the third logic unit is connected to the input terminal of the seventh pressure control unit and one input terminal of the second AND gate, respectively. The other input terminal of the second AND gate is connected to the output terminal of delay module I. The input terminal of the fourth logic unit is connected to the input signal terminal N1 and the output terminal of delay module III or delay module IV, respectively. The output terminal of the fourth logic unit is connected to... The input terminal of the eighth pressure control unit is connected to the input terminal of the ninth pressure control unit and one input terminal of the third AND gate, respectively. The input terminal of the second comparator is connected to the output terminal of the synaptic neuron circuit in the memory module. The output terminal of the second comparator is connected to the other input terminal of the third AND gate. The output terminal of the third AND gate is connected to the input terminal of the tenth pressure control unit. The output terminals of the seventh, eighth, ninth, and tenth pressure control units are respectively connected to one input terminal of the first addition unit. The output terminal of the first addition unit is connected to the input terminal of either experience module I or experience module II. The output terminal of the first addition unit of the prefrontal cortex module I is also connected to the input terminal of the generalization module.

[0011] Preferably, both experience module I and experience module II include a signal processing module and an experience storage module. The input terminal of the signal processing module is connected to the output terminal of the first addition unit of the prefrontal cortex module I or the prefrontal cortex module II, and the output terminal of the signal processing module is connected to the input terminal of the experience storage module. The experience storage module is equipped with a memristor, and the output terminal of the experience storage module is connected to an OR gate D. 35 Connect to the input terminal.

[0012] Preferably, the signal processing module includes a fourth inverting amplifier circuit and a fifth inverting amplifier circuit. The output terminal of the first addition unit in the prefrontal cortex module I or the prefrontal cortex module II is connected to the input terminal of the fourth inverting amplifier circuit. The output terminal of the fourth inverting amplifier circuit is connected to the input terminal of the fifth inverting amplifier circuit. The output terminal of the fifth inverting amplifier is connected to the input terminal of the experience storage module. The experience storage module includes a first mathematical operation unit, a third comparator, a sixth inverting amplifier circuit, and a fourth AND gate. The output of the signal processing module is connected to the positive terminal of the second memristor of the sixth inverting amplifier circuit and one input of the first mathematical operation unit. The output of the sixth inverting amplifier circuit is connected to the other input of the second mathematical operation unit. The output of the first mathematical operation unit is connected to the input of the third comparator. The output of the third comparator is connected to one input of the fourth AND gate. The other input of the fourth AND gate is connected to the output of delay module II or delay module IV. The output of the fourth AND gate is connected to an OR gate D. 35 Connect to the input terminal.

[0013] Preferably, the generalization module includes a signal judgment circuit and a second voltage control circuit. The input terminal of the signal judgment circuit is the input terminal of the generalization module and is connected to the output terminal of the prefrontal cortex module I. The output terminal of the signal judgment circuit is connected to one input terminal of the second voltage control circuit. The input terminal of the second voltage control circuit is connected to the output terminal of the delay module IV and the output terminal of the signal judgment circuit, respectively. The output terminal of the second voltage control circuit is the output terminal of the generalization module and is connected to one input terminal of the first addition unit in the prefrontal cortex module II.

[0014] Preferably, the signal determination circuit includes a fourth comparator, a fifth comparator, and an AND gate D. 33 The inputs of the fourth and fifth comparators are the inputs of the signal judgment circuit, and both inputs are connected to the output of the first addition unit of the prefrontal cortex module I. The outputs of the fourth and fifth comparators are respectively connected to AND gate D. 33 The two input terminals are connected to the gate D.33 The output terminal is the output terminal of the signal judgment circuit and is ANDed with gate D. 33 The output terminal is connected to the input terminal of the second voltage control circuit; The second voltage control circuit includes a NOT gate D. 31 Eleventh pressure control unit and AND gate D 32 NOT gate D 31 The input terminal of the NOT gate is connected to the output terminal of the delay module IV. 31 The output terminal and AND gate D 32 The input terminal is connected to the output terminal of the signal judgment circuit and the AND gate D. 32 Connect to the other input terminal, and use gate D 32 The output terminal is connected to the input terminal of the eleventh pressure control unit, and the output terminal of the eleventh pressure control unit is connected to one input terminal of the first addition operation unit of the prefrontal cortex module II.

[0015] Preferably, the logic circuit includes an OR gate D. 13 Input signal terminal N4 and OR gate D 35 The outputs of the two gates are respectively connected to the OR gate D. 13 The two input terminals are connected together, or gate D 13 The outputs are respectively connected to the AND gate D 12 AND gate D 16 Connect one input terminal to gate D 12 The other input terminal is connected to the output terminal of delay module II, and is connected to gate D. 12 The output terminal is connected to the input terminal of delay module III, and is connected to gate D. 16 The other input terminal is connected to the output terminal of delay module V, and is connected to gate D. 12 The output terminal is connected to the input terminal of delay module IV; The first logic unit includes AND gate D1, AND gate D2 and OR gate D3. The input terminal of AND gate D1 is connected to input signal terminal N1 and input signal terminal N2 respectively. The output terminal of AND gate D1 is connected to one input terminal of OR gate D3. The input terminal of AND gate D2 is connected to input signal terminal N1 and output terminal of delay module I respectively. The output terminal of AND gate D2 is connected to the other input terminal of OR gate D3. The output terminal of OR gate D3 is connected to the input terminal of the first voltage control unit. The second logic unit includes a NOT gate D4 and an AND gate D5. The input terminal of the NOT gate D4 is connected to the input signal terminal N1, the output terminal of the NOT gate D4 is connected to one input terminal of the AND gate D5, the input signal terminal N2 is connected to the other input terminal of the AND gate D5, and the output terminal of the AND gate D5 is connected to the input terminal of the second voltage control unit. The third logic unit includes a fifth AND gate, one input of which is connected to the input signal terminal N1, the other input of which is connected to the output of delay module III or delay module IV, and the output of which is connected to the input of the fifth voltage control unit. The fourth logic unit includes a second NOT gate and a sixth AND gate. The input terminal of the second NOT gate is connected to the input signal terminal N1, the output terminal of the second NOT gate is connected to one input terminal of the sixth AND gate, the other input terminal of the sixth AND gate is connected to the output terminal of delay module III or delay module IV, and the output terminal of the sixth AND gate is connected to the input terminal of the sixth voltage control unit. The first, second, and sixth inverting amplifier circuits each include a first operational amplifier, a memristor, and a first resistor. The non-inverting input of the first operational amplifier is grounded, and the negative input of the first operational amplifier is connected to the negative terminal of the memristor and one end of the first resistor, respectively. The positive terminal of the memristor is the input terminal of the first, second, and sixth inverting amplifier circuits. The other end of the first resistor is connected to the output terminal of the first operational amplifier, and the output terminal of the first operational amplifier is the output terminal of the first, second, and sixth inverting amplifier circuits. The fourth inverting amplifier circuit includes a second operational amplifier, a second resistor, and a first capacitor. The non-inverting input of the second operational amplifier is grounded. The negative input of the second operational amplifier is connected to one end of the second resistor, resistor III, and the first capacitor, respectively. The other end of resistor III is the input of the fourth inverting amplifier circuit and is connected to the output of the prefrontal cortex module I. The other ends of the second resistor and the first capacitor are both connected to the output of the second operational amplifier. The output of the second operational amplifier is connected to the input of the fifth inverting amplifier circuit. The fifth inverting amplifier circuit includes operational amplifier I, with its non-inverting input terminal grounded. The negative input terminal of operational amplifier II is connected to one end of resistor IV and resistor V, respectively. The other end of resistor IV is connected to the output terminal of the second operational amplifier, and the other end of resistor V is connected to the output terminal of operational amplifier I. The output terminal of operational amplifier I is connected to the input terminal of the sixth inverting amplifier circuit and one input terminal of the first mathematical operation unit, respectively. The first addition unit includes a third operational amplifier, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor. One end of the third, fourth, fifth, and sixth resistors is the input terminal of the first addition unit. The other ends of the third, fourth, fifth, and sixth resistors are respectively connected to the non-inverting input terminal of the third operational amplifier and one end of the seventh resistor. The other end of the seventh resistor is grounded. The negative input of the third operational amplifier is respectively connected to one end of the eighth and ninth resistors. The other end of the eighth resistor is grounded. The other end of the ninth resistor is connected to the output terminal of the third operational amplifier. The output terminal of the third operational amplifier is connected to the input terminal of the first addition unit. The first, second, third, fourth, fifth, sixth, seventh, and eighth voltage control units each include a voltage control switch, a voltage source I, and a tenth resistor. The positive input of the voltage control switch is the input terminal of each voltage control unit, and the negative input of the voltage control switch is grounded. The first contact of the voltage control switch is the output terminal of the voltage control unit and is connected to one end of the tenth resistor. The second contact of the voltage control switch is connected to the positive terminal of the voltage source I, and the other end of the tenth resistor and the negative terminal of the voltage source I are both grounded. The first comparator, the second comparator, the third comparator, and the fourth comparator each include a fourth operational amplifier and a voltage source II. The positive terminal of the voltage source II is connected to the non-inverting input terminal of the fourth operational amplifier, and the negative terminal of the voltage source II is grounded. The negative input of the fourth operational amplifier is the input terminal of the first comparator, the second comparator, the third comparator, and the fourth comparator. The output terminal of the fourth operational amplifier is the output terminal of the first comparator, the second comparator, the third comparator, and the fourth comparator. The fifth comparator includes a fifth operational amplifier and a voltage source III. The non-inverting input of the fifth operational amplifier is the input of the fifth comparator. The negative input of the fifth operational amplifier is connected to the positive terminal of the voltage source III. The negative terminal of the voltage source III is grounded. The output of the fifth operational amplifier is the output of the fifth comparator.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) The bridging function in operant conditioning is considered. The bridging function in operant conditioning is realized through a delay module and a prefrontal cortex module. Bridging refers to the fact that the stimulus that appears between the animal's performance of the action and the subsequent reward can bridge the gap between the behavior and the result, thereby promoting the training process. The longer the stimulus, the better the bridging effect and the better the promotion effect. The neural network circuit with bridging function can further improve the integrity of operant conditioning.

[0017] (2) The conditioned reinforcement function in operant conditioning is considered, and the conditioned reinforcement function in operant conditioning is realized by the memory module and the prefrontal cortex module. After the classical conditioning training, the whistle becomes the stimulus reinforcer. The whistle stimulus added in the subsequent operant conditioning training plays an immediate reinforcing role, thereby promoting the training process. In the subsequent training process, classical conditioning and operant conditioning occur simultaneously. The neural network circuit with conditioned reinforcement function can realize more complex associative memory.

[0018] (3) The generalization process of operant conditioning is considered. The generalization function of operant conditioning is realized through the generalization module and the experience module. After operant conditioning training, similar prompt signals can also trigger actions. The neural network circuit with generalization function is more biomimetic.

[0019] This invention implements the learning, forgetting, and delayed learning functions of classical conditioning through a memory module and a delay module, and the learning and forgetting functions of operant conditioning through a prefrontal cortex module and an experience module. Furthermore, it combines classical and operant conditioning to achieve bridging and reinforcement functions. In addition, this invention implements the generalization function of operant conditioning through a generalization module. This invention considers the simultaneous occurrence of classical and operant conditioning in real-world training scenarios, implementing the learning, forgetting, and delayed learning functions of classical conditioning, as well as the bridging, reinforcement, and generalization functions of operant conditioning. The circuit designed in this invention can realize more complex associative memory processes, is more biologically compliant, and more comprehensive, contributing to the construction of more intelligent neural network circuits. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is the circuit schematic diagram of the present invention.

[0022] Figure 2 for Figure 1 The circuit diagram of the memory module is shown.

[0023] Figure 3 for Figure 1 The circuit diagram of delay module I is shown.

[0024] Figure 4 for Figure 1 The circuit diagram of prefrontal cortex module I is shown.

[0025] Figure 5 for Figure 1 The circuit diagram of Experience Module I is shown.

[0026] Figure 6 for Figure 1 The circuit diagram of the generalization module is shown.

[0027] Figure 7 The figure shows the simulation results of the classical conditioned reflection with delay of the present invention, where (a) is the voltage signal at the signal input terminal N1, (b) is the voltage signal at the signal input terminal N2, (c) is the voltage signal at the signal input terminal N3, (d) is the resistance change of memristor M1, (e) is the resistance change of memristor M2, and (f) is the voltage signal at the signal output terminal N6.

[0028] Figure 8 The diagram shows the simulation results of the operational conditioned reflex of the present invention, where (a) is the voltage signal at signal input terminal N3, (b) is the voltage signal at signal input terminal N1, (c) is the voltage signal at signal input terminal N4, and (d) is the voltage V. OP9 The corresponding voltage signals are (e) the resistance change of memristor M7 and (f) the voltage signal at the signal output terminal N7.

[0029] Figure 9 The diagram shows the simulation results of the operant conditioning reflex with short bridging stimulus of the present invention, where (a) is the voltage signal at signal input terminal N3, (b) is the voltage signal at signal input terminal N1, (c) is the voltage signal at signal input terminal N4, (d) is the voltage signal at signal input terminal N2, and (e) is the voltage V. OP9 The corresponding voltage signals are: (f) is the resistance change of memristors M7 and M1, (g) is the voltage signal at the signal input terminal N6, and (h) is the voltage signal at the signal output terminal N7.

[0030] Figure 10 The diagram shows the simulation results of the operant conditioning reflex with long bridging stimulus of the present invention, where (a) is the voltage signal at signal input terminal N3, (b) is the voltage signal at signal input terminal N1, (c) is the voltage signal at signal input terminal N4, (d) is the voltage signal at signal input terminal N2, and (e) is the voltage V. OP9 The corresponding voltage signals are: (f) is the resistance change of memristors M7 and M1, (g) is the voltage signal at the signal input terminal N6, and (h) is the voltage signal at the signal output terminal N7.

[0031] Figure 11The following is a simulation result diagram of the operant conditioning reflex with conditional reinforcement according to the present invention, wherein (a) is the voltage signal at signal input terminal N3, (b) is the voltage signal at signal input terminal N1, (c) is the voltage signal at signal input terminal N4, (d) is the voltage signal at signal input terminal N2, and (e) is the voltage V. M1 Voltage V OP9 The corresponding voltage signals are: (f) is the resistance change of memristors M1 and M7, (g) is the voltage signal at the signal input terminal N6, and (h) is the voltage signal at the signal output terminal N7.

[0032] Figure 12 The diagram shows the generalization simulation results of the operant conditioned reflex of the present invention, where (a) is the voltage signal at signal input terminal N3, (b) is the voltage signal at signal input terminal N5, (c) is the voltage signal at signal input terminal N1, (d) is the voltage signal at signal input terminal N4, (e) is the voltage signal at signal input terminal N2, and (f) is the voltage V. OP9 Voltage V OP11 The corresponding voltage signals are (g) the resistance changes of memristors M7 and M8, and (h) the voltage signal at the signal output terminal N7. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] like Figure 1As shown, an operational conditioned reflex neural network circuit with bridging and conditional reinforcement includes input signal terminals N1-N5, a memory module, delay modules I, II, III, IV, and V, prefrontal cortex module I, prefrontal cortex module II, experience module I, experience module II, and a generalization module. Input signal terminal N1, representing a food signal, is connected to the input terminals of the memory module, prefrontal cortex module I, and prefrontal cortex module II, respectively. Input signal terminal N2, representing a whistle signal, is connected to the input terminal of the memory module. Input signal terminal N3, representing command signal I, is connected to the input terminal of delay module II. Input signal terminal N4, representing an auxiliary signal, is connected to the input terminals of delay modules III and IV via logic circuits, respectively. Input signal terminal N5, representing command signal II, is connected to the input terminal of delay module V. The output terminal of the memory module is connected to the input terminals of delay modules I, prefrontal cortex module I, and prefrontal cortex module II, respectively. The output of delay module I is connected to the inputs of the memory module, prefrontal cortex module I, and prefrontal cortex module II, respectively. The output of delay module II is connected to the logic circuit before delay module III and the input of experience module I, respectively. The output of delay module III is connected to the input of prefrontal cortex module I. The output of delay module IV is connected to the inputs of the generalization module and prefrontal cortex module II, respectively. The output of delay module V is connected to the inputs of delay module IV and experience module II, respectively. The output of prefrontal cortex module I is connected to the inputs of experience module I and the generalization module, respectively. The output of prefrontal cortex module II is connected to the input of experience module II. The output of the generalization module is connected to the input of the addition unit of the prefrontal cortex module II. The output of the memory module is connected to the input of OR gate D9. The input signal terminal N1 is connected to the input of OR gate D9 through resistor R4, which represents the synapse between the food signal and the excited neuron. The outputs of experience module I and experience module II are respectively connected to OR gate D9. 35 The two input terminals are connected together, the output terminal of OR gate D35 is connected to the logic circuit, the output of OR gate D9 is the output terminal N6 representing the excitation signal, and OR gate D 35 The output is output terminal N7, which represents the action signal.

[0035] The memory module is used to implement the classical conditioned reflex process between the food signal and the whistle signal. The delay module generates a delayed pulse after the input signal disappears; the pulse width is related to the module parameters. The prefrontal cortex module applies different training voltages to the experience module during different operant conditioning training processes. The experience module stores the synaptic weights between the command signal and the action signal. The generalization module generates a generalization voltage for experience module II based on the training results of experience module I, thus completing the generalization process of operant conditioning. Input signal terminal N1 receives the food signal, input signal terminal N2 receives the whistle signal, input signal terminal N3 receives command signal I, input signal terminal N4 receives the auxiliary signal, and input signal terminal N5 receives command signal II. Command signal I and command signal II are verbal commands with the same content but different timbres, such as the verbal command "Sit down!" to instruct the trainee to sit down. In the specific implementation, the amplitude of all the above input signals is 5V. Two-input OR gate D9 and OR gate D... 35 The output terminal is the output signal terminal of the circuit. The bridging function in operant conditioning is implemented by the delay module and the prefrontal cortex module. During training, if a whistle signal appears between the auxiliary signal and the food signal, the training voltage output by the prefrontal cortex module decreases during the duration of the whistle signal, thus promoting the training process and achieving the bridging function. The delay module plays a role in associating the auxiliary signal and the food signal in this process. The conditioned reinforcement function in operant conditioning is implemented by the prefrontal cortex module of the memory module. Based on the bridging function, if the whistle signal and the food signal form an associative memory, i.e., the voltage output from the memory module to the prefrontal cortex module is greater than a threshold, the training voltage output by the prefrontal cortex module will become smaller, further promoting the training process and achieving the conditioned reinforcement function of operant conditioning. The generalization function of operant conditioning is implemented by the generalization module and the experience module. When training is performed using only command signal I, the generalization module will also generate a training voltage for experience module II corresponding to command signal II, thus achieving the generalization function of operant conditioning.

[0036] Input signal terminals N1 and N2 are both connected to the input terminals of the memory module. The synaptic weight between the food signal and the whistle signal in the memory module changes according to the input signal. When only signal N1 or N2 is input, the circuit is in test mode. Initially, when only signal N1 is input, the circuit outputs an excitation signal N6. When only signal N2 is input, the circuit does not produce an output. When signals N1 and N2 are input simultaneously, the circuit is in memory mode, and the resistance of the memristor M1 in the memory module gradually decreases, indicating that the synaptic weight between the food signal and the whistle signal gradually increases. After a period of time, the synaptic weight between the two reaches a threshold, and inputting the whistle signal alone can induce excitation.

[0037] like Figure 2 As shown, the memory module includes a voltage control circuit, a synaptic neuron circuit, a NOT gate D6, an adder SUM1, and a first comparator. The input terminal of the voltage control circuit is the input terminal of the memory module, and the input terminal of the voltage control circuit is connected to the output terminal, input signal terminal N1, and input signal terminal N2 of the delay module I, respectively. The output terminal of the voltage control circuit is connected to the positive terminal of the memristor M1 in the synaptic neuron circuit. The output terminal of the synaptic neuron circuit is connected to the input terminals of the prefrontal cortex module I and the prefrontal cortex module II, as well as one input terminal of the adder SUM1, respectively. The input signal terminal N2 is connected to the input terminal of the NOT gate D6. The output terminal of the NOT gate D6 is connected to the other input terminal of the adder SUM1 and one input terminal of the delay module I, respectively. The output terminal of the adder SUM1 is connected to the input terminal of the first comparator. The output terminal of the first comparator is the output terminal of the memory module and outputs an excitation signal representing the completion of memory.

[0038] The voltage control circuit includes a first logic unit, a second logic unit, a first voltage control unit, and a second voltage control unit. The input terminals of the first logic unit are connected to input signal terminals N1 and N2, and the output terminal of delay module I, respectively. The output terminal of the first logic unit is connected to the input terminal of the first voltage control unit. The input terminals of the second logic unit are connected to input signal terminals N1 and N2, respectively. The output terminal of the second logic unit is connected to the input terminal of the second voltage control unit. The output terminals of both the first and second voltage control units are the output terminals of the voltage control circuit, and both output terminals are connected to the input terminals of the synaptic neuron circuit. When the food signal N1 and the whistle signal N2 are simultaneously input, the first logic unit outputs a high level, thereby activating the first voltage control unit. The first voltage control unit then supplies the output voltage V1 of voltage source V1 to the input terminal of the synaptic neuron circuit. At this time, the output of the voltage control circuit is V1. The second logic unit outputs a high level when a whistle signal N2 is input alone, thereby activating the second voltage control unit. The second voltage control unit sends the output V2 of the voltage source V2 to the input of the synaptic neuron circuit. At this time, the output of the voltage control circuit is V2.

[0039] The synaptic neuron circuit includes a first inverting amplifier circuit and a mathematical operation unit ABM1. The positive terminal of the memristor M1 in the first inverting amplifier circuit is the input terminal of the synaptic neuron circuit. The output terminal of the voltage control circuit is connected to both the positive terminal of memristor M1 and one input terminal of the mathematical operation unit ABM1. The negative terminal of memristor M1 is connected to the input terminal of the operational amplifier in the first inverting amplifier circuit. The output terminal of the operational amplifier in the first inverting amplifier circuit is connected to the other input terminal of the mathematical operation unit ABM1. The output of the first inverting amplifier circuit is V. OP1=-R3 / M1 (The resistor or memristor before the operational amplifier is part of the inverting amplifier circuit). The output of the mathematical operation unit ABM1 is the output of the synaptic neuron circuit. The output of the mathematical operation unit ABM1 is V. ABM1 =-V IN2 / V IN1 =M1 / R3. When the output voltage of the voltage control circuit is greater than the positive threshold of memristor M1, the resistance of memristor M1 gradually decreases. Therefore, the output of the mathematical operation unit ABM1 also gradually decreases, which means that the synaptic weight between the food signal N1 and the whistle signal N2 gradually increases. When the output voltage of the voltage control circuit is less than the positive threshold of memristor M1, the resistance of memristor M1 gradually increases. Therefore, the output of the mathematical operation unit ABM1 also gradually increases, which means that the synaptic weight between the food signal N1 and the whistle signal N2 gradually decreases.

[0040] The first logic unit includes AND gate D1, AND gate D2, and OR gate D3. The input of AND gate D1 is connected to input signal terminals N1 and N2, respectively. The output of AND gate D1 is connected to one input of OR gate D3. The input of AND gate D2 is connected to input signal terminal N1 and the output of delay module I, respectively. The output of AND gate D2 is connected to the other input of OR gate D3. The output of OR gate D3 is connected to the input of the first voltage control unit. The second logic unit includes NOT gate D4 and AND gate D5. The input of NOT gate D4 is connected to input signal terminal N1. The output of NOT gate D4 is connected to one input of AND gate D5. Input signal terminal N2 is connected to the other input of AND gate D5. The output of AND gate D5 is connected to the input of the second voltage control unit.

[0041] The first voltage-controlled unit includes a voltage-controlled switch S1, a voltage source V1, and a resistor R1. The positive input of the voltage-controlled switch S1 is the input terminal of the first voltage-controlled unit, and the positive input of the voltage-controlled switch S1 is connected to the output terminal of the OR gate D3 of the first logic unit. The first contact of the voltage-controlled switch S1 is the output terminal of the first voltage-controlled unit and is connected to one end of the resistor R1 and the input terminal of the synaptic neuron circuit, respectively. The other end of the resistor R1 is grounded. The second contact of the voltage-controlled switch S1 is connected to the positive terminal of the voltage source V1, the negative terminal of the voltage source V1 is grounded, and the negative input of the voltage-controlled switch S1 is grounded. The second voltage-controlled unit includes a voltage-controlled switch S2, a voltage source V2, and a resistor R2. The positive input of the voltage-controlled switch S2 is the input terminal of the second voltage-controlled unit, and the positive input of the voltage-controlled switch S2 is connected to the output terminal of the AND gate D5 of the second logic unit. The first contact of the voltage-controlled switch S2 is the output terminal of the second voltage-controlled unit and is connected to one end of the resistor R2, the input terminal of the first inverting proportional amplifier circuit of the synaptic neuron circuit, and one input terminal of the mathematical operation unit ABM1, respectively. The other end of the resistor R2 is grounded. The second contact of the voltage-controlled switch S2 is connected to the positive terminal of the voltage source V2, the negative terminal of the voltage source V2 is grounded, and the negative input of the voltage-controlled switch S2 is grounded.

[0042] The first inverting amplifier circuit includes a memristor M1, an operational amplifier OP1, and a resistor R3. The non-inverting input of the operational amplifier OP1 is grounded. The negative input of the operational amplifier OP1 is connected to the negative terminal of the memristor M1 and one end of the resistor R3. The positive terminal of the memristor M1 is connected to the first contact of the voltage-controlled switch S1 and the voltage-controlled switch S2. The other end of the resistor R3 is connected to the output terminal of the operational amplifier OP1. The output terminal of the operational amplifier OP1 is the output terminal of the first inverting amplifier circuit.

[0043] The first comparator includes an operational amplifier OP2 and a voltage source V3. The positive terminal of the voltage source V3 is connected to the non-inverting input of the operational amplifier OP2, and the negative terminal of the voltage source V3 is grounded. The negative input of the operational amplifier OP2 is the input terminal of the first comparator and is connected to the output terminal of the adder SUM1. The output terminal of the operational amplifier OP2 is the output terminal of the first comparator and is connected to one input terminal of the OR gate D9.

[0044] like Figure 3As shown, delay module I includes NOT gate D7, a third voltage-controlled unit, a fourth voltage-controlled unit, memristor M2, a second inverting amplifier circuit, NMOS transistor T1, PMOS transistor T2, resistors R8 and R9, voltage sources V6, V7, V8 and V9, and AND gate D8. The inputs of NOT gate D7 and the fourth voltage-controlled unit are both connected to the output of NOT gate D6 in the memory module. The input of NOT gate D7 is also the input of delay module I. The output of NOT gate D7 is connected to the input of the third voltage-controlled unit and one input of AND gate D8. The third voltage-controlled unit... The outputs of both the first and fourth voltage-controlled units are connected to the positive terminal of memristor M2 in the second inverting amplifier circuit. The negative terminal of memristor M2 is connected to the input terminal of the operational amplifier in the second proportional amplifier circuit. The output terminal of the operational amplifier in the second proportional amplifier circuit is connected to the gate of NMOS transistor T1. The source of NMOS transistor T1 is connected to the positive terminal of voltage source V8, and the negative terminal of voltage source V8 is grounded. The drain of NMOS transistor T1 is connected to the gate of PMOS transistor T2 and one end of resistor R8. The other end of resistor R8 is connected to the positive terminal of voltage source V6, and the negative terminal of voltage source V6 is grounded. The source of PMOS transistor T2 is connected to the positive terminal of voltage source V9, and the negative terminal of voltage source V9 is grounded. The drain of PMOS transistor T2 is connected to one end of resistor R9 and one input terminal of AND gate D8. The other end of resistor R9 is connected to the positive terminal of voltage source V7, and the negative terminal of voltage source V7 is grounded. The output terminal of AND gate D8 is the output terminal of delay module I. NMOS transistor T1 and PMOS transistor T2 together form a structure similar to a comparator. The drain of PMOS transistor T2 will only output a high level when the difference between the gate voltage and the source voltage of NMOS transistor T1 is greater than the turn-on threshold of NMOS transistor T1. Otherwise, the drain of PMOS transistor T2 will output a low level.

[0045] The third voltage control unit includes a voltage control switch S3, a voltage source V4, and a resistor R5. The positive input of the voltage control switch S3 is the input terminal of the third voltage control unit and is connected to the output terminal of the NOT gate D7. The first contact of the voltage control switch S3 is the output terminal of the third voltage control unit and is connected to one end of the resistor R5 and the positive terminal of the memristor M2. The other end of the resistor R5 is grounded. The second contact of the voltage control switch S3 is connected to the positive terminal of the voltage source V4. The negative terminal of the voltage source V4 is grounded. The negative input of the voltage control switch S3 is grounded. The fourth voltage-controlled unit includes a voltage-controlled switch S4, a voltage source V5, and a resistor R6. The positive input of the voltage-controlled switch S4 is the input terminal of the fourth voltage-controlled unit and is connected to the output terminal of NOT gate D6 and the input terminal of NOT gate D7. The first contact of the voltage-controlled switch S4 is the output terminal of the fourth voltage-controlled unit and is connected to one end of the resistor R6, the output terminal of the third voltage-controlled unit, and the positive terminal of the memristor M2. The other end of the resistor R6 is grounded. The second contact of the voltage-controlled switch S4 is connected to the positive terminal of the voltage source V5. The negative terminal of the voltage source V5 is grounded, and the negative input of the voltage-controlled switch S4 is grounded.

[0046] The second inverting amplifier includes an operational amplifier OP3, a memristor M2, and a resistor R7. The non-inverting input of the operational amplifier OP3 is grounded. The negative input of the operational amplifier OP3 is connected to the negative terminal of the memristor M2 and one end of the resistor R7. The other end of the resistor R7 is connected to the output of the operational amplifier OP3. The output of the operational amplifier OP3 is the output of the first inverting amplifier circuit and is connected to the gate of the NMOS transistor T1.

[0047] Delay module II includes NOT gate D 10 The twelfth voltage-controlled unit, the thirteenth voltage-controlled unit, the seventh inverting proportional amplifier circuit, NMOS transistor T3, PMOS transistor T4, and resistor R. 13 and resistance R 14 Voltage source V 12 Voltage source V 13 Voltage source V 14 and voltage source V 15 And AND gate D 11 Thirteenth voltage control unit, NOT gate D 10 The input terminals of all are connected to the input signal terminal N3, and the NOT gate D 10 The input terminal is the input terminal of delay module II, and the NOT gate D 10 The output terminals are respectively connected to the input terminal of the twelfth voltage control unit and the AND gate D. 11One input terminal is connected to the voltage source. The output terminals of the twelfth and thirteenth voltage-controlled units are both connected to the positive terminal of the memristor M3 in the seventh inverting amplifier circuit. The negative terminal of the memristor M3 is connected to the input terminal of the operational amplifier in the seventh proportional amplifier circuit. The output terminal of the operational amplifier in the seventh proportional amplifier circuit is connected to the gate of the NMOS transistor T3. The source of the NMOS transistor T3 is connected to the voltage source V. 14 Connect the positive terminal to the voltage source V. 14 The negative terminal of the transistor is grounded, and the drain of the NMOS transistor T3 is connected to the gate of the PMOS transistor T4 and the resistor R, respectively. 13 One end is connected to the resistor R. 13 The other end is connected to the voltage source V 12 Connect the positive terminal to the voltage source V. 12 The negative terminal of the PMOS transistor T4 is grounded, and the source of the PMOS transistor T4 is connected to the voltage source V. 15 Connect the positive terminal to the voltage source V. 15 The negative terminal of the PMOS transistor T4 is grounded, and the drain of the PMOS transistor T4 is connected to resistor R. 14 One end and AND gate D 11 Connect one input terminal to the resistor R 14 The other end is connected to the voltage source V 13 Connect the positive terminal to the voltage source V. 13 The negative terminal is grounded, AND gate D 11 The output terminal is the output terminal of delay module II.

[0048] The twelfth voltage control unit includes a voltage control switch S5 and a voltage source V. 10 and resistance R 10 The positive input of the voltage-controlled switch S5 is the input terminal of the twelfth voltage-controlled unit and is connected to the NOT gate D. 10 The output terminal and AND gate D 11 One input terminal is connected, and the first contact of the voltage-controlled switch S5 is the output terminal of the twelfth voltage-controlled unit and is connected to the resistor R. 10 One end of the circuit is connected to the output terminal of the thirteenth voltage-controlled unit and the positive terminal of the memristor M3 in the seventh inverting amplifier circuit. The resistor R 10 The other end is grounded, and the second contact of the voltage-controlled switch S5 is connected to the voltage source V. 10 Connect the positive terminal to the voltage source V. 10 The negative terminal of voltage control switch S6 is grounded, and the negative input of voltage control switch S5 is grounded. The thirteenth voltage control unit includes voltage control switch S6 and voltage source V. 11 and resistance R 11 The positive input of the voltage-controlled switch S6 is the input terminal of the thirteenth voltage-controlled unit and is connected to the input signal terminal N3 and the NOT gate D respectively. 10 The input terminal is connected, and the first contact of the voltage-controlled switch S6 is the output terminal of the thirteenth voltage-controlled unit and is connected to the resistor R. 11One end is connected to the positive terminal of memristor M3, and resistor R 11 The other end is grounded, and the second contact of the voltage-controlled switch S6 is connected to the voltage source V. 11 Connect the positive terminal to the voltage source V. 11 The negative terminal of the voltage-controlled switch S6 is grounded, and the negative input of the voltage-controlled switch S6 is grounded.

[0049] The seventh inverting amplifier includes operational amplifier OP4, memristor M3, and resistor R. 12 The non-inverting input of operational amplifier OP4 is grounded, and the negative input of operational amplifier OP4 is connected to the negative terminal of memristor M3 and resistor R, respectively. 12 One end is connected to the resistor R. 12 The other end is connected to the output of operational amplifier OP4, which is the output of the seventh inverting amplifier circuit.

[0050] Logic circuits include OR gates D 13 Input signal terminal N4 and OR gate D 35 The output terminal, i.e., the output signal terminal N7, is respectively connected to the OR gate D. 13 The two input terminals are connected together, or gate D 13 The outputs are respectively connected to the AND gate D 12 AND gate D 16 Connect one input terminal to gate D 12 The other input terminal is connected to the output terminal of delay module II, and is connected to gate D. 12 The output terminal is connected to the input terminal of delay module III, and is connected to gate D. 16 The other input terminal is connected to the output terminal of delay module V, and is connected to gate D. 12 The output terminal is connected to the input terminal of delay module IV.

[0051] Delay module III includes NOT gate D 14 Fourteenth voltage-controlled unit, fifteenth voltage-controlled unit, eighth inverting proportional amplifier circuit, NMOS transistor T5, PMOS transistor T6, resistor R 18 and resistance R 19 Voltage source V 18 Voltage source V 19 Voltage source V 20 and voltage source V 21 And AND gate D 15 AND gate D 12 The output terminals are respectively connected to the input terminal of the fifteenth voltage control unit and the NOT gate D. 14 Connect the input terminals of the NOT gate D to the input terminals. 14 The output terminals are respectively connected to the input terminal of the fourteenth voltage control unit and the AND gate D. 15One input terminal is connected to the circuit. The output terminals of the fourteenth and fifteenth voltage-controlled units are both connected to the positive terminal of the memristor M4 in the eighth inverting amplifier circuit. The negative terminal of the memristor M4 is connected to the input terminal of the operational amplifier in the eighth amplifier circuit. The output terminal of the eighth inverting amplifier circuit is connected to the gate of the NMOS transistor T5. The source of the NMOS transistor T5 is connected to the voltage source V. 20 Connect the positive terminal to the voltage source V. 20 The negative terminal of the transistor is grounded, and the drain of the NMOS transistor T5 is connected to the gate of the PMOS transistor T6 and the resistor R, respectively. 18 One end is connected to the resistor R. 18 The other end is connected to the voltage source V 18 Connect the positive terminal to the voltage source V. 18 The negative terminal of the PMOS transistor T6 is grounded, and the source of the PMOS transistor T6 is connected to the voltage source V. 21 Connect the positive terminal to the voltage source V. 21 The negative terminal of the PMOS transistor T6 is grounded, and the drain of the PMOS transistor T6 is connected to resistor R. 19 One end and AND gate D 15 Connect one input terminal to the resistor R 19 The other end is connected to the voltage source V 19 Connect the positive terminal to the voltage source V. 19 The negative terminal is grounded, AND gate D 15 The output terminal is the output terminal of delay module III.

[0052] The fourteenth voltage control unit includes a voltage control switch S7 and a voltage source V. 16 and resistance R 15 The positive input of the voltage-controlled switch S7 is the input terminal of the fourteenth voltage-controlled unit and is connected to the NOT gate D. 14 The output terminal and AND gate D 15 One input terminal is connected, and the first contact of the voltage-controlled switch S7 is the output terminal of the fourteenth voltage-controlled unit and is connected to the resistor R. 15 One end is connected to the positive terminal of memristor M4, and resistor R 15 The other end is grounded, and the second contact of the voltage-controlled switch S7 is connected to the voltage source V. 16 Connect the positive terminal to the voltage source V. 16 The negative terminal of voltage control switch S7 is grounded, and the negative input of voltage control switch S7 is grounded. The fifteenth voltage control unit includes voltage control switch S8 and voltage source V. 17 and resistance R 16 The positive input terminal of the voltage-controlled switch S8 is the input terminal of the fifteenth voltage-controlled unit and is connected to the AND gate D. 12 The output of the NOT gate D 14 The input terminal is connected, and the first contact of the voltage-controlled switch S8 is the output terminal of the fifteenth voltage-controlled unit and is connected to the resistor R. 16 One end is connected to the positive terminal of memristor M4, and resistor R16 The other end is grounded, and the second contact of the voltage-controlled switch S8 is connected to the voltage source V. 17 Connect the positive terminal to the voltage source V. 17 The negative terminal of the voltage-controlled switch S8 is grounded, and the negative input of the voltage-controlled switch S8 is grounded.

[0053] The eighth inverting amplifier includes operational amplifier OP5, memristor M4, and resistor R. 17 The non-inverting input of operational amplifier OP5 is grounded, and the negative input of operational amplifier OP5 is connected to the negative terminal of memristor M4 and resistor R, respectively. 17 One end is connected to the resistor R. 17 The other end is connected to the output of operational amplifier OP5, which is the output of the eighth inverting amplifier circuit.

[0054] Delay module IV includes NOT gate D 17 Sixteenth voltage-controlled unit, seventeenth voltage-controlled unit, ninth inverting proportional amplifier circuit, NMOS transistor T7, PMOS transistor T8, resistor R 23 and resistance R 24 Voltage source V 24 Voltage source V 25 Voltage source V 26 and voltage source V 27 And AND gate D 18 AND gate D 16 The output terminals are respectively connected to the input terminals of the seventeenth voltage control unit and the NOT gate D. 17 Connect the input terminals of the NOT gate D to the input terminals. 17 The output terminals are respectively connected to the input terminal of the sixteenth voltage control unit and the AND gate D. 18 One input terminal is connected to the voltage source. The output terminals of the sixteenth and seventeenth voltage-controlled units are both connected to the positive terminal of memristor M5 in the ninth inverting amplifier circuit. The negative terminal of memristor M5 is connected to the input terminal of the operational amplifier in the ninth proportional amplifier circuit. The output terminal of the operational amplifier in the ninth inverting amplifier circuit is connected to the gate of NMOS transistor T7. The source of NMOS transistor T7 is connected to the voltage source V. 26 Connect the positive terminal to the voltage source V. 26 The negative terminal of the transistor is grounded, and the drain of the NMOS transistor T7 is connected to the gate of the PMOS transistor T8 and the resistor R, respectively. 23 One end is connected to the resistor R. 23 The other end is connected to the voltage source V 24 Connect the positive terminal to the voltage source V. 24 The negative terminal of the PMOS transistor T8 is grounded, and the source of the PMOS transistor T8 is connected to the voltage source V. 27 Connect the positive terminal to the voltage source V. 27 The negative terminal of the PMOS transistor T8 is grounded, and the drain of the PMOS transistor T8 is connected to resistor R. 24One end and AND gate D 18 Connect one input terminal to the resistor R 24 The other end is connected to the voltage source V 25 Connect the positive terminal to the voltage source V. 25 The negative terminal is grounded, AND gate D 18 The output terminal is the output terminal of delay module IV.

[0055] The sixteenth voltage control unit includes a voltage control switch S9 and a voltage source V. 22 and resistance R 20 The positive input of the voltage-controlled switch S9 is the input terminal of the sixteenth voltage-controlled unit and is connected to the NOT gate D. 17 The output terminal and AND gate D 18 One input terminal is connected, and the first contact of the voltage-controlled switch S9 is the output terminal of the sixteenth voltage-controlled unit and is connected to the resistor R. 20 One end is connected to the positive terminal of memristor M5, and resistor R 20 The other end is grounded, and the second contact of the voltage-controlled switch S9 is connected to the voltage source V. 22 Connect the positive terminal to the voltage source V. 22 The negative terminal of the voltage control unit is grounded, and the negative input of the voltage control switch S9 is grounded. The seventeenth voltage control unit includes the voltage control switch S... 10 Voltage source V 23 and resistance R 21 Pressure-controlled switch S 10 The positive input is the input terminal of the seventeenth voltage-controlled unit and is connected to the AND gate D. 16 The output of the NOT gate D 17 Connect to the input terminal of the voltage-controlled switch S 10 The first contact is the output terminal of the seventeenth voltage-controlled unit and is connected to resistor R. 21 One end is connected to the positive terminal of memristor M5, and resistor R 21 The other end is grounded, voltage-controlled switch S 10 The second contact and voltage source V 23 Connect the positive terminal to the voltage source V. 23 The negative terminal is grounded, and the voltage-controlled switch S 10 The inverting input terminal is grounded.

[0056] The ninth inverting amplifier includes operational amplifier OP6, memristor M5, and resistor R. 22 The non-inverting input of operational amplifier OP6 is grounded, and the negative input of operational amplifier OP6 is connected to the negative terminal of memristor M5 and resistor R, respectively. 22 One end is connected to the resistor R. 22 The other end is connected to the output of operational amplifier OP6, which is the output of the ninth proportional amplifier circuit.

[0057] Delay module V includes NOT gate D 19 Eighteenth Voltage Controlled Unit, Nineteenth Voltage Controlled Unit, Memristor M6, Tenth Inverting Amplifier Circuit, NMOS Transistor T9, PMOS Transistor T 10 Resistance R 28 and resistance R 29 Voltage source V 30 Voltage source V 31 Voltage source V 32 and voltage source V 33 And AND gate D 20 , the nineteenth voltage control unit and NOT gate D 19 The input terminals of all are connected to the input signal terminal N5, and the NOT gate D 19 The input terminal is the input terminal of delay module V, and the NOT gate D 19 The output terminals are respectively connected to the input terminal of the eighteenth voltage control unit and the AND gate D. 11 One input terminal is connected to the positive terminal of memristor M6. The output terminals of the eighteenth and nineteenth voltage-controlled units are both connected to the positive terminal of memristor M6. The negative terminal of memristor M6 is connected to the input terminal of the operational amplifier of the tenth inverting amplifier circuit. The output terminal of the tenth inverting amplifier circuit is connected to the gate of NMOS transistor T9. The source of NMOS transistor T9 is connected to the voltage source V. 32 Connect the positive terminal to the voltage source V. 32 The negative terminal of the NMOS transistor T9 is grounded, and the drain of the NMOS transistor T9 is connected to the PMOS transistor T9. 10 Gate and resistor R 28 One end is connected to the resistor R. 28 The other end is connected to the voltage source V 30 Connect the positive terminal to the voltage source V. 30 The negative terminal of the PMOS transistor is grounded, and the PMOS transistor T 10 The source and voltage source V 33 Connect the positive terminal to the voltage source V. 33 The negative terminal of the PMOS transistor is grounded, and the PMOS transistor T 10 The drain of the resistor is connected to the resistor R respectively. 29 One end and AND gate D 20 Connect one input terminal to the resistor R 29 The other end is connected to the voltage source V 31 Connect the positive terminal to the voltage source V. 31 The negative terminal is grounded, AND gate D 20 The output terminal is the output terminal of delay module II.

[0058] The eighteenth pressure control unit includes a pressure control switch S. 11 Voltage source V 28 and resistance R 25 Pressure-controlled switch S 11 The positive input is the input terminal of the eighteenth voltage-controlled unit and is respectively connected to the NOT gate D.19 The output terminal and AND gate D 20 Connected to one input terminal, voltage-controlled switch S 11 The first contact is the output terminal of the eighteenth voltage-controlled unit and is connected to resistor R. 25 One end is connected to the positive terminal of memristor M6 in the tenth inverting amplifier circuit, and resistor R 25 The other end is grounded, voltage-controlled switch S 11 The second contact and voltage source V 28 Connect the positive terminal to the voltage source V. 28 The negative terminal is grounded, and the voltage-controlled switch S 11 The negative input is grounded. The nineteenth voltage control unit includes the voltage control switch S. 12 Voltage source V 29 and resistance R 26 Pressure-controlled switch S 12 The positive input is the input terminal of the nineteenth voltage-controlled unit and is connected to the input signal terminal N5 and the NOT gate D. 19 Connect to the input terminal of the voltage-controlled switch S 12 The first contact is the output terminal of the nineteenth voltage-controlled unit and is connected to resistor R. 26 One end is connected to the positive terminal of memristor M6, and resistor R 26 The other end is grounded, voltage-controlled switch S 12 The second contact and voltage source V 29 Connect the positive terminal to the voltage source V. 29 The negative terminal is grounded, and the voltage-controlled switch S 12 The negative input is grounded.

[0059] The tenth proportional amplifier includes operational amplifier OP7, memristor M6, and resistor R. 27 The non-inverting input of operational amplifier OP7 is grounded, and the negative input of operational amplifier OP7 is connected to the negative terminal of memristor M6 and resistor R, respectively. 27 One end is connected to the resistor R. 27 The other end is connected to the output of operational amplifier OP7, which is the output of the tenth inverting amplifier circuit.

[0060] like Figure 4 As shown, prefrontal cortex module I includes a third logic unit, a fourth logic unit, and an AND gate D. 24 Second comparator, AND gate D 25 The seventh, eighth, ninth, and tenth voltage control units, and the first addition unit, the input terminal of the third logic unit is connected to the input signal terminal N1 and the output terminal of the delay module III, and the output terminal of the third logic unit is connected to the input terminal of the seventh voltage control unit and the AND gate D. 24 Connect one input terminal to gate D 24The other input terminal is connected to the output terminal of delay module I. The input terminal of the fourth logic unit is connected to the input signal terminal N1 and the output terminal of delay module III. The output terminal of the fourth logic unit is connected to the input terminal of the eighth voltage control unit. AND gate D 24 The output terminals are respectively connected to the input terminal of the ninth voltage control unit and the AND gate D. 25 The input terminal of the first comparator is connected to the input terminal of the second comparator, and the input terminal of the second comparator is connected to the output terminal of the mathematical operation unit ABM1 of the synaptic neuron circuit in the memory module. The output terminal of the second comparator is connected to the AND gate D. 25 Connect to the other input terminal, and use gate D 25 The output terminal of the first addition unit is connected to the input terminal of the tenth pressure control unit. The output terminals of the seventh, eighth, ninth and tenth pressure control units are each connected to an input terminal of the first addition unit. The output terminal of the first addition unit is the output terminal of the prefrontal cortex module I and the output terminal of the first addition unit is connected to the input terminal of the experience module I.

[0061] The third logic unit includes AND gate D. 21 AND gate D 21 The input terminal is the input terminal of the third logic unit and is connected to the AND gate D of the input signal terminal N1 and the delay module III, respectively. 15 Connect to the output terminal of gate D. 21 The output terminal is the output terminal of the third logic unit and is connected to the input terminal of the seventh voltage control unit.

[0062] The fourth logic unit includes NOT gate D. 22 AND gate D 23 NOT gate D 22 The input terminals and AND gate D 23 One input terminal is the input terminal of the fourth logic unit, NOT gate D. 22 The input terminal of the NOT gate is connected to the input signal terminal N1. 22 The output terminal and AND gate D 23 Connect one input terminal to gate D 23 The other input terminal is ANDed with the delay module III's gate D. 15 Connect to the output terminal of gate D. 23 The output terminal is the output terminal of the fourth logic unit and is connected to the input terminal of the eighth voltage control unit.

[0063] The seventh pressure control unit includes a pressure control switch S 13 Voltage source V 35 and resistance R 30 Pressure-controlled switch S 13 The positive input is the input terminal of the seventh voltage control unit and the voltage control switch S 13 The positive input terminal is connected to the output terminal of the third logic unit, and the voltage-controlled switch S 13The first contact is the output terminal of the seventh voltage-controlled unit and is connected to resistor R. 30 One end is connected to the input terminal of the first addition unit, and the resistor R 30 The other end is grounded, voltage-controlled switch S 13 The second contact and voltage source V 35 The positive terminal is connected, and the voltage source V 35 Negative terminal grounded, voltage-controlled switch S 13 The negative input is grounded. The eighth voltage control unit includes a voltage control switch S. 14 Voltage source V 36 and resistance R 31 Pressure-controlled switch S 14 The positive input is the input terminal of the eighth voltage control unit and the voltage control switch S 14 The positive input is connected to the output of the fourth logic unit, and the voltage-controlled switch S 14 The first contact is the output terminal of the eighth voltage-controlled unit and is connected to resistor R. 31 One end is connected to the input terminal of the first addition unit, and the resistor R 31 The other end is grounded, voltage-controlled switch S 14 The second contact and voltage source V 36 The positive terminal is connected, and the voltage source V 36 Negative terminal grounded, voltage-controlled switch S 14 The negative input is grounded. The ninth voltage control unit includes a voltage control switch S. 15 Voltage source V 37 and resistance R 32 Pressure-controlled switch S 15 The positive input is the input terminal of the ninth voltage control unit, and the voltage control switch S 15 The positive input terminal and the AND gate D 24 Connect the output terminal of the voltage-controlled switch S to the voltage control switch. 15 The first contact is the output terminal of the ninth voltage-controlled unit and is connected to resistor R. 32 One end is connected to the input terminal of the first addition unit, and the resistor R 32 The other end is grounded, voltage-controlled switch S 15 The second contact and voltage source V 37 The positive terminal is connected, and the voltage source V 37 Negative terminal grounded, voltage-controlled switch S 15 The negative input is grounded. The tenth voltage control unit includes the voltage control switch S. 16 Voltage source V 38 and resistance R 33 Pressure-controlled switch S 16 The positive input is the input terminal of the tenth voltage control unit and the voltage control switch S 16 Positive input and AND gate D 25 Connect the output terminal of the voltage-controlled switch S to the voltage control switch. 16The first contact is the output terminal of the tenth voltage-controlled unit and is connected to resistor R. 33 One end is connected to the input terminal of the first addition unit, and the resistor R 33 The other end is grounded, voltage-controlled switch S 16 The second contact and voltage source V 38 The positive terminal is connected, and the voltage source V 38 Negative terminal grounded, voltage-controlled switch S 16 The negative input is grounded.

[0064] The second comparator includes operational amplifier OP8 and voltage source V. 34 Voltage source V 34 The positive terminal is connected to the non-inverting input of operational amplifier OP8, and the voltage source V... 34 The negative terminal of the operational amplifier OP8 is grounded. The negative input of OP8 is the input of the second comparator and is connected to the output of the mathematical operation unit ABM1. The output of OP8 is the output of the second comparator and is connected to the AND gate D. 25 It is connected to one of the input terminals.

[0065] The first addition unit includes operational amplifier OP9 and resistor R. 34 -R 40 The non-inverting input of operational amplifier OP9 is connected to resistor R. 34 Resistance R 35 Resistance R 36 Resistance R 37 and resistance R 38 One end is connected to the resistor R. 34 Resistance R 35 Resistance R 36 and resistance R 37 The other end is the input terminal of the first addition unit and is connected to the output terminals of the seventh, eighth, ninth, and tenth voltage control units, respectively. Resistor R 38 The other end is grounded, and the resistor R 38 Its function is to couple to ground; the negative input of operational amplifier OP9 is connected to resistor R. 39 and resistance R 40 One end is connected to the resistor R. 39 The other end is grounded, and the resistor R 40 The other end is connected to the output of operational amplifier OP9, with resistor R 39 and resistance R 40 Its function is to adjust the output ratio. The output terminal of operational amplifier OP9 serves as the output terminal of the first adder unit. The function of the first adder unit is to sum the voltages output by the seventh, eighth, ninth, and tenth voltage control units and apply them to the input terminal of empirical module I.

[0066] like Figure 1 As shown, the prefrontal cortex module II includes a fifth logic unit, a sixth logic unit, and an AND gate D. 29 Fourth comparator, AND gate D 30 The twentieth, twenty-first, twenty-second, and twenty-third voltage control units, the second addition unit, and the fifth logic unit have their input terminals connected to the input signal terminal N1 and the output terminal of the delay module IV. The output terminal of the fifth logic unit is connected to the input terminal of the twentieth voltage control unit and the AND gate D. 29 Connect one input terminal to gate D 29 The other input terminal is connected to the output terminal of AND gate D8 of delay module I. The input terminal of the sixth logic unit is connected to the input signal terminal N1 and the output terminal of delay module IV. The output terminal of the sixth logic unit is connected to the input terminal of the twenty-first voltage control unit. AND gate D... 29 The output terminals are respectively connected to the input terminal of the twenty-second voltage control unit and the AND gate D. 30 The input terminal of the fourth comparator is connected to the input terminal of the first comparator, and the input terminal of the fourth comparator is connected to the output terminal of the mathematical operation unit ABM1 of the synaptic neuron circuit in the memory module. The output terminal of the fourth comparator is connected to the AND gate D. 30 Connect to the other input terminal, and use gate D 30 The output terminal of the second addition unit is connected to the input terminal of the 23rd pressure control unit. The output terminals of the 20th, 21st, 22nd, and 23rd pressure control units are each connected to one input terminal of the second addition unit. The output terminal of the second addition unit is the output terminal of the prefrontal cortex module II and is also connected to the input terminal of the experience module II. The output terminal of the generalization module is connected to the input terminal of the experience module II via resistor R. 58 It is connected to one input terminal of the second addition unit.

[0067] The fifth logic unit includes AND gate D. 26 AND gate D 26 The input terminal is the input terminal of the fifth logic unit and is connected to the input signal terminal N1 and the output terminal of the delay module IV, respectively, and is connected to the gate D. 26 The output terminal is the output terminal of the fifth logic unit and is connected to the input terminal of the twentieth voltage control unit.

[0068] The sixth logic unit includes NOT gate D. 27 AND gate D 28 NOT gate D 27 The input terminals and AND gate D 28 One input terminal is the input terminal of the sixth logic unit, NOT gate D. 27 The input terminal of the NOT gate is connected to the input signal terminal N1. 27 The output terminal and AND gate D28 Connect one input terminal to gate D 28 The other input is ANDed with the delay module IV's gate D. 18 Connect to the output terminal of gate D. 28 The output terminal is the output terminal of the sixth logic unit and is connected to the input terminal of the twenty-first voltage control unit.

[0069] The twentieth pressure control unit includes a pressure control switch S. 17 Voltage source V 40 and resistance R 41 Pressure-controlled switch S 17 The positive input is the input terminal of the twentieth voltage control unit and the voltage control switch S 17 The positive input terminal is connected to the output terminal of the fifth logic unit, and the voltage-controlled switch S 17 The first contact is the output terminal of the twentieth voltage-controlled unit and is connected to resistor R. 41 One end of the resistor R is connected to the input of the second addition unit. 41 The other end is grounded, voltage-controlled switch S 17 The second contact and voltage source V 40 The positive terminal is connected, and the voltage source V 40 Negative terminal grounded, voltage-controlled switch S 17 The negative input is grounded. The twenty-first voltage control unit includes a voltage control switch S. 18 Voltage source V 41 and resistance R 42 Pressure-controlled switch S 18 The positive input is the input terminal of the twenty-first voltage control unit, and the voltage control switch S 18 The positive input is connected to the output of the sixth logic unit, and the voltage-controlled switch S 18 The first contact is the output terminal of the twenty-first voltage-controlled unit and is connected to resistor R. 42 One end of the resistor R is connected to the input of the second addition unit. 42 The other end is grounded, voltage-controlled switch S 18 The second contact and voltage source V 41 The positive terminal is connected, and the voltage source V 41 Negative terminal grounded, voltage-controlled switch S 18 The negative input is grounded. The twenty-second voltage control unit includes a voltage control switch S. 19 Voltage source V 42 and resistance R 43 Pressure-controlled switch S 19 The positive input is the input terminal of the twenty-second voltage control unit, and the voltage control switch S 19 Positive input and AND gate D 29 Connect the output terminal of the voltage-controlled switch S to the voltage control switch. 19The first contact is the output terminal of the twenty-second voltage-controlled unit and is connected to resistor R. 43 One end of the resistor R is connected to the input of the second addition unit. 43 The other end is grounded, voltage-controlled switch S 19 The second contact and voltage source V 42 The positive terminal is connected, and the voltage source V 42 Negative terminal grounded, voltage-controlled switch S 19 The negative input is grounded. The twenty-third voltage control unit includes a voltage control switch S. 20 Voltage source V 43 and resistance R 44 Pressure-controlled switch S 20 The positive input is the input terminal of the twenty-third voltage control unit, and the voltage control switch S 20 Positive input and AND gate D 30 Connect the output terminal of the voltage-controlled switch S to the voltage control switch. 20 The first contact is the output terminal of the twenty-third voltage-controlled unit and is connected to resistor R. 44 One end of the resistor R is connected to the input of the second addition unit. 44 The other end is grounded, voltage-controlled switch S 20 The second contact and voltage source V 43 The positive terminal is connected, and the voltage source V 43 Negative terminal grounded, voltage-controlled switch S 20 The negative input is grounded.

[0070] The fourth comparator includes an operational amplifier (OP). 10 and voltage source V 39 Voltage source V 39 The positive terminal and the operational amplifier OP 10 Connect the non-inverting input terminal to the voltage source V. 39 The negative terminal is grounded, and the operational amplifier OP... 10 The negative input is the input terminal of the fourth comparator and is connected to the output terminal of the mathematical operation unit ABM1. The operational amplifier OP 10 The output terminal is the output terminal of the fourth comparator and is ANDed with gate D. 30 It is connected to one of the input terminals.

[0071] The second addition unit includes an operational amplifier (OP). 11 and resistance R 45 -R 51 Resistance R 58 Operational amplifier (OP) 11 The non-inverting input terminal is connected to resistor R respectively. 45 Resistance R 46 Resistance R 47 Resistance R 48 Resistance R 49Resistance R 58 One end is connected to the resistor R. 45 Resistance R 46 Resistance R 47 Resistance R 48 Resistance R 58 The other end is the input terminal of the second addition unit and is connected to the output terminals of the twentieth, twenty-first, twenty-second, and twenty-third voltage control units and the generalization module, respectively. Resistor R 49 The other end is grounded, operational amplifier OP 11 The negative input is connected to resistor R respectively. 50 and resistance R 51 One end is connected to the resistor R. 50 The other end is grounded, and the resistor R 51 The other end is connected to the operational amplifier OP. 11 Connect the output terminal of the operational amplifier OP to the output terminal. 11 The output terminal is used as the output terminal of the second addition unit. The function of the second addition unit is to sum the voltages output by the twentieth voltage control unit, the twenty-first voltage control unit, the twenty-second voltage control unit, the twenty-third voltage control unit, and the generalization module, and apply the sum to the input terminal of the empirical module II.

[0072] like Figure 5 As shown, the experience module I includes a signal processing module I and an experience storage module I. The input terminal of the signal processing module I is the input terminal of the experience module I, and the input terminal of the signal processing module I is connected to the output terminal of the prefrontal cortex module I. The output terminal of the signal processing module I is connected to the input terminal of the experience storage module I. The output terminal of the experience storage module I is the output terminal of the experience module I, and it outputs an action signal.

[0073] Signal processing module I includes a fourth inverting amplifier circuit and a fifth inverting amplifier circuit. The output of the first addition unit in prefrontal cortex module I is connected to the input of the fourth inverting amplifier circuit. The output of the fourth amplifier circuit is connected to one end of the fifth inverting amplifier circuit. The output of the fifth amplifier circuit is the output of signal processing module I, and the output of the fifth amplifier circuit is connected to the input of experience storage module I.

[0074] Experience storage module I includes a mathematical operation unit ABM2, a third comparator, a sixth inverting amplifier circuit, and an AND gate D. 34The positive terminal of memristor M7 in the sixth inverting amplifier circuit is the input terminal of the experience storage module I. The output terminal of signal processing module I is connected to the positive terminal of memristor M7 and one input terminal of mathematical operation unit ABM2. The negative terminal of memristor M7 is connected to the input terminal of the operational amplifier in the sixth inverting amplifier circuit. The output terminal of the sixth amplifier circuit is connected to the other input terminal of mathematical operation unit ABM2. The output terminal of mathematical operation unit ABM2 is connected to the input terminal of the third comparator. The output terminal of the third comparator and AND gate D... 34 Connect one input terminal to gate D 34 The other input terminal is ANDed with the delay module II's gate D. 11 Connect to the output terminal of gate D. 34 The output terminal is the output terminal of the experience storage module I and ANDed with gate D. 34 Output action signal.

[0075] The fourth inverting amplifier circuit includes an operational amplifier (OP). 13 Resistance R 53 Resistance R 55 And capacitor C1, operational amplifier OP 13 The non-inverting input terminal is grounded, and the operational amplifier OP... 13 The negative input is connected to resistor R respectively. 53 Resistance R 55 Connect one end of capacitor C1, and resistor R 53 The other end is connected to the output of operational amplifier OP9, with resistor R 55 The other end of capacitor C1 is connected to the operational amplifier OP. 13 Connect the output terminal of the operational amplifier OP to the output terminal. 13 The output terminal is connected to the input terminal of the fifth inverting amplifier circuit. The function of the fourth inverting amplifier circuit is to use the charging and discharging of capacitor C1 to prevent the output voltage of the fourth inverting amplifier circuit from jumping.

[0076] The fifth inverting amplifier circuit includes an operational amplifier (OP). 12 Resistance R 52 and resistance R 54 Operational amplifier (OP) 12 The non-inverting input terminal is grounded, and the operational amplifier OP... 12 The negative input is connected to resistor R respectively. 52 and resistance R 54 One end is connected to the resistor R. 52 The other end is connected to the operational amplifier OP. 13 Connect the output terminal of the resistor R to the resistor R. 54 The other end is the output terminal of the fifth proportional amplifier circuit and the resistor R 54 The other end is connected to the operational amplifier OP.12 The output terminal is connected to the circuit. The function of the fifth inverting amplifier circuit is to invert the input voltage and output it.

[0077] The sixth inverting amplifier circuit includes an operational amplifier (OP). 14 Memristor M7 and resistor R 56 Operational amplifier (OP) 14 The non-inverting input terminal is grounded, and the operational amplifier OP... 14 The negative input is connected to the negative terminal of memristor M7 and resistor R, respectively. 56 One end is connected to the resistor R. 56 The other end is connected to the operational amplifier OP. 14 Connect the output terminal of the operational amplifier OP to the output terminal. 14 The output terminal is connected to the other input terminal of the mathematical operation unit ABM2.

[0078] The third comparator includes an operational amplifier (OP). 15 and voltage source V 44 Voltage source V 44 The positive terminal and the operational amplifier OP 15 Connect the non-inverting input terminal to the voltage source V. 44 The negative terminal is grounded, and the operational amplifier OP... 15 The negative input is the input terminal of the third comparator and is connected to the output terminal of the mathematical operation unit ABM2. The operational amplifier OP 15 The output terminal is the output terminal of the third comparator and is ANDed with gate D. 34 Connect to one input terminal of the AND gate D. 34 The other input is ANDed with the gate D of delay module II. 11 Connect to the output terminal.

[0079] The experience module II includes a signal processing module II and an experience storage module II. The input terminal of the signal processing module II is the input terminal of the experience module II and is connected to the output terminal of the prefrontal cortex module II. The output terminal of the signal processing module II is connected to the input terminal of the experience storage module II. The output terminal of the experience storage module II is the output terminal of the experience module II and outputs an action signal.

[0080] Signal processing module II includes an eleventh inverting amplifier circuit, a twelfth inverting amplifier circuit, and the operational amplifier OP of the second adder unit in prefrontal cortex module II. 11 The output terminal is connected to the input terminal of the eleventh proportional amplifier circuit. The output terminal of the eleventh inverting proportional amplifier circuit is connected to the input terminal of the twelfth inverting proportional amplifier circuit. The output terminal of the twelfth inverting proportional amplifier circuit is the output terminal of the signal processing module II, and the output terminal of the twelfth inverting proportional amplifier circuit is connected to the input terminal of the experience storage module II.

[0081] Experience storage module II includes mathematical operation unit ABM3, sixth comparator, thirteenth inverting amplifier circuit and AND gate D. 36 The positive terminal of memristor M8 in the thirteenth inverting amplifier circuit is the input terminal of the empirical storage module II. The output terminal of the signal processing module II is connected to the positive terminal of memristor M8 and one input terminal of the mathematical operation unit ABM3. The negative terminal of memristor M8 is connected to the operational amplifier OP of the thirteenth proportional amplifier circuit. 20 The input terminal of the thirteenth proportional amplifier circuit is connected to another input terminal of the mathematical operation unit ABM3. The output terminal of the mathematical operation unit ABM3 is connected to the input terminal of the sixth comparator. The output terminal of the sixth comparator is connected to the AND gate D. 36 Connect one input terminal to gate D 36 The other input is ANDed with the delay module V's gate D. 20 Connect to the output terminal of gate D. 36 The output terminal is the output terminal of the experience storage module II and is ANDed with gate D. 36 The output action signal is the output signal disconnection N7.

[0082] The eleventh inverting amplifier circuit includes an operational amplifier (OP). 19 Resistance R 60 Resistance R 62 And capacitor C2, operational amplifier OP 19 The non-inverting input terminal is grounded, and the operational amplifier OP... 19 The negative input is connected to resistor R respectively. 60 Resistance R 62 Connect one end of capacitor C2, and resistor R 60 The other end is connected to the operational amplifier OP. 11 Connect the output terminal of the resistor R to the resistor R. 62 The other end of capacitor C2 is connected to the operational amplifier OP. 19 Connect the output terminal of the operational amplifier OP to the output terminal. 19 The output terminal is connected to the input terminal of the twelfth inverting amplifier circuit.

[0083] The twelfth inverting amplifier circuit includes an operational amplifier (OP). 18 Resistance R 59 and resistance R 61 Operational amplifier (OP) 18 The non-inverting input terminal is grounded, and the operational amplifier OP... 18 The negative input is connected to resistor R respectively. 59 Resistance R 61 One end is connected to the resistor R. 59 The other end is connected to the operational amplifier OP. 19Connect the output terminal of the resistor R to the resistor R. 61 The other end is connected to the operational amplifier OP. 18 Connect the output terminal of the operational amplifier OP to the output terminal. 18 The output terminal is connected to the input terminal of the thirteenth inverting amplifier circuit.

[0084] The thirteenth inverting amplifier circuit includes an operational amplifier (OP). 20 Memristor M8 and resistor R 63 Operational amplifier (OP) 20 The non-inverting input terminal is grounded, and the operational amplifier OP... 20 The negative input of is connected to the negative terminal of memristor M8 and resistor R, respectively. 63 One end is connected to the resistor R. 63 The other end is connected to the operational amplifier OP. 20 Connect the output terminal of the operational amplifier OP to the output terminal. 20 The output terminal is connected to the other input terminal of the mathematical operation unit ABM3.

[0085] The sixth comparator includes an operational amplifier (OP). 21 and voltage source V 48 Voltage source V 48 The positive terminal and the operational amplifier OP 21 Connect the non-inverting input terminal to the voltage source V. 48 The negative terminal is grounded, and the operational amplifier OP... 21 The negative input is the input terminal of the sixth comparator and is connected to the output terminal of the mathematical operation unit ABM3. The operational amplifier OP 21 The output terminal is the output terminal of the sixth comparator and is ANDed with gate D. 36 It is connected to one of the input terminals.

[0086] like Figure 6 As shown, the generalization module includes a signal judgment circuit and a voltage control circuit. The input terminal of the signal judgment circuit is the input terminal of the generalization module and is connected to the output terminal of the prefrontal cortex module I. The output terminal of the signal judgment circuit is connected to one input terminal of the voltage control circuit. The input terminal of the voltage control circuit is connected to the output terminal of the delay module IV and the output terminal of the signal judgment circuit, respectively. The output terminal of the voltage control circuit is the output terminal of the generalization module and is connected to one input terminal of the first adder circuit in the prefrontal cortex module II.

[0087] The signal determination circuit includes a fourth comparator, a fifth comparator, and an AND gate D. 33The inputs of the fourth and fifth comparators are the inputs of the signal judgment circuit, and both inputs are connected to the output of operational amplifier OP9 of prefrontal cortex module I. The outputs of the fourth and fifth comparators are respectively connected to AND gate D. 33 The two input terminals are connected to the gate D. 33 The output terminal is the output terminal of the signal judgment circuit.

[0088] The voltage control circuit includes a NOT gate D. 31 Eleventh pressure control unit and AND gate D 32 NOT gate D 31 The input terminals and AND gate D 32 One input terminal is one of the two input terminals of the voltage control circuit, and the NOT gate D 31 The input terminal of the delay module IV is ANDed with the gate D. 18 Connect the output terminal of the NOT gate D to the output terminal. 31 The output terminal and AND gate D 32 The AND gate D of the signal judgment circuit is connected to one of its input terminals. 33 The output terminal and AND gate D 32 Connect to the other input terminal, and use gate D 32 The output terminal of the eleventh voltage control unit is connected to the input terminal of the eleventh voltage control unit, and the output terminal of the eleventh voltage control unit is connected to the resistor R. 58 One end is connected to the resistor R. 58 The other end connects to the operational amplifier OP of the prefrontal cortex module II. 11 The positive input is connected.

[0089] The fourth comparator includes an operational amplifier (OP). 16 and voltage source V 46 Voltage source V 46 The positive terminal of the operational amplifier OP 16 Connect the non-inverting input terminal to the voltage source V. 46 The negative terminal is grounded, and the operational amplifier OP... 16 The negative input is the input terminal of the fourth comparator and is connected to the output terminal of operational amplifier OP9. 16 The output terminal is the output terminal of the fourth comparator and is ANDed with gate D. 33 It is connected to one of the input terminals.

[0090] The fifth comparator includes an operational amplifier (OP). 17 and voltage source V 47 Voltage source V 47 The positive terminal of the operational amplifier OP 16 The negative input is connected to the voltage source V. 47 The negative terminal is grounded, and the operational amplifier OP... 17The negative input is the input terminal of the fifth comparator and is connected to the output terminal of operational amplifier OP9. 16 The output terminal is the output terminal of the fifth comparator and is ANDed with gate D. 33 It is connected to the other input terminal.

[0091] The eleventh pressure control unit includes a pressure control switch S. 21 Voltage source V 45 and resistance R 57 Pressure-controlled switch S 21 The positive input is the input terminal of the eleventh voltage control unit, and the voltage control switch S... 21 The negative input is grounded, and the voltage-controlled switch S 21 The first contact is the output terminal of the voltage control unit and the voltage control switch S 21 The first contact and resistor R 57 One end is connected to the voltage-controlled switch S 21 The second contact and voltage source V 45 Connect the positive terminal to the resistor R. 57 The other end and voltage source V 45 The negative terminals are all grounded.

[0092] Figure 7 This is a simulation result of classical conditioned reflex with time delay, where N1 is the food signal, N2 is the whistle signal, and V... M1 The voltage signal is applied to memristor M1, M1 and M2 represent the resistance changes of memristors M1 and M2, respectively, and N6 is the excitation signal output by the circuit. 0-5s is the testing process; in the initial stage, only the food signal can induce excitation, while the whistle signal cannot. 5-19s is the synchronous learning process, where the food signal and the whistle signal appear simultaneously for a period of time. At voltage V... M1 Under a voltage of 10V, the resistance of memristor M1 gradually decreases, meaning the synaptic weight between the whistle neuron and the excitatory neuron in the synaptic neuron circuit gradually increases. After a period of time, the synaptic weight rises above the threshold, and the whistle signal can then induce excitation. The period from 19-23 seconds is the forgetting process, occurring when a whistle signal is applied alone for a period of time. At a voltage of V... M1 Under a voltage of -5V, the resistance of memristor M1 gradually increases, meaning the synaptic weight between the whistle neuron and the excitatory neuron gradually decreases. After a period of time, the synaptic weight drops below the threshold, and the whistle signal no longer causes excitation. 23-33s is the delayed learning process 1; after the whistle and food signals appear sequentially for a period of time, the whistle signal can cause excitation. 33-37 seconds is the forgetting process; the whistle signal, applied alone for a period of time, no longer causes excitation. 37-49s is the delayed learning process 2; after the whistle and food signals appear with a delay for a period of time, the whistle signal can cause excitation. 49-55s is the forgetting process.

[0093] Figure 8 This is a simulation result of operant conditioning, where N3 is the command signal, N1 is the food signal, N4 is the auxiliary signal, and V... OP9 The voltage applied across memristor M7 represents the change in resistance of memristor M7, and N7 represents the action signal output by the circuit. The learning process lasts 0-37 seconds, with the command signal and auxiliary signal appearing sequentially. Due to uncontrollable factors in actual training, the food reward after the animal completes the prescribed action is often delayed. Therefore, the food signal appears 1 second after the auxiliary signal disappears, and this cycle is repeated for training. In the initial stage, the action signal outputs a low level after the command signal appears. During training, the resistance of memristor M7 changes with voltage V. OP9 Under a voltage of 10V, the synaptic weight gradually decreases, meaning the synaptic weight between the command signal and the action neuron gradually increases. After 22 seconds of learning, the synaptic weight reaches the threshold, and the action signal outputs a high level upon receiving the command signal. Afterward, the auxiliary signal is removed, and the training process continues, allowing the synaptic weight between the command signal and the action neuron to continue increasing. The period from 37-55 seconds is the forgetting process; after the circuit outputs the action signal, no further food signals are input. The resistance of memristor M7 varies with voltage V. OP9 The voltage gradually increases from -5V, meaning the synaptic weight between the command signal and the action neuron gradually decreases. Around 50 seconds later, the synaptic weight drops below the threshold, and after the command signal appears, the action signal remains at a low level.

[0094] Figure 9 This is a simulation result of operant conditioning with short bridging stimuli, where N3 is the command signal, N1 is the food signal, N4 is the auxiliary signal, N2 is the whistle signal, and V... OP9 The voltage applied to memristor M7 is represented by M7 and M1, which represent the resistance changes of memristors M7 and M1, respectively. N6 represents the excitation signal output by the circuit, and N7 represents the action signal output by the circuit. The learning process lasts 0-33 seconds, during which the command signal and auxiliary signal appear sequentially, with the food signal appearing 1 second after the auxiliary signal disappears. A whistle signal with an amplitude of 5V and a width of 0.5s is inserted during the time interval between the food signal and the auxiliary signal. The whistle signal serves as a bridging stimulus, bridging the gap between the action and the food reward, thus promoting the training process. After 18 seconds of learning, the synaptic weight between the command signal and the action neuron reaches the threshold, and the action signal outputs a high level after the command signal appears. The auxiliary signal is then removed, and the training process continues, allowing the synaptic weight between the command signal and the action neuron to continue to increase. Furthermore, the synaptic weight between the whistle signal and the excitation neuron increases slowly during the learning process but never reaches the threshold; the whistle signal never induces excitation. Therefore, during the learning process, the whistle signal does not act as a secondary reinforcer but only as a bridging stimulus. The period from 33 to 51 seconds is the forgetting process; after the circuit issues an action signal, it no longer inputs food signals. The resistance of memristor M7 is related to the voltage V. OP9The voltage gradually increases from -5V, meaning the synaptic weight between the command signal and the action neuron gradually decreases. Around 45 seconds, the synaptic weight drops below the threshold, and after the command signal appears, the action signal remains low.

[0095] Figure 10 This is a simulation result of operant conditioning with long bridging stimuli, where N3 is the command signal I, N1 is the food signal, N4 is the auxiliary signal, N2 is the whistle signal, and V... OP9 The voltage applied to memristor M7 is represented by M7 and M1, which represent the resistance changes of memristors M7 and M1, respectively. N6 represents the excitation signal output by the circuit, and N7 represents the action signal output by the circuit. The learning process lasts 0-29 seconds, during which the command signal and auxiliary signal appear sequentially, and the food signal appears 1 second after the auxiliary signal disappears. A whistle signal with an amplitude of 5V and a width of 1 second is used as a bridging stimulus during the time interval between the food signal and the auxiliary signal. Because the facilitating effect of long bridging stimuli is greater than that of short bridging stimuli, after 14 seconds of learning, the synaptic weight between the command signal I and the action neuron reaches the threshold, and the action signal outputs a high level after the command signal I appears. Afterward, the auxiliary signal is removed, and the training process continues, allowing the synaptic weight between the command signal I and the action neuron to continue to increase. Furthermore, the whistle signal also functions only as a bridging stimulus during this process. The forgetting process lasts 29-47 seconds; after the circuit outputs the action signal, the food signal is no longer input. The resistance of memristor M7 varies with voltage V. OP9 The voltage gradually increases from -5V, meaning the synaptic weight between the command signal and the action neuron gradually decreases. Around 42 seconds, the synaptic weight drops below the threshold, and after the command signal appears, the action signal remains at a low level.

[0096] Figure 11 The simulation results are for an operant conditioning reflex with conditional reinforcement, where N3 is the command signal I, N1 is the food signal, N4 is the auxiliary signal, N2 is the whistle signal, and V... M1 and V OP9 The voltage applied across memristors M1 and M7 represents the resistance changes of memristors M1 and M7. N6 represents the excitation signal output by the circuit, and N7 represents the action signal output by the circuit. The 0-7s period is the pre-training process, during which the food signal and the whistle signal occur simultaneously. The resistance of memristor M1 varies with voltage V. M1The resistance gradually decreases under a voltage of 10V, meaning the synaptic weight between the whistle signal and the excited neuron gradually increases. From 17-19 seconds, the testing process occurs; a single whistle signal is sufficient to induce excitation, indicating a strong connection between the whistle signal and the excited neuron, making the whistle signal a secondary reinforcer. From 19-44 seconds, the learning process of operant conditioning occurs, filling the time interval between the food signal and the auxiliary signal with the whistle signal. During this process, the whistle signal acts as both a bridging stimulus and a secondary reinforcer, promoting the training process. The resistance of memristor M7 varies with voltage V. OP9 The voltage gradually decreases under the influence of 6.8V, meaning the synaptic weight between the command signal I and the action neuron gradually increases. After 10 seconds of learning, the synaptic weight between the command signal I and the action neuron reaches a threshold, and the action signal outputs a high level upon the appearance of the command signal I. Furthermore, during this process, the synaptic weight between the whistle signal and the excitatory neuron also gradually increases; that is, classical and operant conditioning occur simultaneously. From 44 to 62 seconds is the forgetting process; after the circuit outputs the action signal, no more food signals are input. After a period of time, the command signal I no longer triggers an action.

[0097] Figure 12 The results are generalized simulations of operant conditioning, where N3 is command signal I, N5 is command signal II, N1 is the food signal, N4 is the auxiliary signal, N2 is the whistle signal, and V... OP9 and V OP11 The voltage applied across memristors M7 and M8 represents the resistance changes of memristors M7 and M8, and N7 represents the circuit's output action signal. The test process from 0-8s is the initial state test; in the initial state, neither command signal I nor command signal II can trigger an action. The generalization process from 8-45s is the operant conditioning process. Command signal I, auxiliary signal, and food signal appear sequentially, with a whistle signal filling the time interval between the food signal and the auxiliary signal. The resistance of memristor M7 varies with voltage V. OP9 Under the influence of 10V, the synaptic weight gradually decreases, meaning the synaptic weight between command signal I and the action neuron gradually increases. Furthermore, the synaptic weight between command signal II and the action neuron also gradually increases during this process. The testing phase is from 45-54 seconds after training. After training with command signal I, both command signal I and command signal II can trigger the action, marking the end of the generalization process of operant conditioning.

[0098] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An operational conditioned reflex neural network circuit with bridging and conditional reinforcement, characterized in that, The system includes input signal terminals N1-N5, a memory module, delay modules I, II, III, IV, and V, prefrontal cortex modules I and II, experience modules I and II, and a generalization module. Input signal terminal N1, representing a food signal, is connected to the input terminals of the memory module, prefrontal cortex module I, and prefrontal cortex module II, respectively. Input signal terminal N2, representing a whistle signal, is connected to the input terminal of the memory module. Input signal terminal N3, representing command signal I, is connected to the input terminal of delay module II. Input signal terminal N4, representing an auxiliary signal, is connected to the input terminals of delay modules III and IV via logic circuits, respectively. Input signal terminal N5, representing command signal II, is connected to the input terminal of delay module V. The output terminal of the memory module is connected to the input terminals of delay modules I, prefrontal cortex module I, and prefrontal cortex module II, respectively. The output of module I is connected to the inputs of the memory module, prefrontal cortex module I, and prefrontal cortex module II, respectively. The output of delay module II is connected to the inputs of the logic circuit and experience module I, respectively. The output of delay module III is connected to the input of prefrontal cortex module I. The output of delay module IV is connected to the inputs of the generalization module and prefrontal cortex module II, respectively. The output of delay module V is connected to the inputs of the logic circuit and experience module II, respectively. The output of prefrontal cortex module I is connected to the inputs of experience module I and the generalization module, respectively. The output of prefrontal cortex module II is connected to the input of experience module II, and the output of the generalization module is connected to the input of prefrontal cortex module II. The output of the memory module and its input signal terminal N1 are both connected to the input of OR gate D9 through resistor R4. The outputs of experience module I and experience module II are respectively connected to OR gate D9. 35 The two input terminals are connected together, OR gate D 35 The output terminal is connected to the logic circuit; the output of OR gate D9 represents the excitation signal. 35 The output represents the action signal.

2. The operational conditioned reflex neural network circuit with bridging and conditional reinforcement according to claim 1, characterized in that, The memory module includes a first voltage control circuit, a synaptic neuron circuit, a NOT gate D6, an adder SUM1, and a first comparator. The input terminal of the first voltage control circuit is connected to the output terminal, input signal terminal N1, and input signal terminal N2 of the delay module I, respectively. The output terminal of the first voltage control circuit is connected to the positive terminal of the memristor M1 in the synaptic neuron circuit. The output terminal of the synaptic neuron circuit is connected to the input terminals of the prefrontal cortex module I and the prefrontal cortex module II, as well as one input terminal of the adder SUM1, respectively. The input signal terminal N2 is connected to the input terminal of the NOT gate D6. The output terminal of the NOT gate D6 is connected to the other input terminal of the adder SUM1 and the input terminal of the delay module I, respectively. The output terminal of the adder SUM1 is connected to the input terminal of the first comparator. The output terminal of the first comparator is connected to one input terminal of the OR gate D9 and outputs a signal representing the completion of memory.

3. The operational conditioned reflex neural network circuit with bridging and conditional reinforcement according to claim 2, characterized in that, The first voltage control circuit includes a first logic unit, a second logic unit, a first voltage control unit, and a second voltage control unit. The input terminal of the first logic unit is connected to the input signal terminal N1 and the input signal terminal N2, respectively. The output terminal of the first logic unit is connected to the input terminal of the first voltage control unit. The input terminal of the second logic unit is connected to the input signal terminal N1 and the input signal terminal N2, respectively. The output terminal of the second logic unit is connected to the input terminal of the second voltage control unit. The output terminals of the first voltage control unit and the second voltage control unit are the output terminals of the first voltage control circuit, and both the output terminals of the first voltage control unit and the second voltage control unit are connected to the input terminal of the synaptic neuron circuit. The synaptic neuron circuit includes a first inverting amplifier circuit and a mathematical operation unit ABM1. The output terminals of the first voltage control unit and the second voltage control unit of the first voltage control circuit are respectively connected to the positive terminal of the memristor M1 of the first inverting amplifier circuit and one input terminal of the mathematical operation unit ABM1. The negative terminal of the memristor M1 is connected to the input terminal of the operational amplifier of the first inverting amplifier circuit. The output terminal of the first inverting amplifier circuit is connected to the other input terminal of the mathematical operation unit ABM1. The output terminal of the mathematical operation unit ABM1 is the output terminal of the synaptic neuron circuit and is connected to the input terminals of the prefrontal cortex module I and the prefrontal cortex module II, respectively.

4. The operational conditioned reflex neural network circuit with bridging and conditional reinforcement according to claim 3, characterized in that, Delay modules I, II, III, IV, and V each include a first NOT gate, a third voltage-controlled unit, a fourth voltage-controlled unit, a second inverting amplifier circuit, a first NMOS transistor, a first PMOS transistor, and a first AND gate. The input of the first NOT gate is the input of delay modules II, III, IV, and V. The output of the first NOT gate is connected to the input of the third voltage-controlled unit and one input of the first AND gate, respectively. The outputs of the third and fourth voltage-controlled units are both connected to the positive terminal of the first memristor of the second inverting amplifier circuit, and the negative terminal of the first memristor is connected to the input of the operational amplifier of the second inverting amplifier circuit. The output of the second inverting amplifier circuit is connected to the gate of the first NMOS transistor. The source of the first NMOS transistor is connected to the positive terminal of the first voltage source, and the negative terminal of the first voltage source is grounded. The drain of the first NMOS transistor is connected to the gate of the first PMOS transistor and one end of resistor I. The other end of resistor I is connected to the positive terminal of the second voltage source, and the negative terminal of the second voltage source is grounded. The source of the first PMOS transistor is connected to the positive terminal of the third voltage source, and the negative terminal of the third voltage source is grounded. The drain of the first PMOS transistor is connected to one end of resistor II and one input terminal of the first AND gate. The other end of resistor II is connected to the positive terminal of the fourth voltage source, and the negative terminal of the fourth voltage source is grounded.

5. The operational conditioned reflex neural network circuit with bridging and conditional reinforcement according to claim 3 or 4, characterized in that, Both the prefrontal cortex module I and the prefrontal cortex module II include a third logic unit, a fourth logic unit, a second AND gate, a second comparator, a third AND gate, a seventh pressure control unit, an eighth pressure control unit, a ninth pressure control unit, a tenth pressure control unit, and a first addition unit. The input terminal of the third logic unit is connected to the input signal terminal N1 and the output terminal of either delay module III or delay module IV. The output terminal of the third logic unit is connected to the input terminal of the seventh pressure control unit and one input terminal of the second AND gate. The other input terminal of the second AND gate is connected to the output terminal of delay module I. The input terminal of the fourth logic unit is connected to the input signal terminal N1 and the output terminal of either delay module III or delay module IV. The output terminal of the fourth logic unit is connected to the eighth... The input terminals of the pressure control unit are connected together. The output terminal of the second AND gate is connected to the input terminal of the ninth pressure control unit and one input terminal of the third AND gate, respectively. The input terminal of the second comparator is connected to the output terminal of the synaptic neuron circuit in the memory module. The output terminal of the second comparator is connected to the other input terminal of the third AND gate. The output terminal of the third AND gate is connected to the input terminal of the tenth pressure control unit. The output terminals of the seventh, eighth, ninth, and tenth pressure control units are connected to one input terminal of the first addition unit, respectively. The output terminal of the first addition unit is connected to the input terminal of either experience module I or experience module II. The output terminal of the first addition unit of prefrontal cortex module I is also connected to the input terminal of the generalization module.

6. The operational conditioned reflex neural network circuit with bridging and conditional reinforcement according to claim 5, characterized in that, Both experience module I and experience module II include a signal processing module and an experience storage module. The input terminal of the signal processing module is connected to the output terminal of the first addition unit of the prefrontal cortex module I or the prefrontal cortex module II. The output terminal of the signal processing module is connected to the input terminal of the experience storage module. The experience storage module contains a memristor. The output terminal of the experience storage module is connected to an OR gate D. 35 Connect to the input terminal.

7. The operational conditioned reflex neural network circuit with bridging and conditional reinforcement according to claim 6, characterized in that, The signal processing module includes a fourth inverting amplifier circuit and a fifth inverting amplifier circuit. The output terminal of the first addition unit in the prefrontal cortex module I or the prefrontal cortex module II is connected to the input terminal of the fourth inverting amplifier circuit. The output terminal of the fourth inverting amplifier circuit is connected to the input terminal of the fifth inverting amplifier circuit. The output terminal of the fifth inverting amplifier is connected to the input terminal of the experience storage module. The experience storage module includes a first mathematical operation unit, a third comparator, a sixth inverting amplifier circuit, and a fourth AND gate. The output of the signal processing module is connected to the positive terminal of the second memristor of the sixth inverting amplifier circuit and one input of the first mathematical operation unit. The output of the sixth inverting amplifier circuit is connected to the other input of the second mathematical operation unit. The output of the first mathematical operation unit is connected to the input of the third comparator. The output of the third comparator is connected to one input of the fourth AND gate. The other input of the fourth AND gate is connected to the output of delay module II or delay module IV. The output of the fourth AND gate is connected to an OR gate D. 35 Connect to the input terminal.

8. The operational conditioned reflex neural network circuit with bridging and conditional reinforcement according to claim 7, characterized in that, The generalization module includes a signal judgment circuit and a second voltage control circuit. The input terminal of the signal judgment circuit is the input terminal of the generalization module and is connected to the output terminal of the prefrontal cortex module I. The output terminal of the signal judgment circuit is connected to one input terminal of the second voltage control circuit. The input terminal of the second voltage control circuit is connected to the output terminal of the delay module IV and the output terminal of the signal judgment circuit, respectively. The output terminal of the second voltage control circuit is the output terminal of the generalization module and is connected to one input terminal of the first addition unit in the prefrontal cortex module II.

9. The operational conditioned reflex neural network circuit with bridging and conditional reinforcement according to claim 8, characterized in that, The signal determination circuit includes a fourth comparator, a fifth comparator, and an AND gate D. 33 The inputs of the fourth and fifth comparators are the inputs of the signal judgment circuit, and both inputs are connected to the output of the first addition unit of the prefrontal cortex module I. The outputs of the fourth and fifth comparators are respectively connected to AND gate D. 33 The two input terminals are connected to the gate D. 33 The output terminal is the output terminal of the signal judgment circuit and is ANDed with gate D. 33 The output terminal is connected to the input terminal of the second voltage control circuit; The second voltage control circuit includes a NOT gate D. 31 Eleventh pressure control unit and AND gate D 32 NOT gate D 31 The input terminal of the NOT gate is connected to the output terminal of the delay module IV. 31 The output terminal and AND gate D 32 The input terminal is connected to the output terminal of the signal judgment circuit and the AND gate D. 32 Connect to the other input terminal of gate D 32 The output terminal is connected to the input terminal of the eleventh pressure control unit, and the output terminal of the eleventh pressure control unit is connected to one input terminal of the first addition operation unit of the prefrontal cortex module II.

10. The operational conditioned reflex neural network circuit with bridging and conditional reinforcement according to claim 9, characterized in that, The logic circuit includes an OR gate D. 13 Input signal terminal N4 and OR gate D 35 The outputs of the two gates are respectively connected to the OR gate D. 13 The two input terminals are connected together, OR gate D 13 The outputs are respectively connected to the AND gate D 12 AND gate D 16 Connect one input terminal to gate D 12 The other input terminal is connected to the output terminal of delay module II, and is connected to gate D. 12 The output terminal is connected to the input terminal of delay module III, and is connected to gate D. 16 The other input terminal is connected to the output terminal of delay module V, and is connected to gate D. 12 The output terminal is connected to the input terminal of delay module IV; The first logic unit includes AND gate D1, AND gate D2 and OR gate D3. The input terminal of AND gate D1 is connected to input signal terminal N1 and input signal terminal N2 respectively. The output terminal of AND gate D1 is connected to one input terminal of OR gate D3. The input terminal of AND gate D2 is connected to input signal terminal N1 and output terminal of delay module I respectively. The output terminal of AND gate D2 is connected to the other input terminal of OR gate D3. The output terminal of OR gate D3 is connected to the input terminal of the first voltage control unit. The second logic unit includes a NOT gate D4 and an AND gate D5. The input terminal of the NOT gate D4 is connected to the input signal terminal N1, the output terminal of the NOT gate D4 is connected to one input terminal of the AND gate D5, the input signal terminal N2 is connected to the other input terminal of the AND gate D5, and the output terminal of the AND gate D5 is connected to the input terminal of the second voltage control unit. The third logic unit includes a fifth AND gate, one input of which is connected to the input signal terminal N1, the other input of which is connected to the output of delay module III or delay module IV, and the output of which is connected to the input of the fifth voltage control unit. The fourth logic unit includes a second NOT gate and a sixth AND gate. The input terminal of the second NOT gate is connected to the input signal terminal N1, the output terminal of the second NOT gate is connected to one input terminal of the sixth AND gate, the other input terminal of the sixth AND gate is connected to the output terminal of delay module III or delay module IV, and the output terminal of the sixth AND gate is connected to the input terminal of the sixth voltage control unit. The first, second, and sixth inverting amplifier circuits each include a first operational amplifier, a memristor, and a first resistor. The non-inverting input of the first operational amplifier is grounded, and the inverting input of the first operational amplifier is connected to the negative terminal of the memristor and one end of the first resistor, respectively. The positive terminal of the memristor is the input terminal of the first, second, and sixth inverting amplifier circuits. The other end of the first resistor is connected to the output terminal of the first operational amplifier, and the output terminal of the first operational amplifier is the output terminal of the first, second, and sixth inverting amplifier circuits. The fourth inverting amplifier circuit includes a second operational amplifier, a second resistor, and a first capacitor. The non-inverting input of the second operational amplifier is grounded, and the inverting input of the second operational amplifier is connected to one end of the second resistor, resistor III, and the first capacitor, respectively. The other end of resistor III is the input of the fourth inverting amplifier circuit and is connected to the output of the prefrontal cortex module I. The other ends of the second resistor and the first capacitor are both connected to the output of the second operational amplifier. The output of the second operational amplifier is connected to the input of the fifth inverting amplifier circuit. The fifth inverting amplifier circuit includes operational amplifier I, with its non-inverting input terminal grounded. The inverting input terminal of operational amplifier II is connected to one end of resistor IV and resistor V, respectively. The other end of resistor IV is connected to the output terminal of the second operational amplifier, and the other end of resistor V is connected to the output terminal of operational amplifier I. The output terminal of operational amplifier I is connected to the input terminal of the sixth inverting amplifier circuit and one input terminal of the first mathematical operation unit, respectively. The first addition unit includes a third operational amplifier, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor. One end of the third, fourth, fifth, and sixth resistors is the input terminal of the first addition unit. The other ends of the third, fourth, fifth, and sixth resistors are respectively connected to the non-inverting input terminal of the third operational amplifier and one end of the seventh resistor. The other end of the seventh resistor is grounded. The inverting input terminal of the third operational amplifier is respectively connected to one end of the eighth and ninth resistors. The other end of the eighth resistor is grounded. The other end of the ninth resistor is connected to the output terminal of the third operational amplifier. The output terminal of the third operational amplifier is connected to the input terminal of the first addition unit. The first, second, third, fourth, fifth, sixth, seventh, and eighth voltage control units each include a voltage control switch, a voltage source I, and a tenth resistor. The positive input of the voltage control switch is the input terminal of each voltage control unit, and the negative input of the voltage control switch is grounded. The first contact of the voltage control switch is the output terminal of the voltage control unit and is connected to one end of the tenth resistor. The second contact of the voltage control switch is connected to the positive terminal of the voltage source I, and the other end of the tenth resistor and the negative terminal of the voltage source I are both grounded. The first comparator, the second comparator, the third comparator, and the fourth comparator each include a fourth operational amplifier and a voltage source II. The positive terminal of the voltage source II is connected to the non-inverting input terminal of the fourth operational amplifier, and the negative terminal of the voltage source II is grounded. The inverting input terminal of the fourth operational amplifier is the input terminal of the first comparator, the second comparator, the third comparator, and the fourth comparator. The output terminal of the fourth operational amplifier is the output terminal of the first comparator, the second comparator, the third comparator, and the fourth comparator. The fifth comparator includes a fifth operational amplifier and a voltage source III. The non-inverting input of the fifth operational amplifier is the input of the fifth comparator, the inverting input of the fifth operational amplifier is connected to the positive terminal of the voltage source III, the negative terminal of the voltage source III is grounded, and the output of the fifth operational amplifier is the output of the fifth comparator.

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