Storage devices including error correction devices

Abstract

A storage device includes: a plurality of first cell blocks configured to store first data; a second cell block configured to store second data; a third cell block configured to store third data; a repair information storage circuit configured to output a repair usage signal corresponding to an input address based on repair information stored therein; and an error correction circuit configured to receive second data from the second cell block as a first error correction code when selectively receiving the third data as a second error correction code from the third cell block according to the repair usage signal, and to correct errors in the first data from the first cell block using the first error correction code and the second error correction code.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2022-0116842, filed on September 16, 2022, the entirety of which is incorporated herein by reference. Technical Field

[0003] Various embodiments of the present invention relate to semiconductor design technology, and more specifically to memory devices comprising memory cell arrays including redundant cell blocks and error correction code (ECC) cell blocks. Background Technology

[0004] In the early stages of the semiconductor memory industry, memory chips were manufactured using semiconductor fabrication processes to produce defect-free memory cells. However, as the capacity of memory devices increased, manufacturing memory devices with defect-free memory cells became difficult. Currently, it is virtually impossible to manufacture a memory device with no defective memory cells. To address this issue, repair methods that use redundant memory cells to replace defective memory cells, or error correction methods that use error correction circuits to correct errors in memory devices, are being used. Summary of the Invention

[0005] Embodiments of the present invention relate to a storage device capable of efficiently utilizing redundant resources.

[0006] According to an embodiment of the present invention, a storage device includes: a plurality of first unit blocks configured to store first data; a second unit block configured to store second data; a third unit block configured to store third data; a repair information storage circuit configured to output a repair usage signal corresponding to an input address based on repair information stored therein; and an error correction circuit configured to receive second data from the second unit block as a first error correction code when selectively receiving third data from the third unit block as a second error correction code according to the repair usage signal, and to correct errors in the first data from the first unit block using the first error correction code and the second error correction code.

[0007] According to an embodiment of the present invention, a storage device includes: a storage cell array including a plurality of normal cell blocks, error correction code (ECC) cell blocks, and redundant cell blocks; and an error correction circuit configured to: selectively receive data from the ECC cell blocks as a first error correction code when receiving data as a second error correction code from the redundant cell blocks according to a repair use signal indicating whether a cell of the redundant cell block is used in a repair operation, and using the first error correction code and the second error correction code to correct errors in the data read from the normal cell blocks.

[0008] According to an embodiment of the present invention, an error correction circuit includes: an error correction code generation circuit configured to: generate a first preliminary error correction code and a second preliminary error correction code using low data and high data in input data, respectively; and provide the first preliminary error correction code and the second preliminary error correction code to a first unit block and a second unit block respectively, or provide a comparison result between the first preliminary error correction code and the second preliminary error correction code to the first unit block according to a repair use signal; and an error correction circuit configured to: receive data read from a first unit block as a first error correction code when selectively receiving data read from a second unit block as a second error correction code according to a repair use signal; and use the first error correction code and the second error correction code to correct errors in data read from a third unit block.

[0009] According to an embodiment of the present invention, a storage device includes: a group of cell blocks configured to store data of a predetermined size and a first error correction code (ECC); a redundant cell block configured to replace a defective cell block in the group when a control signal hold is enabled, the group and the redundant cell block sharing a word line; an ECC encoding / decoding circuit configured to: generate a first ECC for data to correct errors by the first ECC when the control signal hold is enabled, and generate a first ECC for a portion of the data and a second ECC for another portion of the data to correct errors by the first ECC and the second ECC when the control signal hold is disabled; and a control circuit configured to control the redundant cell block to store the second ECC when the control signal hold is disabled.

[0010] According to embodiments of the present invention, storage devices can maximize error correction capabilities without increasing area by using unused redundant resources as error correction resources. Attached Figure Description

[0011] Figure 1 This is a block diagram illustrating a storage device according to an embodiment of the present invention.

[0012] Figure 2 This is a diagram showing in more detail the configuration of a storage device according to an embodiment of the present invention.

[0013] Figure 3 This illustrates an embodiment of the present invention. Figure 1 The circuit diagram of the repair information storage circuit.

[0014] Figure 4 This illustrates an embodiment of the present invention. Figure 1 Block diagram of the error correction device.

[0015] Figures 5A to 5D This illustrates an embodiment of the present invention. Figure 4 A diagram of the verification matrix of the error correction device.

[0016] Figure 6 This is according to an embodiment of the present invention. Figure 4 Detailed block diagram of the error correction code generation circuit.

[0017] Figure 7 This is according to an embodiment of the present invention. Figure 4 Detailed block diagram of the error correction circuit.

[0018] Figure 8 This is according to an embodiment of the present invention. Figure 7 The circuit diagram of the error corrector.

[0019] Figure 9A and Figure 9B This is a diagram illustrating the operation of a storage device according to an embodiment of the present invention.

[0020] Figure 10A and Figure 10B This is a diagram illustrating the operation of a storage device according to an embodiment of the present invention.

[0021] Figure 11 This is a diagram showing in more detail the configuration of a storage device according to another embodiment of the invention. Detailed Implementation

[0022] Various embodiments of the invention will be described in more detail below with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and to fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in all the different drawings and embodiments of the invention.

[0023] It will be understood that when an element is referred to as being “coupled” or “connected” to another element, it means that the two are directly coupled or that the two are electrically connected to each other with another circuitry between them. It should also be understood that when the terms “comprising,” “including,” and “having,” etc., are used in this specification, they specify the presence of the declared features, numbers, steps, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or combinations thereof. In this disclosure, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise.

[0024] Figure 1 This is a block diagram illustrating a storage device 100 according to an embodiment of the present invention.

[0025] refer to Figure 1The storage device 100 may include a storage cell array 110, a row control circuit 120, a column control circuit 130, a repair control circuit 140, a repair information storage circuit 142, an error correction device 150, a data input / output (I / O) circuit 160, a command input circuit 172, an address input circuit 174, and a command decoder 176.

[0026] From an external device (e.g., a memory controller), command input circuit 172 can receive command CMD, and address input circuit 174 can receive address ADD. Address input circuit 174 can receive address ADD and output row address RADD and column address CADD. Each of command CMD and address ADD may include a multi-bit signal. Command decoder 176 can decode the command CMD input through command input circuit 172 and can generate activation command ACT, precharge command PCG, read command RD, and write command WT, etc. By decoding the received command CMD, command decoder 176 can generate refresh command, mode register command, and other commands.

[0027] The memory cell array 110 may include multiple memory cells MC coupled to multiple word lines WL and multiple bit lines. The memory cell array 110 may include multiple memory banks. The number of memory banks or the number of memory cells MC can be determined according to the capacity of the memory device 100.

[0028] The memory cell array 110 can be coupled to the row control circuit 120 via multiple word lines WL, and to the column control circuit 130 via multiple bit lines BL. The memory cell array 110 may include multiple cell blocks. In one embodiment of the invention, the multiple cell blocks may include multiple normal cell blocks (…). Figure 2 MB0 to MB15), and at least one error-correcting code (ECC) unit block ( Figure 2 MBECC) and at least one redundant unit block ( Figure 2 MBRED).

[0029] The row control circuit 120 can activate the word line WL corresponding to the row address RADD according to the activation command ACT, and can precharge the activated word line WL according to the precharge command PCG.

[0030] The column control circuit 130 can select some bit lines from the bit lines BL according to the column address CADD. For reference, a predetermined number of bit lines BL can be coupled to a column select line. Figure 2The column control circuit 130 can select at least one column select line (CSL) from a plurality of column select lines based on the column address (CADD). Because the bit lines are selected by the column control circuit 130, data D0 to D127 and error correction codes P0 to P15 can be read from or written to the memory cell array 110.

[0031] The repair information storage circuit 142 can store the addresses of defective cells in normal cell blocks MB0 to MB15 and ECC cell blocks MBECC as repair information R_INF. In this disclosure, the address indicating a defective cell can be referred to as a defective address. The repair information storage circuit 142 can provide multiple block repair signals C_REP# and repair use signals RED_USED corresponding to the column address CADD based on the stored repair information R_INF. The multiple block repair signals C_REP# are signals provided to control the repair operation and can be provided in a number corresponding to the number of normal cell blocks MB0 to MB15 and ECC cell blocks MBECC (i.e., # = 17). The repair use signal RED_USED can be a signal indicating whether a cell in the redundant cell block MBRED specified by the column address CADD is used in the repair operation. Detailed configuration of the repair information storage circuit 142 will be referenced. Figure 3 To describe.

[0032] Based on the block repair signal C_REP# and the repair use signal RED_USED, the repair control circuit 140 can transmit data D0 to D127 and error correction codes P0 to P15 between the column control circuit 130 and the error correction device 150, while selectively switching the data lines for transmitting data D0 to D127 and error correction codes P0 to P15.

[0033] During a write operation, the error correction device 150 can generate error correction codes P0 to P15 using 128 bits of data DO0 to DO127 provided from the data I / O circuit 160 via data pads DQ0 to DQ7. Furthermore, during a read operation, the error correction device 150 can correct errors in the data D0 to D127 provided from the memory cell array 110 using the error correction codes P0 to P15 provided from the memory cell array 110 via the repair control circuit 140. The erroneously corrected data DO0 to DO127 can be output to the outside via the data I / O circuit 160 through data pads DQ0 to DQ7. In one embodiment of the invention, the error correction device 150 can adjust its error correction capability by adjusting the size of the error correction codes P0 to P15 according to the repair use signal RED_USED. In the following description, the error correction codes P0 to P7 of the low-bit group are defined as first error correction codes, and the error correction codes P8 to P15 of the high-bit group are defined as second error correction codes. Detailed configuration of the error correction device 150 will be provided in the reference section. Figures 4 to 8 To describe.

[0034] Data I / O circuit 160 can input / output data DO0 to DO127 via data pads DQ0 to DQ7. During a write operation, data can be input in units of 16 bits through one data pad, and during a read operation, data can be output in units of 16 bits through one data pad. When all eight data pads DQ0 to DQ7 are configured in the storage device 100, 128 bits of data DO0 to DO127 can be input to the storage device 100 during a write operation, and 128 bits of data DO0 to DO127 can be output from the storage device 100 during a read operation.

[0035] Figure 2 This is a diagram showing in more detail the configuration of a storage device 100 according to an embodiment of the present invention.

[0036] refer to Figure 2 The memory cell array 110 may include multiple cell blocks MB0 to MB15, MBECC, and MBRED. Each of the cell blocks MB0 to MB15, MBECC, and MBRED may include multiple memory cells MC arranged in a matrix between multiple word lines WL and multiple bit lines BL. In one embodiment of the invention, a "cell block" may be defined as a collection of memory cells that share word lines WL and bit lines BL and are arranged in the same manner.

[0037] Cell blocks MB0 to MB15, MBECC, and MBRED may include first normal cell blocks MB0 to sixteenth normal cell blocks MBR15, ECC cell block MBECC, and redundant cell block MBRED. First normal cell blocks MB0 to sixteenth normal cell blocks MB15 may store data D0 to D127 received from an external device via data I / O circuitry 160. First normal cell blocks MB0 to sixteenth normal cell blocks MB15 may be areas for storing user data and are memory blocks used to determine the storage capacity of storage device 100. ECC cell block MBECC may store first error correction codes P0 to P7 generated by error correction device 150 for error correction operations. Redundant cell block MBRED may be provided for repair operations of first normal cell blocks MB0 to sixteenth normal cell blocks MB15 and ECC cell block MBECC, and may include multiple redundant cells (e.g., multiple redundant bit lines) to replace defective cells (e.g., multiple defective bit lines) in first normal cell blocks MB0 to sixteenth normal cell blocks MB15 and ECC cell block MBECC. In one embodiment of the present invention, when the redundant cell block MBRED is not used in the repair operation, the repair use signal RED_USED is deactivated, so the redundant cell block MBRED can store the second error correction codes P8 to P15 generated from the error correction device 150 for the error correction operation. The first error correction codes P0 to P7 and the second error correction codes P8 to P15 may include known parity bits.

[0038] exist Figure 2 In the diagram, one ECC cell block MBECC and one redundant cell block MBRED are shown, but the invention is not limited thereto, and one or more ECC cell blocks MBECC and redundant cell blocks MBRED can be configured. Normal cell blocks MB0 to MB15 can be divided into first normal cell blocks MB0 to eighth normal cell blocks MB7 corresponding to the high group and ninth normal cell blocks MB8 to sixteenth normal cell blocks MB15 corresponding to the low group. In this case, the first normal cell blocks MB0 to eighth normal cell blocks MB7, the ECC cell block MBECC, the ninth normal cell blocks MB8 to sixteenth normal cell blocks MB15, and the redundant cell block MBRED can be arranged sequentially along the row direction.

[0039] The column control circuit 130 may include a column decoder 132 and column switches CSW0 through CSW17. The column decoder 132 can decode the column address CADD to generate a column selection signal YI. The column switches CSW0 through CSW17 may correspond to the first normal cell blocks MB0 through the eighth normal cell block MB7, the ECC cell block MBECC, the ninth normal cell block MB8 through the sixteenth normal cell block MB15, and the redundant cell block MBRED, respectively. Each of the column switches CSW0 through CSW17 can select one of the column selection lines CSL of the corresponding cell block according to the column selection signal YI. When one of the column selection lines CSL is selected, a predetermined number (e.g., 8) bit lines can be selected. According to an embodiment, the column control circuit 130 may further include a sense amplifier circuit that senses and amplifies the data of the selected column selection line according to a read command RD; and a write driver that writes data to the memory cell array 110 through the selected column selection line according to a write command WT.

[0040] The repair control circuit 140 may include a first path selector 1401 to a seventeenth path selector 1417 corresponding to the first normal cell blocks MB0 to the eighth normal cell blocks MB7, the ECC cell block MBECC, and the ninth normal cell blocks MB8 to the sixteenth normal cell blocks MB15, respectively. The first path selector 1401 to the seventeenth path selector 1417 may, in response to the first repair signal C_REP0 to the seventeenth repair signal C_REP16, transmit data D0 to D127 and the first error correction codes P0 to P7 between the corresponding cell block and one of the adjacent cell blocks in the row direction.

[0041] For example, during a read operation, the first path selector 1401 can transmit data D0 to D7 output from the first normal cell block MB0 to the error correction device 150 when the first repair signal C_REP0 is deactivated to a logic low level, and can transmit data D0 to D7 output from the second normal cell block MB1 to the error correction device 150 when the first repair signal C_REP0 is activated to a logic high level. During a write operation, the first path selector 1401 can transmit data D0 to D7 provided by the error correction device 150 to the first normal cell block MB0 when the first repair signal C_REP0 is deactivated, and can transmit data D0 to D7 from the error correction device 150 to the second normal cell block MB1 when the first repair signal C_REP0 is activated.

[0042] For example, during a read operation, the ninth path selector 1409 can transmit the first error correction codes P0 to P7 output from the ECC cell block MBECC to the error correction device 150 when the ninth repair signal C_REP8 is deactivated to a logic low level, and can transmit the first error correction codes P0 to P7 output from the ninth normal cell block MB8 to the error correction device 150 when the ninth repair signal C_REP8 is activated to a logic high level. During a write operation, the ninth path selector 1409 can transmit the first error correction codes P0 to P7 provided by the error correction device 150 to the ECC cell block MBECC when the ninth repair signal C_REP8 is deactivated, and can transmit data D0 to D7 from the error correction device 150 to the ninth normal cell block MB8 when the ninth repair signal C_REP8 is activated.

[0043] For example, during a read operation, the seventeenth path selector 1417 can transmit data D119 to D127 from the sixteenth normal cell block MB15 to the error correction device 150 when the seventeenth block repair signal C_REP16 is deactivated to a logic low level, and can transmit data D119 to D127 from the redundant cell block MBRED to the error correction device 150 when the seventeenth block repair signal C_REP16 is activated to a logic high level. During a write operation, the seventeenth path selector 1417 can transmit data D119 to D127 provided by the error correction device 150 to the sixteenth normal cell block MB15 when the seventeenth block repair signal C_REP16 is deactivated, and can transmit data D119 to D127 from the error correction device 150 to the redundant cell block MBRED when the seventeenth block repair signal C_REP16 is activated.

[0044] The repair control circuit 140 may further include a path blocking switch 1418 for transmitting second error correction codes P8 to P15 between the redundant cell block MBRED and the error correction device 150 in response to the repair use signal RED_USED. When the repair use signal RED_USED is activated to a logic high level, the path blocking switch 1418 can be turned off to block the transmission of the second error correction codes P8 to P15 between the redundant cell block MBRED and the error correction device 150. On the other hand, when the repair use signal RED_USED is deactivated to a logic low level, the path blocking switch 1418 can be turned on to transmit the second error correction codes P8 to P15 between the redundant cell block MBRED and the error correction device 150.

[0045] The data I / O circuit 160 may include: first input / output (I / O) units 161 to eighth input / output (I / O) units 168, which correspond to data pads DQ0 to DQ7 and are used to input / output 128-bit data DO0 to DO127 through data pads DQ0 to DQ7. Each of the first I / O units 161 to the eighth I / O units 168 can receive 16-bit data through the corresponding data pad during a write operation and output 16-bit data through the corresponding data pad during a read operation.

[0046] When the repair use signal RED_USED is activated, the error correction device 150 can generate 8-bit first error correction codes P0 to P7 using 128-bit data DO0 to DO127 during a write operation, and correct data D0 to D127 based on the 8-bit first error correction codes P0 to P7 during a read operation. On the other hand, when the repair use signal RED_USED is deactivated, the error correction device 150 can generate 16-bit first error correction codes P0 to P7 and second error correction codes P8 to P15 using 128-bit data DO0 to DO127 during a write operation, and correct data D0 to D127 based on the 16-bit first error correction codes P0 to P7 and second error correction codes P8 to P15 during a read operation.

[0047] As described above, according to one embodiment of the present invention, when the redundant cell block MBRED is not used for repair operations, the size of the error correction code used for error correction operations can be increased by using the redundant cell block MBRED to store the additional error correction code. Therefore, the error correction capability can be maximized without an additional increase in area.

[0048] Figure 3 This illustrates an embodiment of the present invention. Figure 1 The circuit diagram of the repair information storage circuit 142.

[0049] refer to Figure 3 The repair information storage circuit 142 may include a first address storage circuit 210_0 to a seventeenth address storage circuit 210_16 and a signal generator 230.

[0050] The first address storage circuits 210_1 to the seventeenth address storage circuits 210_16 can correspond to the first normal cell block MB0 to the eighth normal cell block MB7, the ECC cell block MBECC, and the ninth normal cell block MB8 to the sixteenth normal cell block MB15, respectively. Each of the first address storage circuits 210_1 to the seventeenth address storage circuits 210_16 can store at least one defective address of the corresponding cell block. The first address storage circuits 210_1 to the seventeenth address storage circuits 210_16 can generate a first matching signal M0 to a seventeenth matching signal M16 by comparing the column address CADD with the stored defective address. The first address storage circuits 210_1 to the seventeenth address storage circuits 210_16 can activate the corresponding matching signal to a logic high level when the column address CADD matches the stored defective address.

[0051] Signal generator 230 can generate first repair signals C_REP0 to seventeenth repair signals C_REP16 corresponding to the first matching signal M0 to the seventeenth matching signal M16. When the first matching signal M0 is activated, signal generator 230 activates the first repair signals C_REP0 to seventeenth repair signals C_REP16 to a logic high level. When the second matching signal M1 is activated, signal generator 230 activates the second repair signals C_REP1 to seventeenth repair signals C_REP16 to a logic high level. In this way, signal generator 230 activates the kth repair signals C_REP(k-1) to seventeenth repair signals C_REP16 to a logic high level when the kth matching signal M(k-1) is activated.

[0052] Specifically, the signal generator 230 may include first OR gates 230_1 to sixteenth OR gates 230_16. The signal generator 230 may output a first matching signal M0 as a first block repair signal C_REP0, and the first OR gate 230_1 may perform a logical OR operation on the second matching signal M1 and the first block repair signal C_REP0 to output a second block repair signal C_REP1. The seventh OR gate 230_7 may perform a logical OR operation on the eighth matching signal M7 and the seventh block repair signal C_REP6 to output an eighth block repair signal C_REP7. That is, the first OR gates 230_1 to sixteenth OR gates 230_16 may perform a logical OR operation on the corresponding matching signal and the block repair signal at the previous stage to output the corresponding block repair signal.

[0053] Furthermore, when any one of the first matching signal M0 to the seventeenth matching signal M16 is activated, the signal generator 230 can activate the repair use signal RED_USED to notify that the redundant unit block MBRED has been used for repair operations. For example, the signal generator 230 can output the seventeenth block repair signal C_REP16 as the repair use signal RED_USED.

[0054] Figure 4 This illustrates an embodiment of the present invention. Figure 1 Block diagram of the error correction device 150.

[0055] refer to Figure 4 The error correction device 150 may include an error correction code generation circuit 152 and an error correction circuit 154.

[0056] During a write operation in which the write command WT is input, the error correction code generation circuit 152 can generate either an 8-bit first error correction code P0 to P7 or a 16-bit first error correction code P0 to P7 and a second error correction code P8 to P15 using 128-bit data DO0 to DO127, based on the repair use signal RED_USED. Because error correction codes P0 to P15 are generated by the error correction code generation circuit 152 during the write operation without requiring the execution of an error correction circuit, the data DO0 to DO127 input to the error correction code generation circuit 152 is identical to the data D0 to D127 output from the error correction code generation circuit 152. Detailed configuration of the error correction code generation circuit 152 will be provided in [reference needed]. Figure 6 Detailed description.

[0057] During a read operation where the read command RD is input, the error correction circuit 154 can correct errors in data D0 to D127 using either 8-bit first error correction codes P0 to P7 or 16-bit first error correction codes P0 to P7 and second error correction codes P8 to P15, based on the repair use signal RED_USED. Here, error correction can mean detecting errors in data D0 to D127 using first error correction codes P0 to P7 and second error correction codes P8 to P15, and correcting the errors when they are detected. The data D0 to D127, whose errors have been corrected by the error correction circuit 154, can be output to the outside via data pads DQ0 to DQ7 through the data I / O circuit 160. Detailed configuration of the error correction circuit 154 will be referenced in [reference needed]. Figure 7 and Figure 8 Detailed description.

[0058] Error correction code generation circuit 152 and error correction circuit 154 can use a parity check matrix, also referred to as the H matrix, which will be described below, to generate error correction codes.

[0059] Figures 5A to 5D This illustrates an embodiment of the present invention. Figure 4A diagram of the parity-check matrix used in the error correction code generation circuit 152 and the error correction circuit 154 is shown. Here, for ease of description, 8-bit data D0 to D7 and 4-bit error correction codes E0 to E3 are used.

[0060] refer to Figure 5A The parity-check matrix can be formed by (the number of bits in the error-correcting code) x (the number of bits in the error-correcting code + the number of bits in the data). Here, since the error-correcting code is formed by 4 bits and the data is formed by 8 bits, the parity-check matrix can be a 4 x 12 matrix. Each element of the parity-check matrix can have a value of 1 or 0.

[0061] The column vectors of the parity-check matrix can correspond to the bits of data D0 to D7 and the bits of error correction code E0 to E3, respectively. For example, in 12 column vectors, 8 column vectors can correspond to the bits of data D0 to D7, and 4 column vectors can correspond to the bits of error correction code E0 to E3. Figure 5A In the diagram, we can see that 'D1' corresponds to the column vector with the value '1101', and 'E2' corresponds to the column vector with the value '0010'.

[0062] refer to Figure 5B This illustrates how the error correction code generation circuit 152 or the error correction circuit 154 uses the parity check matrix. The error correction code generation circuit 152 or the error correction circuit 154 can generate error correction codes E0 to E3 in such a manner that each column vector of the parity check matrix is ​​multiplied by the corresponding bits of the data and the error correction code, and then the sum of each row is made 0 (which is an even number). That is, error correction codes E0 to E3 can be generated to satisfy... Figure 5B All four equations shown.

[0063] refer to Figure 5C The error correction code generation circuit 152 is shown using... Figure 5A The parity-check matrix generates error correction codes E0 to E3 (0,1,1,0) for the data D0 to D7 (1,1,0,0,1,0,1,0). When the data D0 to D7 (1,1,0,0,1,0,1,0) and the error correction codes E0 to E3 (0,1,1,0) are substituted into the four equations above, it can be seen that the sum of each row is 0 (i.e., even) and satisfies these four equations, as shown below. Figure 5C As shown.

[0064] During the process of correcting errors in data D0 to D7 and error correction codes E0–E3 using error correction circuit 154, it is also possible to use Figure 5B The four equations in the equations. If the sum of each row calculated by the four equations is 0 (i.e., even), it indicates that there is no error; if it is not 0, it indicates that there is an error at the position indicated by the result.

[0065] refer to Figure 5D This illustrates the process by which the error correction circuit 154 corrects errors based on error correction codes. Figure 5D An error occurred, where bit D6 in data D0 to D7 (1,1,0,0,1,0,1,0) was changed from 1 to 0 (1→0), making data D0 to D7 (1,1,0,0,1,0,0,0).

[0066] Figure 5D The result shown is obtained by substituting the data D0 to D7 (1,1,0,0,1,0,0,0) and the error correction codes E0 to E3 (0,1,1,0) into the parity check matrix and calculating four equations. The result "1,0,0,1" indicates the location of the error. Because the column vectors in the parity check matrix with values ​​of "1,0,0,1" correspond to bit D6, the error correction circuit 154 can determine that bit D6 is erroneous and invert bit D6 to 0→1 to correct the error. That is, the error can be correctly corrected.

[0067] Figure 6 This is according to an embodiment of the present invention. Figure 4 Detailed block diagram of the error correction code generation circuit 152.

[0068] refer to Figure 6 The error correction code generation circuit 152 may include a first parity check matrix calculation circuit 310, a second parity check matrix calculation circuit 320, an encoding selector 330, and a logic gate 340.

[0069] In response to the write command WT, the first parity check matrix calculation circuit 310 can receive 64 bits of low data DO0 to DO63 from the 128-bit data DO0 to DO127 provided by the data I / O circuit 160. The first parity check matrix calculation circuit 310 can use the 64 bits of low data DO0 to DO63 to generate 8 bits of first preliminary error correction codes E0 to E7. In this case, the low data DO0 to DO63 input to the first parity check matrix calculation circuit 310 and the low data D0 to D63 output from the first parity check matrix calculation circuit 310 can be the same.

[0070] In response to the write command WT, the second parity check matrix calculation circuit 320 can receive 64 bits of high data DO64 to DO127 from the 128-bit data DO0 to DO127 provided by the data I / O circuit 160. The second parity check matrix calculation circuit 320 can use the 64 bits of high data DO64 to DO127 to generate 8 bits of second preliminary error correction codes E8 to E15. The second preliminary error correction codes E8 to E15 can be provided as second error correction codes P8 to P15. In this case, the high data DO64 to DO127 input to the second parity check matrix calculation circuit 320 and the high data D64 to D127 output from the second parity check matrix calculation circuit 320 can be the same.

[0071] The first parity check matrix calculation circuit 310 and the second parity check matrix calculation circuit 320 can be used Figures 5A to 5D The parity check matrix described herein generates first error-correcting codes P0 to P7 and second error-correcting codes P8 to P15. However, the present invention is not limited thereto, and the first parity check matrix calculation circuit 310 and the second parity check matrix calculation circuit 320 can generate error-correcting codes by applying known BCH codes, Hamming codes, or RS codes or other types of parity check codes.

[0072] Encoder selector 330 can select one of the all-zero code "00000000" (i.e., 0) and the second preliminary error correction code E8 to E15 based on the repair use signal RED_USED. Encoder selector 330 can select the second preliminary error correction code E8 to E15 when the repair use signal RED_USED is activated to a logic high level, and can select the all-zero code "00000000" when the repair use signal RED_USED is deactivated to a logic low level.

[0073] Logic gate 340 can perform a logical XOR operation on the first preliminary error correction codes E0 to E7 and the code selected from the code selector 330 to output the first error correction codes P0 to P7.

[0074] Using the above configuration, during a write operation, when the repair use signal RED_USED is activated to a logic high level, the error correction code generation circuit 152 can generate 8-bit first error correction codes P0 to P7 using 128-bit data DO0 to DO127. On the other hand, during a write operation, when the repair use signal RED_USED is deactivated to a logic low level, the error correction code generation circuit 152 can generate 8-bit first error correction codes P0 to P7 using 64-bit low data DO0 to DO63, and generate 8-bit second error correction codes P8 to P15 using 64-bit high data DO64 to DO127.

[0075] Figure 7 This is according to an embodiment of the present invention. Figure 4 Detailed block diagram of the error correction circuit 154. Figure 8 This is according to an embodiment of the present invention. Figure 7 The circuit diagram of the error corrector 492.

[0076] refer to Figure 7 The error correction circuit 154 may include a first parity matrix calculation circuit 410, a second parity matrix calculation circuit 420, a first decoder selector 430, a logic gate 440, a first corrector generator 450, a second corrector generator 460, a second decoder selector 470, a first error location detector 480, a second error location detector 490, and an error corrector 492.

[0077] In response to the read command RD, the first parity check matrix calculation circuit 410 can receive 64 bits of low data D0 to D63 from the 128 bits of data D0 to D127 provided by the storage cell array 110. The first parity check matrix calculation circuit 410 can use the 64 bits of low data D0 to D63 to generate 8 bits of first preliminary error correction codes E0 to E7.

[0078] In response to the read command RD, the second parity check matrix calculation circuit 420 can receive 64 bits of high data D64 to D127 from the 128 bits of data D0 to D127 provided by the storage cell array 110. The second parity check matrix calculation circuit 420 can use the 64 bits of high data D64 to D127 to generate 8 bits of second preliminary error correction codes E8 to E15.

[0079] For reference only. Figure 7 The error correction circuit 154 includes a first parity check matrix calculation circuit 410 and a second parity check matrix calculation circuit 420, which can have the same characteristics as... Figure 6 The error correction code generation circuit 152 includes a first parity check matrix calculation circuit 310 and a second parity check matrix calculation circuit 320, which are substantially identical in configuration. According to an embodiment, the first parity check matrix calculation circuit 410 of the error correction circuit 154 and the first parity check matrix calculation circuit 310 of the error correction code generation circuit 152 can be combined into a single configuration, and the second parity check matrix calculation circuit 420 of the error correction circuit 154 and the second parity check matrix calculation circuit 320 of the error correction code generation circuit 152 can also be combined into a single configuration.

[0080] The first decoder selector 430 can select one of the all-zero code "00000000" (i.e., 0) and the second preliminary error correction code E8 to E15 based on the repair use signal RED_USED. The first decoder selector 430 can select the second preliminary error correction code E8 to E15 when the repair use signal RED_USED is activated to a logic high level, and select the all-zero code "00000000" when the repair use signal RED_USED is deactivated to a logic low level.

[0081] Logic gate 440 can perform a logical XOR operation on the first preliminary error correction codes E0 to E7 and the code selected from the first decoder selector 430 to output the third preliminary error correction codes E'0 to E'7.

[0082] By comparing bit by bit the first error correction codes P0 to P7 provided from the storage cell array 110 with the third preliminary error correction codes E'0 to E'7, the first corrector generator 450 can generate first corrector data SD1 as encoded information related to the error location.

[0083] By comparing the second error correction codes P8 to P15 provided from the storage cell array 110 with the second preliminary error correction codes E8 to E15, the second corrector generator 460 can generate second corrector data SD2 as encoded information related to error location information.

[0084] The second decoder selector 470 can select one of the first corrector data SD1 and the second corrector data SD2 based on the repair use signal RED_USED to output the third corrector data SD2'. The second decoder selector 470 can select the first corrector data SD1 when the repair use signal RED_USED is activated to a logic high level, and select the second corrector data SD2 when the repair use signal RED_USED is deactivated to a logic low level.

[0085] The first error location detector 480 can detect the error locations of low data D0 to D63 based on the first correction sub-data SD1. The first error location detector 480 can decode the first correction sub-data SD1 to generate 64-bit first error flags ERR_P0 to ERR_P63 indicating the error locations of low data D0 to D63. The first error flags ERR_P0 to ERR_P63 can indicate which bits of low data D0 to D63 are erroneous.

[0086] The second error location detector 490 can detect the error locations of high data D64 to D127 based on the third correction sub-data SD2'. The second error location detector 490 can decode the third correction sub-data SD2' to generate 64-bit second error flags ERR_P64 to ERR_P127 indicating the error location information of high data D64 to D127. The second error flags ERR_P64 to ERR_P127 can indicate which bits of high data D64 to D127 are erroneous.

[0087] Error corrector 492 can correct errors in low data D0 to D63 based on first error flags ERR_P0 to ERR_P63 and correct errors in high data D64 to D127 based on second error flags ERR_P64 to ERR_P127 to output corrected data D0 to D127.

[0088] refer to Figure 8 Error corrector 492 may include first XOR gates XR1 through 128 XOR gates XR128. By performing a logical XOR operation on each of the first error flags ERR_P0 through ERR_P63 and each bit of the low data D0 through D63, first XOR gates XR1 through 64 XOR gates XR64 can output corrected data DO0 through DO63. By performing a logical XOR operation on each of the second error flags ERR_P64 through ERR_P127 and each bit of the high data D64 through D127, 65 XOR gates XR65 through 128 XOR gates XR128 can output corrected data DO64 through DO127. Using the above configuration, by outputting the bits at the positions where the error did not occur as is and inverting and outputting the bits at the positions where the error occurred, error corrector 492 can output corrected data DO0 through DO127.

[0089] Using the above configuration, during a read operation, when the repair use signal RED_USED is activated to a logic high level, the error correction circuit 154 can use 8-bit first error correction codes P0 to P7 to correct errors in 128 bits of data D0 to D127. Conversely, during a read operation, when the repair use signal RED_USED is deactivated to a logic low level, the error correction circuit 154 can use 8-bit first error correction codes P0 to P7 to correct errors in 64 bits of low data D0 to D63, and use 8-bit second error correction codes P8 to P15 to correct errors in 64 bits of high data D64 to D127.

[0090] In the following description, the operation of a storage device 100 according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0091] Figure 9A and Figure 9BThis diagram illustrates write and read operations of a memory device according to an embodiment of the present invention when the repair use signal RED_USED is deactivated.

[0092] refer to Figure 9A Because the redundant cell block MBRED is not used for repair operations, the repair use signal RED_USED is deactivated to logic low. In this case, the first repair signal C_REP0 to the seventeenth repair signal C_REP16 can also be deactivated to logic low.

[0093] In response to the write command WT, the first parity check matrix calculation circuit 310 of the error correction code generation circuit 152 can generate 8-bit first preliminary error correction codes E0 to E7 using the 64-bit low data DO0 to DO127 provided from the data I / O circuit 160. The second parity check matrix calculation circuit 320 can generate 8-bit second preliminary error correction codes E8 to E15 using the 64-bit high data DO64 to DO127 provided from the data I / O circuit 160. According to the logic low-level repair use signal RED_USED, the encoder selector 330 can select the all-zero code "00000000", and the logic gate 340 can output the first preliminary error correction codes E0 to E7 as is as the first error correction codes P0 to P7. The second preliminary error correction codes E8 to E15 can be provided as the second error correction codes P8 to P15.

[0094] Therefore, during the write operation, the error correction code generation circuit 152 can use 64 bits of low data DO0 to DO63 to generate 8 bits of first error correction codes P0 to P7, and use 64 bits of high data DO64 to DO127 to generate 8 bits of second error correction codes P8 to P15. At this time, the low data DO0 to DO63 input to the first parity check matrix calculation circuit 310 and the low data D0 to D63 output from the first parity check matrix calculation circuit 310 can be the same, and the high data DO64 to DO127 input to the second parity check matrix calculation circuit 320 and the high data D64 to D127 output from the second parity check matrix calculation circuit 320 can be the same.

[0095] In response to the first repair signal C_REP0 to the eighth repair signal C_REP7 at a logic low level, the first path selector 1401 to the eighth path selector 1408 of the repair control circuit 140 can transmit 64 bits of low data D0 to D63 to the first normal cell block MB0 to the eighth normal cell block MB7. In response to the ninth repair signal C_REP8 at a logic low level, the ninth path selector 1409 can transmit 8 bits of the first error correction code P0 to P7 to the ECC cell block MBECC. In response to the tenth repair signal C_REP9 to the seventeenth repair signal C_REP16 at a logic low level, the tenth path selector 1410 to the seventeenth path selector 1417 can transmit 64 bits of high data D64 to D127 to the ninth normal cell block MB8 to the sixteenth normal cell block MB15. In response to the low-level repair use signal RED_USED, the path blocking switch 1418 can be turned on to transmit the second error correction code P8 to P15 to the redundant unit block MBRED.

[0096] refer to Figure 9B In response to the first repair signal C_REP0 to the eighth repair signal C_REP7 at a logic low level, the first path selector 1401 to the eighth path selector 1408 of the repair control circuit 140 can transmit 64 bits of low data D0 to D63 from the first normal cell block MB0 to the eighth normal cell block MB7 to the error correction circuit 154. In response to the ninth repair signal C_REP8 at a logic low level, the ninth path selector 1409 can transmit 8 bits of the first error correction code P0 to P7 provided from the ECC cell block MBECC to the error correction circuit 154. In response to the tenth repair signal C_REP9 to the seventeenth repair signal C_REP16 at a logic low level, the tenth path selector 1410 to the seventeenth path selector 1417 can transmit 64 bits of high data D64 to D127 provided from the ninth normal cell block MB8 to the sixteenth normal cell block MB15 to the error correction circuit 154. In response to the logic low-level repair use signal RED_USED, the path blocking switch 1418 can be turned on to transmit the second error correction codes P8 to P15 provided from the redundant unit block MBRED to the error correction circuit 154.

[0097] In response to the read command RD, the first parity check matrix calculation circuit 410 of the error correction circuit 154 can generate 8-bit first preliminary error correction codes E0 to E7 using 64 bits of low data D0 to D63. In response to the read command RD, the second parity check matrix calculation circuit 420 can generate 8-bit second preliminary error correction codes E8 to E15 using 64 bits of high data D64 to D127. According to the logic low-level repair use signal RED_USED, the first decoder selector 430 can select the all-zero code "00000000", and the logic gate 440 can output the first preliminary error correction codes E0 to E7 as the third preliminary error correction codes E'0 to E'7. The first corrector generator 450 can generate first corrector data SD1 by comparing the first error correction codes P0 to P7 with the third preliminary error correction codes E'0 to E'7 (i.e., the first preliminary error correction codes E0 to E7), and the second corrector generator 460 can generate second corrector data SD2 by comparing the second error correction codes P8 to P15 with the second preliminary error correction codes E8 to E15.

[0098] The second decoder selector 470 can select the second correction sub-data SD2. The first error position detector 480 can detect the error positions of low data D0 to D63 based on the first correction sub-data SD1, and the second error position detector 490 can detect the error positions of high data D64 to D127 based on the second correction sub-data SD2. The error corrector 492 can correct the errors of low data D0 to D63 based on the first error flags ERR_P0 to ERR_P63, and correct the errors of high data D64 to D127 based on the second error flags ERR_P64 to ERR_P127 to output the corrected data D0 to D127.

[0099] As described above, in one embodiment of the present invention, when the redundant cell block MBRED is not used for repair operations, errors in 128-bit data can be corrected using 16-bit error correction codes by using the redundant cell block MBRED to store additional error correction codes. Therefore, error correction capability can be maximized without increasing the additional area.

[0100] Figure 10A and Figure 10B This is a diagram illustrating write and read operations of a storage device according to an embodiment of the present invention when the repair use signal RED_USED is activated.

[0101] refer to Figure 10ABecause the redundant cell block MBRED is used for the repair operation, the repair use signal RED_USED is activated to a logic high level. When a defective bit line exists in the sixth normal cell block MB5, the first repair signal C_REP0 to the fifth repair signal C_REP4 are deactivated to a logic low level, while all the sixth repair signals C_REP5 to the seventeenth repair signal C_REP16 are activated to a logic high level.

[0102] In response to the write command WT, the first parity check matrix calculation circuit 310 of the error correction code generation circuit 152 can generate 8-bit first preliminary error correction codes E0 to E7 using the 64-bit low data DO0 to DO127 provided from the data I / O circuit 160. The second parity check matrix calculation circuit 320 can generate 8-bit second preliminary error correction codes E8 to E15 using the 64-bit high data DO64 to DO127 provided from the data I / O circuit 160. According to the logic high-level repair use signal RED_USED, the encoder selector 330 can select the second preliminary error correction codes E8 to E15, and the logic gate 340 can output the first preliminary error correction codes E0 to E7 by performing a logical XOR operation on the first preliminary error correction codes E0 to E7 and the second preliminary error correction codes E8 to E15.

[0103] Therefore, the error correction code generation circuit 152 can use 128 bits of data DO0 to DO127 to generate 8 bits of the first error correction code P0 to P7.

[0104] In response to the first repair signal C_REP0 to the fifth repair signal C_REP4 at a logic low level, the first path selector 1401 to the fifth path selector 1405 of the repair control circuit 140 can transmit 40 bits of low data D0 to D39 to the first normal cell block MB0 to the fifth normal cell block MB4. In response to the sixth repair signal C_REP5 to the eighth repair signal C_REP7 at a logic high level, the sixth path selector 1406 to the eighth path selector 1408 can transmit 24 bits of low data D40 to D63 to the seventh normal cell block MB6, the eighth normal cell block MB7, and the ECC cell block MBECC.

[0105] In response to the logic high level of the ninth block repair signal C_REP8, the ninth path selector 1409 can transmit 8 bits of the first error correction code P0 to P7 to the ninth normal cell block MB8. Therefore, the first error correction code P0 to P7 can be written to the ninth normal cell block MB8 instead of the ECC cell block MBECC. That is, when the redundant cell block MBRED is used for a repair operation on one of the first normal cell blocks MB0 to the eighth normal cell blocks MB7, the first error correction code P0 to P7 can be stored in the adjacent cell block of the ECC cell block (i.e., the ninth normal cell block MB8).

[0106] In response to the logic high level of the tenth repair signal C_REP9 through the seventeenth repair signal C_REP16, the tenth path selector 1410 through the seventeenth path selector 1417 can transmit 64 bits of high data D64 through D127 to the tenth normal cell block MB9 through the sixteenth normal cell block MB15 and the redundant cell block MBRED. In response to the logic high level of the repair use signal RED_USED, the path blocking switch 1418 can be turned off to block the transmission path of the second error correction codes P8 through P15.

[0107] refer to Figure 10B In response to the first repair signal C_REP0 to the fifth repair signal C_REP4 at a logic low level, the first path selector 1401 to the fifth path selector 1405 of the repair control circuit 140 can transmit 40 bits of low data D0 to D39 provided from the first normal unit block MB0 to the fifth normal unit block MB4 to the error correction circuit 154. In response to the sixth repair signal C_REP5 to the eighth repair signal C_REP7 at a logic high level, the sixth path selector 1406 to the eighth path selector 1408 can transmit 24 bits of low data D40 to D63 from the seventh normal unit block MB6, the eighth normal unit block MB7, and the ECC unit block MBECC to the error correction circuit 154.

[0108] In response to the logic high level of the ninth repair signal C_REP8, the ninth path selector 1409 can transmit 8 bits of the first error correction code P0 to P7 from the ninth normal unit block MB8 to the error correction circuit 154. In response to the logic high level of the tenth repair signal C_REP9 to the seventeenth repair signal C_REP16, the tenth path selector 1410 to the seventeenth path selector 1417 can transmit 64 bits of high data D64 to D127 from the tenth normal unit block MB9 to the sixteenth normal unit block MB15 and the redundant unit block MBRED to the error correction circuit 154. In response to the logic high level of the repair use signal RED_USED, the path blocking switch 1418 can be turned off to block the transmission path of the second error correction code P8 to P15.

[0109] In response to the read command RD, the first parity check matrix calculation circuit 410 of the error correction circuit 154 can generate 8-bit first preliminary error correction codes E0 to E7 using 64 bits of low data D0 to D63. In response to the read command RD, the second parity check matrix calculation circuit 420 can generate 8-bit second preliminary error correction codes E8 to E15 using 64 bits of high data D64 to D127. According to the logic high-level repair use signal RED_USED, the first decoder selector 430 can select the second preliminary error correction codes E8 to E15, and the logic gate 440 can output the third preliminary error correction codes E'0 to E'7 by performing a logical XOR operation on the first preliminary error correction codes E0 to E7 and the second preliminary error correction codes E8 to E15.

[0110] The first corrector generator 450 compares the first error correction codes P0 to P7 with the third preliminary error correction codes E'0 to E'7 to generate the first corrector data SD1, and the second decoder selector 470 selects the first corrector data SD1. The first error location detector 480 and the second error location detector 490 can detect the error locations of the low data D0 to D63 and the high data D64 to D127 respectively based on the first corrector data SD1. The error corrector 492 can correct the errors of the low data D0 to D63 based on the first error flags ERR_P0 to ERR_P63, and correct the errors of the high data D64 to D127 based on the second error flags ERR_P64 to ERR_P127 to output the corrected data D0 to D127.

[0111] As described above, when the redundant unit block MBRED is used for repair operations, the error correction circuit 154 can use an 8-bit error correction code to correct errors in 128 bits of data.

[0112] In the above embodiments, it has been described that the first normal cell block MB0 to the eighth normal cell block MB7, the ECC cell block MBECC, and the ninth normal cell block MB8 to the sixteenth normal cell block MB15 are arranged sequentially along the row direction. However, the invention is not limited to this, and the multiple cell blocks can be arranged in various forms.

[0113] Figure 11 This is a diagram showing in more detail the configuration of a storage device 500 according to another embodiment of the present invention.

[0114] refer to Figure 11The storage cell array 510 may include first normal cell blocks MB0 to sixteenth normal cell blocks MB15, a redundant cell block MBRED, and an ECC cell block MBECC. The first normal cell blocks MB0 to sixteenth normal cell blocks MB15 may store data D0 to D127 received from an external device via data I / O circuitry 560. The first normal cell blocks MB0 to sixteenth normal cell blocks MB15 may be areas for storing user data and are memory blocks used to determine the storage capacity of the storage device 500. The redundant cell block MBRED may provide for repair operations on the first normal cell blocks MB0 to sixteenth normal cell blocks MB15 and may include multiple redundant cells (e.g., redundant bit lines) for replacing defective cells (e.g., defective bit lines) in the first normal cell blocks MB0 to sixteenth normal cell blocks MB15. The ECC cell block MBECC may store first error correction codes P0 to P7 generated by error correction device 550 for error correction operations.

[0115] In one embodiment of the invention, when the redundant cell block MBRED is not used for repair operations, the repair use signal RED_USED is deactivated, so the redundant cell block MBRED can store the second error correction codes P8 to P15 generated by the error correction device 550. In this case, the first normal cell blocks MB0 to the sixteenth normal cell block MB15, the redundant cell block MBRED, and the ECC cell block MBECC can be sequentially arranged along the row direction.

[0116] The column control circuit 530 may include a column decoder 532 and first column switches CSW0 to eighteenth column switches CSW17. Because the column control circuit 530 has... Figure 2 The column control circuit 130 has essentially the same configuration, so its detailed description will be omitted.

[0117] The repair control circuit 540 may include first path selectors 541 to sixteenth path selectors 5416, each corresponding to a first normal cell block MB0 to a sixteenth normal cell block MB15. Responding to the first block repair signal C_REP0 to the sixteenth block repair signal C_REP15, the first path selectors 541 to sixteenth path selectors 5416 may transmit data D0 to D127 and first error correction codes P0 to P7 between the corresponding cell block and one of the adjacent cell blocks in the row direction. Furthermore, the repair control circuit 540 may also include a path blocking switch 5417, which is used to transmit second error correction codes P8 to P15 between the redundant cell block MBRED and the error correction device 550 in response to the repair use signal RED_USED. The first path selectors 541 to sixteenth path selectors 5416 and the path blocking switch 5417 have... Figure 2The repair control circuit 140 has essentially the same configuration, so its detailed description will be omitted.

[0118] When the repair use signal RED_USED is activated, the error correction device 550 can generate 8-bit first error correction codes P0 to P7 using 128-bit data DO0 to DO127 during a write operation, and correct data D0 to D127 based on the 8-bit first error correction codes P0 to P7 during a read operation. Conversely, when the repair use signal RED_USED is deactivated, the error correction device 550 can generate 16-bit first error correction codes P0 to P7 and second error correction codes P8 to P15 using 128-bit data DO0 to DO127 during a write operation, and correct data D0 to D127 based on the 16-bit first error correction codes P0 to P7 and second error correction codes P8 to P15 during a read operation. The error correction device 550 has... Figures 4 to 8 The configuration of the error correction device 150 is substantially the same, therefore its detailed description will be omitted.

[0119] The data I / O circuit 560 can correspond to data pads DQ0 to DQ7 and can input / output 128-bit data DO0 to DO127 through the corresponding data pads. The data I / O circuit 560 has... Figure 2 The data I / O circuit 160 has essentially the same configuration, so its detailed description will be omitted.

[0120] Various embodiments of this disclosure have been described in the accompanying drawings and specification. While specific terminology is used herein, it is for the purpose of describing embodiments of this disclosure only. Therefore, this disclosure is not limited to the embodiments described above, and many variations are possible within the spirit and scope of this disclosure. Those skilled in the art will appreciate that various modifications can be made based on the technical scope of this disclosure and the embodiments disclosed herein. Embodiments can be combined to form other embodiments.

[0121] It should be noted that although the technical essence of this disclosure has been described in conjunction with embodiments thereof, this is for descriptive purposes only and should not be construed as limiting. Those skilled in the art will understand that various changes can be made without departing from the technical essence of the disclosure and the appended claims.

[0122] For example, the logic gates and transistors provided as examples in the above embodiments can be implemented in different positions and types depending on the polarity of the input signal.

Claims

1. A storage device, comprising: Multiple first unit blocks, each storing first data; The second unit block stores the second data; The third unit block stores the third data; The repair information storage circuit outputs a repair use signal corresponding to the input address based on the repair information stored therein; as well as Error correction circuit, which: When selectively receiving the third data as a second error correction code from the third unit block according to the repair signal, receiving the second data as a first error correction code from the second unit block, and The first error correction code and the second error correction code are used to correct errors in the first data from the first cell block.

2. The storage device according to claim 1, in, The error correction circuit: when the repair signal is activated, uses the first error correction code to correct errors in the first data, and The error correction circuit, when the repair signal is deactivated, uses the first error correction code and the second error correction code to correct errors in the first data.

3. The storage device according to claim 1, wherein, The repair information storage circuit includes: Multiple address storage circuits, each corresponding to the first unit block and the second unit block, each address storage circuit storing at least one defective address of a corresponding one of the first unit block and the second unit block; and Signal generator, which: Multiple block repair signals are generated, each of which is activated based on a comparison between the input address and the defective address stored in a corresponding address storage unit. The repair use signal is activated when one of the block repair signals is activated.

4. The storage device according to claim 3 further includes a repair control circuit, which uses units of the third unit block to repair defective units of the first unit block and the second unit block according to the block repair signal.

5. The storage device according to claim 4, wherein, The repair control circuit includes: A plurality of path selectors corresponding to the first unit block and the second unit block, each path selector: in response to a corresponding one of the block repair signals, transmits data between the error correction circuit and a corresponding unit block in the first unit block and the second unit block, as well as one of the adjacent unit blocks of the corresponding unit block.

6. The storage device according to claim 5, wherein, The repair control circuit also includes a path blocking switch that transmits data between the third unit block and the error correction circuit in response to the deactivation of the repair use signal.

7. The storage device according to claim 1, wherein, The error correction circuit includes: The computing circuit generates a first preliminary error correction code using the low data in the first data, and generates a second preliminary error correction code using the high data in the first data; A first decoding selector, which selects one of an all-zero code and a second preliminary error correction code based on the repair signal; A logic gate that outputs a third preliminary error correction code by performing a logical XOR operation on the first preliminary error correction code and the selected code; A first corrector generator generates first corrector data by comparing the first error correction code with the third preliminary error correction code bit by bit. The second corrector generator generates second corrector data by comparing the second error correction code with the second preliminary error correction code bit by bit. A second decoding selector, which: outputs third correction data by selecting one of the first correction data and the second correction data according to the repair usage signal; and An error corrector that corrects errors by detecting the error location of the low data based on the first corrector data and by detecting the error location of the high data based on the third corrector data.

8. The storage device according to claim 1, further comprising an error correction code generation circuit, wherein the error correction code generation circuit: The first preliminary error correction code is generated using the low data in the input data. A second preliminary error correction code is generated using the high data from the input data, and Based on the repair signal, the first preliminary error correction code and the second preliminary error correction code are provided as the second data and the third data, respectively, or the comparison result between the first preliminary error correction code and the second preliminary error correction code is provided as the second data.

9. The storage device according to claim 8, wherein, The error correction code generation circuit includes: The computing circuit generates the first preliminary error correction code and the second preliminary error correction code, and outputs the second preliminary error correction code as the second error correction code. An encoding selector, which: selects one of an all-zero code and a second preliminary error-correcting code based on the repair signal; and A logic gate that outputs the first error correction code by performing a logical XOR operation on the first preliminary error correction code and the selected code.

10. The storage device according to claim 1, in, The first unit block includes the first normal unit block to the 2mth normal unit block, where m is a natural number. The first normal unit block to the m-th normal unit block, the second unit block, the (m+1)-th to the 2m-th normal unit block, and the third unit block are arranged sequentially along the first direction.

11. A storage device comprising: A storage cell array, comprising multiple normal cell blocks, error-correcting code cell blocks, and redundant cell blocks; as well as Error correction circuit, which: When selectively receiving data as a second error correction code from the redundant unit block according to the repair usage signal, data is received as a first error correction code from the error correction code unit block. The repair usage signal indicates whether a unit of the redundant unit block is used in the repair operation. The first error correction code and the second error correction code are used to correct errors in the data read from the normal cell block.

12. The storage device according to claim 11, in, The error correction circuit: when the repair signal is activated, corrects the error using the first error correction code, and The error correction circuit, when the repair signal is deactivated, corrects errors using the first error correction code and the second error correction code.

13. The storage device according to claim 11, further comprising an error correction code generation circuit, wherein the error correction code generation circuit: The first preliminary error correction code is generated using the low data in the input data. A second preliminary error correction code is generated using the high data from the input data, and Based on the repair usage signal, the first preliminary error correction code and the second preliminary error correction code are provided to the error correction code unit block and the redundancy unit block, respectively, or a comparison result between the first preliminary error correction code and the second preliminary error correction code is provided to the error correction code unit block.

14. The storage device according to claim 13, in, When the repair signal is activated, the error correction code generation circuit provides a result by performing a logical XOR operation on the first preliminary error correction code and the second preliminary error correction code, and When the repair signal is deactivated, the error correction circuit provides the first preliminary error correction code and the second preliminary error correction code to the error correction code unit block and the redundancy unit block, respectively.

15. The storage device according to claim 11, in, The normal unit blocks include the first normal unit block to the 2mth normal unit block, where m is a natural number. The first normal unit block to the m-th normal unit block, the error correction code unit block, the (m+1)-th normal unit block to the 2m-th normal unit block, and the redundant unit block are arranged sequentially along the first direction.

16. An error correction device, comprising: The error correction code generation circuit has the following characteristics: The first and second preliminary error-correcting codes are generated using the low and high data from the input data, respectively. Based on the repair usage signal, the first preliminary error correction code and the second preliminary error correction code are provided to the first unit block and the second unit block respectively, or a comparison result between the first preliminary error correction code and the second preliminary error correction code is provided to the first unit block; and Error correction circuit, which: When selectively receiving data read from the second unit block as a second error correction code according to the repair signal, receiving data read from the first unit block as a first error correction code, and The first and second error correction codes are used to correct errors in the data read from the third unit block.

17. The error correction device according to claim 16, in, When the repair signal is activated, the error correction code generation circuit provides a result by performing a logical XOR operation on the first preliminary error correction code and the second preliminary error correction code, and When the repair signal is deactivated, the error correction circuit provides the first preliminary error correction code and the second preliminary error correction code to the first unit block and the second unit block, respectively.

18. The error correction device according to claim 16, wherein, The error correction code generation circuit includes: The computing circuit generates the first preliminary error correction code and the second preliminary error correction code, and outputs the second preliminary error correction code as the second error correction code. An encoding selector, which: selects one of an all-zero code and a second preliminary error-correcting code based on the repair signal; and A logic gate that outputs the first error correction code by performing a logical XOR operation on the first preliminary error correction code and the selected code.

19. The error correction device according to claim 16, in, The error correction circuit: when the repair signal is activated, corrects the error using the first error correction code, and The error correction circuit, when the repair signal is deactivated, corrects errors using the first error correction code and the second error correction code.

20. The error correction device according to claim 16, wherein, The error correction circuit includes: The computing circuit generates a third preliminary error correction code and a fourth preliminary error correction code using the low data and high data from the data read from the third unit block, respectively. A first decoding selector, which selects one of the all-zero code and the fourth preliminary error correction code based on the repair signal; A logic gate that outputs a fifth preliminary error correction code by performing a logical XOR operation on the third preliminary error correction code and the selected code; A first corrector generator generates first corrector data by comparing the first error correction code with the fifth preliminary error correction code bit by bit. The second corrector generator generates second corrector data by comparing the second error correction code with the fourth preliminary error correction code bit by bit. A second decoding selector, which: outputs third correction data by selecting one of the first correction data and the second correction data according to the repair usage signal; and An error corrector that corrects errors by detecting the error location of the low data in the data read from the third unit block based on the first corrector data and the error location of the high data in the data read from the third unit block based on the third corrector data.

21. The error correction device according to claim 16, wherein, The repair signal is activated when a unit of the second unit block is used to repair a defective unit of the first unit block and the third unit block.

22. A storage device comprising: A group of unit blocks that stores data of a predetermined size and a first error correction code; Redundant cell blocks, which replace defective cell blocks in the group when the control signal is enabled, the group and the redundant cell blocks share word lines; Error correction code encoding / decoding circuit, which: While the control signal remains enabled, a first error correction code is generated for the data to correct errors in the data using the first error correction code. While the control signal remains disabled, a first error correction code for a portion of the data and a second error correction code for another portion of the data are generated to correct errors in the data using the first and second error correction codes; and A control circuit that controls the redundant unit block to store the second error correction code when the control signal is disabled.

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