Data receiving circuit, data receiving system and storage device

Abstract

This disclosure provides a data receiving circuit, a data receiving system, and a storage device. The data receiving circuit includes a decision feedback equalization module configured to perform decision feedback equalization on the receiving module based on a feedback signal to adjust a first output signal and a second output signal. The feedback signal is obtained based on previously received data, and the decision feedback equalization module responds to a first control signal group and a second control signal group to change its adjustment capability. The first control signal group corresponds to a data port corresponding to the data signal, and the second control signal group corresponds to all data ports. This disclosure provides at least the advantage of flexibly controlling the adjustment capability of the decision feedback equalization module on the first and second output signals, and this adjustment capability has a large adjustable range, thereby reducing the impact of inter-symbol interference of received data on the data receiving circuit and improving the receiving performance of the data receiving circuit.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a data receiving circuit, a data receiving system, and a storage device. Background Technology

[0002] In memory applications, as signal transmission rates increase, channel loss has a greater impact on signal quality, easily leading to inter-symbol interference. Currently, equalization circuits are commonly used to compensate for channel loss. These circuits can be either CTLE (Continuous Time Linear Equalizer) or DFE (Decision Feedback Equalizer).

[0003] However, the current equalization circuits have limited ability to adjust signals, and the accuracy of signal adjustment by equalization circuits needs to be improved. Summary of the Invention

[0004] This disclosure provides a data receiving circuit, a data receiving system, and a storage device, which at least facilitates flexible control of the decision feedback equalization module's ability to adjust the first and second output signals, thereby reducing the impact of inter-symbol interference of the data received by the data receiving circuit on the data receiving circuit and improving the receiving performance of the data receiving circuit.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a data receiving circuit, including: a receiving module configured to receive a reference signal and a data signal from a data port, compare the data signal and the reference signal in response to a sampling clock signal, and output a first output signal and a second output signal; and a decision feedback equalization module connected to a feedback node of the receiving module, configured to perform decision feedback equalization on the receiving module based on the feedback signal to adjust the first output signal and the second output signal, wherein the feedback signal is obtained based on previously received data, and the decision feedback equalization module responds to a first control signal group and a second control signal group to adjust the adjustment capability of the first output signal and the second output signal; wherein the first control signal group corresponds to one of the data ports corresponding to the data signal, and the second control signal group corresponds to all of the data ports.

[0006] In some embodiments, the decision feedback equalization module includes: a first adjustment unit configured to adjust the equivalent resistance value of the first adjustment unit in response to a first coded signal group, wherein the equivalent resistance value of the first adjustment unit is recorded as a first resistance value, and the first coded signal group is obtained based on a first compilation of the first control signal group and / or the second control signal group; and a second adjustment unit connected in parallel with the first adjustment unit configured to adjust the equivalent resistance value of the second adjustment unit in response to a second coded signal group, wherein the equivalent resistance value of the second adjustment unit is recorded as a second resistance value, and the second coded signal group is obtained based on a second compilation of the first control signal group or the second control signal group; wherein the equivalent resistance value of the first adjustment unit and the second adjustment unit connected in parallel is related to the adjustment capability of the decision feedback equalization module for the first output signal and the second output signal.

[0007] In some embodiments, the first coded signal group includes a zeroth coded signal and a first coded signal; the first adjustment unit includes a zeroth transistor and a first transistor connected in parallel, the channel width-to-length ratio of the zeroth transistor being n, the channel width-to-length ratio of the first transistor being 2n, and the gate of the zeroth transistor and the gate of the first transistor respectively receiving the zeroth coded signal and the first coded signal; the second coded signal group includes a second coded signal, a third coded signal, and a fourth coded signal; the second adjustment unit includes a second transistor, a third transistor, and a fourth transistor connected in parallel, the channel width-to-length ratio of the second transistor being n, the channel width-to-length ratio of the third transistor being 2n, the channel width-to-length ratio of the fourth transistor being 2n, and the gate of the second transistor, the gate of the third transistor, and the gate of the fourth transistor respectively receiving the second coded signal, the third coded signal, and the fourth coded signal, where n is an integer greater than or equal to 1.

[0008] In some embodiments, the decision feedback equalization module further includes: a decoding circuit, used to perform logical operations on the first control signal group and the second control signal group to obtain the first encoded signal group and the second encoded signal group.

[0009] In some embodiments, the decoding circuit is configured such that if the data of the highest bit in the second control signal group is 1, both the third encoded signal and the fourth encoded signal are in a valid state, and the third transistor is turned on in response to the valid state of the third encoded signal, and the fourth transistor is turned on in response to the valid state of the fourth encoded signal.

[0010] In some embodiments, the decoding circuit is configured such that: if the data of the two highest bits in the second control signal group are both 1, then the first encoded signal is in an active state; or, if the data of the highest bit in the first control signal group is 1, then the first encoded signal is in an active state; wherein, the first transistor is turned on in response to the active state of the first encoded signal.

[0011] In some embodiments, the first control signal group includes a zeroth control signal and a first control signal; the second control signal group includes a second control signal, a third control signal, and a fourth control signal; the decoding circuit includes: three first inverters, each of which receives the zeroth control signal, the second control signal, and the fourth control signal respectively, and outputs the zeroth encoded signal, the second encoded signal, and the fourth encoded signal respectively; a NOR gate, the two inputs of which receive the third control signal and the fourth control signal respectively, and outputs a third encoded signal; and a logic circuit, the three inputs of which receive the first control signal, the third control signal, and the fourth control signal respectively, and output a first encoded signal; wherein, if both the third control signal and the fourth control signal are logic high, then the first encoded signal is logic low; if at least one of the third control signal and the fourth control signal is logic low, then the first encoded signal is out of phase with the first control signal.

[0012] In some embodiments, the logic circuit includes: an OR gate, the two inputs of which receive the inverted signal of the third control signal and the inverted signal of the fourth control signal, respectively; a NAND gate, one input of which receives the inverted signal of the first control signal, and the other input of which is connected to the output of the OR gate; and a second inverter, the input of which is connected to the output of the NAND gate, and the output of which outputs the first encoded signal.

[0013] In some embodiments, the logic circuit further includes: a third inverter, which receives the first control signal and outputs an inverted signal of the first control signal; and two fourth inverters, each of which receives the third control signal and the fourth control signal respectively and outputs an inverted signal of the third control signal and an inverted signal of the fourth control signal respectively.

[0014] In some embodiments, the receiving module includes: a first amplification module configured to receive the data signal and the reference signal, compare the data signal and the reference signal in response to the sampling clock signal, and output a first voltage signal through a first node and a second voltage signal through a second node; a second amplification module connected to the first node and the second node, configured to amplify the voltage difference between the first voltage signal and the second voltage signal, and output the first output signal through a third node and the second output signal through a fourth node; wherein the feedback node includes a first feedback node and a second feedback node, the first node serving as the first feedback node and the second node serving as the second feedback node, and the decision feedback equalization module configured to perform decision feedback equalization on the first node and the second node based on the feedback signal to adjust the first voltage signal and the second voltage signal.

[0015] In some embodiments, the data receiving circuit further includes an offset compensation module connected to the second amplification module and configured to compensate for the offset voltage of the second amplification module.

[0016] In some embodiments, the receiving module includes: a first amplification module configured to receive the data signal and the reference signal, compare the data signal and the reference signal in response to the sampling clock signal, and output a first voltage signal through a first node and a second voltage signal through a second node; a second amplification module connected to the first node and the second node, configured to amplify the voltage difference between the first voltage signal and the second voltage signal, and output the first output signal through a third node and the second output signal through a fourth node, wherein the second amplification module has a first internal node and a second internal node, and the first output signal and the second output signal are obtained based on the signals of the first internal node and the second internal node; wherein the feedback node includes a first feedback node and a second feedback node, the first internal node serves as the first feedback node, the second internal node serves as the second feedback node, and the decision feedback equalization module is configured to perform decision feedback equalization on the first internal node and the second internal node based on the feedback signal.

[0017] In some embodiments, the data receiving circuit further includes: an offset compensation module connected to the first amplification module and configured to compensate for the offset voltage of the first amplification module.

[0018] In some embodiments, the first amplification module includes: a current source configured to be connected between a power supply node and a fifth node, providing current to the fifth node in response to the sampling clock signal; and a comparison unit connected to the fifth node, the first node, and the second node, configured to receive the data signal and the reference signal, compare the data signal and the reference signal when the current source provides current to the fifth node in response to the sampling clock signal, and output the first voltage signal through the first node and the second voltage signal through the second node.

[0019] In some embodiments, the first amplification module further includes: a first reset unit, connected to the first node and the second node, configured to reset the first node and the second node.

[0020] In some embodiments, the second amplification module includes: an input unit connected to the first node and the second node, configured to compare the first voltage signal and the second voltage signal, and provide a third voltage signal to a seventh node and a fourth voltage signal to an eighth node, wherein the second amplification module has a first internal node and a second internal node, and the seventh node is the first internal node and the eighth node is the second internal node; and a latching unit configured to amplify and latch the third voltage signal and the fourth voltage signal, and output the first output signal to the third node and the second output signal to the fourth node.

[0021] According to some embodiments of this disclosure, another aspect of this disclosure provides a data receiving system, including: a plurality of cascaded data transmission circuits, each data transmission circuit including the data receiving circuit described in any of the above embodiments and a latching circuit connected to the data receiving circuit, each data receiving circuit being connected to the data port to receive the data signal; a decision feedback equalization module of a higher-level data transmission circuit being connected to a lower-level data transmission circuit, the output of the higher-level data transmission circuit serving as the feedback signal of the decision feedback equalization module of the lower-level data transmission circuit; and a final-level data transmission circuit being connected to the decision feedback equalization module of a first-level data transmission circuit, the output of the final-level data transmission circuit serving as the feedback signal of the decision feedback equalization module of the first-level data transmission circuit.

[0022] According to some embodiments of this disclosure, another aspect of this disclosure also provides a storage device, including: a plurality of data ports; a plurality of data receiving systems as described in the above embodiments, each of the data receiving systems corresponding to one of the data ports.

[0023] The technical solutions provided in this disclosure have at least the following advantages:

[0024] By integrating the decision feedback equalization module into the data receiving circuit, and adjusting the first and second output signals through the decision feedback equalization module to reduce the impact of inter-symbol interference (ISI) on data reception, this embodiment of the present disclosure offers advantages over related technologies where the storage device uses a separate decision feedback equalizer to reduce ISI. This allows for signal adjustment of the data receiving circuit output with a smaller circuit layout area and lower power consumption. Furthermore, by flexibly controlling the decision feedback equalization module's adjustment capability of the first and second output signals, the impact of ISI on the data receiving circuit is reduced, thereby improving the receiving performance of the data receiving circuit and minimizing the impact of ISI on the accuracy of the output signal. Moreover, the decision feedback equalization module's adjustment capability of the first and second output signals is related not only to the first control signal group corresponding to the data port but also to the second control signal group corresponding to all data ports. This makes the aforementioned adjustment capability variable based on two different control signal groups and has a large variable range, thus further improving the ISI problem. Attached Figure Description

[0025] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A functional block diagram of a data receiving circuit provided in an embodiment of this disclosure;

[0027] Figure 2 A functional block diagram of a data receiving system provided in an embodiment of this disclosure;

[0028] Figures 3 to 4 Two other functional block diagrams of a data receiving circuit provided in one embodiment of this disclosure;

[0029] Figure 5 This is another functional block diagram of a data receiving circuit provided in an embodiment of the present disclosure;

[0030] Figure 6 for Figure 3 A corresponding circuit structure diagram;

[0031] Figure 7 This is yet another functional block diagram of a data receiving circuit provided in an embodiment of the present disclosure;

[0032] Figure 8 Another functional block diagram of a data receiving circuit provided in an embodiment of this disclosure;

[0033] Figures 9 to 11 This is a partial circuit structure diagram of the decision feedback equalization module in a data receiving circuit provided in an embodiment of the present disclosure;

[0034] Figure 12 This is a schematic diagram of the equivalent circuit between the first control signal group, the second control signal group and the decision enable signal in the decision feedback equalization module in one embodiment of the present disclosure.

[0035] Figure 13 and Figure 14 The following are schematic diagrams of two other circuit structures of a data receiving circuit provided in one embodiment of this disclosure. Detailed Implementation

[0036] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0037] This disclosure provides a data receiving circuit according to an embodiment. The data receiving circuit provided by this disclosure will be described in detail below with reference to the accompanying drawings. Figure 1 A functional block diagram of a data receiving circuit provided in an embodiment of this disclosure; Figures 3 to 4 Two other functional block diagrams of a data receiving circuit provided in one embodiment of this disclosure; Figure 5 This is another functional block diagram of a data receiving circuit provided in an embodiment of the present disclosure; Figure 6 for Figure 3 The corresponding circuit structure diagram; Figure 7 This is yet another functional block diagram of a data receiving circuit provided in an embodiment of the present disclosure; Figure 8 Another functional block diagram of a data receiving circuit provided in an embodiment of this disclosure; Figures 9 to 11 This is a partial circuit structure diagram of the decision feedback equalization module in a data receiving circuit provided in an embodiment of the present disclosure; Figure 12 and Figure 13The following are schematic diagrams of two other circuit structures of a data receiving circuit provided in one embodiment of this disclosure.

[0038] refer to Figure 1 The data receiving circuit 110 includes: a receiving module 100 configured to receive a reference signal Vref and a data signal DQ from a data port, compare the data signal DQ and the reference signal Vref in response to a sampling clock signal CLK1, and output a first output signal Vout and a second output signal VoutN; and a decision feedback equalization module 103 connected to the feedback node of the receiving module 100, configured to perform decision feedback equalization on the receiving module 100 based on the feedback signal to adjust the first output signal Vout and the second output signal VoutN, wherein the feedback signal is obtained based on previously received data, and the decision feedback equalization module 103 responds to a first control signal group PerPin.<m:0> Second control signal group PerByte<N:0> To adjust the adjustment capability of the first output signal Vout and the second output signal VoutN; the first control signal group PerPin<m:0> Corresponding to a data port with a corresponding data signal, the second control signal group PerByte<N:0> Corresponding to all data ports.

[0039] Integrating the decision feedback equalization module 103 into the data receiving circuit allows for adjustments to the output signal of the data receiving circuit using a smaller circuit layout area and lower power consumption. Furthermore, the decision feedback equalization module 103 provided in this embodiment has adjustable capabilities for adjusting the first output signal Vout and the second output signal VoutN. This means that when the data signal DQ and / or reference signal Vref received by the receiving module 100 change, the adjustment capabilities of the decision feedback equalization module 103 for the first output signal Vout and the second output signal VoutN can be flexibly controlled to reduce the impact of inter-symbol interference (ISI) on the data receiving circuit, thereby improving the receiving performance of the data receiving circuit and reducing the impact of ISI on the accuracy of the output signal of the data receiving circuit. In addition, the adjustment capabilities of the decision feedback equalization module 103 for the first output signal Vout and the second output signal VoutN are related to the first control signal group PerPin.<m:0> Second control signal group PerByte<N:0> The adjustment capability is related to both individual data ports and all data ports, which makes the decision feedback equalization module 103 have a larger adjustable range, a stronger ability to improve inter-symbol interference, and a stronger targeting for different data ports.

[0040] First control signal group PerPin<m:0> This corresponds to the data port for transmitting this data signal, namely, the first control signal group PerPin.<m:0> The control signals in the diagram correspond only to specific data ports. It can be understood that for different data receiving circuits at each data port—for example, the first data receiving circuit connected to data port DQ1 and the second data receiving circuit connected to data port DQ2—the corresponding first control signal group PerPin...<m:0> The difference lies in the first control signal group PerPin corresponding to the first data receiving circuit.<m:0> It is designed based on data port DQ1, and the first control signal group PerPin corresponding to the second data receiving circuit is...<m:0> It is designed based on data port DQ2. Because the inter-symbol interference (ISI) received by different data ports varies, the interference experienced by each data signal DQ in the transmission path is also different. Therefore, a different first control signal group PerPin is designed for each data port's received data signal DQ.<m:0> This allows for targeted adjustment of each data port via the adjustment unit 1132, thereby further improving the receiving performance of the data receiving circuit.

[0041] Second control signal group PerByte<N:0> All data ports in the corresponding data receiving circuit, i.e., the second control signal group PerByte<N:0> The control signals in the second control group PerByte correspond to all data ports.<N:0> The control signals in the second control signal group PerByte can be universal for all data receiving circuits. That is, for different data receiving circuits connected to different data ports, the second control signal group PerByte is provided to different data receiving circuits.<N:0> It is universal. A second control group (PerByte) is designed to be universal across different data ports.<N:0> This is beneficial for further increasing the adjustment range of the decision feedback equalization capability of each data receiving circuit.

[0042] It should be noted that the connection between the decision feedback equalization module 103 and the feedback node of the receiving module 100 includes at least the following two examples.

[0043] In some embodiments, reference Figure 3 Receiver module 100 (reference) Figure 1The system may include: a first amplification module 101, configured to receive a data signal DQ and a reference signal Vref, compare the data signal DQ and the reference signal Vref in response to a sampling clock signal CLK1, and output a first voltage signal through a first node n_stg1 and a second voltage signal through a second node p_stg1; and a second amplification module 102, connected to the first node n_stg1 and the second node p_stg1, configured to amplify the voltage difference between the first voltage signal and the second voltage signal, and output a second voltage signal through a third node net3 (reference...). Figure 6 The first output signal Vout is output through the fourth node net4 (reference). Figure 6 The second output signal VoutN is output; wherein the feedback nodes include a first feedback node and a second feedback node, the first node n_stg1 is the first feedback node, the second node p_stg1 is the second feedback node, and the decision feedback equalization module 103 is configured to perform decision feedback equalization on the first node n_stg1 and the second node p_stg1 based on the feedback signal to adjust the first voltage signal and the second voltage signal.

[0044] It should be noted that the second amplification module 102 receives the first voltage signal and the second voltage signal, and amplifies the voltage difference between the first voltage signal and the second voltage signal to output a first output signal Vout and a second output signal VoutN. That is, the first output signal Vout and the second output signal VoutN are affected by the first voltage signal and the second voltage signal. The decision feedback equalization module 103 adjusts the first voltage signal and the second voltage signal based on the feedback signal, and can also further adjust the first output signal Vout and the second output signal VoutN. Moreover, the adjustment of the first voltage signal and the second voltage signal by the decision feedback equalization module 103 will be explained in detail later with reference to the specific circuit diagram.

[0045] In some embodiments, continue to refer to Figure 3 The data receiving circuit may further include an offset compensation module 104, connected to the second amplification module 102, configured to compensate for the offset voltage of the second amplification module 102. It should be noted that the specific connection relationship between the offset compensation module 104 and the second amplification module 102 will be explained in detail later with reference to specific circuit diagrams.

[0046] In other embodiments, reference is made to... Figure 13 Receiver module 100 (reference) Figure 1The amplification module 102 may include: a first amplification module 101, configured to receive a data signal DQ and a reference signal Vref, compare the data signal DQ and the reference signal Vref in response to a sampling clock signal CLK1, and output a first voltage signal through a first node n_stg1 and a second voltage signal through a second node p_stg1; and a second amplification module 102, connected to the first node n_stg1 and the second node p_stg1, configured to amplify the voltage difference between the first voltage signal and the second voltage signal, and output a first output signal Vout through a third node net3 and a second output signal Vout through a fourth node net4. outN, the second amplification module 102 has a first internal node n_stg2 and a second internal node p_stg2, and the first output signal Vout and the second output signal VoutN are obtained based on the signals of the first internal node n_stg2 and the second internal node p_stg2; wherein, the feedback node includes a first feedback node and a second feedback node, the first internal node n_stg2 is used as the first feedback node, the second internal node p_stg2 is used as the second feedback node, and the decision feedback equalization module 103 is configured to perform decision feedback equalization on the first internal node n_stg2 and the second internal node p_stg2 based on the feedback signal.

[0047] It should be noted that the voltage signal at the first internal node n_stg2 is the third voltage signal, and the voltage signal at the second internal node p_stg2 is the fourth voltage signal. The decision feedback equalization module 103 performs decision feedback equalization on the first internal node n_stg2 and the second internal node p_stg2 based on the feedback signal, that is, the decision feedback equalization module 103 adjusts the third and fourth voltage signals. The first output signal Vout and the second output signal VoutN are based on the third and fourth voltage signals, so the decision feedback equalization module 103 can further adjust the first output signal Vout and the second output signal VoutN by adjusting the third and fourth voltage signals based on the feedback signal. Moreover, the adjustment of the third and fourth voltage signals by the decision feedback equalization module 103 will be explained in detail later with reference to the specific circuit diagram.

[0048] In some embodiments, the data receiving circuit may further include: an offset compensation module connected to the first amplification module, configured to compensate for the offset voltage of the first amplification module. It should be noted that the specific connection relationship between the offset compensation module and the first amplification module will be described in detail later.

[0049] In the two examples above, the data receiving circuit employs a two-stage amplification module, namely the first amplification module 101 and the second amplification module 102, to process the data signal DQ and the reference signal Vref. This enhances the amplification capability of the data receiving circuit and increases the voltage amplitude of the first output signal Vout and the second output signal VoutN, facilitating processing by subsequent circuits. Furthermore, the decision feedback equalization module 103 is used to reduce inter-symbol interference by equivalently adjusting the data signal DQ.

[0050] The following will combine Figures 4 to 13 The specific structure of a data receiving circuit provided in one embodiment of this disclosure will be described in detail below. It should be noted that the following detailed descriptions of each module apply to both of the aforementioned examples.

[0051] In some embodiments, reference Figure 4 The first amplification module 101 may include: a current source 111, configured to be connected to the power supply node Vcc (reference). Figure 6 Between the current source 111 and the fifth node net5, current is supplied to the fifth node net5 in response to the sampling clock signal CLK1; the comparison unit 121, connected to the fifth node net5, the first node n_stg1 and the second node p_stg1, is configured to receive the data signal DQ and the reference signal Vref, and when the current source 111 supplies current to the fifth node net5 in response to the sampling clock signal CLK1, compares the data signal DQ and the reference signal Vref, and outputs a first voltage signal through the first node n_stg1 and a second voltage signal through the second node p_stg1.

[0052] It is understood that the comparison unit 121 can control the difference between the current supplied to the first node n_stg1 and the current supplied to the second node p_stg1 based on the difference between the data signal DQ and the reference signal Vref, so as to output a first voltage signal and a second voltage signal.

[0053] The following combination Figure 6 , Figure 12 and Figure 13 The first amplification module 101 is described in detail.

[0054] In some embodiments, reference Figure 6 , Figure 12 and Figure 13The current source 111 may include a first PMOS transistor MP1 connected between the power supply node Vcc and the fifth node net5. The gate of the first PMOS transistor MP1 receives the sampling clock signal CLK1. When the sampling clock signal CLK1 is low, the gate of the first PMOS transistor MP1 is turned on, providing current to the fifth node net5, so that the comparison unit 121 is in working state, comparing the received data signal DQ and the reference signal Vref.

[0055] In some embodiments, continue to refer to Figure 12 In addition to including the first PMOS transistor MP1, the current source 111 may further include a second PMOS transistor MP2, connected between the power supply node Vcc and the first PMOS transistor MP1. The gate of the second PMOS transistor MP2 receives the enable signal SampEnN. When the sampling clock signal CLK1 is low and the enable signal SampEnN is also low, both the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on, providing current to the fifth node net5, thereby putting the comparison unit 121 into operation and comparing the received data signal DQ with the reference signal Vref.

[0056] Furthermore, by setting a second PMOS transistor MP2 based on the on or off state of the enable signal SampEnN, it is beneficial to control the second PMOS transistor MP2 to turn off based on the enable signal SampEnN when the device containing the data receiving circuit is in a low-power mode, thereby shutting down the data receiving circuit corresponding to the second PMOS transistor MP2 and reducing the overall power consumption of the device containing the data receiving circuit.

[0057] In some embodiments, reference Figure 6 , Figure 12 and Figure 13 The comparison unit 121 may include: a third PMOS transistor MP3, connected between the fifth node net5 and the first node n_stg1, the gate of the third PMOS transistor MP3 receiving the data signal DQ; and a fourth PMOS transistor MP4, connected between the fifth node net5 and the second node p_stg1, the gate of the fourth PMOS transistor MP4 receiving the reference signal Vref.

[0058] It should be noted that the level changes of the data signal DQ and the reference signal Vref are asynchronous. This causes the turn-on time of the third PMOS transistor MP3, which receives the data signal DQ, to differ from the turn-on time of the fourth PMOS transistor MP4, which receives the reference signal Vref. Furthermore, at the same time, the conduction degree of the third PMOS transistor MP3 differs from that of the fourth PMOS transistor MP4. Understandably, because the conduction degree of the third PMOS transistor MP3 differs from that of the fourth PMOS transistor MP4, their current shunting capabilities at the fifth node net5 also differ, resulting in a difference between the voltage at the first node n_stg1 and the voltage at the second node p_stg1.

[0059] In one example, when the level of the data signal DQ is lower than the level of the reference signal Vref, the conduction level of the third PMOS transistor MP3 is greater than that of the fourth PMOS transistor MP4. This causes more current to flow into the path of the third PMOS transistor MP3 at the fifth node net5, making the current at the first node n_stg1 greater than the current at the second node p_stg1. Consequently, the level of the first voltage signal output by the first node n_stg1 is higher, and the level of the second voltage signal output by the second node p_stg1 is lower.

[0060] In some embodiments, reference Figure 4 The first amplification module 101 may further include a first reset unit 131, connected to the first node n_stg1 and the second node p_stg1, configured to reset the first node n_stg1 and the second node p_stg1. Thus, after the data receiving circuit completes the reception of a data signal DQ and a reference signal Vref, and the output of the first output signal Vout and the second output signal VoutN, the first reset unit 131 can restore the level values ​​at the first node n_stg1 and the second node p_stg1 to their initial values, facilitating subsequent data reception and processing by the data receiving circuit.

[0061] In some embodiments, continue to refer to Figure 6 , Figure 12 and Figure 13 The first reset unit 131 may include: a first NMOS transistor MN1, connected between the first node n_stg1 and the ground terminal, the gate of the first NMOS transistor MN1 receiving the sampling clock signal CLK1; and a second NMOS transistor MN2, connected between the second node p_stg1 and the ground terminal, the gate of the second NMOS transistor MN2 receiving the sampling clock signal CLK1.

[0062] In one example, when both the sampling clock signal CLK1 and the enable signal SampEnN are low, the first PMOS transistor MP1 and the second PMOS transistor MP2 are both turned on, while the first NMOS transistor MN1 and the second NMOS transistor MN2 are both turned off to ensure the normal operation of the data receiving circuit. At the same time, the first NMOS transistor MN1 and the second NMOS transistor MN2 can serve as the load of the first amplification module 101 to increase the amplification gain of the first amplification module 101. When the sampling clock signal CLK1 is high, the first PMOS transistor MP1 is turned off, while the first NMOS transistor MN1 and the second NMOS transistor MN2 are both turned on. This pulls down the voltage at the first node n_stg1 and the voltage at the second node p_stg1 to reset the first node n_stg1 and the second node p_stg1.

[0063] The decision feedback equalization module 103 is described in detail below through two examples. In one example, the decision feedback equalization module 103 is connected to the first node n_stg1 and the second node p_stg1 in the first amplification module 101 to adjust the first voltage signal and the second voltage signal output by the first amplification module 101. In another example, the decision feedback equalization module 103 is connected to the first internal node n_stg2 and the second internal node p_stg2 in the second amplification module 102 to adjust the voltage at the first internal node n_stg2 and the voltage at the second internal node p_stg2.

[0064] In some embodiments, reference Figure 6 and Figure 12 The first node n_stg1 can serve as the first feedback node, and the second node p_stg1 can serve as the second feedback node. The feedback signals include the first feedback signal fbn and the second feedback signal fbp. The decision feedback equalization module 103 can include: a first decision feedback unit 113, connected to the first node n_stg1 and the fifth node net5, configured to perform decision feedback equalization on the first node n_stg1 based on the first feedback signal fbn to adjust the first voltage signal; and a second decision feedback unit 123, connected to the second node p_stg1 and the fifth node net5, configured to perform decision feedback equalization on the second node p_stg1 based on the second feedback signal fbp to adjust the second voltage signal.

[0065] The first decision feedback unit 113 is used to adjust the current in the third PMOS transistor MP3 to adjust the voltage at the first node n_stg1, which is equivalent to adjusting the data signal DQ. The second decision feedback unit 123 is used to adjust the current in the fourth PMOS transistor MP4 to adjust the voltage at the second node p_stg1, which is equivalent to adjusting the reference signal Vref.

[0066] In some embodiments, reference Figure 5 The decision feedback equalization module 103 may include: a first adjustment unit 12, configured to adjust the equivalent resistance value of the first adjustment unit 12 in response to the first coded signal group C1, wherein the equivalent resistance value of the first adjustment unit 12 is recorded as a first resistance value, and the first coded signal group C1 is based on the first control signal group PerPin.<m:0> and / or the second control signal group PerByte<N:0> The first compilation yields a second adjustment unit 13 connected in parallel with the first adjustment unit 12, configured to adjust the equivalent resistance value of the second adjustment unit 13 in response to the second coded signal group C2. The equivalent resistance value of the second adjustment unit 13 is recorded as the second resistance value. The second coded signal group C2 is based on the first control signal group PerPin.<m:0> Or the second control signal group PerByte<N:0> The second compilation is performed to obtain the equivalent resistance value of the first adjustment unit 12 and the second adjustment unit 13 connected in parallel, which is related to the adjustment capability of the decision feedback equalization module 103 on the first output signal Vout and the second output signal VoutN.

[0067] The first adjustment unit 12 and the second adjustment unit 13 together constitute the adjustment unit 1132. The adjustment unit 1132 is the load of the decision feedback equalization module 103. The adjustment capability of the decision feedback equalization module 103 changes with the change in the equivalent resistance value of the load.

[0068] In some examples, a portion of the encoded signals in the first encoded signal group C1 can be generated by the first control signal group PerPin.<m:0> Or the second control signal group PerByte<N:0> The remaining encoded signals can be obtained through compilation, and can be obtained from the first control signal group PerPin.<m:0> Second control signal group PerByte<N:0> Obtained through compilation.

[0069] In some embodiments, reference Figure 7The first coded signal group C1 includes a zero-order coded signal Code0 and a first coded signal Code1; the first adjustment unit 12 may include a zero-order transistor M00 and a first transistor M01 connected in parallel, wherein the channel width-to-length ratio of the zero-order transistor M00 is n and the channel width-to-length ratio of the first transistor M01 is 2n, and the gates of the zero-order transistor M00 and the first transistor M01 respectively receive the zero-order coded signal Code0 and the first coded signal Code1. The second coded signal group C2 includes a second coded signal Code2, a third coded signal Code3, and a fourth coded signal Code4; the second adjustment unit 13 includes a second transistor M02, a third transistor M03, and a fourth transistor M04 connected in parallel. The channel width-to-length ratio of the second transistor M02 is n, the channel width-to-length ratio of the third transistor M03 is 2n, and the channel width-to-length ratio of the fourth transistor M04 is 2n. The gates of the second transistor M02, the third transistor M03, and the fourth transistor M04 respectively receive the second coded signal Code2, the third coded signal Code3, and the fourth coded signal Code4, where n is an integer greater than or equal to 1.

[0070] In other words, the channel width-to-length ratios of the fourth transistor M04, the third transistor M03, and the first transistor M01 are the same, and this ratio is defined as the first channel width-to-length ratio; the channel width-to-length ratios of the zeroth transistor M00 and the second transistor M02 are the same, and this ratio is defined as the second channel width-to-length ratio. The first channel width-to-length ratio is greater than the second channel width-to-length ratio.

[0071] In a specific example, the width-to-length ratio of the first channel can be twice that of the width-to-length ratio of the second channel.

[0072] In a more specific example, the channel lengths of the zeroth transistor M00, the first transistor M01, the second transistor M02, the third transistor M03, and the fourth transistor M04 can all be the same. Correspondingly, the ratio of the channel widths of the zeroth transistor M00, the first transistor M01, the second transistor M02, the third transistor M03, and the fourth transistor M04 is 1:2:1:2:2. The load at the sixth node net6 is related to the equivalent capacitance of each transistor. The smaller the channel width of the transistor, the smaller the equivalent capacitance of the transistor. Compared with the technical solution where the ratio of the channel widths of the zeroth transistor, the first transistor, the second transistor, the third transistor, and the fourth transistor is 1:2:1:2:4, the ratio of the channel widths of the zeroth transistor M00, the first transistor M01, the second transistor M02, the third transistor M03, and the fourth transistor M04 is 1:2:1:2:2. Since the channel width of the fourth transistor M04 is smaller, the total size of the transistors required by the first adjustment unit 12 is also smaller, resulting in a smaller equivalent capacitance at the sixth node net6. Consequently, the load at the sixth node net6 is also smaller, which helps to reduce the load on the data receiving circuit.

[0073] Among them, the zeroth transistor M00, the first transistor M01, the second transistor M02, the third transistor M03, and the fourth transistor M04 are all PMOS transistors, and are all connected in parallel between the sixth node net6 and the first node n_stg1. They receive their respective coded signals to control the conduction or cutoff between the sixth node net6 and the first node n_stg1, thereby making the overall equivalent resistance value of the adjustment unit 1132 flexibly controllable, thereby realizing flexible control of the voltage at the first node n_stg1, and thus adjusting the decision feedback capability.

[0074] It is understandable that the resistance of each of the zeroth transistor M00, the first transistor M01, the second transistor M02, the third transistor M03, and the fourth transistor M04 is related to their respective channel width-to-length ratios. The channel width-to-length ratios of the zeroth transistor M00, the first transistor M01, the second transistor M02, the third transistor M03, and the fourth transistor M04 are n:2n:n:2n:2n, respectively. Then, the equivalent resistances of the corresponding zeroth transistor M00, the first transistor M01, the second transistor M02, the third transistor M03, and the fourth transistor M04 are 2R:1R:2R:1R:1R, respectively, so that the equivalent resistance value of the adjustment unit 1132 can be linearly adjusted, thereby realizing the linear adjustment of the voltage at the first node n_stg1 and the voltage at the second node p_stg1.

[0075] In some embodiments, by adjusting the conduction of each transistor (i.e., the zeroth to the fourth transistor) in the first adjustment unit 12 and the second adjustment unit 13, only 5 transistors are needed to obtain eight linear DFE adjustment capabilities. Furthermore, as the foregoing analysis shows, the channel width of the transistors in the first adjustment unit 12 is relatively small, and the total size of the transistors used in the first adjustment unit 12 and the second adjustment unit 13 is relatively small, resulting in a smaller equivalent capacitance. This smaller equivalent capacitance places a smaller load on the sixth node net6, thereby reducing the load on the data receiving circuit.

[0076] In some embodiments, reference Figure 7 Either the first decision feedback unit 113 or the second decision feedback unit 123 may include: a switching unit 1131 configured to conduct the fifth node net5 and the sixth node net6 in response to a feedback signal; and an adjustment unit 1132 connected between the sixth node net6 and the output node, wherein the output node is one of the first node n_stg1 and the second node p_stg1, configured to adjust the equivalent resistance value between the sixth node net6 and the output node in response to a control signal; wherein, in the first decision feedback unit 113, the feedback signal is the first feedback signal fbn, the output node is the first node n_stg1, and the switching unit 1131 responds to the first feedback signal fbn; and in the second decision feedback unit 123, the feedback signal is the second feedback signal fbp, the output node is the second node p_stg1, and the switching unit 1131 responds to the second feedback signal fbp.

[0077] In this system, the switching unit 1131 in the first decision feedback unit 113 is either on or off based on the first feedback signal fbn, and the switching unit 1131 in the second decision feedback unit 123 is either on or off based on the second feedback signal fbp. Whether it's the first decision feedback unit 113 or the second decision feedback unit 123, the regulating unit 1132 will only be operational when the switching unit 1131 is on, in order to regulate the voltage at the first node n_stg1 or the second node p_stg1.

[0078] In some embodiments, continue to refer to Figure 7 The switching unit 1131 may include: a fifth PMOS transistor MP5, connected between the fifth node net5 and the sixth node net6, and the gate of the fifth PMOS transistor MP5 receives a feedback signal.

[0079] It should be noted that, Figure 7 In this example, the gate of the fifth PMOS transistor MP5 receives the first feedback signal fbn, and the output node is the first node n_stg1. Figure 7The diagram shows the specific structure of the first decision feedback unit 113. In practical applications, the specific structure of the second decision feedback unit 123 is similar to that of the first decision feedback unit 113. The difference is that the gate of the fifth PMOS transistor MP5 in the second decision feedback unit 123 receives the second feedback signal fbp, and the output node is the second node p_stg1. Everything else is the same.

[0080] In one example, the first feedback signal fbn received by the switching unit 1131 in the first decision feedback unit 113 is low, and the fifth PMOS transistor MP5 is turned on. At this time, the adjustment unit 1132 adjusts the voltage at the first node n_stg1 based on the control signal. In another example, the second feedback signal fbp received by the switching unit 1131 in the second decision feedback unit 123 is low, and the fifth PMOS transistor MP5 is turned on. At this time, the adjustment unit 1132 adjusts the voltage at the second node p_stg1 based on the control signal.

[0081] refer to Figure 8 The decision feedback equalization module 103 may further include: a decoding circuit 14, used for processing the first control signal group PerPin<m:0> Second control signal group PerByte<N:0> Perform logical operations to obtain the first coded signal group C1 and the second coded signal group C2.

[0082] Second control signal group PerByte<N:0> It contains the highest bit data, i.e., the data at the Nth bit position, and also the highest two bits data, i.e., the data at the Nth bit position and the (N-1)th bit position. First control group PerPin<m:0> The data with the highest bit position, i.e., the data at the m-th bit position.

[0083] Decoding circuit 14 can be configured such that: if the second control signal group PerByte<N:0> If the highest bit of the data is 1, then both the third encoding signal Code3 and the fourth encoding signal Code4 are in a valid state. The third transistor M03 turns on in response to the valid state of the third encoding signal M03, and the fourth transistor M04 turns on in response to the valid state of the fourth encoding signal Code4.

[0084] The channel width-to-length ratio of the third transistor M03 and the channel width-to-length ratio of the fourth transistor M04 are both twice that of the second transistor M02. Compared to the adjustment capability of the decision feedback equalization module 103 when only the second transistor M02 is turned on, the decision feedback equalization module 103 has at least 4 times the adjustment capability when both the third transistor M03 and the fourth transistor M04 are turned on. That is, at least 4 times the adjustment capability can be obtained when only two transistors are turned on.

[0085] Decoding circuit 14 can be configured such that: if the second control signal group PerByte<N:0> If the two highest bits of the data are both 1, then the first encoded signal Code1 is valid; or, if the first control signal group PerPin...<m:0> If the highest bit of the data is 1, then the first encoding signal Code1 is in an active state; wherein, the first transistor M01 is turned on in response to the active state of the first encoding signal Code1.

[0086] Compared to the adjustment capability of the decision feedback equalization module 103 during the conduction of the zeroth transistor M00, the decision feedback equalization module 103 has at least twice the adjustment capability during the conduction of the first transistor M01. In other words, at least twice the adjustment capability can be obtained with only one transistor being turned on.

[0087] It is understandable that if the third transistor M03 is an NMOS transistor, then the third encoding signal Code3 is valid when it is 1; if the third transistor M03 is a PMOS transistor, then the third encoding signal Code3 is valid when it is 0. Similarly, if the fourth transistor M04 is an NMOS transistor, then the fourth encoding signal Code4 is valid when it is 1; if the fourth transistor M04 is a PMOS transistor, then the fourth encoding signal Code4 is valid when it is 0. Likewise, if the first transistor M01 is an NMOS transistor, then the first encoding signal Code1 is valid when it is 1; if the first transistor M01 is a PMOS transistor, then the first encoding signal Code1 is valid when it is 0.

[0088] In some embodiments, the first control signal group PerPin<m:0> It can be 2-bit data, the first control signal group PerPin<m:0> Including the zeroth PerPin <0> and the first control signal PerPin <1> Second control signal group PerByte<N:0> It can be 3-bit data, the second control signal group PerByte<N:0> Including the second control signal PerByte <0> Third control signal PerByte <1> and the fourth control signal PerByte <2> .

[0089] In some embodiments, the decoding circuit 14 can be configured to: if the fourth control signal PerByte <2> If the value is 1, then both the third encoding signal Code3 and the fourth encoding signal Code4 are 0, and the corresponding third transistor M03 and fourth transistor M04 are turned on. That is, a value of 0 for the third encoding signal Code3 indicates that the third encoding signal Code3 is in an active state, and a value of 0 for the fourth encoding signal Code4 indicates that the fourth encoding signal Code4 is in an active state.

[0090] In some embodiments, the decoding circuit 14 can also be configured to, if the fourth control signal PerByte <2> and the third control signal PerByte <1> If both are 1, then the first encoding signal Code1 is 0, and correspondingly, the first transistor M01 is turned on; or, if the first control signal PerPin <1> If the value is 1, then the first encoded signal Code1 is 0, and correspondingly, the first transistor M01 is turned on. That is, a value of 0 for the first encoded signal Code1 indicates that the first encoded signal Code1 is in a valid state. (Reference) Figures 9 to 11 The decoding circuit 14 may include three first inverters inv1, each of which receives the zeroth control signal PerPin. <0> Second control signal PerByte <0> and the fourth control signal PerByte <2> The corresponding outputs are the zeroth encoding signal Code0, the second encoding signal Code2, and the fourth encoding signal Code4; the NOR gate Nor receives the third control signal PerByte at its two inputs. <1> and the fourth control signal PerByte <2> It outputs the third encoded signal Code3; logic circuit 141, the three input terminals of logic circuit 141 respectively receive the first control signal PerPin <1> Third control signal PerByte <1> and the fourth control signal PerByte <2> and output the first encoded signal Code1; wherein, if the third control signal PerByte <1> and the fourth control signal PerByte <2> If all are logic high, then the first encoding signal Code1 is logic low; if the third control signal PerByte... <1> and the fourth control signal PerByte <2> If at least one of them is at a logic low level, then the first encoding signal Code1 and the first control signal PerPin <1> The voltage levels are opposite in phase.

[0091] The zeroth encoding signal Code0 is the zeroth control signal PerPin. <0> The inverted signal; the second encoded signal Code2 is the second control signal PerByte. <0> The inverted signal; the fourth encoded signal Code4 is the fourth control signal PerByte. <2> The inverted signal. Correspondingly, the zeroth transistor M00 is based on the first control signal group PerPin corresponding to a specific data port.<m:0> Whether the second transistor M02 and the fourth transistor M04 are turned on or off is based on the second control signal group PerByte corresponding to all data ports.<N:0> control.

[0092] The first encoded signal Code1 is generated by the first control signal PerPin. <1> Third control signal PerByte <1> and the fourth control signal PerByte <2> Obtained through compilation. Correspondingly, whether the first transistor M01 is turned on or off is based on the first control signal group PerPin.<m:0> Second control signal group PerByte<N:0> Joint control. If the third control signal PerByte <1> and the fourth control signal PerByte <2> If all signals are at logic high, then the first transistor M01 is turned on; if the third control signal PerByte... <1> and the fourth control signal PerByte <2> At least one of them is at a logic low level, and the first control signal PerPin <1> If the logic level is high, the first transistor M01 is turned on; if the third control signal PerByte... <1> and the fourth control signal PerByte <2> At least one of them is at a logic low level, and the first control signal PerPin <1> If the logic level is low, the first transistor M01 will not be turned on.

[0093] Continue to refer to Figure 10 The logic circuit 141 may include an OR gate 1411, whose two inputs respectively receive a third control signal PerByte. <1> The inverted signal and the fourth control signal PerByte <2> The inverted signal; NAND gate 1412, one input of NAND gate 1412 receives the first control signal PerPin. <1> The inverted signal is connected to the output of the OR gate 1411; the second inverter inv2 is connected to the output of the NAND gate 1412, and the output of the second inverter inv2 outputs the first encoded signal Code1.

[0094] Third control signal PerByte <1> The inverted signal is the third inverted control signal DfeTrim <3> Fourth control signal PerByte <2> The inverted signal is the fourth inverted control signal DfeTrim <4> First control signal PerPin <1> The inverted signal is the first inverted control signal DfePerPin. <1> .

[0095] Continue to refer to Figure 11The logic circuit 141 may further include: a third inverter inv3, which receives the first control signal PerPin. <1> And output the first control signal PerPin <1> The inverted signal is the first inverted control signal DfePerPin <1> Two fourth inverters, inv4, each receiving a third control signal, PerByte. <1> and the fourth control signal PerByte <2> and output the third control signal PerByte respectively. <1> The inverted signal and the fourth control signal PerByte <2> The inverted signal, i.e., the third inverted control signal DfeTrim, is output respectively. <3> and the fourth inverting control signal DfeTrim <4> .

[0096] Using the aforementioned decision feedback equalization module 103, the zeroth transistor M00, the first transistor M01, the second transistor M02, the third transistor M03, and the fourth transistor M04 are each controlled to be turned on or off by different encoded signals. This not only enables the decision feedback equalization function to be turned off, but also enables the adjustment capability of decision feedback equalization of 7 different magnitudes.

[0097] Table 1 illustrates the channel width-to-length ratio of the transistors (i.e., the zeroth to the fourth transistors) corresponding to the zeroth to the fourth encoded signals when the first and second control signal groups have different values. Here, "0" for the zeroth to the fourth encoded signals indicates that the transistor is off, "1" indicates that the transistor with a channel width-to-length ratio of n is on, and "2" indicates that the transistor with a channel width-to-length ratio of 2n is on. DFE represents the equivalent width-to-length ratio of the equivalent transistor obtained by connecting the first adjustment unit 12 and the second adjustment unit 13 in parallel. This equivalent width-to-length ratio is related to the equivalent resistance value. The larger the equivalent width-to-length ratio, the smaller the equivalent resistance value, that is, the smaller the equivalent resistance of the adjustment unit in the decision feedback equalization module 103.

[0098] Table 1

[0099]

[0100]

[0101] It should be noted that in Table 1, Code0 = 0 indicates that the zeroth transistor M00 corresponding to Code0 is off, and Code0 = 1 indicates that the zeroth transistor M00 is on; Code1 = 0 indicates that the first transistor M01 corresponding to Code1 is off, and Code1 = 2 indicates that the first transistor M01 is on; Code2 = 0 indicates that the second transistor M02 corresponding to Code2 is off, and Code2 = 1 indicates that the second transistor M02 is on; Code3 = 0 indicates that the third transistor M03 corresponding to Code3 is off, and Code3 = 2 indicates that the third transistor M03 is on; Code4 = 0 indicates that the fourth transistor M04 corresponding to Code4 is off, and Code4 = 2 indicates that the fourth transistor M04 is on; Code5 = 0 indicates that the fifth transistor M05 corresponding to Code5 is off, and Code5 = 2 indicates that the fifth transistor M05 is on.

[0102] In Table 1, the first bit of PerByte (3 bits) is the fourth control signal PerByte, from the first bit to the last bit. <2> Third control signal PerByte <1> Second control signal PerByte <0> In PerPin (2 bits), the first bit from the first bit to the last bit represents the first control signal PerPin. <1> Zero control signal PerPin <0> A DFE of 0 indicates that the decision feedback equalization function is not enabled. When all four control signals are 0, DFE is not enabled. DFE values ​​of 1, 2, 3, 4, 5, 6, 7, and 8 indicate that the decision feedback equalization function is enabled, and the adjustment unit can have eight different equivalent transistors. The channel equivalent width-to-length ratio of the eight different equivalent transistors is 1:2:3:4:5:6:7:8. Thus, the decision feedback equalization module 103 can have different adjustment capabilities for the first output signal and the second output signal. It is understood that the decision feedback equalization module 103 provided in this embodiment, in addition to having the decision feedback equalization function disabled, also has eight adjustable adjustment capabilities, namely, adjustment capabilities of 1x, 2x, 3x, 4x, 5x, 6x, 7x, and 8x respectively.

[0103] In some specific examples, the first control signal group PerPin<m:0> The control signals can be provided by mode register 70 (MR70), mode register 71 (MR71), mode register 72 (MR72), or mode register 73 (MR73). Second control signal group PerByte<N:0> The control signals in the mode register 24 (MR24) can be provided.

[0104] Figure 12PerPin is the first control signal group in the decision feedback equalization module 103 of this embodiment.<m:0> Second control signal group PerByte<N:0> A schematic diagram of an equivalent circuit between the decision enable signal DfeEn and the decision feedback equalization module 103 is shown. When the decision enable signal DfeEn is active, the decision feedback equalization module 103 activates its decision feedback equalization function; when the decision enable signal DfeEn is inactive, the decision feedback equalization module 103 does not activate its decision feedback equalization function, i.e., DFE is not enabled. It is understood that the decision enable signal DfeEn is an equivalent signal, and the data receiving circuit does not need to receive this decision enable signal DfeEn.

[0105] In some embodiments, taking the case where the decision enable signal DfeEn is 0 as an example, DFE is not enabled; correspondingly, the first control signal group PerPin...<m:0> Second control signal group PerByte<N:0> The equivalent circuit between the decision enable signal DfeEn and the input gate Nor1 includes a first NOR gate, each input of which receives a first control group PerPin.<m:0> The control signals in the code, namely the first control signal PerPin <1> and the zeroth control signal PerPin <0> The second NOR gate (Nor2) receives the second control signal group (PerByte) at each input.<N:0> The control signals in the code, namely the fourth control signal PerByte <2> Third control signal PerByte <1> Second control signal PerByte <0> The second NAND gate 1413 has two input terminals connected to the output terminals of the first NOR gate Nor1 and the second NOR gate Nor2, respectively. The output terminal of the second NAND gate 1413 outputs the decision enable signal DfeEn.

[0106] refer to Figure 12 Fourth control signal PerByte <2> Third control signal PerByte <1> Second control signal PerByte <0> First control signal PerPin <1> and the zeroth control signal PerPin <0> When both are 0, the decision enable signal DfeEn is 0, indicating an invalid state. Correspondingly, the decision feedback equalization module 103 does not enable the decision feedback equalization function, which is consistent with the case where DFE is 0 in Table 1 above. Fourth control signal PerByte <2> Third control signal PerByte <1> Second control signal PerByte <0> First control signal PerPin <1> and the zeroth control signal PerPin <0> If at least one control signal is 1, then the decision enable signal DfeEn is 1, which is an effective state. The decision feedback equalization module 103 enables the decision feedback equalization function, and the decision feedback equalization module 103 has adjustable adjustment capability. The specific adjustable implementation method can be referred to the foregoing description, and will not be repeated here.

[0107] In other embodiments, reference is made to... Figure 14 The first internal node n_stg2 serves as the first feedback node, and the second internal node p_stg2 serves as the second feedback node. The feedback signals include the first feedback signal fbn and the second feedback signal fbp. The decision feedback equalization module 103 may include: a first decision feedback unit 113, connected to the first internal node n_stg2 and ground, configured to perform decision feedback equalization on the first internal node n_stg2 based on the first feedback signal fbn; and a second decision feedback unit 123, connected to the second internal node p_stg2 and ground, configured to perform decision feedback equalization on the second internal node p_stg2 based on the second feedback signal fbp.

[0108] The first decision feedback unit 113 is used to adjust the current in the third NMOS transistor MN3 to adjust the voltage at the first internal node n_stg2, and the second decision feedback unit 123 is used to adjust the current in the fourth NMOS transistor MN4 to adjust the voltage at the second internal node p_stg2.

[0109] It should be noted that when the decision feedback equalization module 103 is connected to the first internal node n_stg2 and the second internal node p_stg2 in the second amplification module 102, the specific structure of the first decision feedback unit 113 and the second decision feedback unit 123 and Figure 7 Similar to the example shown, the only difference is the type of MOS transistor in the switching unit 1131. For instance, when the decision feedback equalization module 103 is connected to the first node n_stg1 and the second node p_stg1 in the first amplification module 101, the MOS transistor in the switching unit 1131 is a PMOS transistor. When the decision feedback equalization module 103 is connected to the first internal node n_stg2 and the second internal node p_stg2 in the second amplification module 102, the MOS transistor in the switching unit 1131 is an NMOS transistor. Details identical or corresponding to those described above will not be repeated here. The following provides a detailed explanation of the differences between the decision feedback equalization module 103 connected to the second amplification module 102 and the decision feedback equalization module 103 connected to the first amplification module 101.

[0110] refer to Figure 14Each of the first decision feedback unit 113 and the second decision feedback unit 123 includes: a switching unit 1131 configured to conduct the first internal node n_stg2 and the sixth node net6, or the second internal node p_stg2 and the sixth node net6, in response to a feedback signal; and an adjustment unit 1132 connected between the sixth node net6 and ground, configured to adjust the equivalent resistance value between the sixth node net6 and ground in response to a control signal. In the first decision feedback unit 113, the feedback signal is a first feedback signal fbn, and the switching unit 1131 conducts the first internal node n_stg2 and the sixth node net6 in response to the first feedback signal fbn. In the second decision feedback unit 123, the feedback signal is a second feedback signal fbp, and the switching unit 1131 conducts the second internal node p_stg2 and the sixth node net6 in response to the second feedback signal fbp.

[0111] Continue to refer to Figure 14 The switching unit 1131 may include: an eleventh NMOS transistor MN11, connected between the first internal node n_stg2 and the sixth node net6, with its gate receiving a first feedback signal fbn; or connected between the second internal node p_stg2 and the sixth node net6, with its gate receiving a second feedback signal fbp. It can be understood that the eleventh NMOS transistor MN11 is equivalent to... Figure 7 The fifth PMOS transistor, MP5.

[0112] In one example, the first feedback signal fbn received by the switching unit 1131 in the first decision feedback unit 113 is low, and the eleventh NMOS transistor MN11 is turned on. At this time, the adjustment unit 1132 adjusts the voltage at the first internal node n_stg2 based on the control signal. The second feedback signal fbp received by the switching unit 1131 in the second decision feedback unit 123 is low, and the eleventh NMOS transistor MN11 is turned on. At this time, the adjustment unit 1132 adjusts the voltage at the second internal node p_stg2 based on the control signal.

[0113] It should be noted that, Figure 14 Taking the NMOS transistor included in the adjustment unit 1132 as an example, in actual applications, the specific structure of the adjustment unit 1132 is similar to that in the aforementioned embodiment, and will not be described again here.

[0114] In some embodiments, reference Figures 4 to 14The second amplification module 102 may include: an input unit 112, connected to the first node n_stg1 and the second node p_stg1, configured to compare the first voltage signal and the second voltage signal, and provide a third voltage signal to the seventh node n_stg2 and a fourth voltage signal to the eighth node p_stg2, wherein the second amplification module 102 has a first internal node n_stg2 and a second internal node p_stg2, and the seventh node n_stg2 is the first internal node n_stg2, and the eighth node p_stg2 is the second internal node p_stg2; and a latching unit 122, configured to amplify and latch the third voltage signal and the fourth voltage signal, and output a first output signal Vout to the third node net3 and a second output signal VoutN to the fourth node net4.

[0115] The input unit 112 is used to compare the first voltage signal and the second voltage signal to output the third voltage signal and the fourth voltage signal; the latch unit 122 is used to output a high-level signal to the third node net3 and a low-level signal to the fourth node net4 according to the third voltage signal and the fourth voltage signal, or output a low-level signal to the third node net3 and a high-level signal to the fourth node net4.

[0116] In some embodiments, reference Figure 6 , Figure 13 and Figure 14 The input unit 112 may include: a third NMOS transistor MN3, connected between the seventh node n_stg2 and ground, the gate of the third NMOS transistor MN3 receiving a first voltage signal; and a fourth NMOS transistor MN4, connected between the eighth node p_stg2 and ground, the gate of the fourth NMOS transistor MN4 receiving a second voltage signal.

[0117] In one example, when the first voltage signal level output by the first node n_stg1 is higher than the second voltage signal level output by the second node p_stg1, the conduction level of the third NMOS transistor MN3 is greater than that of the fourth NMOS transistor MN4. This causes the voltage at the seventh node n_stg2 to be less than the voltage at the eighth node p_stg2, which in turn causes the conduction level of the fifth NMOS transistor MN5 to be greater than that of the sixth NMOS transistor MN6. The voltage at the third node net3 is less than the voltage at the fourth node net4. Therefore, the conduction level of the seventh PMOS transistor MP7 is greater than that of the sixth PMOS transistor MP6. The latch unit 122 forms positive feedback amplification, which further causes the first output signal Vout output by the third node net3 to be low and the second output signal VoutN output by the fourth node net4 to be high.

[0118] In some embodiments, continue to refer to Figure 6 , Figure 13 and Figure 14 The latch unit 122 may include: a fifth NMOS transistor MN5, connected between the seventh node n_stg2 and the third node net3, the gate of the fifth NMOS transistor MN5 receiving the second output signal VoutN; a sixth NMOS transistor MN6, connected between the eighth node p_stg2 and the fourth node net4, the gate of the sixth NMOS transistor MN6 receiving the first output signal Vout; a sixth PMOS transistor MP6, connected between the power supply node Vcc and the third node net3, the gate of the sixth PMOS transistor MP6 receiving the second output signal VoutN; and a seventh PMOS transistor MP7, connected between the power supply node Vcc and the fourth node net4, the gate of the seventh PMOS transistor MP7 receiving the first output signal Vout.

[0119] In some embodiments, reference Figure 4 The second amplification module 102 may further include a second reset unit 142, connected to the latch unit 122, configured to reset the latch unit 122. Thus, after the data receiving circuit completes the reception of a data signal DQ and a reference signal Vref, and the output of the first output signal Vout and the second output signal VoutN, the second reset unit 142 can restore the level values ​​at the third node net3 and the fourth node net4 to their initial values, facilitating the subsequent data receiving circuit to perform the next data reception and processing.

[0120] In some embodiments, continue to refer to Figure 6 , Figure 13 and Figure 14 The second reset unit 142 may include: an eighth PMOS transistor MP8 connected between the power supply node Vcc and the third node net3; and a ninth PMOS transistor MP9 connected between the power supply node Vcc and the fourth node net4. The gates of the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are both responsive to the inverted signal CLK2 of the sampling clock signal CLK1.

[0121] In one example, when the sampling clock signal CLK1 and the enable signal SampEnN are low, both the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on, while the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned off. The inverted signal CLK2 of the sampling clock signal CLK1 is high, and both the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are turned off to ensure the normal operation of the data receiving circuit. When the sampling clock signal CLK1 is high, the first PMOS transistor MP1 is turned off, while both the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned on. The inverted signal CLK2 of the sampling clock signal CLK1 is low, and both the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are turned on. This pulls up the voltage at the third node net3 and the fourth node net4 to reset the third node net3 and the fourth node net4.

[0122] In some embodiments, reference Figure 13 Based on the inclusion of the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 in the second reset unit 142, the second reset unit 142 may further include: a tenth PMOS transistor MP10 connected between the power supply node Vcc and the seventh node n_stg2; and an eleventh PMOS transistor MP11 connected between the power supply node Vcc and the eighth node p_stg2. The gates of both the tenth PMOS transistor MP10 and the eleventh PMOS transistor MP11 respond to the inverted signal CLK2 of the sampling clock signal CLK1. Thus, when the data receiving circuit does not need to receive the data signal DQ and the reference signal Vref, it is beneficial to further ensure that the voltage at the third node net3 and the voltage at the fourth node net4 are pulled up, thereby achieving the reset of the third node net3 and the fourth node net4.

[0123] The following provides a detailed explanation of the specific connection relationship between the offset compensation module 104 and the second amplification module 102.

[0124] In some embodiments, reference Figure 6 The first node n_stg1 serves as the first feedback node, and the second node p_stg1 serves as the second feedback node. The data receiving circuit may also include an offset compensation module 104, which is connected to the seventh node n_stg2 and the eighth node p_stg2 and is configured to compensate for the offset voltage of the input unit 112.

[0125] In some embodiments, reference Figure 6The offset compensation module 104 may include: a first offset compensation unit 114 connected between the seventh node n_stg2 and ground; and a second offset compensation unit 124 connected between the eighth node p_stg2 and ground. The first offset compensation unit 114 is used to compensate for the parameters of the third NMOS transistor MN3; the second offset compensation unit 124 is used to compensate for the parameters of the fourth NMOS transistor MN4. The first offset compensation unit 114 and the second offset compensation unit 124 can adjust the offset voltage of the data receiving circuit by compensating for the parameters of the third NMOS transistor MN3 and the fourth NMOS transistor MN4.

[0126] In some embodiments, reference Figure 6 The first offset compensation unit 114 may include: at least two sets of transistor groups connected in parallel, each transistor group including: a seventh NMOS transistor MN7, the first terminal of the seventh NMOS transistor MN7 being connected to the seventh node n_stg2, and the gate of the seventh NMOS transistor MN7 being connected to the first node n_stg1; and a seventh MOS transistor M7, which is configured one-to-one with the seventh NMOS transistor MN7, and is connected between the second terminal of the seventh NMOS transistor MN7 and the ground terminal, with the gate of the seventh MOS transistor M7 receiving the first mismatch adjustment signal Offset_1. It should be noted that, for the sake of simplicity in the illustration, Figure 6 Only one group of transistors in the first offset compensation unit 114 is shown in the diagram.

[0127] Thus, the conduction level of the seventh NMOS transistor MN7 can be controlled by the first mismatch adjustment signal Offset_1 to adjust the overall equivalent resistance of the first mismatch compensation unit 114, thereby further adjusting the voltage at the seventh node n_stg2.

[0128] In some embodiments, reference Figure 6 The second offset compensation unit 124 may include: at least two sets of transistor groups connected in parallel, each transistor group including: an eighth NMOS transistor MN8, the first terminal of the eighth NMOS transistor MN8 is connected to the eighth node p_stg2, and the gate of the eighth NMOS transistor MN8 is connected to the second node p_stg1; an eighth MOS transistor M8, the eighth MOS transistor M8 and the eighth NMOS transistor M8 are arranged in a one-to-one correspondence, the eighth MOS transistor M8 is connected between the second terminal of the eighth NMOS transistor MN8 and the ground terminal, and the gate of the eighth MOS transistor M8 receives the second mismatch adjustment signal Offset_2. It should be noted that, for the sake of simplicity of the illustration, Figure 6 Only one group of transistors in the second offset compensation unit 124 is shown in the diagram.

[0129] Thus, the conduction level of the eighth NMOS transistor MN8 can be controlled by the second mismatch adjustment signal Offset_2 to adjust the overall equivalent resistance of the second offset compensation unit 124, thereby further adjusting the voltage at the eighth node p_stg2.

[0130] The following provides a detailed explanation of the specific connection relationship between the offset compensation module 104 and the first amplification module 101.

[0131] In some embodiments, the seventh node n_stg2 serves as the first feedback node and the eighth node p_stg2 serves as the second feedback node; the data receiving circuit may further include: an offset compensation module 104, connected to the first node n_stg1 and the second node p_stg1, configured to compensate the offset voltage of the comparison unit 121.

[0132] The offset compensation module 104 may include: a first offset compensation unit 114 connected between the fifth node net5 and the first node n_stg1; and a second offset compensation unit 124 connected between the fifth node net5 and the second node p_stg1. The first offset compensation unit 114 is used to compensate for the parameters of the third PMOS transistor MP3; the second offset compensation unit 124 is used to compensate for the parameters of the fourth PMOS transistor MP4. The first offset compensation unit 114 and the second offset compensation unit 124 can adjust the offset voltage of the data receiving circuit by compensating for the parameters of the third PMOS transistor MP3 and the fourth PMOS transistor MP4.

[0133] In some embodiments, reference Figure 13 The data receiving circuit may also include: a thirteenth MOSFET M1, the gate of the thirteenth MOSFET M1 receiving the sampling clock signal CLK1, the drain of the thirteenth MOSFET M1 connected to the fifth node net5, and the source of the thirteenth MOSFET M1 connected to ground.

[0134] In summary, integrating the decision feedback equalization module 103 into the data receiving circuit allows for the adjustment of the signal output by the data receiving circuit using a smaller circuit layout area and lower power consumption. Furthermore, the decision feedback equalization module 103 provided in this embodiment has adjustable adjustment capabilities for the first output signal Vout and the second output signal VoutN. This means that when the data signal DQ and / or the reference signal Vref received by the receiving module 100 change, the adjustment capabilities of the decision feedback equalization module 103 for the first output signal Vout and the second output signal VoutN can be flexibly controlled to reduce inter-symbol interference in the data receiving circuit, thereby improving the receiving performance of the data receiving circuit. Additionally, the decision feedback equalization module 103 can change its adjustment capability according to a first control signal group and a second control signal group. The first control signal group corresponds to a data port connected to the data receiving circuit, and the second control signal group corresponds to all data ports, making the adjustable range of the decision feedback equalization module 103 wider, which is beneficial for further improving the ability to reduce inter-symbol interference.

[0135] Another embodiment of this disclosure also provides a data receiving system, which will be described in detail below with reference to the accompanying drawings. Figure 2 A functional block diagram of a data receiving system provided in another embodiment of this disclosure.

[0136] refer to Figure 2 The data receiving system includes: multiple cascaded data transmission circuits 130, each data transmission circuit 130 including a data receiving circuit 110 as described in an embodiment of the present disclosure and a latching circuit 120 connected to the data receiving circuit 110, each data receiving circuit 110 being connected to a data port to receive a data signal DQ; the upper-level data transmission circuit 130 is connected to the decision feedback equalization module DFE of the lower-level data transmission circuit 130, and the output of the upper-level data transmission circuit 130 serves as the feedback signal of the decision feedback equalization module DFE of the lower-level data transmission circuit 130; the last-level data transmission circuit 130 is connected to the decision feedback equalization module DFE of the first-level data transmission circuit 130, and the output of the last-level data transmission circuit 130 serves as the feedback signal of the decision feedback equalization module DFE of the first-level data transmission circuit 130.

[0137] The latch circuit 120 is configured in a one-to-one correspondence with the data receiving circuit 110. The latch circuit 120 is used to latch and output the signal output by the data receiving circuit 110 corresponding to the latch circuit 120.

[0138] It should be noted that the output of any data transmission circuit 130 can include the following two scenarios: In some embodiments, the output of the data transmission circuit 130 refers to the output of the data receiving circuit 110. This means that the output of the previous-level data receiving circuit 110 serves as the feedback signal for the decision feedback equalization module DFE of the next-level data receiving system, and the output of the last-level data receiving circuit 110 serves as the feedback signal for the decision feedback equalization module DFE of the first-level data receiving system. Thus, the output of the data receiving circuit 110 is directly transmitted to the decision feedback equalization module DFE without passing through the latching circuit 120, which is beneficial for reducing... Low data transmission latency; in other embodiments, the output of the data transmission circuit 130 refers to the output of the latch circuit 120. It can be understood that after the output of the previous level data receiving circuit 110 is latched by the latch circuit 120 corresponding to the data receiving circuit 110, it is connected to the decision feedback equalization module DFE of the next level data receiving system via the output terminal of the latch circuit 120. That is, the output of the previous level latch circuit 120 serves as the feedback signal of the decision feedback equalization module DFE of the next level data receiving system, and the output of the last level latch circuit 120 serves as the feedback signal of the decision feedback equalization module DFE of the first level data receiving system.

[0139] It should be noted that, Figure 1 The Sino-Israeli data receiving system includes four cascaded data receiving circuits 110. Taking the phase difference of the sampling clock signals of adjacent data receiving circuits 110 as an example, the number of cascaded data receiving circuits 110 included in the data receiving system is not limited in practical applications. The phase difference of the sampling clock signals of adjacent data receiving circuits 110 can be reasonably set based on the number of cascaded data receiving circuits 110.

[0140] In some embodiments, the phase difference between the sampling clock signals of adjacent data receiving circuits 110 is 90°, and the period of the sampling clock signal is twice the period of the data signal DQ received by the data port. This is beneficial for clock routing and saves power consumption.

[0141] In summary, the data receiving system provided in another embodiment of this disclosure can flexibly control the adjustment capability of the first output signal Vout and the second output signal VoutN, so as to reduce the impact of inter-symbol interference of the data received by the data receiving circuit 110 on the data receiving circuit 110, thereby improving the receiving performance of the data receiving circuit 110 and reducing the impact of inter-symbol interference of the data on the accuracy of the signal output by the data receiving circuit 110, thereby improving the receiving performance of the data receiving system.

[0142] Another embodiment of this disclosure also provides a storage device, including: a plurality of data ports; and a plurality of data receiving systems as provided in another embodiment of this disclosure, each data receiving system corresponding to a data port. Thus, each data port in the storage device can flexibly control the received data signal DQ through the data receiving system, and improve the adjustment capability of the first output signal Vout and the second output signal VoutN, thereby improving the receiving performance of the storage device.

[0143] In some embodiments, the storage device may be a DDR memory, such as a DDR4 memory, DDR5 memory, DDR6 memory, LPDDR4 memory, LPDDR5 memory, or LPDDR6 memory. Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A data receiving circuit, characterized by comprising: include: The receiving module is configured to receive a reference signal and a data signal from a data port, compare the data signal and the reference signal in response to a sampling clock signal, and output a first output signal and a second output signal. A decision feedback equalization module, connected to the feedback node of the receiving module, is configured to perform decision feedback equalization on the receiving module based on a feedback signal to adjust the first output signal and the second output signal. The feedback signal is obtained based on previously received data, and the decision feedback equalization module responds to a first control signal group and a second control signal group to adjust the adjustment capability of the first output signal and the second output signal. The first control signal group corresponds to one of the data ports corresponding to the data signal, and the second control signal group corresponds to all of the data ports. The decision feedback equalization module includes: The first adjustment unit is configured to adjust the equivalent resistance value of the first adjustment unit in response to the first coded signal group, wherein the equivalent resistance value of the first adjustment unit is recorded as the first resistance value, and the first coded signal group is obtained based on a first compilation of the first control signal group and / or the second control signal group; The second adjustment unit connected in parallel with the first adjustment unit is configured to adjust the equivalent resistance value of the second adjustment unit in response to the second coded signal group, and the equivalent resistance value of the second adjustment unit is recorded as the second resistance value. The second coded signal group is obtained based on the second compilation of the first control signal group or the second control signal group. The equivalent resistance value of the first adjustment unit and the second adjustment unit connected in parallel is related to the adjustment capability of the decision feedback equalization module for the first output signal and the second output signal.

2. The data receiving circuit of claim 1, wherein, The first coded signal group includes a zeroth coded signal and a first coded signal; the first adjustment unit includes: The zeroth transistor and the first transistor are connected in parallel. The channel width-to-length ratio of the zeroth transistor is n, and the channel width-to-length ratio of the first transistor is 2n. The gate of the zeroth transistor and the gate of the first transistor respectively receive the zeroth encoded signal and the first encoded signal. The second coded signal group includes a second coded signal, a third coded signal, and a fourth coded signal; the second adjustment unit includes: A second transistor, a third transistor, and a fourth transistor are connected in parallel. The channel width-to-length ratio of the second transistor is n, the channel width-to-length ratio of the third transistor is 2n, and the channel width-to-length ratio of the fourth transistor is 2n. The gates of the second transistor, the third transistor, and the fourth transistor respectively receive the second encoded signal, the third encoded signal, and the fourth encoded signal, where n is an integer greater than or equal to 1.

3. The data receiving circuit of claim 2, wherein, The decision feedback equalization module also includes: The decoding circuit is used to perform logical operations on the first control signal group and the second control signal group to obtain the first encoded signal group and the second encoded signal group.

4. The data receiving circuit of claim 3, wherein, The decoding circuit is configured such that if the highest bit in the second control signal group is 1, both the third and fourth encoded signals are in a valid state, and the third transistor turns on in response to the valid state of the third encoded signal, and the fourth transistor turns on in response to the valid state of the fourth encoded signal.

5. The data receiving circuit of claim 3, wherein, The decoding circuit is configured such that: if the data of the two highest bits in the second control signal group are both 1, then the first encoded signal is in an active state; or, if the data of the highest bit in the first control signal group is 1, then the first encoded signal is in an active state; wherein, the first transistor is turned on in response to the active state of the first encoded signal.

6. The data receiving circuit of claim 3, wherein, The first control signal group includes a zeroth control signal and a first control signal; the second control signal group includes a second control signal, a third control signal, and a fourth control signal; the decoding circuit includes: Three first inverters, each of which receives the zeroth control signal, the second control signal and the fourth control signal respectively, and outputs the zeroth encoded signal, the second encoded signal and the fourth encoded signal respectively; The NOR gate receives the third control signal and the fourth control signal at its two inputs, and outputs the third encoded signal. A logic circuit, wherein the three input terminals of the logic circuit respectively receive the first control signal, the third control signal and the fourth control signal, and output the first encoded signal; Wherein, if both the third control signal and the fourth control signal are at logic high level, then the first encoded signal is at logic low level; if at least one of the third control signal and the fourth control signal is at logic low level, then the first encoded signal is in opposite phase to the first control signal.

7. The data receiving circuit as described in claim 6, characterized in that, The logic circuit includes: An OR gate, wherein the two inputs of the OR gate receive the inverted signal of the third control signal and the inverted signal of the fourth control signal, respectively; A NAND gate, one input of which receives the inverted signal of the first control signal, and the other input is connected to the output of the OR gate; The second inverter has its input connected to the output of the NAND gate, and its output outputs the first encoded signal.

8. The data receiving circuit as described in claim 7, characterized in that, The logic circuit also includes: A third inverter receives the first control signal and outputs an inverted signal of the first control signal; Two fourth inverters, each of which receives the third control signal and the fourth control signal respectively, and outputs the inverted signal of the third control signal and the inverted signal of the fourth control signal respectively.

9. The data receiving circuit as described in claim 1, characterized in that, The receiving module includes: The first amplification module is configured to receive the data signal and the reference signal, compare the data signal and the reference signal in response to the sampling clock signal, and output a first voltage signal through a first node and a second voltage signal through a second node. The second amplification module, connected to the first node and the second node, is configured to amplify the voltage difference between the first voltage signal and the second voltage signal, and output the first output signal through the third node and the second output signal through the fourth node. The feedback node includes a first feedback node and a second feedback node, with the first node serving as the first feedback node and the second node serving as the second feedback node. The decision feedback equalization module is configured to perform decision feedback equalization on the first node and the second node based on the feedback signal to adjust the first voltage signal and the second voltage signal.

10. The data receiving circuit as described in claim 9, characterized in that, The data receiving circuit further includes an offset compensation module, connected to the second amplification module, configured to compensate for the offset voltage of the second amplification module.

11. The data receiving circuit as described in claim 1, characterized in that, The receiving module includes: The first amplification module is configured to receive the data signal and the reference signal, compare the data signal and the reference signal in response to the sampling clock signal, and output a first voltage signal through a first node and a second voltage signal through a second node. The second amplification module, connected to the first node and the second node, is configured to amplify the voltage difference between the first voltage signal and the second voltage signal, and output the first output signal through the third node and the second output signal through the fourth node. The second amplification module has a first internal node and a second internal node, and the first output signal and the second output signal are obtained based on the signals of the first internal node and the second internal node. The feedback nodes include a first feedback node and a second feedback node, with the first internal node serving as the first feedback node and the second internal node serving as the second feedback node. The decision feedback equalization module is configured to perform the decision feedback equalization on the first internal node and the second internal node based on the feedback signal.

12. The data receiving circuit as described in claim 11, characterized in that, The data receiving circuit further includes an offset compensation module, connected to the first amplification module, configured to compensate for the offset voltage of the first amplification module.

13. The data receiving circuit as described in claim 9 or 11, characterized in that, The first amplification module includes: A current source is configured to be connected between the power supply node and the fifth node, and to provide current to the fifth node in response to the sampling clock signal; The comparison unit, connected to the fifth node, the first node, and the second node, is configured to receive the data signal and the reference signal, compare the data signal and the reference signal when the current source provides current to the fifth node in response to the sampling clock signal, and output the first voltage signal through the first node and the second voltage signal through the second node.

14. The data receiving circuit as described in claim 13, characterized in that, The first amplification module also includes: A first reset unit, connected to the first node and the second node, is configured to reset the first node and the second node.

15. The data receiving circuit as described in claim 9 or 11, characterized in that, The second amplification module includes: An input unit, connected to the first node and the second node, is configured to compare the first voltage signal and the second voltage signal, and provide a third voltage signal to the seventh node and a fourth voltage signal to the eighth node, wherein the second amplification module has a first internal node and a second internal node, and the seventh node is the first internal node and the eighth node is the second internal node; The latching unit is configured to amplify and latch the third voltage signal and the fourth voltage signal, and output the first output signal to the third node and the second output signal to the fourth node.

16. A data receiving system, characterized in that, include: Multiple cascaded data transmission circuits, each of which includes a data receiving circuit as described in any one of claims 1-15 and a latching circuit connected to the data receiving circuit, each of which is connected to the data port to receive the data signal; the decision feedback equalization module of the next-level data transmission circuit is connected to the previous-level data transmission circuit, and the output of the previous-level data transmission circuit serves as the feedback signal of the decision feedback equalization module of the next-level data transmission circuit; The final stage of the data transmission circuit is connected to the decision feedback equalization module of the first stage of the data transmission circuit, and the output of the final stage of the data transmission circuit serves as the feedback signal of the decision feedback equalization module of the first stage of the data transmission circuit.

17. A storage device, characterized in that, include: Multiple data ports; Multiple data receiving systems as described in claim 16, each of the data receiving systems corresponding to one of the data ports.

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