A clock extraction method, decoding method and device based on Manchester code

Abstract

The embodiment of the present application provides a clock extraction method, decoding method and device based on Manchester code, and the clock extraction method includes: in the fast blind picking stage: according to the transition edge of the Manchester code stream, the data rate frequency division ratio is estimated to obtain the edge detection frequency division ratio value; in the capture and tracking stage, the following process is repeated at least once: a plurality of continuous high levels and a plurality of continuous low levels in the Manchester code stream are sampled and counted to obtain the high level count value corresponding to the plurality of continuous high levels and the low level count value corresponding to the plurality of continuous low levels; according to the statistical algorithm, the high level count value, the low level count value and the edge detection frequency division ratio value are calculated to obtain the target frequency division ratio mean value; the target frequency division ratio mean value is provided to the clock generation unit. The embodiment of the present application improves the accuracy of the obtained decoding clock signal and ultimately improves the decoding accuracy.

Description

Technical Field

[0001] The present application relates to the field of decoding. Specifically, embodiments of the present application relate to a clock extraction method, a decoding method and a device based on Manchester code. Background Art

[0002] Figure 1 A decoding system provided for related technologies includes a synchronization unit, an edge detection unit (i.e., an edge capture unit), a steady-state counter (including a high steady-state counter and a low steady-state counter), and a clock generation unit, wherein the synchronization unit uses a local system clock to synchronize the input Manchester code to reduce the influence of metastable states. The edge detection unit mainly performs edge detection on the data stream. The steady-state counter mainly performs sampling and counting on the code stream, and logically determines that the time width exceeds a single Manchester code element (referred to as Manchester code element). The clock generation unit mainly processes the results of edge detection and steady-state detection to extract the clock.

[0003] The prior art uses a system clock with a 16x frequency multiplication (i.e., a fixed value with a frequency division ratio of 16) to sample the received Manchester code stream. When the Manchester code element is logic "1", the high steady-state counter based on this system clock increments, otherwise the low steady-state counter increments. When the edge detection unit is valid, the high / low steady-state counters are cleared respectively.

[0004] The prior art counts logic '1' or logic '0' at a 16x multiplied system clock. The inventor of the present application found in research that if a Manchester code stream contains alternating '1' and '0', when the counter is reset, Figure 1 The system actually only counts one Manchester code element and cannot achieve synchronous counting of a large number of code elements. As a result, the data rate is offset due to clock offset or jitter, resulting in a large error in the clock division ratio extracted from each code element, which in turn affects the clock extraction effect and ultimately reduces the decoding accuracy. Summary of the invention

[0005] The purpose of the embodiment of the present application is to provide a clock extraction method, decoding method and device based on Manchester code, and the embodiment of the present application is used to sample and count a large amount of data and perform average processing, thereby optimizing the frequency division ratio count value. In the capture and tracking stage, the count value can be dynamically adjusted to avoid the single recording value error caused by clock offset and jitter, significantly improve the accuracy of the frequency division ratio, thereby improving the accuracy of the decoded clock signal and ultimately improving the decoding accuracy.

[0006] In a first aspect, an embodiment of the present application provides a clock extraction method based on Manchester code, the clock extraction method comprising: in a fast blind picking stage: estimating a data rate division ratio according to a transition edge of a Manchester code stream to obtain an edge detection division ratio value; in a capture and tracking stage, repeating the following process at least once: sampling and counting a plurality of consecutive high levels and a plurality of consecutive low levels in the Manchester code stream to obtain a high level count value corresponding to the plurality of consecutive high levels and a low level count value corresponding to the plurality of consecutive low levels; calculating the high level count value, the low level count value and the edge detection division ratio value according to a statistical algorithm to obtain a target division ratio mean; providing the target division ratio mean to a clock generation unit, so that the clock generation unit obtains a clock signal for decoding according to the target division ratio mean.

[0007] The embodiments of the present application sample a large number of code elements (i.e., multiple consecutive high levels and multiple consecutive low levels) during the capture and tracking stage, record the count values ​​of the high and low levels, and then perform statistical processing. This is essentially a mean filtering method that can avoid large errors in single recorded values ​​caused by clock offset and jitter.

[0008] In some embodiments, the data rate division ratio is estimated according to the transition edge of the Manchester code stream to obtain the edge detection division ratio value, including: recording the count value between the first edge and the second edge by the system clock to obtain the first count value N1; recording the count value from the second edge to the first edge by the system clock to obtain the second count value N2; calculating the edge detection division ratio value according to the first count value and the second count value; wherein the first edge is a rising edge and the second edge is a falling edge, or the first edge is a falling edge and the second edge is a rising edge.

[0009] Some embodiments of the present application can quickly determine the data rate division ratio according to the transition edge of the input signal during the fast blind picking stage to obtain the corresponding division ratio (ie, obtain the edge detection division ratio value).

[0010] In some embodiments, the first edge is a rising edge and the second edge is a falling edge, wherein the calculating the edge detection frequency division ratio according to the first count value and the second count value includes: if it is confirmed that the leading code of the Manchester code stream is at least one group of 000, 111, 001 or 110, the edge detection frequency division ratio is calculated as follows: w_fast_div_n = (N1+N2) / 2; if it is confirmed that the leading code of the Manchester code stream is at least one group of 010 or 101, the edge detection frequency division ratio is calculated as follows: w_fast_div_n = (N1+N2) / 4; if it is confirmed that the leading code of the Manchester code stream is at least one group of 011, the edge detection frequency division ratio is calculated as follows: w_fast_div_n = (2 N1+N2) / 4; if it is confirmed that the leading code of the Manchester code stream is at least one group of 100, the calculation formula of the edge detection frequency division ratio is: w_fast_div_n = (N1+2 N2) / 4.

[0011] Some embodiments of the present application propose differentiated edge detection frequency division ratio calculation formulas based on the type of preamble code, which can improve the accuracy of the obtained value.

[0012] In some embodiments, in the capture and tracking stage, the clock extraction method includes: in the capture stage: in the i-th cycle, sampling and counting the M consecutive high levels and the M consecutive low levels in the Manchester code stream, obtaining the i-th captured high level count value corresponding to the M consecutive high levels and the i-th captured low level count value corresponding to the M consecutive low levels; calculating the i-th captured high level count value, the i-th captured low level count value and the edge detection division ratio value according to the statistical algorithm to obtain the i-th captured target division ratio mean; providing the i-th captured target division ratio mean to the clock generation unit; wherein i is greater than 1 and less than the capture cycle An integer of the loop count threshold, M is an integer greater than 1; in the tracking stage: in the kth cycle, P consecutive high levels and P consecutive low levels in the Manchester code stream are sampled and counted to obtain a kth tracking high level count value corresponding to the consecutive P high levels and a kth tracking low level count value corresponding to the consecutive P low levels; according to a statistical algorithm, the kth tracking high level count value, the kth tracking low level count value and the edge detection division ratio value are calculated to obtain a kth tracking target division ratio mean; the kth tracking target division ratio mean is provided to the clock generation unit; wherein k is an integer greater than 1, and P is an integer greater than 1 and greater than M.

[0013] Some embodiments of the present application obtain a more accurate division ratio by setting a capture phase and a tracking phase, and counting a large amount of code element information in a cyclic manner in each phase, thereby improving the clock signal obtained by the clock generation unit according to the corresponding division ratio.

[0014] In some embodiments, the value of M is 2, the i-th captured high level count value is N3, the i-th captured low level count value is N4, and the edge detection frequency division ratio value is w_fast_div_n, wherein the i-th captured high level count value, the i-th captured low level count value and the edge detection frequency division ratio value are calculated according to the statistical algorithm to obtain the i-th captured target frequency division ratio mean, including: calculating the i-th captured target frequency division ratio mean w_cap_div_n according to the following first statistical algorithm formula: w_cap_div_n = (N3+N4+4 w_fast_div_n) / 8.

[0015] Some embodiments of the present application provide a corresponding target frequency division ratio average calculation formula for the case of counting two consecutive levels in the capture phase, thereby improving the accuracy of the value calculation.

[0016] In some embodiments, the value of P is 8, the kth tracking high level count value is N5, and the kth tracking low level count value is N6, wherein the kth tracking high level count value, the kth tracking low level count value and the edge detection division ratio value are calculated according to a statistical algorithm to obtain the kth tracking target division ratio mean value, including: calculating the kth tracking target division ratio mean value w_track_div_n according to the following second statistical algorithm formula:

[0017] w_track_div_n = (N5+N6+16 w_cap_div_n) / 32.

[0018] Some embodiments of the present application provide a corresponding target frequency division ratio average calculation formula for the case of counting eight consecutive levels in the tracking phase, thereby improving the accuracy of the value calculation.

[0019] In a second aspect, some embodiments of the present application provide a decoding method, which includes: in a fast blind picking stage: estimating a data rate division ratio according to the transition edge of a Manchester code stream to obtain an edge detection division ratio value; in a capture and tracking stage, repeating the following process at least once: sampling and counting a plurality of consecutive high levels and a plurality of consecutive low levels in the Manchester code stream to obtain a high level count value corresponding to the plurality of consecutive high levels and a low level count value corresponding to the plurality of consecutive low levels; calculating the high level count value, the low level count value and the edge detection division ratio value according to a statistical algorithm to obtain a target division ratio mean, and providing the target division ratio mean to a clock generation unit; in a decoding stage: decoding the Manchester code stream by means of a clock output signal obtained by the clock generation unit according to the target division ratio mean.

[0020] In a third aspect, some embodiments of the present application provide a device for clock extraction, comprising: a fast blind picking unit, configured to estimate the data rate division ratio according to the transition edge of the Manchester code stream in the fast blind picking stage to obtain an edge detection division ratio value; a capture and tracking unit, configured to repeat the following process at least once in the capture and tracking stage: sample and count multiple consecutive high levels and multiple consecutive low levels in the Manchester code stream to obtain high level count values ​​corresponding to the multiple consecutive high levels and low level count values ​​corresponding to the multiple consecutive low levels; calculate the high level count value, the low level count value and the edge detection division ratio value according to a statistical algorithm to obtain a target division ratio mean; a clock generation unit, configured to obtain a decoding clock signal according to the target division ratio mean.

[0021] In some embodiments, the capture and tracking unit includes: a capture unit, configured to: in the i-th cycle, sample and count M consecutive high levels and M consecutive low levels in the Manchester code stream, obtain the i-th captured high level count value corresponding to the M consecutive high levels and the i-th captured low level count value corresponding to the M consecutive low levels; calculate the i-th captured high level count value, the i-th captured low level count value and the edge detection division ratio value according to a statistical algorithm to obtain the i-th captured target division ratio mean; provide the i-th captured target division ratio mean to the clock generation unit; wherein i is greater than 1 and less than the capture cycle number threshold An integer, M is an integer greater than 1; the tracking unit is configured to: in the kth cycle, sample and count P consecutive high levels and P consecutive low levels in the Manchester code stream, and obtain a kth tracking high level count value corresponding to the P consecutive high levels and a kth tracking low level count value corresponding to the P consecutive low levels; calculate the kth tracking high level count value, the kth tracking low level count value and the edge detection division ratio value according to a statistical algorithm to obtain a kth tracking target division ratio mean; and provide the kth tracking target division ratio mean to the clock generation unit; wherein k is an integer greater than 1, and P is an integer greater than 1 and greater than M.

[0022] In a fourth aspect, some embodiments of the present application provide a decoding device, comprising: a device for clock extraction as described in the third aspect and a decoding unit, wherein the decoding unit is configured to decode a Manchester code stream according to a clock signal provided by the device for clock extraction. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 Decoding system architecture diagram provided for related technologies;

[0025] Figure 2 One of the flowcharts of the clock extraction method based on Manchester code provided in an embodiment of the present application;

[0026] Figure 3 A schematic diagram of obtaining a first count value and a second count value when the leading code is 000X provided in an embodiment of the present application;

[0027] Figure 4A schematic diagram of obtaining a first count value and a second count value when a preamble code 111X is provided in an embodiment of the present application;

[0028] Figure 5 A schematic diagram of obtaining a first count value and a second count value when the leading code is 001X provided in an embodiment of the present application;

[0029] Figure 6 A schematic diagram of obtaining a first count value and a second count value when a preamble code 110X is provided in an embodiment of the present application;

[0030] Figure 7 A schematic diagram of obtaining a first count value and a second count value when the leading code is 010X provided in an embodiment of the present application;

[0031] Figure 8 A schematic diagram of obtaining a first count value and a second count value when a preamble code 101X is provided in an embodiment of the present application;

[0032] Fig. 9 A schematic diagram of obtaining a first count value and a second count value when the leading code is 011X provided in an embodiment of the present application;

[0033] Fig.10 A schematic diagram of obtaining a first count value and a second count value when the preamble code 100X is provided in an embodiment of the present application;

[0034] Fig.11 A schematic diagram of calculating the frequency division ratio of a capture unit provided in an embodiment of the present application;

[0035] Fig.12 A schematic diagram of calculating the frequency division ratio of the tracking unit provided in an embodiment of the present application;

[0036] Fig.13 A block diagram of a clock extraction device according to an embodiment of the present application;

[0037] Fig.14 A block diagram of the decoding device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0039] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0040] In order to overcome the relevant technical problems raised in the background technology part, some embodiments of the present application sample a large number of code elements through a capture and tracking unit in the capture and tracking stage, record the count values ​​of their high and low levels, and then perform averaging processing. This is essentially a mean filtering processing method. The embodiments of the present application can effectively avoid the situation where the error of a single recorded value is large due to clock offset and jitter.

[0041] Please see Figure 2 , Figure 2 A clock extraction method based on Manchester code is provided for an embodiment of the present application. The clock extraction method comprises: in a fast blind picking stage: S101, estimating a data rate division ratio according to a transition edge of a Manchester code stream to obtain an edge detection division ratio value; in a capture and tracking stage, repeating the following process at least once (i.e., the process of S102-S104): S102, sampling and counting a plurality of continuous high levels and a plurality of continuous low levels in the Manchester code stream to obtain a high level count value corresponding to the plurality of continuous high levels and a low level count value corresponding to the plurality of continuous low levels; S103, calculating the high level count value, the low level count value and the edge detection division ratio value according to a statistical algorithm to obtain a target division ratio mean; S104 providing the target division ratio mean to a clock generation unit, so that the clock generation unit obtains a clock signal for decoding according to the target division ratio mean.

[0042] The embodiments of the present application sample a large number of code elements (i.e., multiple consecutive high levels and multiple consecutive low levels) during the capture and tracking stage, record the count values ​​of the high and low levels, and then perform statistical processing. This is essentially a mean filtering method that can avoid large errors in single recorded values ​​caused by clock offset and jitter.

[0043] The following is an example of Figure 2 The implementation process of each step.

[0044] In some embodiments of the present application, S101 exemplarily includes:

[0045] In the first step, the count value between the first edge and the second edge is recorded by the system clock to obtain a first count value N1.

[0046] In the second step, the system clock records the count value from the second edge to the first edge to obtain a second count value N2.

[0047] The third step is to calculate the edge detection frequency division ratio according to the first count value and the second count value.

[0048] It should be noted that the first edge is a rising edge and the second edge is a falling edge, or the first edge is a falling edge and the second edge is a rising edge.

[0049] It is not difficult to understand that some embodiments of the present application can quickly determine the data rate division ratio according to the transition edge of the input signal during the fast blind picking stage to obtain the corresponding division ratio (i.e., obtain the edge detection division ratio value).

[0050] Combine the following Figure 3-Figure 10 The relationship between the first count value and the second count value and the preamble code in some embodiments of the present application is exemplified by taking the first edge as a rising edge and the second edge as a falling edge.

[0051] like Figure 3 As shown, the leading code of the original code stream is 000, and the corresponding Manchester code encoding result (i.e., the Manchester code stream) is 101010 from the first bit to the sixth bit. Some embodiments of the present application obtain a second count value N2 corresponding to the falling edge to the rising edge (the value is the total number of pulses of the system clock corresponding to the second bit signal 0 in the Manchester code) through fast blind picking of the system clock, and obtain a first count value N1 corresponding to the rising edge to the falling edge (the value is the total number of pulses of the system clock corresponding to the third bit signal 1 in the Manchester code).

[0052] like Figure 4 As shown, the leading code 111 of the original code stream, and the corresponding Manchester code encoding result (i.e., the Manchester code stream) are 010101 from the first bit to the sixth bit. Some embodiments of the present application obtain a first count value N1 corresponding to the rising edge to the falling edge (the value is the total number of pulses of the system clock corresponding to the second bit signal 1 in the Manchester code) through fast blind picking of the system clock, and obtain a second count value N2 corresponding to the falling edge to the rising edge (the value is the total number of pulses of the system clock corresponding to the third bit signal 0 in the Manchester code).

[0053] like Figure 5 As shown, the leading code of the original code stream is 001, and the corresponding Manchester code encoding result (i.e., the Manchester code stream) is 101001 from the first bit to the sixth bit. Some embodiments of the present application obtain a second count value N2 corresponding to the falling edge to the rising edge (the value is the total number of pulses of the system clock corresponding to the second bit signal 0 in the Manchester code) through fast blind picking of the system clock, and obtain a first count value N1 corresponding to the rising edge to the falling edge (the value is the total number of pulses of the system clock corresponding to the third bit signal 1 in the Manchester code).

[0054] like Figure 6As shown, the leading code 110 of the original code stream, the corresponding Manchester code encoding result (i.e., the Manchester code stream) is 010110 from the first bit to the sixth bit. Some embodiments of the present application obtain a first count value N1 corresponding to the rising edge to the falling edge (the value is the total number of pulses of the system clock corresponding to the second bit signal 1 in the Manchester code) through fast blind picking of the system clock, and obtain a second count value N2 corresponding to the falling edge to the rising edge (the value is the total number of pulses of the system clock corresponding to the third bit signal 0 in the Manchester code).

[0055] It should be noted that, in some embodiments of the present application, corresponding to Figure 3 , Figure 4 , Figure 5 as well as Figure 6 The calculation formula for the edge detection frequency division ratio (at this time N1≈N2) is: w_fast_div_n = (N1+N2) / 2, where w_fast_div_n represents the edge detection frequency division ratio. That is, when N1≈N2, the edge detection frequency division ratio w_fast_div_n = (N1+N2) / 2.

[0056] like Figure 7 As shown, the leading code of the original code stream is 010, and the corresponding Manchester code encoding result (i.e., the Manchester code stream) is 100110 from the first bit to the sixth bit. Some embodiments of the present application obtain a second count value N2 corresponding to the falling edge to the rising edge (the value is the total number of pulses of the system clock corresponding to the second bit signal 0 and the third bit signal 0 in the Manchester code) through fast blind picking of the system clock, and obtain a first count value N1 corresponding to the rising edge to the falling edge (the value is the total number of pulses of the system clock corresponding to the fourth bit signal 1 and the fifth bit signal 1 in the Manchester code).

[0057] like Figure 8 As shown, the leading code 101 of the original code stream, the corresponding Manchester code encoding result (i.e., the Manchester code stream) is 011001 from the first bit to the sixth bit. Some embodiments of the present application obtain a first count value N1 corresponding to the rising edge to the falling edge (the value is the total number of pulses of the system clock corresponding to the second bit signal 1 and the third bit signal 1 in the Manchester code) through fast blind picking of the system clock, and obtain a second count value N2 corresponding to the falling edge to the rising edge (the value is the total number of pulses of the system clock corresponding to the fourth bit signal 0 and the fifth bit signal 0 in the Manchester code).

[0058] It should be noted that, in some embodiments of the present application, corresponding to Figure 7 and Figure 8The calculation formula for the edge detection frequency division ratio is: w_fast_div_n = (N1+N2) / 4. That is, if N1≈N2, the edge detection frequency division ratio w_fast_div_n = (N1+N2) / 4.

[0059] like Fig. 9 As shown, the leading code of the original code stream is 011, and the corresponding Manchester code encoding result (i.e., the Manchester code stream) is 100101 from the first bit to the sixth bit. Some embodiments of the present application obtain a second count value N2 corresponding to the falling edge to the rising edge (the value is the total number of pulses of the system clock corresponding to the second bit signal 0 and the third bit signal 0 in the Manchester code) through fast blind picking of the system clock, and obtain a first count value N1 corresponding to the rising edge to the falling edge (the value is the total number of pulses of the system clock corresponding to the fourth bit signal 1 in the Manchester code).

[0060] It should be noted that, in some embodiments of the present application, Fig. 9 The corresponding edge detection frequency division ratio calculation formula is: w_fast_div_n = (2 N1+N2) / 4. That is, if N1≈2N2, the edge detection division ratio w_fast_div_n = (N1+2 N2) / 4.

[0061] like Fig.10 As shown, the leading code 100 of the original code stream, and the corresponding Manchester code encoding result (i.e., the Manchester code stream) are 011010 from the first bit to the sixth bit. Some embodiments of the present application obtain a first count value N1 corresponding to the rising edge to the falling edge (the value is the total number of pulses of the system clock corresponding to the second bit signal 1 and the third bit signal 1 in the Manchester code) through fast blind picking of the system clock, and obtain a second count value N2 corresponding to the falling edge to the rising edge (the value is the total number of pulses of the system clock corresponding to the fourth bit signal 0 in the Manchester code).

[0062] It should be noted that, in some embodiments of the present application, Fig.10 The corresponding edge detection frequency division ratio calculation formula is: w_fast_div_n = (N1+2 N2) / 4. That is, if 2N1≈N2, then the edge detection division ratio w_fast_div_n = (2 N1+N2) / 4.

[0063] Some embodiments of the present application propose differentiated edge detection frequency division ratio calculation formulas based on the type of preamble code, which can improve the accuracy of the obtained value.

[0064] It should be noted that in the embodiment of the present application, after the edge detection frequency division ratio is obtained, the capture and tracking stage is entered, and the frequency division ratio is updated in real time during this stage to improve the accuracy of the clock signal obtained by the clock generation unit.

[0065] That is, in some embodiments of the present application, in the capture and tracking stage, the clock extraction method includes: in the capture stage: in the i-th cycle, S102 exemplarily includes: sampling and counting M consecutive high levels and M consecutive low levels in the Manchester code stream, obtaining the i-th captured high level count value corresponding to the M consecutive high levels and the i-th captured low level count value corresponding to the M consecutive low levels; S103 exemplarily includes: calculating the i-th captured high level count value, the i-th captured low level count value and the edge detection division ratio value according to a statistical algorithm to obtain the i-th captured target division ratio mean; S104 exemplarily includes: providing the i-th captured target division ratio mean to the clock generation unit; wherein i is greater than 1 and An integer less than the capture cycle number threshold, M is an integer greater than 1; in the tracking stage: in the kth cycle, S102 exemplarily includes: sampling and counting P consecutive high levels and P consecutive low levels in the Manchester code stream, obtaining the kth tracking high level count value corresponding to the P consecutive high levels and the kth tracking low level count value corresponding to the P consecutive low levels; S103 exemplarily includes: calculating the kth tracking high level count value, the kth tracking low level count value and the edge detection division ratio value according to a statistical algorithm to obtain the kth tracking target division ratio mean; S104 exemplarily includes: providing the kth tracking target division ratio mean to the clock generation unit; wherein k is an integer greater than 1, and P is an integer greater than 1 and greater than M.

[0066] It should be noted that some embodiments of the present application obtain a more accurate division ratio by setting a capture phase and a tracking phase, and counting a large amount of code element information in a cyclic manner in each phase, thereby improving the clock signal obtained by the clock generation unit according to the corresponding division ratio.

[0067] For example, in some embodiments of the present application, the value of M is 2, and the i-th captured high level count value N3 (such as Figure 3-Figure 10 The value of N3 shown is equal to the total number of pulses corresponding to the system clock corresponding to N3), and the i-th captured low level count value is N4 (such as Figure 3-Figure 10The N4 shown in the figure is equal to the total number of pulses corresponding to the system clock corresponding to N4), the edge detection frequency division ratio value is w_fast_div_n, wherein the i-th capture high level count value, the i-th capture low level count value and the edge detection frequency division ratio value are calculated according to the statistical algorithm to obtain the i-th capture target frequency division ratio mean, including: calculating the i-th capture target frequency division ratio mean w_cap_div_n according to the following first statistical algorithm formula: w_cap_div_n = (N3+N4+4 w_fast_div_n) / 8.

[0068] For example, Fig.11 As shown, in some embodiments of the present application, the value of i is 4, and the figure shows the original synchronization clock, the original code stream, the Manchester code stream and the system clock, wherein the original code stream is: 0001010010, wherein "000" is the preamble code and the code element after the preamble code is valid, and the Manchester code stream corresponding to the original code stream is 10101001100110100110, Fig.11 The second count value N2 and the first count value N1 corresponding to the fast blind pick are shown, and the high-level count value N3 obtained by the first cycle repeat1, the second cycle repeat2, the third cycle repeat3 and the fourth cycle repeat4 (i.e., i=4) is obtained. Fig.11 The total number of pulses of the system clock corresponding to this value in the capture low level count value is N4 (the size of this value is Fig.11 The total number of pulses of the system clock corresponding to the value in the first loop repeat1 is specifically: the first captured high level count value corresponding to the first loop repeat1 is N3_repeat1 and the first captured low level count value is N4_repeat1, the first captured high level count value corresponding to the second loop repeat2 is N3_repeat2 and the second captured low level count value is N4_repeat2, the third captured high level count value corresponding to the third loop repeat3 is N3_repeat3 and the third captured low level count value is N4_repeat3, and the fourth captured high level count value corresponding to the fourth loop repeat4 is N3_repeat4 and the fourth captured low level count value is N4_repeat4. That is to say, Fig.11 Sampling and counting are performed with the system clock, and four cycles are performed. The count value of the first high level is recorded as Cnt3_0, and the count value of the second high level is recorded as Cnt3_1. The count value of the first low level is recorded as Cnt4_0, and the count value of the second low level is recorded as Cnt4_1.

[0069] Some embodiments of the present application provide a corresponding target frequency division ratio average calculation formula for the case of counting two consecutive levels in the capture phase, thereby improving the accuracy of the value calculation.

[0070] For example, in some embodiments of the present application, the value of P is 8, the k-th tracking high level count value is N5, and the k-th tracking low level count value is N6, wherein the k-th tracking high level count value, the k-th tracking low level count value, and the edge detection division ratio value are calculated according to a statistical algorithm to obtain the k-th tracking target division ratio mean value, including: calculating the k-th tracking target division ratio mean value w_track_div_n according to the following second statistical algorithm formula:

[0071] w_track_div_n = (N5+N6+16 w_cap_div_n) / 32.

[0072] For example, Fig.12 As shown in the figure, the Fig.11 Four cycles of Fig.12 The figure shows the counting diagram of the tracking phase after the fourth cycle repeat4 of the tracking phase. The figure fully shows the first cycle repeat1 of the tracking phase (i.e. Fig.12 ), and the figure shows the original synchronization clock, the original code stream, the Manchester code stream and the system clock, wherein the original code stream is (all valid code elements): 1010110101, and the Manchester code stream corresponding to the original code stream is 01100110010110011001, Fig.12 The fourth capture high level count value corresponding to the fourth cycle of the capture phase is N3_repeat4 and the fourth capture low level count value is N4_repeat4, and the first cycle of the final phase, in which the value of P is 8, and the first tracking high level count value corresponding to 8 high level is continuously counted (this count value is the sum of the following 8 count values, that is, in Fig.12 The first high level count value recorded in is Cnt5_0, the second is Cnt5_1, the third is Cnt5_2, the fourth is Cnt5_3, the fifth is Cnt5_4, the sixth is Cnt5_5, the seventh is Cnt5_6, and the eighth is Cnt5_7) and the first tracking low level count value corresponding to the 8 low levels (this count value is the sum of the following 8 count values, that is, in Fig.12 The count value of the first low level recorded in is Cn6_0, the second is Cnt6_1, the third is Cnt6_2, the fourth is Cnt6_3, the fifth is Cnt6_4, the sixth is Cnt6_5, the seventh is Cnt6_6, and the eighth is Cnt6_7).

[0073] Some embodiments of the present application provide a corresponding target frequency division ratio average calculation formula for the case of counting eight consecutive levels in the tracking phase, thereby improving the accuracy of the value calculation.

[0074] Some embodiments of the present application provide a decoding method, which includes: in a fast blind picking stage: estimating a data rate division ratio according to a transition edge of a Manchester code stream to obtain an edge detection division ratio value; in a capture and tracking stage, repeating the following process at least once: sampling and counting a plurality of consecutive high levels and a plurality of consecutive low levels in the Manchester code stream to obtain a high level count value corresponding to the plurality of consecutive high levels and a low level count value corresponding to the plurality of consecutive low levels; calculating the high level count value, the low level count value and the edge detection division ratio value according to a statistical algorithm to obtain a target division ratio mean, and providing the target division ratio mean to a clock generation unit; in a decoding stage: decoding the Manchester code stream by using a clock output signal obtained by the clock generation unit according to the target division ratio mean.

[0075] It should be noted that, for the implementation details involved in each step of the decoding method, reference may be made to the corresponding description of the method for clock extraction above, and no further details will be given here to avoid repetition.

[0076] like Fig.13 As shown, some embodiments of the present application provide a device for clock extraction, the device comprising: a fast blind picking unit 130, a capture and tracking unit 140 and a clock generating unit 150.

[0077] The fast blind picking unit is configured to estimate the data rate division ratio according to the transition edge of the Manchester code stream in the fast blind picking stage to obtain the edge detection division ratio value.

[0078] The capture and tracking unit is configured to repeat the following process at least once in the capture and tracking stage: sampling and counting a plurality of consecutive high levels and a plurality of consecutive low levels in the Manchester code stream to obtain a high level count value corresponding to the plurality of consecutive high levels and a low level count value corresponding to the plurality of consecutive low levels; calculating the high level count value, the low level count value and the edge detection division ratio value according to a statistical algorithm to obtain a target division ratio average; and the clock generation unit is configured to obtain a decoding clock signal according to the target division ratio average.

[0079] like Fig.13 As shown, in some embodiments of the present application, the capture and tracking unit 140 includes: a capture unit 141 and a tracking unit 142.

[0080] The capture unit is configured to: in the i-th cycle, sample and count M consecutive high levels and M consecutive low levels in the Manchester code stream, obtain the i-th captured high level count value corresponding to the M consecutive high levels and the i-th captured low level count value corresponding to the M consecutive low levels; calculate the i-th captured high level count value, the i-th captured low level count value and the edge detection division ratio value according to a statistical algorithm to obtain the i-th captured target division ratio mean; provide the i-th captured target division ratio mean to the clock generation unit; wherein i is an integer greater than 1 and less than a capture cycle number threshold, and M is an integer greater than 1.

[0081] The tracking unit is configured to: in the kth cycle, sample and count P consecutive high levels and P consecutive low levels in the Manchester code stream to obtain a kth tracking high level count value corresponding to the P consecutive high levels and a kth tracking low level count value corresponding to the P consecutive low levels; calculate the kth tracking high level count value, the kth tracking low level count value and the edge detection division ratio value according to a statistical algorithm to obtain a kth tracking target division ratio average; provide the kth tracking target division ratio average to the clock generation unit; wherein k is an integer greater than 1, and P is an integer greater than 1 and greater than M.

[0082] against Fig.13 The working process of each unit in the method can refer to the specific process in the above method, and will not be described in detail here to avoid repetition.

[0083] like Fig.14 As shown, some embodiments of the present application provide a decoding device, the decoding device and Fig.13 The difference lies in that the decoding unit 160 is connected after the clock generating unit, and the processing of the IDLE phase module in the initial phase, the decoding device includes: Fig.13 The device for clock extraction and the decoding unit 160 are shown, wherein the decoding unit 160 is configured to decode the Manchester code stream according to the clock signal provided by the device for clock extraction.

[0084] Combine the following Fig.14 Each unit in the figure exemplifies the decoding process of some embodiments of the present application.

[0085] The first step, IDLE stage: When the module is not working, it is in the IDLE stage, and all internal values ​​are in the initial state. When the configuration is start, the module enters the next stage.

[0086] The second step is fast blind detection (i.e., the fast blind detection process performed by the fast blind detection unit 130): the data rate division ratio w_fast_div_n is quickly determined according to the transition edge of the input signal. The count value before the transition edge is recorded, assuming that N1 is the count value between the rising edge and the falling edge, and N2 is the count value between the falling edge and the rising edge. For different symbol sequences, the values ​​between N1 and N2 and the division ratio have different relationships as follows:

[0087] a) If N1≈N2, the division ratio w_fast_div_n = (N1+N2) / 2

[0088] b) If N1≈N2, the division ratio w_fast_div_n = (N1+N2) / 4

[0089] c) If N1≈2N2, the division ratio w_fast_div_n = (N1+2 N2) / 4

[0090] d) If 2N1≈N2, the division ratio w_fast_div_n = (2 N1+N2) / 4

[0091] After w_fast_div_n is determined quickly, the module enters the capture phase.

[0092] The third step is the capture phase (i.e. Fig.14 The capture unit 121 of the capture unit 121 performs a fast correction of the data rate division ratio. In the capture phase, the system clock is used to sample the high and low levels of the code element respectively, and then the count values ​​are recorded respectively to recalculate the capture phase division ratio. For example, continuously sample 2 (i.e., M is exemplarily taken as 2) high levels, record the accumulated value of the division ratio as N3; continuously sample 2 low levels, record the accumulated value of the division ratio as N4, and obtain the new division ratio w_cap_div_n = (N3+N4+4 w_fast_div_n) / 8, loop 4 times, then jump out of the capture phase and enter the tracking phase.

[0093] Combination Fig.11 This process is explained by way of example. Fig.11 Capture phase: The system clock performs sampling counting and performs 4 cycles. The count value of the first high level is recorded as Cnt3_0, and the count value of the second high level is recorded as Cnt3_1. The count value of the first low level is recorded as Cnt4_0, and the count value of the second low level is recorded as Cnt4_1.

[0094] (1) The first loop repeat1:

[0095] The count value of two consecutive high levels is recorded as the first captured high level count value N3_repeat1, and the count value of two consecutive low levels is recorded as the first captured low level count value N4_repeat1.

[0096] The data rate division ratio (i.e. the average of the first capture target division ratio) is calculated as w_cap_div_n = N3_repeat1+ N4_ repeat1+4 w_fast_div_n) / 8

[0097] (2) Second loop repeat2:

[0098] The count value of recording two high levels is the second captured high level count value N3_repeat2, and the count value of recording two low levels is the second captured low level count value N4_repeat2.

[0099] The data rate division ratio (i.e., the average of the second capture target division ratio) is calculated as w_cap_div_n = N3_repeat2+ N4_ repeat2+4 w_fast_div_n) / 8

[0100] (3) The third loop repeat3:

[0101] The count value of recording two high levels is the third captured high level count value N3_repeat3, and the count value of recording two low levels is the third captured low level count value N4_repeat3.

[0102] The calculated data rate division ratio (i.e., the average of the third capture target division ratio) is w_cap_div_n = N3_repeat3+ N4_ repeat3+4 w_fast_div_n) / 8

[0103] (4) repeat4:

[0104] The count value of recording two high levels is the fourth captured high level count value N3_repeat4, and the count value of recording two low levels is the fourth captured low level count value N4_repeat4.

[0105] The data rate division ratio (i.e., the average of the fourth capture target division ratio) is calculated as w_cap_div_n = N3_repeat4+ N4_ repeat4+4 w_fast_div_n) / 8.

[0106] The fourth step is the tracking phase (i.e. Fig.14The tracking unit 122 performs the operation of this stage) to track and correct the data rate division ratio. It should be noted that the tracking and capturing ideas of some embodiments of the present application are consistent, but there is a difference in the number of accumulated values ​​of sampling '1' or sampling '0'. For example, the value of P in the tracking stage is 8, that is, the accumulated value of the division ratio corresponding to 8 sampling '1' is recorded as N5, and the accumulated value of the division ratio corresponding to 8 sampling '0' is recorded as N6 in the tracking stage, and the new w_track_div_n = (N5+N6+16 w_cap_div_n) / 32, after which the data rate division ratio calculation is always in tracking units.

[0107] by Fig.12 For example, the figure uses the system clock for sampling and counting, and keeps looping in the tracking stage. The count value of the first high level is recorded as Cnt5_0, the second is Cnt5_1, the third is Cnt5_2, the fourth is Cnt5_3, the fifth is Cnt5_4, the sixth is Cnt5_5, the seventh is Cnt5_6, and the eighth is Cnt5_7. The count value of the first low level is recorded as Cn6_0, the second is Cnt6_1, the third is Cnt6_2, the fourth is Cnt6_3, the fifth is Cnt6_4, the sixth is Cnt6_5, the seventh is Cnt6_6, and the eighth is Cnt6_7.

[0108] In the first cycle repeat1 of the tracking phase: the count value of 8 high levels is recorded as the first tracking high level count value N5_repeat1, and the count value of 8 low levels is recorded as the first tracking low level count value N6_repeat1.

[0109] The calculated division ratio (i.e. the average division ratio of the first tracking target) is w_track_div_n = (N5_repeat1+N6_repeat1+16 w_cap_div_n) / 32.

[0110] Taking the first cycle process of the tracking phase as an example, the tracking phase is cycled continuously to dynamically update the division ratio.

[0111] In the fifth step, the clock generation unit extracts the clock according to the frequency division ratio of each stage, which is actually the r_data_valid signal of the data. When r_data_valid is valid, the data is sampled and the sampling result is saved to the tmp[2:0] shift register. When the value of the shift register is 001 or 110, the module enters the decoding stage.

[0112] It can be understood that in some embodiments of the present application, the frequency division ratio r_div_n of the clock generation unit can be derived from different stages. When the transmission is in the fast blind detection stage, r_div_n=w_fast_div_n. When the transmission is in the capture stage, r_div_n=w_cap_div_n. When the transmission is in the tracking stage, r_div_n=w_track_div_n. When the counter counts to r_div_n / 2, the r_data_valid signal is generated. At this time, the r_data_valid signal has already characterized the clock information required by the Manchester code stream. Sampling and decoding processing can be performed when r_data_valid is valid.

[0113] Step 6: The decoding unit completes the data decoding. When r_data_valid is valid, the data is sampled and the values ​​of two consecutive samples are temporarily stored in the r_prdata register. For example, if the r_prdata value is equal to 2'b10, it is translated into 1'b1; if the r_prdata value is equal to 2'b01, it is translated into 1'b0; if the r_prdata value is equal to 2'b00 or 2'b11, the decoding is wrong and the decoding stops.

[0114] It should be noted that in some embodiments of the present application, the number of high and low level accumulated values ​​in the capture phase or the tracking phase is adjustable, and those skilled in the art can adjust the values ​​of M and P according to actual needs.

[0115] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0116] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0117] If the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, and other media that can store program codes.

[0118] The above description is only an embodiment of the present application and is not intended to limit the scope of protection of the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0119] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0120] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

Claims

1. A clock extraction method based on Manchester code, the clock extraction method comprising: In the rapid blind test phase: The data rate frequency division ratio is estimated according to the transition edge of the Manchester code stream to obtain the edge detection frequency division ratio value; Repeat the following process at least once during the capture and tracking phase: Sampling and counting a plurality of continuous high levels and a plurality of continuous low levels in the Manchester code stream, and obtaining high level count values ​​corresponding to the plurality of continuous high levels and low level count values ​​corresponding to the plurality of continuous low levels; Calculate the high level count value, the low level count value and the edge detection frequency division ratio value according to a statistical algorithm to obtain a target frequency division ratio mean value; Providing the target frequency division ratio average value to a clock generation unit, so that the clock generation unit obtains a clock signal for decoding according to the target frequency division ratio average value; In the capture and tracking stage, the clock extraction method includes: During the capture phase: In the i-th cycle, sampling and counting are performed on M consecutive high levels and M consecutive low levels in the Manchester code stream, and an i-th captured high level count value corresponding to the M consecutive high levels and an i-th captured low level count value corresponding to the M consecutive low levels are obtained; Calculate the i-th captured high level count value, the i-th captured low level count value and the edge detection frequency division ratio value according to the statistical algorithm to obtain an i-th captured target frequency division ratio mean value; providing the i-th captured target frequency division ratio average value to the clock generating unit; Wherein, i is an integer greater than 1 and less than the capture cycle number threshold, and M is an integer greater than 1; During the tracking phase: In the kth cycle, sampling and counting P consecutive high levels and P consecutive low levels in the Manchester code stream, obtaining a kth tracking high level count value corresponding to the P consecutive high levels and a kth tracking low level count value corresponding to the P consecutive low levels; Calculate the kth tracking high level count value, the kth tracking low level count value and the edge detection frequency division ratio value according to the statistical algorithm to obtain a kth tracking target frequency division ratio mean value; providing the kth tracking target frequency division ratio average value to the clock generating unit; Wherein, k is an integer greater than 1, and P is an integer greater than 1 and greater than M.

2. The clock extraction method according to claim 1, characterized in that: The step of estimating the data rate frequency division ratio according to the transition edge of the Manchester code stream to obtain the edge detection frequency division ratio value comprises: Record the count value between the first edge and the second edge by the system clock to obtain a first count value N1; Recording the count value from the second edge to the first edge by the system clock to obtain a second count value N2; Calculate the edge detection frequency division ratio according to the first count value and the second count value; The first edge is a rising edge and the second edge is a falling edge, or the first edge is a falling edge and the second edge is a rising edge.

3. The clock extraction method according to claim 2, characterized in that: The first edge is a rising edge and the second edge is a falling edge, wherein, The calculating the edge detection frequency division ratio according to the first count value and the second count value comprises: If it is confirmed that the leading code of the Manchester code stream is at least one group of 000, 111, 001 or 110, the calculation formula of the edge detection frequency division ratio is: w_fast_div_n=(N1+N2) / 2; If it is confirmed that the leading code of the Manchester code stream is at least one group of 010 or 101, the calculation formula of the edge detection frequency division ratio is: w_fast_div_n=(N1+N2) / 4; If it is confirmed that the leading code of the Manchester code stream is at least one group of 011, the calculation formula of the edge detection frequency division ratio is: w_fast_div_n=(2×N1+N2) / 4; If it is confirmed that the leading code of the Manchester code stream is at least one group of 100, the calculation formula of the edge detection frequency division ratio is: w_fast_div_n=(N1+2×N2) / 4.

4. The clock extraction method according to claim 1, characterized in that: The value of M is 2, the i-th captured high level count value is N3, the i-th captured low level count value is N4, and the edge detection frequency division ratio value is w_fast_div_n, wherein, The step of calculating the i-th captured high level count value, the i-th captured low level count value, and the edge detection frequency division ratio value according to the statistical algorithm to obtain the i-th captured target frequency division ratio mean value includes: The i-th capture target frequency division ratio mean value w_cap_div_n is calculated according to the following first statistical algorithm formula: w_cap_div_n=(N3+N4+4×w_fast_div_n) / 8.

5. The clock extraction method according to claim 4, characterized in that: The value of P is 8, the k-th tracking high level count value is N5, and the k-th tracking low level count value is N6, wherein, The step of calculating the kth tracking high level count value, the kth tracking low level count value, and the edge detection frequency division ratio value according to the statistical algorithm to obtain the kth tracking target frequency division ratio mean value includes: The k-th tracking target frequency division ratio mean value w_track_div_n is calculated according to the following second statistical algorithm formula: w_track_div_n=(N5+N6+16×w_cap_div_n) / 32.

6. A decoding method, the decoding method comprising: In the rapid blind test phase: The data rate frequency division ratio is estimated according to the transition edge of the Manchester code stream to obtain the edge detection frequency division ratio value; Repeat the following process at least once during the capture and tracking phase: Sampling and counting a plurality of continuous high levels and a plurality of continuous low levels in the Manchester code stream, and obtaining high level count values ​​corresponding to the plurality of continuous high levels and low level count values ​​corresponding to the plurality of continuous low levels; Calculate the high level count value, the low level count value and the edge detection frequency division ratio value according to a statistical algorithm to obtain a target frequency division ratio mean value, and provide the target frequency division ratio mean value to a clock generation unit; In the decoding stage: Decoding the Manchester code stream by using a clock output signal obtained by the clock generating unit according to the target frequency division ratio average value; In the capture and tracking stage, the clock extraction method includes: During the capture phase: In the i-th cycle, sampling and counting are performed on M consecutive high levels and M consecutive low levels in the Manchester code stream, and an i-th captured high level count value corresponding to the M consecutive high levels and an i-th captured low level count value corresponding to the M consecutive low levels are obtained; Calculate the i-th captured high level count value, the i-th captured low level count value and the edge detection frequency division ratio value according to the statistical algorithm to obtain an i-th captured target frequency division ratio mean value; providing the i-th captured target frequency division ratio average value to the clock generating unit; Wherein, i is an integer greater than 1 and less than the capture cycle number threshold, and M is an integer greater than 1; During the tracking phase: In the kth cycle, sampling and counting P consecutive high levels and P consecutive low levels in the Manchester code stream, obtaining a kth tracking high level count value corresponding to the P consecutive high levels and a kth tracking low level count value corresponding to the P consecutive low levels; Calculate the kth tracking high level count value, the kth tracking low level count value and the edge detection frequency division ratio value according to the statistical algorithm to obtain a kth tracking target frequency division ratio mean value; providing the kth tracking target frequency division ratio average value to the clock generating unit; Wherein, k is an integer greater than 1, and P is an integer greater than 1 and greater than M.

7. A device for clock extraction, characterized in that: The device comprises: The fast blind detection unit is configured to: The data rate frequency division ratio is estimated according to the transition edge of the Manchester code stream to obtain the edge detection frequency division ratio value; The capture and tracking unit is configured to repeat the following process at least once during the capture and tracking phase: Sampling and counting a plurality of continuous high levels and a plurality of continuous low levels in the Manchester code stream, and obtaining high level count values ​​corresponding to the plurality of continuous high levels and low level count values ​​corresponding to the plurality of continuous low levels; Calculate the high level count value, the low level count value and the edge detection frequency division ratio value according to a statistical algorithm to obtain a target frequency division ratio mean value; A clock generating unit, configured to obtain a decoding clock signal according to the target frequency division ratio average value; The capture and tracking unit comprises: The capture unit is configured as: In the i-th cycle, sampling and counting are performed on M consecutive high levels and M consecutive low levels in the Manchester code stream, and an i-th captured high level count value corresponding to the M consecutive high levels and an i-th captured low level count value corresponding to the M consecutive low levels are obtained; Calculate the i-th captured high level count value, the i-th captured low level count value and the edge detection frequency division ratio value according to the statistical algorithm to obtain an i-th captured target frequency division ratio mean value; providing the i-th captured target frequency division ratio mean value to the clock generating unit; Wherein, i is an integer greater than 1 and less than the capture cycle number threshold, and M is an integer greater than 1; The tracking unit is configured to: In the kth cycle, sampling and counting P consecutive high levels and P consecutive low levels in the Manchester code stream, obtaining a kth tracking high level count value corresponding to the P consecutive high levels and a kth tracking low level count value corresponding to the P consecutive low levels; Calculate the kth tracking high level count value, the kth tracking low level count value and the edge detection frequency division ratio value according to the statistical algorithm to obtain a kth tracking target frequency division ratio mean value; providing the kth tracking target frequency division ratio average value to the clock generating unit; Wherein, k is an integer greater than 1, and P is an integer greater than 1 and greater than M.

8. A decoding device, characterized in that: The decoding device comprises: the device for clock extraction as claimed in claim 7 and a decoding unit, wherein the decoding unit is configured to perform decoding on the Manchester code stream according to the clock signal provided by the device for clock extraction.

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