Light ray detection structure and method thereof, display substrate and display device

Abstract

A light detection structure and a method thereof, a display substrate and a display device, wherein the light detection structure can include a photoelectric conversion device, a current conversion device and a control device; the photoelectric conversion device is electrically connected with the current conversion device, is arranged to convert incident light of N colors into a current signal, and provides the current signal to the current conversion device under the control of a control signal; the current conversion device is arranged to convert the current signal into a voltage signal corresponding to the current signal; the control device is electrically connected with the photoelectric conversion device and the current conversion device respectively, is arranged to generate the control signal, and generates a chromaticity parameter of the light according to the voltage signal corresponding to the current signal, the chromaticity parameter including brightness, color temperature and color coordinates.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of light detection technology, specifically to a light detection structure and method, a display substrate, and a display device. Background Technology

[0002] With the widespread use of artificial intelligence technology, AI technology has been applied to mobile display products, enabling these products to customize applications for specific environments based on the user's context, thereby enhancing the user experience in different settings. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] In a first aspect, this disclosure provides a light detection structure, including: a photoelectric conversion device, a current conversion device, and a control device;

[0005] The photoelectric conversion device is electrically connected to the current conversion device and is configured to convert incident light of N colors into current signals, and provide the current signals to the current conversion device under the control of a control signal, where N is a positive integer greater than or equal to 1.

[0006] The current conversion device is configured to convert the current signal into a voltage signal corresponding to the current signal; the control device is electrically connected to the photoelectric conversion device and the current conversion device respectively, and is configured to generate a control signal and generate chromaticity parameters of light according to the voltage signal corresponding to the current signal, wherein the chromaticity parameters include: brightness, color temperature, and color coordinates.

[0007] In some possible implementations, when N=4, the photoelectric conversion device includes: four photoelectric conversion elements; the four photoelectric conversion elements include: a first photoelectric conversion element, a second photoelectric conversion element, a third photoelectric conversion element, and a fourth photoelectric conversion element, and the current signal includes: a first current signal, a second current signal, a third current signal, and a fourth current signal;

[0008] The first photoelectric conversion element is electrically connected to the sensing signal terminal and the first node respectively, and is configured to convert the incident light of the first color into a first current signal and write the first current signal into the first node;

[0009] The second photoelectric conversion element is electrically connected to the sensing signal terminal and the second node, respectively, and is configured to convert the incident light of the second color into a second current signal and write the second current signal into the second node;

[0010] The third photoelectric conversion element is electrically connected to the sensing signal terminal and the third node, respectively, and is configured to convert the incident third color light into a third current signal and write the third current signal into the third node;

[0011] The fourth photoelectric conversion element is electrically connected to the sensing signal terminal and the fourth node, respectively, and is configured to convert the incident fourth color light into a fourth current signal and write the fourth current signal into the fourth node;

[0012] The first color, the second color, the third color, and the fourth color are one of red, green, blue, and white, and the first color, the second color, the third color, and the fourth color are different colors, and the voltage value of the signal at the sensing signal terminal is constant.

[0013] In some possible implementations, the first photoelectric conversion element includes: a first photoelectric sensor; the second photoelectric conversion element includes: a second photoelectric sensor; the third photoelectric conversion element includes: a third photoelectric sensor; and the fourth photoelectric conversion element includes: a fourth photoelectric sensor.

[0014] The anode of the first photoelectric sensor is electrically connected to the first node, and the cathode of the first photoelectric sensor is electrically connected to the sensing signal terminal. The anode of the second photoelectric sensor is electrically connected to the second node, and the cathode of the second photoelectric sensor is electrically connected to the sensing signal terminal. The anode of the third photoelectric sensor is electrically connected to the third node, and the cathode of the third photoelectric sensor is electrically connected to the sensing signal terminal. The anode of the fourth photoelectric sensor is electrically connected to the fourth node, and the cathode of the fourth photoelectric sensor is electrically connected to the sensing signal terminal.

[0015] Alternatively, the cathode of the first photoelectric sensor is electrically connected to the first node, the anode of the first photoelectric sensor is electrically connected to the sensing signal terminal, the cathode of the second photoelectric sensor is electrically connected to the second node, the anode of the second photoelectric sensor is electrically connected to the sensing signal terminal, the cathode of the third photoelectric sensor is electrically connected to the third node, the anode of the third photoelectric sensor is electrically connected to the sensing signal terminal, the cathode of the fourth photoelectric sensor is electrically connected to the fourth node, and the anode of the fourth photoelectric sensor is electrically connected to the sensing signal terminal.

[0016] In some possible implementations, the photoelectric conversion device further includes: a component selection circuit and a gear selection circuit; the control signals include: a first component selection signal to a fourth component selection signal and a first gear selection signal to a fourth gear selection signal;

[0017] The component selection circuit is electrically connected to the first component selection signal terminal to the fourth component selection signal terminal, the first node, the second node, the third node, the fourth node, and the fifth node, respectively. It is configured to provide the first node, the second node, the third node, or the fourth node to the fifth node in a time-division manner under the control of the signals from the first component selection signal terminal to the fourth component selection signal terminal. The signal of the i-th component selection signal terminal is the i-th component selection signal, where i is 1 to 4.

[0018] The gear selection circuit is electrically connected to the first gear selection signal terminal to the fourth gear selection signal terminal, the fifth node, the sixth node, the seventh node, the eighth node, and the ninth node, respectively. It is configured to provide the signal of the fifth node to the sixth node, the seventh node, the eighth node, and the ninth node in a time-division manner under the control of the signals from the first gear selection signal terminal to the fourth gear selection signal terminal. The signal of the i-th gear selection signal terminal is the i-th gear selection signal.

[0019] In some possible implementations, when the selection signal of the i-th element is an active level signal, all other element selection signals are inactive level signals, and the end time of the active level signal of the i-th element selection signal is earlier than or equal to the start time of the active level signal of the (i+1)-th element selection signal.

[0020] When the i-th gear selection signal is an active level signal, all other gear selection signals are inactive level signals.

[0021] When the i-th element selection signal is an active level signal, the first gear selection signal to the fourth gear selection signal are active level signals in sequence, and the duration of the i-th element selection signal being an active level signal is greater than or equal to the sum of the durations of the first gear selection signal to the fourth gear selection signal being active level signals.

[0022] In some possible implementations, when the end time of the i-th element selection signal being an active level signal is earlier than the start time of the (i+1)-th element selection signal being an active level signal, the interval between the end time of the i-th element selection signal being an active level signal and the start time of the (i+1)-th element selection signal being an active level signal is equal to the duration of any of the first to fourth gear selection signals being an active level signal.

[0023] In some possible implementations, the component selection circuit includes: a first component selection sub-circuit to a fourth component selection sub-circuit;

[0024] The first element selection sub-circuit is electrically connected to the first element selection signal terminal, the first node, and the fifth node, respectively, and is configured to provide the signal of the first node to the fifth node under the control of the signal of the first element selection signal terminal;

[0025] The second element selection sub-circuit is electrically connected to the second element selection signal terminal, the second node, and the fifth node, respectively, and is configured to provide the signal of the second node to the fifth node under the control of the signal of the second element selection signal terminal;

[0026] The third element selection sub-circuit is electrically connected to the third element selection signal terminal, the third node, and the fifth node, respectively, and is configured to provide the signal of the third node to the fifth node under the control of the signal of the third element selection signal terminal;

[0027] The fourth element selection sub-circuit is electrically connected to the fourth element selection signal terminal, the fourth node, and the fifth node, respectively, and is configured to provide the signal of the fourth node to the fifth node under the control of the signal of the fourth element selection signal terminal.

[0028] In some possible implementations, the first element selection sub-circuit includes a first element selection transistor, the second element selection sub-circuit includes a second element selection transistor, the third element selection sub-circuit includes a third element selection transistor, and the fourth element selection sub-circuit includes a fourth element selection transistor.

[0029] The control electrode of the first element selection transistor is electrically connected to the first element selection signal terminal, the first electrode of the first element selection transistor is electrically connected to the first node, and the second electrode of the first element selection transistor is electrically connected to the fifth node.

[0030] The control terminal of the second element selection transistor is electrically connected to the second element selection signal terminal, the first terminal of the second element selection transistor is electrically connected to the second node, and the second terminal of the second element selection transistor is electrically connected to the fifth node.

[0031] The control terminal of the third element selection transistor is electrically connected to the third element selection signal terminal, the first terminal of the third element selection transistor is electrically connected to the third node, and the second terminal of the third element selection transistor is electrically connected to the fifth node.

[0032] The control terminal of the fourth element selection transistor is electrically connected to the fourth element selection signal terminal, the first terminal of the fourth element selection transistor is electrically connected to the fourth node, and the second terminal of the fourth element selection transistor is electrically connected to the fifth node.

[0033] In some possible implementations, the gear selection circuit includes: a first gear selection sub-circuit to a fourth gear selection sub-circuit;

[0034] The first gear selection sub-circuit is electrically connected to the first gear selection signal terminal, the fifth node, and the sixth node, respectively, and is configured to provide the signal of the fifth node to the sixth node under the control of the signal of the first gear selection signal terminal;

[0035] The second gear selection sub-circuit is electrically connected to the second gear selection signal terminal, the fifth node, and the seventh node, respectively, and is configured to provide the signal of the fifth node to the seventh node under the control of the signal of the second gear selection signal terminal;

[0036] The third gear selection sub-circuit is electrically connected to the third gear selection signal terminal, the fifth node, and the eighth node, respectively, and is configured to provide the signal of the fifth node to the eighth node under the control of the signal of the third gear selection signal terminal.

[0037] The fourth position selection sub-circuit is electrically connected to the fourth position selection signal terminal, the fifth node, and the ninth node, respectively, and is configured to provide the signal of the fifth node to the ninth node under the control of the signal of the fourth position selection signal terminal.

[0038] In some possible implementations, the first gear selection sub-circuit includes a first gear selection transistor, the second gear selection sub-circuit includes a second gear selection transistor, the third gear selection sub-circuit includes a third gear selection transistor, and the fourth gear selection sub-circuit includes a fourth gear selection transistor.

[0039] The control electrode of the first gear selection transistor is electrically connected to the first gear selection signal terminal, the first electrode of the first gear selection transistor is electrically connected to the fifth node, and the second electrode of the first gear selection transistor is electrically connected to the sixth node.

[0040] The control electrode of the second-position selection transistor is electrically connected to the second-position selection signal terminal, the first electrode of the second-position selection transistor is electrically connected to the fifth node, and the second electrode of the second-position selection transistor is electrically connected to the seventh node.

[0041] The control electrode of the third-position selection transistor is electrically connected to the third-position selection signal terminal, the first electrode of the third-position selection transistor is electrically connected to the fifth node, and the second electrode of the third-position selection transistor is electrically connected to the eighth node.

[0042] The control electrode of the fourth position selection transistor is electrically connected to the fourth position selection signal terminal, the first electrode of the fourth position selection transistor is electrically connected to the fifth node, and the second electrode of the fourth position selection transistor is electrically connected to the ninth node.

[0043] In some possible implementations, the voltage signal includes: a first voltage signal to a fourth voltage signal, and the current conversion device includes: a sampling circuit and a filtering circuit;

[0044] The sampling circuit is electrically connected to the sixth to thirteenth nodes and the reference signal terminal, respectively. It is configured to sample the signals of the sixth to ninth nodes, generate the first to fourth initial voltage signals corresponding to the current signals, and provide the first to fourth initial voltage signals corresponding to the current signals to the tenth to thirteenth nodes, respectively.

[0045] The filtering circuit is electrically connected to the tenth to thirteenth nodes, the ground terminal, and the control device, respectively. It is configured to filter the first to fourth initial voltage signals corresponding to the current signal to generate the first to fourth voltage signals corresponding to the current signal, and provide the first to fourth voltage signals corresponding to the current signal to the control device, respectively.

[0046] In some possible implementations, the sampling circuit includes: a first sampling sub-circuit, a second sampling sub-circuit, a third sampling sub-circuit, and a fourth sampling sub-circuit;

[0047] The first sampling sub-circuit is electrically connected to the sixth node, the tenth node and the reference signal terminal respectively, and is configured to sample the signal of the sixth node, generate a first initial voltage signal corresponding to the current signal, and provide the first initial voltage signal corresponding to the current signal to the tenth node.

[0048] The second sampling sub-circuit is electrically connected to the seventh node, the eleventh node and the reference signal terminal respectively, and is configured to sample the signal of the seventh node, generate the second initial voltage signal corresponding to the current signal, and provide the second initial voltage signal corresponding to the current signal to the eleventh node.

[0049] The third sampling sub-circuit is electrically connected to the eighth node, the twelfth node and the reference signal terminal respectively, and is configured to sample the signal of the eighth node, generate the third initial voltage signal corresponding to the current signal, and provide the third initial voltage signal corresponding to the current signal to the twelfth node.

[0050] The fourth sampling sub-circuit is electrically connected to the ninth node, the thirteenth node and the reference signal terminal, respectively. It is configured to sample the signal of the ninth node, generate the fourth initial voltage signal corresponding to the current signal, and provide the fourth initial voltage signal corresponding to the current signal to the thirteenth node.

[0051] In some possible implementations, the first sampling sub-circuit includes: a first operational amplifier, a first sampling resistor, and a first feedback capacitor; the second sampling sub-circuit includes: a second operational amplifier, a second sampling resistor, and a second feedback capacitor; the third sampling sub-circuit includes: a third operational amplifier, a third sampling resistor, and a third feedback capacitor; and the fourth sampling sub-circuit includes: a fourth operational amplifier, a fourth sampling resistor, and a fourth feedback capacitor.

[0052] The non-inverting input terminal of the first operational amplifier is electrically connected to the reference signal terminal, the inverting input terminal of the first operational amplifier is electrically connected to the sixth node, and the output terminal of the first operational amplifier is electrically connected to the tenth node.

[0053] The first end of the first sampling resistor is electrically connected to the sixth node, and the second end of the first sampling resistor is electrically connected to the tenth node.

[0054] The first terminal of the first feedback capacitor is electrically connected to the sixth node, and the second terminal of the first feedback capacitor is electrically connected to the tenth node.

[0055] The non-inverting input of the second operational amplifier is electrically connected to the reference signal terminal, the inverting input of the second operational amplifier is electrically connected to the seventh node, and the output of the second operational amplifier is electrically connected to the eleventh node.

[0056] The first end of the second sampling resistor is electrically connected to the seventh node, and the second end of the second sampling resistor is electrically connected to the eleventh node.

[0057] The first terminal of the second feedback capacitor is electrically connected to the seventh node, and the second terminal of the second feedback capacitor is electrically connected to the eleventh node.

[0058] The non-inverting input of the third operational amplifier is electrically connected to the reference signal terminal, the inverting input of the third operational amplifier is electrically connected to the eighth node, and the output of the third operational amplifier is electrically connected to the twelfth node.

[0059] The first end of the third sampling resistor is electrically connected to the eighth node, and the second end of the third sampling resistor is electrically connected to the twelfth node.

[0060] The first terminal of the third feedback capacitor is electrically connected to the eighth node, and the second terminal of the third feedback capacitor is electrically connected to the twelfth node.

[0061] The non-inverting input of the fourth operational amplifier is electrically connected to the reference signal terminal, the inverting input of the fourth operational amplifier is electrically connected to the ninth node, and the output of the fourth operational amplifier is electrically connected to the thirteenth node.

[0062] The first end of the fourth sampling resistor is electrically connected to the ninth node, and the second end of the fourth sampling resistor is electrically connected to the thirteenth node.

[0063] The first terminal of the fourth feedback capacitor is electrically connected to the ninth node, and the second terminal of the fourth feedback capacitor is electrically connected to the thirteenth node.

[0064] The resistances R1, R2, R3, and R4 of the first sampling resistor: R1 = K × R2 = K 2 ×R3=K3 ×R4, where K is a positive integer greater than 1.

[0065] In some possible implementations, the filter circuit includes: a first filter sub-circuit, a second filter sub-circuit, a third filter sub-circuit, and a fourth filter sub-circuit;

[0066] The first filter sub-circuit is electrically connected to the tenth node, the ground terminal and the control device respectively, and is configured to filter the signal of the tenth node to generate a first voltage signal corresponding to the current signal, and provide the first voltage signal corresponding to the current signal to the control device.

[0067] The second filter sub-circuit is electrically connected to the eleventh node, the ground terminal and the control device, respectively, and is configured to filter the signal of the eleventh node, generate the second voltage signal corresponding to the current signal, and provide the second voltage signal corresponding to the current signal to the control device.

[0068] The third filter sub-circuit is electrically connected to the twelfth node, the ground terminal, and the control device, respectively, and is configured to filter the signal of the twelfth node, generate the third voltage signal corresponding to the current signal, and provide the third voltage signal corresponding to the current signal to the control device.

[0069] The fourth filter sub-circuit is electrically connected to the thirteenth node, the ground terminal, and the control device, respectively. It is configured to filter the signal of the thirteenth node, generate a fourth voltage signal corresponding to the current signal, and provide the fourth voltage signal corresponding to the current signal to the control device.

[0070] In some possible implementations, the first filter sub-circuit includes: a first filter resistor and a first filter capacitor; the second filter sub-circuit includes: a second filter resistor and a second filter capacitor; the third filter sub-circuit includes: a third filter resistor and a third filter capacitor; and the fourth filter sub-circuit includes: a fourth filter resistor and a fourth filter capacitor.

[0071] The first end of the first filter resistor is electrically connected to the tenth node, the second end of the first filter resistor is electrically connected to the control device and the first end of the first filter capacitor, and the second end of the first filter capacitor is electrically connected to the ground terminal.

[0072] The first end of the second filter resistor is electrically connected to the eleventh node, the second end of the second filter resistor is electrically connected to the control device and the first end of the second filter capacitor, and the second end of the second filter capacitor is electrically connected to the ground terminal.

[0073] The first end of the third filter resistor is electrically connected to the twelfth node, the second end of the third filter resistor is electrically connected to the control device and the first end of the third filter capacitor, and the second end of the third filter capacitor is electrically connected to the ground terminal.

[0074] The first end of the fourth filter resistor is electrically connected to the thirteenth node, the second end of the fourth filter resistor is electrically connected to the control device and the first end of the fourth filter capacitor, and the second end of the fourth filter capacitor is electrically connected to the ground terminal.

[0075] In some possible implementations, the control device includes: an analog-to-digital converter, a controller, and a level converter;

[0076] The analog-to-digital conversion element is electrically connected to the filter circuit and is configured to convert the first voltage signal to the fourth voltage signal corresponding to the current signal into the first digital voltage signal to the fourth digital voltage signal corresponding to the current signal.

[0077] The controller is electrically connected to the analog-to-digital conversion element and is configured to generate a first initial element selection signal to a fourth initial element selection signal and a first initial gear selection signal to a fourth initial gear selection signal, and to generate chromaticity parameters of light according to the first digital voltage signal to the fourth digital voltage signal corresponding to the current signal.

[0078] The level converter is electrically connected to the controller, the first component selection signal terminal to the fourth component selection signal terminal, and the first gear selection signal terminal to the fourth gear selection signal terminal. It is configured to perform level conversion on the first initial component selection signal to the fourth initial component selection signal to generate the first component selection signal to the fourth component selection signal, and provide the first component selection signal to the fourth component selection signal terminal respectively. It also performs level conversion on the first initial gear selection signal to the fourth initial gear selection signal to generate the first gear selection signal to the fourth gear selection signal, and provide the first gear selection signal to the fourth gear selection signal terminal respectively.

[0079] In some possible implementations, the analog-to-digital conversion element includes: a signal selector, a signal buffer, and an analog-to-digital converter;

[0080] The signal selector is electrically connected to the filter circuit and the signal buffer respectively, and is configured to transmit the first voltage signal to the fourth voltage signal corresponding to the current signal to the signal buffer in a time-division manner.

[0081] The signal buffer is configured to store the first to fourth voltage signals corresponding to the time-division input current signals of the signal selector;

[0082] The analog-to-digital converter is electrically connected to the signal buffer and is configured to convert the first to fourth voltage signals corresponding to the current signals in the signal buffer into the first to fourth digital voltage signals corresponding to the current signals in a time-division multiplexing manner.

[0083] In some possible implementations, the voltage value of the signal at the reference signal terminal is constant, and the voltage value of the signal at the reference signal terminal is less than the maximum input voltage value of the analog-to-digital converter and greater than the minimum input voltage value of the analog-to-digital converter.

[0084] In some possible implementations, the controller includes: eight first interfaces configured as standard general purpose input / output ports;

[0085] The eight first interfaces are electrically connected to the level converter and are configured to transmit the first initial element selection signal to the fourth initial element selection signal and the first initial gear selection signal to the fourth initial gear selection signal, respectively.

[0086] In some possible implementations, the controller further includes: a first digital register to a fourth digital register;

[0087] The controller is configured to pre-store a first threshold voltage value and a second threshold voltage value, sequentially determine whether the voltage values ​​of the first to fourth digital voltage signals corresponding to the i-th current signal meet the threshold conditions, convert the digital voltage signal corresponding to the i-th current signal that meets the threshold conditions into a full-range digital voltage signal, and store the converted full-range digital voltage signal in the i-th digital register. It is also configured to generate the chromaticity parameters of light based on the full-range digital voltage signals in the first to fourth digital registers.

[0088] The threshold condition for the first digital voltage signal corresponding to the i-th current signal is greater than the second threshold voltage value. The threshold conditions for the second and third digital voltage signals corresponding to the i-th current signal are greater than the first threshold voltage value and less than the second threshold voltage value. The threshold condition for the fourth digital voltage signal corresponding to the i-th current signal is less than the first threshold voltage value. The first threshold voltage value is greater than the minimum input voltage value of the analog-to-digital converter, and the second threshold voltage value is less than the maximum input voltage value of the mode converter.

[0089] The difference between the minimum input voltage value of the analog-to-digital converter and the first threshold voltage value is equal to the difference between the maximum output voltage value of the analog-to-digital converter and the second threshold voltage value.

[0090] In some possible implementations, the controller is configured according to formula V Dcount =V Dj / Gain j The j-th digital voltage signal is converted into a full-range digital voltage signal Dcount, where the j-th digital voltage signal is the digital voltage signal corresponding to the i-th current signal that meets the threshold condition, and Gain j Gain is the magnification factor. j =K j V Dcount The voltage value of the full-range digital voltage signal, V Dj Let be the voltage value of the j-th digital voltage signal, where j = 1, 2, 3, or 4.

[0091] In some possible implementations, the control device further includes: a transmission interface connected to the controller, the transmission interface being configured as a serial interface and set to transmit the chromaticity parameters of the light generated by the controller;

[0092] The transmission interface includes: I 2 C interface or SPI interface.

[0093] Secondly, this disclosure also provides a display substrate, including: a display area and a non-display area, wherein the non-display area is provided with the above-mentioned light detection structure.

[0094] In some possible implementations, the non-display area includes a border area and a binding area, the binding area being located on the side of the border area away from the display area, the photoelectric conversion device in the light detection structure being disposed in the border area, and the current conversion device and control device in the light detection structure being disposed in the binding area.

[0095] Thirdly, this disclosure also provides a display device, including: the aforementioned display substrate.

[0096] Among some possible implementations, an application is also included;

[0097] The application is electrically connected to the light detection structure in the display substrate and is configured to acquire the chromaticity parameters of the light.

[0098] Fourthly, this disclosure also provides a light detection method applied to the above-mentioned light detection structure, the method comprising:

[0099] The control device generates control signals;

[0100] The photoelectric conversion device converts incident light of N colors into current signals, and provides the current signals under the control of the control signal;

[0101] The current conversion device converts the current signal into a voltage signal corresponding to the current signal;

[0102] The control device generates chromaticity parameters of the light based on the voltage signal corresponding to the current signal. The chromaticity parameters include: brightness, color temperature, and color coordinates.

[0103] In some possible implementations, the photoelectric conversion device converts incident N colors of light into electrical signals including:

[0104] The incident light of the first color is converted into a first current signal and written into the first node; the incident light of the second color is converted into a second current signal and written into the second node; the incident light of the third color is converted into a third current signal and written into the third node; the incident light of the fourth color is converted into a fourth current signal and written into the fourth node.

[0105] The photoelectric conversion device, under the control of a control signal, provides the current signal to the current conversion device, including:

[0106] Under the control of the signals from the first element selection signal terminal to the fourth element selection signal terminal, the signals of the first node, the second node, the third node, or the fourth node are provided to the fifth node in a time-division manner;

[0107] Under the control of the signals from the first gear selection signal terminal to the fourth gear selection signal terminal, the signal of the fifth node is provided to the sixth, seventh, eighth and ninth nodes in a time-division manner;

[0108] The provision of signals from the first element selection signal terminal to the fourth element selection signal terminal to the fifth node in a time-division manner includes: providing the first node's signal to the fifth node under the control of the first element selection signal terminal; providing the second node's signal to the fifth node under the control of the second element selection signal terminal; providing the third node's signal to the fifth node under the control of the third element selection signal terminal; and providing the fourth node's signal to the fifth node under the control of the fourth element selection signal terminal.

[0109] The provision of the signal of the fifth node to the sixth, seventh, eighth, and ninth nodes in a time-division manner, under the control of the signals from the first to the fourth gear selection signal terminals, includes: providing the signal of the fifth node to the sixth node under the control of the signal from the first gear selection signal terminal; providing the signal of the fifth node to the seventh node under the control of the signal from the second gear selection signal terminal; providing the signal of the fifth node to the eighth node under the control of the signal from the third gear selection signal terminal; and providing the signal of the fifth node to the ninth node under the control of the signal from the fourth gear selection signal terminal.

[0110] In some possible implementations, the voltage signal includes: a first voltage signal to a fourth voltage signal, and the current conversion device converts the current signal into a voltage signal corresponding to the current signal by:

[0111] The signals from the sixth to the ninth nodes are sampled to generate the first to fourth initial voltage signals corresponding to the current signals, and the first to fourth initial voltage signals corresponding to the current signals are provided to the tenth to the thirteenth nodes respectively.

[0112] The first to fourth initial voltage signals corresponding to the current signal are filtered to generate the first to fourth voltage signals corresponding to the current signal, and the first to fourth voltage signals corresponding to the current signal are respectively provided to the control device.

[0113] The step of sampling the signals from the sixth to the ninth nodes to generate the first to fourth initial voltage signals corresponding to the current signals, and providing the first to fourth initial voltage signals corresponding to the current signals to the tenth to the thirteenth nodes respectively, includes: sampling the signal from the sixth node to generate the first initial voltage signal corresponding to the current signal and providing the first initial voltage signal corresponding to the current signal to the tenth node; sampling the signal from the seventh node to generate the second initial voltage signal corresponding to the current signal and providing the second initial voltage signal corresponding to the current signal to the eleventh node; sampling the signal from the eighth node to generate the third initial voltage signal corresponding to the current signal and providing the third initial voltage signal corresponding to the current signal to the twelfth node; and sampling the signal from the ninth node to generate the fourth initial voltage signal corresponding to the current signal and providing the fourth initial voltage signal corresponding to the current signal to the thirteenth node.

[0114] The step of filtering the first to fourth initial voltage signals corresponding to the current signal to generate the first to fourth voltage signals corresponding to the current signal, and providing the first to fourth voltage signals corresponding to the current signal to the control device respectively, includes: filtering the signal of the tenth node to generate the first voltage signal corresponding to the current signal and providing the first voltage signal corresponding to the current signal to the control device; filtering the signal of the eleventh node to generate the second voltage signal corresponding to the current signal and providing the second voltage signal corresponding to the current signal to the control device; filtering the signal of the twelfth node to generate the third voltage signal corresponding to the current signal and providing the third voltage signal corresponding to the current signal to the control device; and filtering the signal of the thirteenth node to generate the fourth voltage signal corresponding to the current signal and providing the fourth voltage signal corresponding to the current signal to the control device.

[0115] In some possible implementations, the control device generates chromaticity parameters of the light based on the voltage signal corresponding to the current signal, including:

[0116] Convert the first to fourth voltage signals corresponding to the current signal into the first to fourth digital voltage signals corresponding to the current signal;

[0117] The chromaticity parameters of the light are generated based on the first to fourth digital voltage signals corresponding to the current signal.

[0118] In some possible implementations, generating the chromaticity parameters of the light based on the first to fourth digital voltage signals corresponding to the current signal includes:

[0119] The first threshold voltage value and the second threshold voltage value are stored in advance;

[0120] Sequentially determine whether the voltage values ​​of the first to fourth digital voltage signals corresponding to the i-th current signal meet the corresponding threshold conditions, convert the digital voltage signal corresponding to the i-th current signal that meets the corresponding threshold conditions into a full-range digital voltage signal, and store the converted full-range digital voltage signal in the i-th digital register;

[0121] The chromaticity parameters of the light are generated based on the full-range digital voltage signals in the first to fourth digital registers.

[0122] The threshold condition for the first digital voltage signal corresponding to the i-th current signal is greater than the second threshold voltage value. The threshold conditions for the second and third digital voltage signals corresponding to the i-th current signal are greater than the first threshold voltage value and less than the second threshold voltage value. The threshold condition for the fourth digital voltage signal corresponding to the i-th current signal is less than the first threshold voltage value. The first threshold voltage value is greater than the minimum input voltage value of the analog-to-digital converter, and the second threshold voltage value is less than the maximum input voltage value of the mode converter.

[0123] In some possible implementations, converting the digital voltage signal corresponding to the i-th current signal that satisfies the threshold condition into a full-range digital voltage signal includes:

[0124] According to formula V Dcount =V Dj / Gain j The j-th digital voltage signal is converted into a full-range digital voltage signal Dcount, where the j-th digital voltage signal is the digital voltage signal corresponding to the i-th current signal that meets the threshold condition, and Gain j Gain is the magnification factor. j=K j V Dcount The voltage value of the full-range digital voltage signal, V Dj Let be the voltage value of the j-th digital voltage signal, where j = 1, 2, 3, or 4.

[0125] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0126] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0127] Figure 1 This is a schematic diagram of the light detection structure provided in an embodiment of the present disclosure;

[0128] Figure 2 A schematic diagram of the structure of a photoelectric conversion device provided for an exemplary embodiment;

[0129] Figure 3 A schematic diagram of the structure of a photoelectric conversion device provided for another exemplary embodiment;

[0130] Figure 4 A schematic diagram of the structure of a current conversion device provided for an exemplary embodiment;

[0131] Figure 5 A schematic diagram of the structure of a current conversion device provided for another exemplary embodiment;

[0132] Figure 6 A schematic diagram of the structure of a control device provided for an exemplary embodiment;

[0133] Figure 7 A schematic diagram of the structure of a control device provided for another exemplary embodiment;

[0134] Figure 8 An equivalent schematic diagram of a light detection device provided for an exemplary embodiment;

[0135] Figure 9 This is a timing diagram of a control signal.

[0136] Figure 10 A flowchart of the light detection method provided in the embodiments of this disclosure;

[0137] Figure 11 This is a schematic diagram of the structure of a display substrate;

[0138] Figure 12 A schematic diagram of the structure of a display substrate provided for an exemplary embodiment. Detailed Implementation

[0139] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0140] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0141] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0142] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0143] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0144] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0145] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0146] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0147] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0148] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0149] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0150] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfered corners, curved edges, and other variations.

[0151] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0152] With the widespread application of artificial intelligence, to enhance the user experience, it's not enough to simply detect the brightness of ambient light; the color temperature of the ambient light must also be detected. This allows for better customization of applications for specific environments. Display products offer relatively limited access to lighting parameters, which cannot meet the demands of artificial intelligence.

[0153] Figure 1 This is a schematic diagram of the light detection structure provided in an embodiment of this disclosure. Figure 1 As shown, the light detection structure provided in this embodiment may include: a photoelectric conversion device 100, a current conversion device 200, and a control device 300.

[0154] like Figure 1 As shown, the photoelectric conversion device 100 can be electrically connected to the current conversion device 200, and is configured to convert incident light of N colors into current signals, and provide current signals to the current conversion device 200 under the control of a control signal, where N is a positive integer greater than or equal to 1. The current conversion device 200 is configured to convert the current signals into voltage signals corresponding to the current signals; the control device 300 is electrically connected to both the photoelectric conversion device 100 and the current conversion device 200, and is configured to generate control signals and generate chromaticity parameters of the light based on the voltage signals corresponding to the current signals.

[0155] In one exemplary embodiment, the chromaticity parameters may include: luminance, color temperature, and color coordinates. The chromaticity parameters may also include: other light parameters, which are not limited in this disclosure.

[0156] In one exemplary embodiment, the incident N colors of light can be ambient light, and may include multiple types of light such as red light, green light, blue light, or white light, without any limitation herein.

[0157] The light detection structure provided in this disclosure includes: a photoelectric conversion device, a current conversion device, and a control device. The photoelectric conversion device, electrically connected to the current conversion device, is configured to convert incident light of N colors into current signals and, under the control of a control signal, provide current signals to the current conversion device. The current conversion device is configured to convert the current signals into voltage signals corresponding to the current signals. The control device, electrically connected to both the photoelectric conversion device and the current conversion device, is configured to generate control signals and, based on the voltage signals corresponding to the current signals, generate chromaticity parameters of the light. These chromaticity parameters include luminance, color temperature, and color coordinates. This disclosure, through the coordinated use of the photoelectric conversion device, the current conversion device, and the control device, obtains chromaticity parameters of light based on incident light of N colors, resulting in a relatively rich set of light parameters. This allows the light detection structure to be applied in display products to meet the needs of artificial intelligence.

[0158] Figure 2 A schematic diagram of the structure of a photoelectric conversion device provided as an exemplary embodiment. Figure 3 A schematic diagram of the structure of a photoelectric conversion device is provided for another exemplary embodiment. Figure 4 A schematic diagram of a current conversion device provided for an exemplary embodiment. Figure 5 A schematic diagram of the structure of a current conversion device is provided for another exemplary embodiment. Figure 6 A schematic diagram of the structure of a control device provided for an exemplary embodiment. Figure 7 A schematic diagram of the structure of a control device is provided for another exemplary embodiment. Figure 8 This is an equivalent schematic diagram of a light detection device provided for an exemplary embodiment. Figure 2 and Figure 3 As shown, when N=4, the photoelectric conversion device 100 includes: four photoelectric conversion elements; the four photoelectric conversion elements include: a first photoelectric conversion element, a second photoelectric conversion element, a third photoelectric conversion element and a fourth photoelectric conversion element, and the current signal includes: a first current signal, a second current signal, a third current signal and a fourth current signal.

[0159] like Figure 2 and Figure 3 As shown, the first photoelectric conversion element is electrically connected to the sensor terminal and the first node N1, respectively, and is configured to convert the incident light of the first color into a first current signal and write the first current signal into the first node N1.

[0160] like Figure 2 and Figure 3 As shown, the second photoelectric conversion element is electrically connected to the sensing signal terminal sensor and the second node N2, respectively, and is configured to convert the incident second color light into a second current signal and write the second current signal into the second node N2.

[0161] like Figure 2 and Figure 3 As shown, the third photoelectric conversion element is electrically connected to the sensor terminal and the third node N3, respectively, and is configured to convert the incident third color light into a third current signal and write the third current signal into the third node N3.

[0162] like Figure 2 and Figure 3 As shown, the fourth photoelectric conversion element is electrically connected to the sensor terminal and the fourth node N4, respectively, and is configured to convert the incident fourth color light into a fourth current signal and write the fourth current signal into the fourth node N4.

[0163] In one exemplary embodiment, the first color, the second color, the third color, and the fourth color are one of red, green, blue, and white, and the first color, the second color, the third color, and the fourth color are different colors, and the voltage value of the signal at the sensor terminal is constant.

[0164] like Figure 8 As shown, the first photoelectric conversion element includes: a first photoelectric sensor D1; the second photoelectric conversion element includes: a second photoelectric sensor D2; the third photoelectric conversion element includes: a third photoelectric sensor D3; and the fourth photoelectric conversion element includes: a fourth photoelectric sensor D4.

[0165] In one exemplary embodiment, one electrode of the first photoelectric sensor D1 to the fourth photoelectric sensor D4 is connected to a common voltage terminal, and the other electrode is electrically connected to a current conversion circuit. Figure 8 The following explanation is based on the example of the cathodes of the first photoelectric sensor D1 to the fourth photoelectric sensor D4 being connected to a common voltage terminal, and the anodes being electrically connected to the current conversion circuit.

[0166] In one exemplary embodiment, the photoelectric sensor may be a photodiode.

[0167] In one exemplary embodiment, the anode of the first photoelectric sensor D1 is electrically connected to the first node N1, and the cathode of the first photoelectric sensor D1 is electrically connected to the sensing signal terminal Vsense. The anode of the second photoelectric sensor D2 is electrically connected to the second node N2, and the cathode of the second photoelectric sensor D2 is electrically connected to the sensing signal terminal Vsense. The anode of the third photoelectric sensor D3 is electrically connected to the third node N3, and the cathode of the third photoelectric sensor D3 is electrically connected to the sensing signal terminal Vsense. The anode of the fourth photoelectric sensor D4 is electrically connected to the fourth node N4, and the cathode of the fourth photoelectric sensor D4 is electrically connected to the sensing signal terminal Vsense.

[0168] In one exemplary embodiment, the sensing signal terminal sensor can determine the working state of the first photoelectric sensor D1 to the fourth photoelectric sensor D4 based on the photoelectric characteristics of the first photoelectric sensor D1 to the fourth photoelectric sensor D4 and the anode potential of the first photoelectric sensor D1 to the fourth photoelectric sensor D4, so as to ensure that the first photoelectric sensor D1 to the fourth photoelectric sensor D4 are in a reverse bias state. This disclosure does not limit this in any way.

[0169] In one exemplary embodiment, the anode of the first photoelectric sensor D1 is electrically connected to the sensing signal terminal Vsense, and the cathode of the first photoelectric sensor D1 is electrically connected to the first node N1. The anode of the second photoelectric sensor D2 is electrically connected to the sensing signal terminal Vsense, and the cathode of the second photoelectric sensor D2 is electrically connected to the second node N2. The anode of the third photoelectric sensor D3 is electrically connected to the sensing signal terminal Vsense, and the cathode of the third photoelectric sensor D3 is electrically connected to the third node N3. The anode of the fourth photoelectric sensor D4 is electrically connected to the sensing signal terminal Vsense, and the cathode of the fourth photoelectric sensor D4 is electrically connected to the fourth node N4.

[0170] In one exemplary embodiment, the sensing signal terminal sensor can determine the working state of the first photoelectric sensor D1 to the fourth photoelectric sensor D4 based on the photoelectric characteristics and the cathode potential of the first photoelectric sensor D1 to the fourth photoelectric sensor D4, so as to ensure that the first photoelectric sensor D1 to the fourth photoelectric sensor D4 are in a biased state. This disclosure does not limit this in any way.

[0171] In one exemplary embodiment, such as Figure 2 and Figure 3 As shown, the photoelectric conversion device 100 further includes: a component selection circuit and a gear selection circuit; the control signals include: a first component selection signal to a fourth component selection signal and a first gear selection signal to a fourth gear selection signal.

[0172] like Figure 2 and Figure 3 As shown, the component selection circuit is electrically connected to the first component selection signal terminal K1 to the fourth component selection signal terminal K4, the first node N1, the second node N2, the third node N3, the fourth node N4, and the fifth node N5, respectively. It is configured to, under the control of the signals from the first component selection signal terminal K1 to the fourth component selection signal terminal K4, provide the signals from the first node N1, the second node N2, the third node N3, or the fourth node N4 to the fifth node N5 in a time-division multiplexing manner. The i-th component selection signal terminal K... i The signal is the selection signal for the i-th element, where i is from 1 to 4.

[0173] like Figure 2 and Figure 3As shown, in the gear selection circuit, the first gear selection signal terminal G1 to the fourth gear selection signal terminal G4, the fifth node N5, the sixth node N6, the seventh node N7, the eighth node N8, and the ninth node N9 are electrically connected. It is configured to, under the control of the signals from the first gear selection signal terminal G1 to the fourth gear selection signal terminal G4, provide the signal of the fifth node N5 to the sixth node N6, the seventh node N7, the eighth node N8, and the ninth node N9 in a time-division manner. The i-th gear selection signal terminal G... i The signal is the selection signal for the i-th gear.

[0174] In one exemplary embodiment, such as Figure 2 and Figure 3 As shown, the first element selection signal terminal K1 to the fourth element selection signal terminal K4 and the first gear selection signal terminal G1 to the fourth gear selection signal terminal G4 are electrically connected to the control device 300.

[0175] In one exemplary embodiment, when the i-th element selection signal is an active level signal, all other element selection signals are inactive level signals. That is, when the i-th element selection signal is active, the second to fourth element selection signals are all inactive level signals. When the second element selection signal is active, the first, third, and fourth element selection signals are all inactive level signals. When the third element selection signal is active, the first, second, and fourth element selection signals are all inactive level signals. When the fourth element selection signal is active, the first to third element selection signals are all inactive level signals.

[0176] In one exemplary embodiment, the end time of the i-th element selection signal being an active level signal is earlier than or equal to the start time of the (i+1)-th element selection signal being an active level signal. That is, the end time of the first element selection signal being an active level signal is earlier than or equal to the start time of the second element selection signal being an active level signal, the end time of the second element selection signal being an active level signal is earlier than or equal to the start time of the third element selection signal being an active level signal, and the end time of the third element selection signal being an active level signal is earlier than or equal to the start time of the fourth element selection signal being an active level signal.

[0177] In one exemplary embodiment, when the i-th gear selection signal is an active level signal, all other gear selection signals are inactive level signals. That is, when the first gear selection signal is active, the second through fourth gear selection signals are inactive level signals. When the second gear selection signal is active, the first, third, and fourth gear selection signals are inactive level signals. When the third gear selection signal is active, the first, second, and fourth gear selection signals are inactive level signals. When the fourth gear selection signal is active, the first through third gear selection signals are inactive level signals.

[0178] In one exemplary embodiment, when the i-th element selection signal is an active level signal, the first gear selection signal to the fourth gear selection signal are active level signals in sequence, and the duration of the i-th element selection signal being an active level signal is greater than or equal to the sum of the durations of the first gear selection signal to the fourth gear selection signal being active level signals.

[0179] In one exemplary embodiment, the duration of the first gear selection signal to the fourth gear selection signal being an active level signal may be the same or different, and this disclosure does not limit this.

[0180] In one exemplary embodiment, when the end time of the i-th element selection signal being an active level signal is earlier than the start time of the (i+1)-th element selection signal being an active level signal, the interval between the end time of the i-th element selection signal being an active level signal and the start time of the (i+1)-th element selection signal being an active level signal is equal to the duration of any one of the first to fourth gear selection signals being an active level signal.

[0181] like Figure 3As shown, in one exemplary embodiment, the component selection circuit may include: a first component selection sub-circuit to a fourth component selection sub-circuit. The first component selection sub-circuit is electrically connected to a first component selection signal terminal K1, a first node N1, and a fifth node N5, respectively, and is configured to provide the signal of the first node N1 to the fifth node N5 under the control of the signal from the first component selection signal terminal K1; the second component selection sub-circuit is electrically connected to a second component selection signal terminal K2, a second node N2, and a fifth node N5, respectively, and is configured to provide the signal of the second node N2 to the fifth node N5 under the control of the signal from the second component selection signal terminal K2; the third component selection sub-circuit is electrically connected to a third component selection signal terminal K3, a third node N3, and a fifth node N5, respectively, and is configured to provide the signal of the third node N3 to the fifth node N5 under the control of the signal from the third component selection signal terminal K3; the fourth component selection sub-circuit is electrically connected to a fourth component selection signal terminal K4, a fourth node N4, and a fifth node N5, respectively, and is configured to provide the signal of the fourth node N4 to the fifth node N5 under the control of the signal from the fourth component selection signal terminal K4.

[0182] like Figure 8 As shown, the first element selection sub-circuit may include: a first element selection transistor T K1 The second element selection sub-circuit may include: a second element selection transistor T K2 The third element selection sub-circuit may include: a third element selection transistor T K3 The fourth element selection sub-circuit may include: a fourth element selection transistor T K4 .

[0183] like Figure 8 As shown, the first element is selected by transistor T. K1 The control electrode is electrically connected to the first element selection signal terminal K1, and the first element selection transistor T K1 The first electrode is electrically connected to the first node N1, and the first element is selected by transistor T. K1 The second electrode is electrically connected to the fifth node N5; the second element is selected by transistor T. K2 The control electrode is electrically connected to the second element selection signal terminal K2, and the second element selection transistor T... K2 The first terminal is electrically connected to the second node N2, and the second element is selected by transistor T. K2 The second electrode is electrically connected to the fifth node N5; the third element is selected from transistor T. K3 The control electrode is electrically connected to the third element selection signal terminal K3, and the third element selection transistor T... K3 The first terminal is electrically connected to the third node N3, and the third element is selected from transistor T. K3 The second electrode is electrically connected to the fifth node N5; the fourth element is selected by transistor T. K4The control electrode is electrically connected to the fourth element selection signal terminal K4, and the fourth element selection transistor T... K4 The first terminal is electrically connected to the fourth node N4, and the fourth element is selected by transistor T. K4 The second pole is electrically connected to the fifth node N5.

[0184] In one exemplary embodiment, transistors can be classified into N-type transistors and P-type transistors based on their characteristics. When a transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0185] In one exemplary embodiment, the first element is selected by transistor T. K1 Second element selection transistor T K2 The third component selects transistor T. K3 and the fourth element selection transistor T K4 It can be a P-type transistor or an N-type transistor. Using the same type of transistor in the component selection circuit can simplify the process flow, reduce process difficulty, and improve product yield.

[0186] In one exemplary embodiment, the first element is selected by transistor T. K1 Second element selection transistor T K2 The third component selects transistor T. K3 and the fourth element selection transistor T K4 It can include P-type transistors and N-type transistors.

[0187] In one exemplary embodiment, the first element is selected by transistor T. K1 Second element selection transistor T K2 The third component selects transistor T. K3 and the fourth element selection transistor T K4Low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) can be used, as can oxide (OPS) thin-film transistors, or a combination of both. The active layer of an LTPS TFT is made of low-temperature polycrystalline silicon, while the active layer of an OPS TFT is made of oxide semiconductor. LTPS TFTs offer advantages such as high mobility and fast charging, while OPS TFTs offer advantages such as low leakage current. By leveraging the advantages of both, low-frequency driving can be achieved, power consumption can be reduced, and display quality can be improved.

[0188] In one exemplary embodiment, the photoelectric conversion device of this disclosure may be provided with M level selection sub-circuits, and the multiple level selection sub-circuits can accurately detect the current signal, where M is a positive integer greater than or equal to 1. Figure 3 This explanation uses an M=4, or four-position selection sub-circuit, as an example.

[0189] like Figure 3 As shown, in one exemplary embodiment, the gear selection circuit may include: a first gear selection sub-circuit to a fourth gear selection sub-circuit. The circuit comprises the following components: a first gear selection sub-circuit, electrically connected to the first gear selection signal terminal G1, the fifth node N5, and the sixth node N6, and configured to provide the fifth node N5 signal to the sixth node N6 under the control of the signal from the first gear selection signal terminal G1; a second gear selection sub-circuit, electrically connected to the second gear selection signal terminal G2, the fifth node N5, and the seventh node N7, and configured to provide the fifth node N5 signal to the seventh node N7 under the control of the signal from the second gear selection signal terminal G2; a third gear selection sub-circuit, electrically connected to the third gear selection signal terminal G3, the fifth node N5, and the eighth node N8, and configured to provide the fifth node N5 signal to the eighth node N8 under the control of the signal from the third gear selection signal terminal G3; and a fourth gear selection sub-circuit, electrically connected to the fourth gear selection signal terminal G4, the fifth node N5, and the ninth node N9, and configured to provide the fifth node N5 signal to the ninth node N9 under the control of the signal from the fourth gear selection signal terminal G4.

[0190] like Figure 8 As shown, the first gear selection sub-circuit may include: a first gear selection transistor T G1 The second-position selection sub-circuit may include: a second-position selection transistor T G2 The third-position selection sub-circuit may include: a third-position selection transistor T G3 The fourth gear selection sub-circuit may include: a fourth gear selection transistor T G4 .

[0191] like Figure 8 As shown, the first gear selector transistor T G1 The control electrode is electrically connected to the first gear selection signal terminal G1, and the first gear selection transistor T G1 The first terminal is electrically connected to the fifth node N5, and the first gear selector transistor T G1 The second terminal is electrically connected to the sixth node N6; the second gear selector transistor T G2 The control electrode is electrically connected to the second gear selection signal terminal G2, and the second gear selection transistor T... G2 The first terminal is electrically connected to the fifth node N5, and the second position selects the transistor T. G2 The second terminal is electrically connected to the seventh node N7; the third position selects the transistor T. G3 The control electrode is electrically connected to the third gear selection signal terminal G3, and the third gear selection transistor T... G3 The first terminal is electrically connected to the fifth node N5, and the third position selects the transistor T. G3 The second terminal is electrically connected to the eighth node N8; the fourth position selects the transistor T. G4 The control electrode is electrically connected to the fourth gear selection signal terminal G4, and the fourth gear selection transistor T... G4 The first terminal is electrically connected to the fifth node N5, and the fourth position selects the transistor T. G4 The second pole is electrically connected to the ninth node N9.

[0192] In one exemplary embodiment, the first gear selection transistor T G1 Second gear selector transistor T G2 The third gear selector transistor T G3 and the fourth gear selector transistor T G4 It can be a P-type transistor or an N-type transistor. Using the same type of transistor in the component selection circuit can simplify the process flow, reduce process difficulty, and improve product yield.

[0193] In one exemplary embodiment, the first gear selection transistor T G1 Second gear selector transistor T G2 The third gear selector transistor T G3 and the fourth gear selector transistor T G4 It can include P-type transistors and N-type transistors.

[0194] In one exemplary embodiment, the first gear selection transistor T G1 Second gear selector transistor T G2 The third gear selector transistor T G3 and the fourth gear selector transistor T G4Low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) can be used, as can oxide (OPS) thin-film transistors, or a combination of both. The active layer of an LTPS TFT is made of low-temperature polycrystalline silicon, while the active layer of an OPS TFT is made of oxide semiconductor. LTPS TFTs offer advantages such as high mobility and fast charging, while OPS TFTs offer advantages such as low leakage current. By leveraging the advantages of both, low-frequency driving can be achieved, power consumption can be reduced, and display quality can be improved.

[0195] In one exemplary embodiment, the voltage signal may include: a first voltage signal to a fourth voltage signal.

[0196] In one exemplary embodiment, the voltage signal is an analog signal.

[0197] like Figure 4 and Figure 5 As shown, in one exemplary embodiment, the current conversion device 200 may include a sampling circuit and a filtering circuit.

[0198] like Figure 4 and Figure 5 As shown, the sampling circuit is electrically connected to the sixth node N6 to the thirteenth node N13 and the reference signal terminal REF, respectively. It is configured to sample the signals from the sixth node N6 to the ninth node N9, generate the first initial voltage signal to the fourth initial voltage signal corresponding to the current signal, and provide the first initial voltage signal to the fourth initial voltage signal corresponding to the current signal to the tenth node N10 to the thirteenth node N13, respectively.

[0199] In one exemplary embodiment, the sampling circuit can be a resistor sampling method. According to Ohm's law, the current signal forms a voltage drop across the resistor, thereby converting the current signal into an initial voltage signal corresponding to the current signal.

[0200] like Figure 4 and Figure 5 As shown, the filtering circuit is electrically connected to the tenth node N10 to the thirteenth node N13, the ground terminal GND, and the control device 300, respectively. It is configured to filter the first initial voltage signal to the fourth initial voltage signal corresponding to the current signal, generate the first voltage signal to the fourth voltage signal corresponding to the current signal, and provide the first voltage signal to the fourth voltage signal corresponding to the current signal to the control device 300, respectively.

[0201] In one exemplary embodiment, the filter circuit primarily eliminates high-frequency noise on the first to fourth initial voltage signals corresponding to the current signal.

[0202] In one exemplary embodiment, the signals from the sixth node N6 to the ninth node N9 are current signals.

[0203] like Figure 5 As shown, in one exemplary embodiment, the sampling circuit may include: a first sampling sub-circuit, a second sampling sub-circuit, a third sampling sub-circuit, and a fourth sampling sub-circuit. The first sampling sub-circuit is electrically connected to the sixth node N6, the tenth node N10, and the reference signal terminal REF, respectively. It is configured to sample the signal at the sixth node N6, generate a first initial voltage signal corresponding to the current signal, and provide the first initial voltage signal corresponding to the current signal to the tenth node N10. The second sampling sub-circuit is electrically connected to the seventh node N7, the eleventh node N11, and the reference signal terminal REF, respectively. It is configured to sample the signal at the seventh node N7, generate a second initial voltage signal corresponding to the current signal, and provide the second initial voltage signal corresponding to the current signal to the eleventh node N11. The third sampling sub-circuit is electrically connected to the eighth node N8, the twelfth node N12, and the reference signal terminal REF, respectively. It is configured to sample the signal of the eighth node N8, generate the third initial voltage signal corresponding to the current signal, and provide the third initial voltage signal corresponding to the current signal to the twelfth node N12. The fourth sampling sub-circuit is electrically connected to the ninth node N9, the thirteenth node N13, and the reference signal terminal REF, respectively. It is configured to sample the signal of the ninth node N9, generate the fourth initial voltage signal corresponding to the current signal, and provide the fourth initial voltage signal corresponding to the current signal to the thirteenth node N13.

[0204] like Figure 8 As shown, in one exemplary embodiment, the first sampling sub-circuit may include: a first operational amplifier OP1, a first sampling resistor SR1, and a first feedback capacitor FC1; the second sampling sub-circuit may include: a second operational amplifier OP2, a second sampling resistor SR2, and a second feedback capacitor FC2; the third sampling sub-circuit may include: a third operational amplifier OP3, a third sampling resistor SR3, and a third feedback capacitor FC3; and the fourth sampling sub-circuit may include: a fourth operational amplifier OP4, a fourth sampling resistor SR4, and a fourth feedback capacitor FC4.

[0205] like Figure 8As shown, the non-inverting input of the first operational amplifier OP1 is electrically connected to the reference signal terminal REF, the inverting input of the first operational amplifier OP1 is electrically connected to the sixth node N6, and the output of the first operational amplifier OP1 is electrically connected to the tenth node N10; the first terminal of the first sampling resistor SR1 is electrically connected to the sixth node N6, and the second terminal of the first sampling resistor SR1 is electrically connected to the tenth node N10; the first terminal of the first feedback capacitor FC1 is electrically connected to the sixth node N6, and the second terminal of the first feedback capacitor FC1 is electrically connected to the tenth node N10; the non-inverting input of the second operational amplifier OP2 is electrically connected to the reference signal terminal REF, the inverting input of the second operational amplifier OP2 is electrically connected to the seventh node N7, and the output of the second operational amplifier OP2 is electrically connected to the eleventh node N11; the first terminal of the second sampling resistor SR2 is electrically connected to the seventh node N7, and the second terminal of the second sampling resistor SR2 is electrically connected to the eleventh node N11; the first terminal of the second feedback capacitor FC2 is electrically connected to the seventh node N7, and the second terminal of the second feedback capacitor FC2 is electrically connected to the eleventh node N11; The non-inverting input of the third operational amplifier OP3 is electrically connected to the reference signal terminal REF, the inverting input of the third operational amplifier OP3 is electrically connected to the eighth node N8, and the output of the third operational amplifier OP3 is electrically connected to the twelfth node N12; the first terminal of the third sampling resistor SR3 is electrically connected to the eighth node N8, and the second terminal of the third sampling resistor SR3 is electrically connected to the twelfth node N12; the first terminal of the third feedback capacitor FC3 is electrically connected to the eighth node N8, and the second terminal of the third feedback capacitor FC3 is electrically connected to the twelfth node N12; the non-inverting input of the fourth operational amplifier OP4 is electrically connected to the reference signal terminal REF, the inverting input of the fourth operational amplifier OP4 is electrically connected to the ninth node N9, and the output of the fourth operational amplifier OP4 is electrically connected to the thirteenth node N13; the first terminal of the fourth sampling resistor SR4 is electrically connected to the ninth node N9, and the second terminal of the fourth sampling resistor SR4 is electrically connected to the thirteenth node N13; the first terminal of the fourth feedback capacitor FC4 is electrically connected to the ninth node N9, and the second terminal of the fourth feedback capacitor FC4 is electrically connected to the thirteenth node N13.

[0206] In one exemplary embodiment, the resistance of the first sampling resistor is R1, the resistance of the second sampling resistor is R2, the resistance of the third sampling resistor is R3, and the resistance of the fourth sampling resistor is R4. When the amplification factor of the fourth sampling sub-circuit is 1, the amplification factor of the first sampling sub-circuit is R1 / R4; the amplification factor of the second sampling sub-circuit is R2 / R4; and the amplification factor of the third sampling sub-circuit is R3 / R4.

[0207] To facilitate the calculation of the amplification factor from the current signal to the voltage signal in the sampling circuit, the resistors R1, R2, R3, and R4 of the first sampling resistor in this disclosure satisfy: R1 = K × R2 = K 2 ×R3=K 3 ×R4, where K is a positive integer greater than 1. At this point, the amplification factor of the first sampling sub-circuit is K. 3 The amplification factor of the second sampling sub-circuit is K. 2 The amplification factor of the third sampling sub-circuit is K.

[0208] In one exemplary embodiment, K can be equal to 10.

[0209] In one exemplary embodiment, when the cathodes of the first to fourth photoelectric sensors are connected to the sensing signal terminal, and the anodes of the cathodes of the first to fourth photoelectric sensors are connected to the component selection circuit, a current signal flows from the photodiode to the component selection circuit. The voltage value Vi of the i-th voltage signal corresponding to the current signal satisfies the following condition: Vi = Vref - I * Ri. Where Vref is the voltage value of the signal at the reference signal terminal REF, I is the current value of the current signal, and Ri is the resistance of the i-th sampling resistor. During sampling, the voltage value of the anode of the photoelectric sensor can be Vref. In this case, the reverse bias voltage of the photoelectric sensor is Vsense - Vref, where Vsense > Vref, and Vsense is the voltage value at the sensing signal terminal.

[0210] When the anodes of the first to fourth photoelectric sensors are connected to the sensing signal terminal Vsense, and the cathodes of the first to fourth photoelectric sensors are connected to the component selection circuit, the current signal flows from the component selection circuit to the photodiode. The voltage value Vi of the i-th voltage signal corresponding to the current signal satisfies the following condition: Vi = Vref + I*Ri. During sampling, the voltage value of the cathode of the photoelectric sensor can be Vref. At this time, the reverse bias voltage of the photoelectric sensor is Vref - Vsense, where Vsense... <Vref。

[0211] In one exemplary embodiment, the leakage current of the first operational amplifier OP1 to the fourth operational amplifier OP4 is less than or equal to one-tenth of the current signal. Since the current signal converted by the photoelectric sensor is particularly small, the smaller the leakage current of the first operational amplifier OP1 to the fourth operational amplifier OP4, the smaller its impact on the current signal and the higher the sampling accuracy.

[0212] like Figure 5As shown, in one exemplary embodiment, the filtering circuit may include: a first filtering sub-circuit, a second filtering sub-circuit, a third filtering sub-circuit, and a fourth filtering sub-circuit. The first filtering sub-circuit is electrically connected to the tenth node N10, the ground terminal GND, and the control device 300, respectively. It is configured to filter the signal from the tenth node N10, removing high-frequency signals from the first initial voltage signal to generate a first voltage signal corresponding to the current signal, and providing the first voltage signal corresponding to the current signal to the control device 300. The second filtering sub-circuit is electrically connected to the eleventh node N11, the ground terminal GND, and the control device 300, respectively. It is configured to filter the signal from the eleventh node N11, removing high-frequency signals from the second initial voltage signal to generate a second voltage signal, and providing the second voltage signal corresponding to the current signal to the control device 300. The third filter sub-circuit is electrically connected to the twelfth node N12, the ground terminal GND, and the control device 300, respectively. It is configured to filter the signal of the twelfth node N12, and after filtering out the high-frequency signal in the third initial voltage signal, generate the third voltage signal and provide the third voltage signal corresponding to the current signal to the control device 300; the fourth filter sub-circuit is electrically connected to the thirteenth node N13, the ground terminal GND, and the control device 300, respectively. It is configured to filter the signal of the thirteenth node N13, and after filtering out the high-frequency signal in the fourth initial voltage signal, generate the fourth voltage signal and provide the fourth voltage signal corresponding to the current signal to the control device 300.

[0213] like Figure 8 As shown, in an exemplary embodiment, the first filter sub-circuit includes: a first filter resistor LR1 and a first filter capacitor LC1; the second filter sub-circuit includes: a second filter resistor LR2 and a second filter capacitor LC2; the third filter sub-circuit includes: a third filter resistor LR3 and a third filter capacitor LC3; and the fourth filter sub-circuit includes: a fourth filter resistor LR4 and a fourth filter capacitor LC4.

[0214] like Figure 8As shown, the first terminal of the first filter resistor LR1 is electrically connected to the tenth node N10, and the second terminal of the first filter resistor LR1 is electrically connected to the control device 300 and the first terminal of the first filter capacitor LC1, respectively. The second terminal of the first filter capacitor LC1 is electrically connected to the ground terminal GND. The first terminal of the second filter resistor LR2 is electrically connected to the eleventh node N11, and the second terminal of the second filter resistor LR2 is electrically connected to the control device 300 and the first terminal of the second filter capacitor LC2, respectively. The second terminal of the second filter capacitor LC2 is electrically connected to the ground terminal GND. The first terminal of the third filter resistor LR3 is electrically connected to the twelfth node N12, and the second terminal of the third filter resistor LR3 is electrically connected to the control device 300 and the first terminal of the third filter capacitor LC3, respectively. The second terminal of the third filter capacitor LC3 is electrically connected to the ground terminal GND. The first terminal of the fourth filter resistor LR4 is electrically connected to the thirteenth node N13, and the second terminal of the fourth filter resistor LR4 is electrically connected to the control device 300 and the first terminal of the fourth filter capacitor LC4, respectively. The second terminal of the fourth filter capacitor LC4 is electrically connected to the ground terminal GND.

[0215] like Figures 6 to 8 As shown, in one exemplary embodiment, the control device 300 may include: an analog-to-digital converter 310, a controller 320, and a level converter 330. The analog-to-digital converter 310 is electrically connected to a filter circuit and is configured to convert a first voltage signal to a fourth voltage signal corresponding to a current signal into a first digital voltage signal to a fourth digital voltage signal corresponding to the current signal. The controller 320 is electrically connected to the analog-to-digital converter 310 and is configured to generate a first initial element selection signal to a fourth initial element selection signal and a first initial gear selection signal to a fourth initial gear selection signal, and generate chromaticity parameters of light based on the first digital voltage signal to the fourth digital voltage signal corresponding to the current signal. The level converter 330 is connected to the controller 320, the first element selection signal terminal K1 to the fourth element selection signal terminal K4, and the first gear selection signal. The signal terminal G1 to the fourth gear selection signal terminal G4 are electrically connected. The system is configured to perform level conversion on the first initial element selection signal KM1 to the fourth initial element selection signal KM4 to generate the first element selection signal to the fourth element selection signal, and provide the first element selection signal to the fourth element selection signal to the first element selection signal terminal K1 to the fourth element selection signal terminal K4 respectively. The system is also configured to perform level conversion on the first initial gear selection signal GM1 to the fourth initial gear selection signal GM4 to generate the first gear selection signal to the fourth gear selection signal, and provide the first gear selection signal to the fourth gear selection signal to the first gear selection signal terminal G1 to the fourth gear selection signal terminal G4 respectively.

[0216] like Figure 7 and Figure 8As shown, in one exemplary embodiment, the analog-to-digital conversion element 310 includes: a signal selector 311, a signal buffer 312, and an analog-to-digital converter 313. The signal selector 311 is electrically connected to both the filter circuit and the signal buffer 312 in the current conversion device, and is configured to transmit a first voltage signal to a fourth voltage signal corresponding to the current signal to the signal buffer 312 in a time-division multiplexing manner. The signal buffer 312 is configured to store the first voltage signal to the fourth voltage signal corresponding to the current signal input by the signal selector in a time-division multiplexing manner. The analog-to-digital converter 313 is electrically connected to the signal buffer 312 and is configured to convert the first voltage signal to the fourth voltage signal corresponding to the current signal in the signal buffer into a first digital voltage signal to a fourth digital voltage signal corresponding to the current signal in a time-division multiplexing manner.

[0217] In one exemplary embodiment, in order to ensure the accuracy of light detection, the analog-to-digital converter 313 must complete the analog-to-digital conversion before the next voltage signal is written to the signal buffer 312, and write the converted digital signal into the register of the analog-to-digital converter.

[0218] In one exemplary embodiment, the analog-to-digital converter may include a linear transfer function from a voltage signal to a digital voltage signal, such that there is a one-to-one correspondence between the voltage signal and the digital voltage signal converted from the voltage signal.

[0219] In one exemplary embodiment, the transfer function of the analog-to-digital conversion element is linear, and the linear function can be: VDi = Vi / VrefADC*2 n +offset, where VDi is the voltage value of the i-th digital voltage signal, Vi is the voltage value of the i-th voltage signal, n is the number of bits in the analog-to-digital converter, and VrefADC is the maximum input voltage value of the analog-to-digital converter.

[0220] In one exemplary embodiment, the number of bits n in the analog-to-digital converter can be 16 bits. When the input voltage signal is a VrefADC, the output digital voltage signal is 2. 16 =65536LSB.

[0221] In one exemplary embodiment, the resistance R4 of the fourth sampling resistor can be determined based on the current signal converted from the light with maximum brightness by the photoelectric conversion element and the input voltage range of the analog-to-digital converter, without any limitation herein. The input voltage range of the analog-to-digital converter may include a maximum input voltage value and a minimum input voltage value.

[0222] In one exemplary embodiment, the maximum input voltage value can be 2V and the minimum input voltage value can be 0V.

[0223] Generally, analog-to-digital converters have good linear transfer functions in the voltage range of 0.2V to VrefADC-0.2.

[0224] In one exemplary embodiment, the voltage value of the signal at the reference signal terminal REF is constant, and the voltage value of the signal at the reference signal terminal REF is less than the maximum input voltage value of the analog-to-digital converter 313 and greater than the minimum input voltage value of the analog-to-digital converter. The difference between the maximum input voltage value of the analog-to-digital converter 313 and the voltage value of the signal at the reference signal terminal is a threshold difference.

[0225] In one exemplary embodiment, the threshold difference can be approximately 0.1 volts to 0.3 volts, and exemplarily, the threshold difference can be 0.2 volts.

[0226] In one exemplary embodiment, such as Figure 7 and Figure 8 As shown, the controller 320 includes eight interfaces P1 to P8, which are configured as standard general purpose input / output ports. Among them, the eight first interfaces are electrically connected to the level converter 330 and are configured to transmit a first initial element selection signal to a fourth initial element selection signal and a first initial gear selection signal to a fourth initial gear selection signal, respectively, to the level converter 330.

[0227] In one exemplary embodiment, the controller 320 may further include: a first digital register to a fourth digital register.

[0228] In one exemplary embodiment, the controller 320 may be configured to pre-store a first threshold voltage value and a second threshold voltage value, sequentially determine whether the voltage values ​​of the first to fourth digital voltage signals corresponding to the i-th current signal meet the corresponding threshold conditions, convert the digital voltage signal corresponding to the i-th current signal that meets the corresponding threshold conditions into a full-range digital voltage signal, and store the converted full-range digital voltage signal in the i-th digital register, and is further configured to generate chromaticity parameters of light based on the full-range digital voltage signals in the first to fourth digital registers.

[0229] In one exemplary embodiment, the controller may also be configured to discard digital voltage signals corresponding to the i-th current signal that do not meet the corresponding threshold conditions.

[0230] In one exemplary embodiment, based on the maximum and minimum leakage current generated by the ambient light sensor under illumination and the sampling resistance, it is determined that only one level of the sampling voltage collects digital signals within the valid data range. Data from other levels are either greater than the maximum digital threshold or less than the minimum digital threshold. Data outside the threshold range indicates that the level selection is inappropriate, and the collected data is discarded.

[0231] In one exemplary embodiment, the threshold condition for the first digital voltage signal corresponding to the i-th current signal is greater than the second threshold voltage value, the threshold conditions for the second and third digital voltage signals corresponding to the i-th current signal are greater than the first threshold voltage value and less than the second threshold voltage value, and the threshold condition for the fourth digital voltage signal corresponding to the i-th current signal is less than the first threshold voltage value.

[0232] In one exemplary embodiment, the first threshold voltage value may be greater than the minimum input voltage value of the analog-to-digital converter (ADC), and the second threshold voltage value may be less than the maximum input voltage value of the ADC. The difference between the first threshold voltage value and the minimum input voltage value of the ADC is equal to the difference between the maximum output voltage value of the ADC and the second threshold voltage value.

[0233] In one exemplary embodiment, the difference between the first threshold voltage value and the minimum input voltage value of the analog-to-digital converter can be 0.1V to 0.3V, and exemplarily, it can be 0.2V.

[0234] In one exemplary embodiment, the first threshold voltage value can be the minimum input voltage value of the analog-to-digital converter plus 0.2V, i.e., 0V+0.2V, and the second threshold voltage value can be the maximum input voltage value of the analog-to-digital converter minus 0.2V.

[0235] In one exemplary embodiment, the sampling circuit satisfies R1=K×R2=K 2 ×R3=K 3 When ×R4, controller 320 can be set according to formula V. Dcount =V Dj / Gain j The j-th digital voltage signal is converted into a full-range digital voltage signal Dcount, where the j-th digital voltage signal is the digital voltage signal corresponding to the i-th current signal that meets the threshold condition, and Gain j Gain is the magnification factor. j =K j V Dcount The voltage value of the full-range digital voltage signal, V Dj Let be the voltage value of the j-th digital voltage signal, where j = 1, 2, 3, or 4.

[0236] In one exemplary embodiment, the control device 300 may further include a transmission interface 340 connected to the controller 320, the transmission interface 340 being configured as a serial interface and set to transmit the chromaticity parameter LS of the light generated by the controller 320.

[0237] In one exemplary embodiment, the transmission interface 340 may include: I 2C interface or SPI interface.

[0238] In one exemplary embodiment, I 2 The C interface includes: bidirectional data line SDA and clock line SCL.

[0239] Figure 9 This is a timing diagram of a control signal. The following is a demonstration of its operation. Figure 8 The working process of the example light detection structure illustrates the light detection structure provided by the exemplary embodiments of this disclosure. Figure 9 This explanation uses an example where all transistors in the light detection structure are N-type transistors. For example... Figure 9 As shown, the working process of the light detection structure can include: a first sampling stage S1 to a fourth sampling stage S4. The number of first sampling stages S1 to fourth sampling stages S4 can be N. The m-th first sampling stage S1 to the m-th fourth sampling stage S4 occur sequentially, and the m-th first sampling stage occurs after the (m-1)-th fourth sampling stage. Figure 9 As shown, the first color sampling stage S1 includes: the first level selection stage S11 to the fourth level selection stage S14; the second color sampling stage S2 includes: the first level selection stage S21 to the fourth level selection stage S24; the third color sampling stage S3 includes: the first level selection sampling stage S31 to the fourth level selection stage S34; and the fourth color sampling stage S4 includes: the first level selection stage S41 to the fourth level selection stage S44.

[0240] In the first color sampling stage S1, during the first level selection stage S11, the first photoelectric sensor D1 converts the light of the first color into a first current signal and writes it into the first node N1; the signal at the first element selection signal terminal K1 is a high-level signal, and the first element selection transistor T... K1 When the circuit is turned on, the signal from the first node N1 is written to the fifth node N5, the signal at the first gear selection terminal G1 is a high-level signal, and the first gear selection transistor T... G1When the circuit is turned on, the signal from the fifth node N5 is written to the sixth node N6. The first sampling sub-circuit samples the first current signal and generates the first initial voltage signal corresponding to the first current signal. The first filtering sub-circuit filters the first initial voltage signal corresponding to the first current signal and generates the first voltage signal corresponding to the first current signal. The signal selector transmits the first voltage signal corresponding to the first current signal to the signal buffer. The signal buffer stores the first voltage signal corresponding to the first current signal. The analog-to-digital converter converts the first voltage signal corresponding to the first current signal into a first digital voltage signal corresponding to the first current signal. The controller determines whether the first digital voltage signal corresponding to the first current signal meets the threshold condition, that is, the voltage value of the first digital voltage signal is greater than the second threshold voltage value. If the first digital voltage signal corresponding to the first current signal meets the threshold condition, it is converted into a full-range digital voltage signal and stored in the first digital register. If the voltage value of the first digital voltage signal corresponding to the first current signal does not meet the threshold condition, that is, the voltage value of the first digital voltage signal is less than the second threshold voltage value, it is discarded.

[0241] In the second level selection stage S12 of the first color sampling stage S1, the first photoelectric sensor D1 converts the light of the first color into a first current signal and writes it into the first node N1; the signal at the first element selection signal terminal K1 is a high-level signal, and the first element selection transistor T... K1 When the circuit is turned on, the signal from the first node N1 is written to the fifth node N5, the signal at the second selector G2 is high, and the second selector transistor T... G2When the circuit is turned on, the signal from the fifth node N5 is written to the seventh node N7. The second sampling sub-circuit samples the first current signal and generates a second initial voltage signal corresponding to the first current signal. The second filtering sub-circuit filters the second initial voltage signal corresponding to the first current signal and generates a second voltage signal corresponding to the first current signal. The signal selector transmits the second voltage signal corresponding to the first current signal to the signal buffer. The signal buffer stores the second voltage signal corresponding to the first current signal. The analog-to-digital converter converts the second voltage signal corresponding to the first current signal into a second digital voltage signal corresponding to the first current signal. The controller determines the second digital voltage signal corresponding to the first current signal. If the voltage signal meets the threshold condition, i.e., the voltage value of the second digital voltage signal corresponding to the first current signal is greater than the first threshold voltage value and less than the second threshold voltage value, the second digital voltage signal corresponding to the first current signal is converted into a full-range digital voltage signal and stored in the first digital register. If the voltage value of the second digital voltage signal corresponding to the first current signal does not meet the threshold condition, i.e., the voltage value of the second digital voltage signal is less than the first threshold voltage value or greater than the second threshold voltage value, the second digital voltage signal corresponding to the first current signal is discarded.

[0242] In the third level selection stage S13 of the first color sampling stage S1, the first photoelectric sensor D1 converts the light of the first color into a first current signal and writes it into the first node N1; the signal at the first element selection signal terminal K1 is a high-level signal, and the first element selection transistor T... K1 When the circuit is turned on, the signal from the first node N1 is written to the fifth node N5, the signal at the third gear selection terminal G3 is a high-level signal, and the third gear selection transistor T... G3When the circuit is turned on, the signal from the fifth node N5 is written to the eighth node N8. The third sampling sub-circuit samples the first current signal and generates a third initial voltage signal corresponding to the first current signal. The third filtering sub-circuit filters the third initial voltage signal corresponding to the first current signal and generates a third voltage signal corresponding to the first current signal. The signal selector provides the third voltage signal corresponding to the first current signal to the signal buffer. The signal buffer stores the third voltage signal corresponding to the first current signal. The analog-to-digital converter converts the third voltage signal corresponding to the first current signal into a third digital voltage signal corresponding to the first current signal. The controller determines the third digital voltage signal corresponding to the first current signal. If the voltage signal meets the threshold condition, i.e., the voltage value of the third digital voltage signal corresponding to the first current signal is greater than the first threshold voltage value and less than the second threshold voltage value, the third digital voltage signal corresponding to the first current signal is converted into a full-range digital voltage signal and stored in the first digital register. If the voltage value of the third digital voltage signal corresponding to the first current signal does not meet the threshold condition, i.e., the voltage value of the third digital voltage signal is less than the first threshold voltage value or greater than the second threshold voltage value, the third digital voltage signal corresponding to the first current signal is discarded.

[0243] In the fourth level selection stage S14 of the first color sampling stage S1, the first photoelectric sensor D1 converts the light of the first color into a first current signal and writes it into the first node N1; the signal at the first element selection signal terminal K1 is a high-level signal, and the first element selection transistor T... K1 When the circuit is turned on, the signal from the first node N1 is written to the fifth node N5, the signal at the fourth gear selection terminal G4 is a high-level signal, and the fourth gear selection transistor T... G4When the circuit is turned on, the signal from the fifth node N5 is written to the ninth node N9. The fourth sampling sub-circuit samples the first current signal and generates the fourth initial voltage signal corresponding to the first current signal. The fourth filtering sub-circuit filters the fourth initial voltage signal corresponding to the first current signal and generates the fourth voltage signal corresponding to the first current signal. The signal selector provides the fourth voltage signal corresponding to the first current signal to the signal buffer. The signal buffer stores the fourth voltage signal corresponding to the first current signal. The analog-to-digital converter converts the fourth voltage signal corresponding to the first current signal into a fourth digital voltage signal corresponding to the first current signal. The controller determines whether the fourth digital voltage signal corresponding to the first current signal meets the threshold condition. If the fourth digital voltage signal meets the threshold condition (i.e., the voltage value of the fourth digital voltage signal is less than the first threshold voltage value), the fourth digital voltage signal corresponding to the first current signal is converted into a full-range digital voltage signal and stored in the first digital register. If the voltage value of the fourth digital voltage signal does not meet the threshold condition (i.e., the voltage value of the fourth digital voltage signal is greater than the first threshold voltage value), the fourth digital voltage signal corresponding to the first current signal is discarded.

[0244] Between the first color sampling stage and the second color sampling stage is a blank stage. During the blank stage, all control signals are low-level signals, all transistors are turned off, and no sampling occurs.

[0245] When the controller determines that the first current signal is not the fourth current signal, it determines whether the voltage values ​​of the first digital voltage signal to the fourth digital voltage signal corresponding to the second current signal meet the threshold condition, that is, it executes the second color sampling stage.

[0246] In the first level selection stage S21 of the second color sampling stage S2, the second photoelectric sensor D2 converts the light of the second color into a second current signal and writes it into the second node N2; the signal at the second element selection signal terminal K2 is a high-level signal, and the second element selection transistor T... K2 When the circuit is turned on, the signal from the second node N2 is written to the fifth node N5, the signal at the first gear selection terminal G1 is a high-level signal, and the first gear selection transistor T... G1When the circuit is turned on, the signal from the fifth node N5 is written to the sixth node N6. The first sampling sub-circuit samples the second current signal and generates the first initial voltage signal corresponding to the second current signal. The first filtering sub-circuit filters the first initial voltage signal corresponding to the second current signal and generates the first voltage signal corresponding to the second current signal. The signal selector transmits the first voltage signal corresponding to the second current signal to the signal buffer. The signal buffer stores the first voltage signal corresponding to the second current signal. The analog-to-digital converter converts the first voltage signal corresponding to the second current signal into a first digital voltage signal corresponding to the second current signal. The controller determines whether the first digital voltage signal corresponding to the second current signal meets the threshold condition. If the first digital voltage signal meets the threshold condition, that is, the voltage value of the first digital voltage signal is greater than the second threshold voltage value, the first digital voltage signal corresponding to the second current signal is converted into a full-range digital voltage signal and stored in the second digital register. If the voltage value of the first digital voltage signal does not meet the threshold condition, that is, the voltage value of the first digital voltage signal is less than the second threshold voltage value, the first digital voltage signal corresponding to the second current signal is discarded.

[0247] In the second color sampling stage S2, during the second level selection stage S22, the second photoelectric sensor D2 converts the second color light into a second current signal and writes it to the second node N2; the signal at the second element selection signal terminal K2 is a high-level signal, and the second element selection transistor T... K2 With the circuit turned on, the signal from the second node N2 is written to the fifth node N5, the signal at the second selector G2 is high, and the second selector transistor T... G2When the circuit is turned on, the signal from node N5 is written to node N7. The second sampling sub-circuit samples the second current signal and generates a second initial voltage signal corresponding to the second current signal. The second filtering sub-circuit filters the second initial voltage signal corresponding to the second current signal and generates a second voltage signal corresponding to the second current signal. The signal selector transmits the second voltage signal corresponding to the second current signal to the signal buffer. The signal buffer stores the second voltage signal corresponding to the second current signal. The analog-to-digital converter converts the second voltage signal corresponding to the second current signal into a second digital voltage signal corresponding to the second current signal. The controller determines the second digital voltage signal corresponding to the second current signal. If the voltage signal meets the threshold condition, i.e., the voltage value of the second digital voltage signal is greater than the first threshold voltage value and less than the second threshold voltage value, the second digital voltage signal corresponding to the second current signal is converted into a full-range digital voltage signal and stored in the second digital register. If the voltage value of the second digital voltage signal corresponding to the second current signal does not meet the threshold condition, i.e., the voltage value of the second digital voltage signal is less than the first threshold voltage value or greater than the second threshold voltage value, the second digital voltage signal corresponding to the second current signal is discarded.

[0248] In the third level selection stage S23 of the second color sampling stage S2, the second photoelectric sensor D2 converts the second color light into a second current signal and writes it to the second node N2; the signal at the second element selection signal terminal K2 is a high-level signal, and the second element selection transistor T... K2 With the circuit turned on, the signal from the second node N2 is written to the fifth node N5, and the signal at the third gear selection terminal G3 is a high-level signal. The third gear selection transistor T... G3When the circuit is turned on, the signal from the fifth node N5 is written to the eighth node N8. The third sampling sub-circuit samples the second current signal and generates the third initial voltage signal corresponding to the second current signal. The third filtering sub-circuit filters the third initial voltage signal corresponding to the second current signal and generates the third voltage signal corresponding to the second current signal. The signal selector provides the third voltage signal corresponding to the second current signal to the signal buffer, which stores the third voltage signal. The analog-to-digital converter converts the third voltage signal corresponding to the second current signal into a third digital voltage signal corresponding to the second current signal. The controller determines the third digital voltage signal corresponding to the second current signal. If the voltage signal meets the threshold condition, i.e., the voltage value of the third digital voltage signal corresponding to the second current signal is greater than the first threshold voltage value and less than the second threshold voltage value, the third digital voltage signal corresponding to the second current signal is converted into a full-range digital voltage signal and stored in the second digital register. If the voltage value of the third digital voltage signal corresponding to the second current signal does not meet the threshold condition, i.e., the voltage value of the third digital voltage signal is less than the first threshold voltage value or greater than the second threshold voltage value, the third digital voltage signal corresponding to the second current signal is discarded.

[0249] In the fourth level selection stage S24 of the second color sampling stage S2, the second photoelectric sensor D2 converts the second color light into a second current signal and writes it to the second node N2; the signal at the second element selection signal terminal K2 is a high-level signal, and the second element selection transistor T... K2 With the circuit turned on, the signal from the second node N2 is written to the fifth node N5, the signal at the fourth gear selection terminal G4 is a high-level signal, and the fourth gear selection transistor T... G4When the circuit is turned on, the signal from the fifth node N5 is written to the ninth node N9. The fourth sampling sub-circuit samples the second current signal and generates the fourth initial voltage signal corresponding to the second current signal. The fourth filtering sub-circuit filters the fourth initial voltage signal corresponding to the second current signal and generates the fourth voltage signal corresponding to the second current signal. The signal selector provides the fourth voltage signal corresponding to the second current signal to the signal buffer, which stores the fourth voltage signal. The analog-to-digital converter converts the fourth voltage signal corresponding to the second current signal into a fourth digital voltage signal corresponding to the second current signal. The controller determines whether the fourth digital voltage signal corresponding to the second current signal meets the threshold condition. If the fourth digital voltage signal meets the threshold condition (i.e., the voltage value of the fourth digital voltage signal is less than the first threshold voltage value), the fourth digital voltage signal corresponding to the second current signal is converted into a full-range digital voltage signal and stored in the second digital register. If the voltage value of the fourth digital voltage signal does not meet the threshold condition (i.e., the voltage value of the fourth digital voltage signal is greater than the first threshold voltage value), the fourth digital voltage signal corresponding to the second current signal is discarded.

[0250] Between the second and third color sampling stages is a blank stage. During the blank stage, all control signals are low-level signals, all transistors are turned off, and no sampling occurs.

[0251] When the controller determines that the second current signal is not the fourth current signal, it determines whether the voltage values ​​of the first to fourth digital voltage signals corresponding to the third current signal meet the threshold condition, that is, it executes the third color sampling stage.

[0252] In the first level selection stage S31 of the third color sampling stage S3, the third photoelectric sensor D3 converts the light of the third color into a third current signal and writes it to the third node N3; the signal at the third element selection signal terminal K3 is a high-level signal, and the third element selection transistor T... K3 When the circuit is turned on, the signal from the third node N3 is written to the fifth node N5, the signal at the first gear selection terminal G1 is a high-level signal, and the first gear selection transistor T... G1When the circuit is turned on, the signal from the fifth node N5 is written to the sixth node N6. The first sampling sub-circuit samples the third current signal and generates the first initial voltage signal corresponding to the third current signal. The first filtering sub-circuit filters the first initial voltage signal corresponding to the third current signal and generates the first voltage signal corresponding to the third current signal. The signal selector transmits the first voltage signal corresponding to the third current signal to the signal buffer. The signal buffer stores the first voltage signal corresponding to the third current signal. The analog-to-digital converter converts the first voltage signal corresponding to the third current signal into a first digital voltage signal corresponding to the third current signal. The controller determines whether the first digital voltage signal corresponding to the third current signal meets the threshold condition. If the first digital voltage signal meets the threshold condition (i.e., the voltage value of the first digital voltage signal is greater than the second threshold voltage value), the first digital voltage signal corresponding to the third current signal is converted into a full-range digital voltage signal and stored in the third digital register. If the voltage value of the first digital voltage signal does not meet the threshold condition (i.e., the voltage value of the first digital voltage signal is less than the second threshold voltage value), the first digital voltage signal corresponding to the third current signal is discarded.

[0253] In the second stage S32 of the third color sampling phase S3, the third photoelectric sensor D3 converts the light of the third color into a third current signal and writes it to the third node N3; the signal at the third element selection signal terminal K3 is a high-level signal, and the third element selection transistor T... K3 With the circuit turned on, the signal from the third node N3 is written to the fifth node N5, the signal at the second selector G2 is high, and the second selector transistor T... G2When the circuit is turned on, the signal from node N5 is written to node N7. The second sampling sub-circuit samples the third current signal and generates a second initial voltage signal corresponding to the third current signal. The second filtering sub-circuit filters the second initial voltage signal corresponding to the third current signal and generates a second voltage signal corresponding to the third current signal. The signal selector transmits the second voltage signal corresponding to the third current signal to the signal buffer. The signal buffer stores the second voltage signal corresponding to the third current signal. The analog-to-digital converter converts the second voltage signal corresponding to the third current signal into a second digital voltage signal corresponding to the third current signal. The controller determines the second digital voltage signal corresponding to the third current signal. If the voltage signal meets the threshold condition, i.e., the voltage value of the second digital voltage signal corresponding to the third current signal is greater than the first threshold voltage value and less than the second threshold voltage value, the second digital voltage signal corresponding to the third current signal is converted into a full-range digital voltage signal and stored in the third digital register. If the voltage value of the second digital voltage signal corresponding to the third current signal does not meet the threshold condition, i.e., the voltage value of the second digital voltage signal is less than the first threshold voltage value or greater than the second threshold voltage value, the second digital voltage signal corresponding to the third current signal is discarded.

[0254] In the third color sampling stage S3, the third gear selection stage S33, the third photoelectric sensor D3 converts the light of the third color into a third current signal and writes it to the third node N3; the signal at the third element selection signal terminal K3 is a high-level signal, and the third element selection transistor T... K3 When the circuit is turned on, the signal from the third node N3 is written to the fifth node N5, the signal at the third gear selection terminal G3 is a high-level signal, and the third gear selection transistor T... G3When the circuit is turned on, the signal from the fifth node N5 is written to the eighth node N8. The third sampling sub-circuit samples the third current signal and generates the third initial voltage signal corresponding to the third current signal. The third filtering sub-circuit filters the third initial voltage signal corresponding to the third current signal and generates the third voltage signal corresponding to the third current signal. The signal selector provides the third voltage signal corresponding to the third current signal to the signal buffer. The signal buffer stores the third voltage signal corresponding to the third current signal. The analog-to-digital converter converts the third voltage signal corresponding to the third current signal into the third digital voltage signal corresponding to the third current signal. The controller determines the third digital voltage signal corresponding to the third current signal. If the voltage signal meets the threshold condition, that is, the voltage value of the third digital voltage signal corresponding to the third current signal is greater than the first threshold voltage value and less than the second threshold voltage value, the third digital voltage signal corresponding to the third current signal is converted into a full-range digital voltage signal and stored in the third digital register. If the voltage value of the third digital voltage signal corresponding to the third current signal does not meet the threshold condition, that is, the voltage value of the third digital voltage signal is less than the first threshold voltage value or greater than the second threshold voltage value, the third digital voltage signal corresponding to the third current signal is discarded.

[0255] In the fourth stage S34 of the third color sampling stage S3, the third photoelectric sensor D3 converts the light of the third color into a third current signal and writes it to the third node N3; the signal at the third element selection signal terminal K3 is a high-level signal, and the third element selection transistor T... K3 With the circuit turned on, the signal from the third node N3 is written to the fifth node N5, and the signal at the fourth selector G4 is high. The fourth selector transistor T... G4When the circuit is turned on, the signal from the fifth node N5 is written to the ninth node N9. The fourth sampling sub-circuit samples the third current signal and generates the fourth initial voltage signal corresponding to the third current signal. The fourth filtering sub-circuit filters the fourth initial voltage signal corresponding to the third current signal and generates the fourth voltage signal corresponding to the third current signal. The signal selector provides the fourth voltage signal corresponding to the third current signal to the signal buffer, which stores the fourth voltage signal. The analog-to-digital converter converts the fourth voltage signal corresponding to the third current signal into a fourth digital voltage signal corresponding to the third current signal. The controller determines whether the fourth digital voltage signal corresponding to the third current signal meets the threshold condition. If the fourth digital voltage signal meets the threshold condition (i.e., the voltage value of the fourth digital voltage signal is less than the first threshold voltage value), the fourth digital voltage signal corresponding to the third current signal is converted into a full-range digital voltage signal and stored in the third digital register. If the voltage value of the fourth digital voltage signal does not meet the threshold condition (i.e., the voltage value of the fourth digital voltage signal is greater than the first threshold voltage value), the fourth digital voltage signal corresponding to the third current signal is discarded.

[0256] Between the third and fourth color sampling stages is a blank stage. During the blank stage, all control signals are low-level signals, all transistors are turned off, and no sampling occurs.

[0257] When the controller determines that the third current signal is not the fourth current signal, it determines whether the voltage values ​​of the first digital voltage signal to the fourth digital voltage signal corresponding to the fourth current signal meet the threshold condition, that is, it executes the fourth color sampling stage.

[0258] In the first level selection stage S41 of the fourth color sampling stage S4, the fourth photoelectric sensor D4 converts the fourth color light into a fourth current signal and writes it to the fourth node N4; the signal at the fourth element selection signal terminal K4 is a high-level signal, and the fourth element selection transistor T... K4 With the circuit turned on, the signal from the fourth node N4 is written to the fifth node N5, the signal at the first gear selection terminal G1 is high, and the first gear selection transistor T... G1When the circuit is turned on, the signal from the fifth node N5 is written to the sixth node N6. The first sampling sub-circuit samples the fourth current signal and generates the first initial voltage signal corresponding to the fourth current signal. The first filtering sub-circuit filters the first initial voltage signal corresponding to the fourth current signal and generates the first voltage signal corresponding to the fourth current signal. The signal selector transmits the first voltage signal corresponding to the fourth current signal to the signal buffer. The signal buffer stores the first voltage signal corresponding to the fourth current signal. The analog-to-digital converter converts the first voltage signal corresponding to the fourth current signal into a first digital voltage signal corresponding to the fourth current signal. The controller determines whether the first digital voltage signal corresponding to the fourth current signal meets the threshold condition. If the first digital voltage signal meets the threshold condition (i.e., the voltage value of the first digital voltage signal is greater than the second threshold voltage value), the first digital voltage signal corresponding to the fourth current signal is converted into a full-range digital voltage signal and stored in the fourth digital register. If the voltage value of the first digital voltage signal does not meet the threshold condition (i.e., the voltage value of the first digital voltage signal is less than the second threshold voltage value), the first digital voltage signal corresponding to the fourth current signal is discarded.

[0259] In the second gear selection stage S42 of the fourth color sampling stage S4, the fourth photoelectric sensor D4 converts the fourth color light into a fourth current signal and writes it to the fourth node N4; the signal at the fourth element selection signal terminal K4 is a high-level signal, and the fourth element selection transistor T... K4 With the circuit turned on, the signal from the fourth node N4 is written to the fifth node N5, the signal at the second selector G2 is high, and the second selector transistor T... G2When the circuit is turned on, the signal from node N5 is written to node N7. The second sampling sub-circuit samples the fourth current signal and generates the second initial voltage signal corresponding to the fourth current signal. The second filtering sub-circuit filters the second initial voltage signal corresponding to the fourth current signal and generates the second voltage signal corresponding to the fourth current signal. The signal selector transmits the second voltage signal corresponding to the fourth current signal to the signal buffer. The signal buffer stores the second voltage signal corresponding to the fourth current signal. The analog-to-digital converter converts the second voltage signal corresponding to the fourth current signal into a second digital voltage signal corresponding to the fourth current signal. The controller determines the second digital voltage signal corresponding to the fourth current signal. If the voltage signal meets the threshold condition, i.e., the voltage value of the second digital voltage signal corresponding to the fourth current signal is greater than the first threshold voltage value and less than the second threshold voltage value, the second digital voltage signal corresponding to the fourth current signal is converted into a full-range digital voltage signal and stored in the fourth digital register. If the voltage value of the second digital voltage signal corresponding to the fourth current signal does not meet the threshold condition, i.e., the voltage value of the second digital voltage signal is less than the first threshold voltage value or greater than the second threshold voltage value, the second digital voltage signal corresponding to the fourth current signal is discarded.

[0260] In the third level selection stage S43 of the fourth color sampling stage S4, the fourth photoelectric sensor D4 converts the light of the fourth color into a fourth current signal and writes it to the fourth node N4; the signal at the fourth element selection signal terminal K4 is a high-level signal, and the fourth element selection transistor T... K4 With the circuit turned on, the signal from the fourth node N4 is written to the fifth node N5, the signal at the third gear selection terminal G3 is high, and the third gear selection transistor T... G3When the circuit is turned on, the signal from the fifth node N5 is written to the eighth node N8. The third sampling sub-circuit samples the fourth current signal and generates the third initial voltage signal corresponding to the fourth current signal. The third filtering sub-circuit filters the third initial voltage signal corresponding to the fourth current signal and generates the third voltage signal corresponding to the fourth current signal. The signal selector provides the third voltage signal corresponding to the fourth current signal to the signal buffer. The signal buffer stores the third voltage signal corresponding to the fourth current signal. The analog-to-digital converter converts the third voltage signal corresponding to the fourth current signal into the third digital voltage signal corresponding to the fourth current signal. The controller determines the third digital voltage signal corresponding to the fourth current signal. If the voltage signal meets the threshold condition, i.e., the voltage value of the third digital voltage signal corresponding to the fourth current signal meets the threshold condition (i.e., the voltage value of the third digital voltage signal is greater than the first threshold voltage value and less than the second threshold voltage value), the third digital voltage signal corresponding to the fourth current signal is converted into a full-range digital voltage signal and stored in the fourth digital register. If the voltage value of the third digital voltage signal corresponding to the fourth current signal does not meet the threshold condition (i.e., the voltage value of the third digital voltage signal is less than the first threshold voltage value or greater than the second threshold voltage value), the third digital voltage signal corresponding to the fourth current signal is discarded.

[0261] In the fourth color sampling stage S4, the fourth position selection stage S44, the fourth photoelectric sensor D4 converts the fourth color light into a fourth current signal and writes it to the fourth node N4; the signal at the fourth element selection signal terminal K4 is a high-level signal, and the fourth element selection transistor T... K4 With the circuit turned on, the signal from the fourth node N4 is written to the fifth node N5, the signal at the fourth gear selection terminal G4 is high, and the fourth gear selection transistor T... G4When the circuit is turned on, the signal from the fifth node N5 is written to the ninth node N9. The fourth sampling sub-circuit samples the fourth current signal and generates the fourth initial voltage signal corresponding to the fourth current signal. The fourth filtering sub-circuit filters the fourth initial voltage signal corresponding to the fourth current signal and generates the fourth voltage signal corresponding to the fourth current signal. The signal selector provides the fourth voltage signal corresponding to the fourth current signal to the signal buffer. The signal buffer stores the fourth voltage signal corresponding to the fourth current signal. The analog-to-digital converter converts the fourth voltage signal corresponding to the fourth current signal into a fourth digital voltage signal corresponding to the fourth current signal. The controller determines whether the fourth digital voltage signal corresponding to the fourth current signal meets the threshold condition. If the fourth digital voltage signal meets the threshold condition (i.e., the voltage value of the fourth digital voltage signal is less than the first threshold voltage value), the fourth digital voltage signal corresponding to the fourth current signal is converted into a full-range digital voltage signal and stored in the fourth digital register. If the voltage value of the fourth digital voltage signal does not meet the threshold condition (i.e., the voltage value of the fourth digital voltage signal is greater than the first threshold voltage value), the fourth digital voltage signal corresponding to the fourth current signal is discarded.

[0262] The controller determines whether the voltage values ​​of the first to fourth digital voltage signals corresponding to the first current signal of the newly acquired first color light meet the threshold condition, and then executes a new first color sampling stage.

[0263] This disclosure allows for the acquisition of first to fourth current signals in a set sequence by controlling the turn-on sequence of multiple element selection transistors and multiple gear selection switch transistors. The signals are then converted into first to fourth voltage signals corresponding to the current signals at different gear positions, ensuring the sampling accuracy of the current signals.

[0264] This disclosure also provides a light detection method. Figure 10 A flowchart illustrating the light detection method provided in this embodiment of the disclosure. Figure 10 As shown, the light detection method provided in this embodiment may include the following steps:

[0265] Step S101: The control device generates a control signal.

[0266] Step S102: The photoelectric conversion device converts the incident N colors of light into current signals and provides current signals under the control of the control signal.

[0267] Step S103: The current conversion device converts the current signal into a voltage signal corresponding to the current signal.

[0268] Step S104: The control device generates the chromaticity parameters of the light based on the voltage signal corresponding to the current signal.

[0269] In one exemplary embodiment, the chromaticity parameters may include: luminance, color temperature, and chromaticity coordinates.

[0270] The light detection method is configured to be applied to the light detection structure provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0271] In one exemplary embodiment, step 102 may include: converting incident light of a first color into a first current signal and writing the first current signal into a first node; converting incident light of a second color into a second current signal and writing the second current signal into a second node; converting incident light of a third color into a third current signal and writing the third current signal into a third node; and converting incident light of a fourth color into a fourth current signal and writing the fourth current signal into a fourth node.

[0272] In one exemplary embodiment, step 102 further includes: under the control of the signals from the first element selection signal terminal to the fourth element selection signal terminal, providing the signals of the first node, the second node, the third node, or the fourth node to the fifth node in a time-division manner; and under the control of the signals from the first gear selection signal terminal to the fourth gear selection signal terminal, providing the signals of the fifth node to the sixth node, the seventh node, the eighth node, and the ninth node in a time-division manner.

[0273] In one exemplary embodiment, under the control of signals from the first element selection signal terminal to the fourth element selection signal terminal, providing signals of the first node, the second node, the third node, or the fourth node to the fifth node in a time-division manner includes: providing the first node's signal to the fifth node under the control of the signal from the first element selection signal terminal; providing the first node's signal to the fifth node under the control of the signal from the second element selection signal terminal; providing the first node's signal to the fifth node under the control of the signal from the third element selection signal terminal; and providing the first node's signal to the fifth node under the control of the signal from the fourth element selection signal terminal.

[0274] In one exemplary embodiment, under the control of signals from the first gear selection signal terminal to the fourth gear selection signal terminal, providing the signal of the fifth node to the sixth, seventh, eighth, and ninth nodes in a time-division manner includes: providing the signal of the fifth node to the sixth node under the control of the signal from the first gear selection signal terminal, providing the signal of the fifth node to the seventh node under the control of the signal from the second gear selection signal terminal, providing the signal of the fifth node to the eighth node under the control of the signal from the third gear selection signal terminal, and providing the signal of the fifth node to the ninth node under the control of the signal from the fourth gear selection signal terminal.

[0275] In one exemplary embodiment, the voltage signal includes: a first voltage signal to a fourth voltage signal.

[0276] In an exemplary embodiment, step S103 may include: sampling the signals from the sixth to the ninth nodes to generate first to fourth initial voltage signals corresponding to the current signals, and providing the first to fourth initial voltage signals corresponding to the current signals to the tenth to the thirteenth nodes respectively; filtering the first to fourth initial voltage signals corresponding to the current signals to generate first to fourth voltage signals corresponding to the current signals, and providing the first to fourth voltage signals corresponding to the current signals to the control device respectively.

[0277] In one exemplary embodiment, sampling the signals from the sixth to the ninth nodes to generate a first to a fourth initial voltage signal corresponding to the current signal, and providing the first to a fourth initial voltage signal corresponding to the current signal to the tenth to the thirteenth nodes respectively, may include: sampling the signal from the sixth node to generate a first initial voltage signal corresponding to the current signal and providing the first initial voltage signal corresponding to the current signal to the tenth node; sampling the signal from the seventh node to generate a second initial voltage signal corresponding to the current signal and providing the second initial voltage signal corresponding to the current signal to the eleventh node; sampling the signal from the eighth node to generate a third initial voltage signal corresponding to the current signal and providing the third initial voltage signal corresponding to the current signal to the twelfth node; and sampling the signal from the ninth node to generate a fourth initial voltage signal corresponding to the current signal and providing the fourth initial voltage signal corresponding to the current signal to the thirteenth node.

[0278] In one exemplary embodiment, filtering the first to fourth initial voltage signals corresponding to the current signal to generate the first to fourth voltage signals corresponding to the current signal, and providing the first to fourth voltage signals corresponding to the current signal to the control device respectively, may include: filtering the signal of the tenth node to generate the first voltage signal corresponding to the current signal and providing the first voltage signal corresponding to the current signal to the control device; filtering the signal of the eleventh node to generate the second voltage signal corresponding to the current signal and providing the second voltage signal corresponding to the current signal to the control device; filtering the signal of the twelfth node to generate the third voltage signal corresponding to the current signal and providing the third voltage signal corresponding to the current signal to the control device; and filtering the signal of the thirteenth node to generate the fourth voltage signal corresponding to the current signal and providing the fourth voltage signal corresponding to the current signal to the control device.

[0279] In one exemplary embodiment, step S104 may include: converting the first voltage signal to the fourth voltage signal corresponding to the current signal into the first digital voltage signal to the fourth digital voltage signal corresponding to the current signal; and generating chromaticity parameters of the light based on the first digital voltage signal to the fourth digital voltage signal corresponding to the current signal.

[0280] In one exemplary embodiment, generating chromaticity parameters of light based on the first to fourth digital voltage signals corresponding to the current signal may include: pre-storing a first threshold voltage value and a second threshold voltage value; sequentially determining whether the voltage values ​​of the first to fourth digital voltage signals corresponding to the i-th current signal satisfy the corresponding threshold conditions, converting the digital voltage signal corresponding to the i-th current signal that satisfies the corresponding threshold conditions into a full-range digital voltage signal, and storing the converted full-range digital voltage signal in the i-th digital register; and generating chromaticity parameters of light based on the full-range digital voltage signals in the first to fourth digital registers.

[0281] The threshold condition for the first digital voltage signal corresponding to the i-th current signal is greater than the second threshold voltage value. The threshold conditions for the second and third digital voltage signals corresponding to the i-th current signal are greater than the first threshold voltage value and less than the second threshold voltage value. The threshold condition for the fourth digital voltage signal corresponding to the i-th current signal is less than the first threshold voltage value. The first threshold voltage value is greater than the minimum input voltage value of the analog-to-digital converter, and the second threshold voltage value is less than the maximum input voltage value of the mode converter.

[0282] In one exemplary embodiment, converting the digital voltage signal corresponding to the i-th current signal that meets the threshold condition into a full-range digital voltage signal may include: according to formula V Dcount =V Dj / Gain j The j-th digital voltage signal is converted into a full-range digital voltage signal Dcount, where the j-th digital voltage signal is the digital voltage signal corresponding to the i-th current signal that meets the threshold condition, and Gain j Gain is the magnification factor. j =K j V Dcount The voltage value of the full-range digital voltage signal, V Dj Let be the voltage value of the j-th digital voltage signal, where j = 1, 2, 3, or 4.

[0283] This disclosure also provides a display substrate. Figure 11 This is a schematic diagram of the structure of a display substrate. (Example) Figure 11As shown, the display substrate provided in this embodiment includes: a display area 400 and a non-display area, wherein a light detection structure is provided in the non-display area.

[0284] The light detection structure is the same as the light detection structure provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0285] In one exemplary embodiment, the display area 400 may include a plurality of regularly arranged sub-pixels, and the sub-pixels may include pixel driving circuits and light-emitting devices.

[0286] like Figure 11 As shown, the non-display area includes: a border area 500 and a binding area 600. The binding area 600 is located on the side of the border area 500 away from the display area 400. The photoelectric conversion device in the light detection structure is located in the border area, and the current conversion device and control device in the light detection structure are located in the binding area.

[0287] In one exemplary embodiment, the bonding region 600 may include bonding circuitry for connecting signal lines to an external driving device, and the border region 500 may include gate driving circuitry and power lines for transmitting voltage signals to a plurality of sub-pixels.

[0288] In one exemplary embodiment, the bonding region 600 may include a bending region 601 and a composite circuit region 602.

[0289] In an exemplary embodiment, the bending region 601 can be bent with a curvature, which can reverse the surface of the composite circuit region 602, that is, the upward-facing surface of the composite circuit region 602 can be transformed into a downward-facing surface by bending the bending region 601. In an exemplary embodiment, when the bending region 601 is bent, the composite circuit region 602 can overlap with the display area 400.

[0290] In an exemplary embodiment, the composite circuit region 602 may include an anti-static region, a driver chip region, and a bonding pin region. An integrated circuit (IC) 10 may be bonded to the driver chip region, and a flexible printed circuit board (FPC) 20 may be bonded to the bonding pin region. In an exemplary embodiment, the integrated circuit 10 can generate driving signals required to drive sub-pixels and can provide these driving signals to the sub-pixels in the display area. For example, the driving signal may be a data signal that drives the brightness of the sub-pixels. In an exemplary embodiment, the integrated circuit 10 may be bonded to the driver chip region via an anisotropic conductive film or other means. In an exemplary embodiment, the bonding pin region may be provided with pads including multiple pins, and the flexible printed circuit board 20 may be bonded to the pads.

[0291] In one exemplary embodiment, the current conversion device and control device in the light detection structure can be integrated into the display substrate, for example, they can be integrated into an integrated circuit in the composite circuit area of ​​the display substrate.

[0292] Figure 12 This is a schematic diagram of a display substrate provided for an exemplary embodiment. Figure 12 As shown, in one exemplary embodiment, the display substrate may further include: a substrate and four shielded signal lines SL disposed on the substrate; the photoelectric conversion device includes: a first element selection transistor T. K1 To the fourth element select transistor T K4 And the first gear selector transistor T G1 Select transistor T at the fourth position G4 The orthographic projection of the i-th shielded signal line SL onto the substrate at least partially overlaps with the orthographic projections of the i-th element selection transistor and the i-th position selection transistor onto the substrate.

[0293] In this disclosure, the orthographic projection of the i-th shielded signal line SL on the substrate at least partially overlaps with the orthographic projections of the i-th element selection transistor and the i-th position selection transistor on the substrate, which ensures that the signals flowing through the i-th element selection transistor and the i-th position selection transistor are not interfered with, thereby improving the accuracy of the light detection structure.

[0294] This disclosure also provides a display device, including a display substrate.

[0295] The display substrate is the same as the display substrate provided in any of the foregoing embodiments. The implementation principle and effect are similar, and will not be described again here.

[0296] In one exemplary embodiment, the display device may further include an application program. The application program is electrically connected to a light detection structure in the display substrate and configured to acquire chromaticity parameters of light.

[0297] In one exemplary embodiment, the application may be a flash, or other application that needs to acquire chromaticity parameters of light, and this disclosure does not limit it in any way.

[0298] In one exemplary embodiment, the display device can be any product or component with display function, such as a liquid crystal panel, electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

[0299] When the display device includes a thin-film transistor display screen, the transistor in the light detection structure of the display substrate can be a thin-film transistor (TFT).

[0300] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0301] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0302] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A light detection structure, comprising: Photoelectric conversion devices, current conversion devices, and control devices; The photoelectric conversion device is electrically connected to the current conversion device and is configured to convert incident light of N colors into current signals, and provide the current signals to the current conversion device under the control of a control signal, where N is a positive integer greater than or equal to 1. The current conversion device is configured to convert the current signal into a voltage signal corresponding to the current signal; The control device is electrically connected to the photoelectric conversion device and the current conversion device respectively, and is configured to generate a control signal and generate chromaticity parameters of light according to the voltage signal corresponding to the current signal. The chromaticity parameters include: brightness, color temperature, and color coordinates. When N=4, the photoelectric conversion device includes: four photoelectric conversion elements, an element selection circuit, and a gear selection circuit; the four photoelectric conversion elements include: a first photoelectric conversion element, a second photoelectric conversion element, a third photoelectric conversion element, and a fourth photoelectric conversion element; the current signal includes: a first current signal, a second current signal, a third current signal, and a fourth current signal; the control signal includes: a first element selection signal to a fourth element selection signal and a first gear selection signal to a fourth gear selection signal. The first photoelectric conversion element is electrically connected to the sensing signal terminal and the first node respectively, and is configured to convert the incident light of the first color into a first current signal and write the first current signal into the first node; The second photoelectric conversion element is electrically connected to the sensing signal terminal and the second node, respectively, and is configured to convert the incident light of the second color into a second current signal and write the second current signal into the second node; The third photoelectric conversion element is electrically connected to the sensing signal terminal and the third node, respectively, and is configured to convert the incident third color light into a third current signal and write the third current signal into the third node; The fourth photoelectric conversion element is electrically connected to the sensing signal terminal and the fourth node, respectively, and is configured to convert the incident fourth color light into a fourth current signal and write the fourth current signal into the fourth node; The first color, the second color, the third color, and the fourth color are one of red, green, blue, and white, and the first color, the second color, the third color, and the fourth color are different colors, and the voltage value of the signal at the sensing signal terminal is constant; The component selection circuit is electrically connected to the first component selection signal terminal to the fourth component selection signal terminal, the first node, the second node, the third node, the fourth node, and the fifth node, respectively. It is configured to provide the first node, the second node, the third node, or the fourth node to the fifth node in a time-division manner under the control of the signals from the first component selection signal terminal to the fourth component selection signal terminal. The signal of the i-th component selection signal terminal is the i-th component selection signal, where i is 1 to 4. The gear selection circuit is electrically connected to the first gear selection signal terminal to the fourth gear selection signal terminal, the fifth node, the sixth node, the seventh node, the eighth node, and the ninth node, respectively. It is configured to provide the signal of the fifth node to the sixth node, the seventh node, the eighth node, and the ninth node in a time-division manner under the control of the signals from the first gear selection signal terminal to the fourth gear selection signal terminal. The signal of the i-th gear selection signal terminal is the i-th gear selection signal.

2. The light detection structure according to claim 1, wherein, The first photoelectric conversion element includes: a first photoelectric sensor; the second photoelectric conversion element includes: a second photoelectric sensor; the third photoelectric conversion element includes: a third photoelectric sensor; and the fourth photoelectric conversion element includes: a fourth photoelectric sensor. The anode of the first photoelectric sensor is electrically connected to the first node, and the cathode of the first photoelectric sensor is electrically connected to the sensing signal terminal. The anode of the second photoelectric sensor is electrically connected to the second node, and the cathode of the second photoelectric sensor is electrically connected to the sensing signal terminal. The anode of the third photoelectric sensor is electrically connected to the third node, and the cathode of the third photoelectric sensor is electrically connected to the sensing signal terminal. The anode of the fourth photoelectric sensor is electrically connected to the fourth node, and the cathode of the fourth photoelectric sensor is electrically connected to the sensing signal terminal. Alternatively, the cathode of the first photoelectric sensor is electrically connected to the first node, the anode of the first photoelectric sensor is electrically connected to the sensing signal terminal, the cathode of the second photoelectric sensor is electrically connected to the second node, the anode of the second photoelectric sensor is electrically connected to the sensing signal terminal, the cathode of the third photoelectric sensor is electrically connected to the third node, the anode of the third photoelectric sensor is electrically connected to the sensing signal terminal, the cathode of the fourth photoelectric sensor is electrically connected to the fourth node, and the anode of the fourth photoelectric sensor is electrically connected to the sensing signal terminal.

3. The light detection structure according to claim 1, wherein, When the selection signal of the i-th element is an active level signal, all other element selection signals are inactive level signals, and the end time of the active level signal of the i-th element selection signal is earlier than or equal to the start time of the active level signal of the (i+1)-th element selection signal. When the i-th gear selection signal is an active level signal, all other gear selection signals are inactive level signals. When the i-th element selection signal is an active level signal, the first gear selection signal to the fourth gear selection signal are active level signals in sequence, and the duration of the i-th element selection signal being an active level signal is greater than or equal to the sum of the durations of the first gear selection signal to the fourth gear selection signal being active level signals.

4. The light detection structure according to claim 3, wherein, When the end time of the active level signal of the i-th element selection signal is earlier than the start time of the active level signal of the (i+1)-th element selection signal, the interval between the end time of the active level signal of the i-th element selection signal and the start time of the active level signal of the (i+1)-th element selection signal is equal to the duration of any one of the gear selection signals from the first gear selection signal to the fourth gear selection signal being an active level signal.

5. The light detection structure according to claim 1, wherein, The component selection circuit includes: a first component selection sub-circuit to a fourth component selection sub-circuit; The first element selection sub-circuit is electrically connected to the first element selection signal terminal, the first node, and the fifth node, respectively, and is configured to provide the signal of the first node to the fifth node under the control of the signal of the first element selection signal terminal; The second element selection sub-circuit is electrically connected to the second element selection signal terminal, the second node, and the fifth node, respectively, and is configured to provide the signal of the second node to the fifth node under the control of the signal of the second element selection signal terminal; The third element selection sub-circuit is electrically connected to the third element selection signal terminal, the third node, and the fifth node, respectively, and is configured to provide the signal of the third node to the fifth node under the control of the signal of the third element selection signal terminal; The fourth element selection sub-circuit is electrically connected to the fourth element selection signal terminal, the fourth node, and the fifth node, respectively, and is configured to provide the signal of the fourth node to the fifth node under the control of the signal of the fourth element selection signal terminal.

6. The light detection structure according to claim 5, wherein, The first element selection sub-circuit includes: a first element selection transistor; the second element selection sub-circuit includes: a second element selection transistor; the third element selection sub-circuit includes: a third element selection transistor; and the fourth element selection sub-circuit includes: a fourth element selection transistor. The control electrode of the first element selection transistor is electrically connected to the first element selection signal terminal, the first electrode of the first element selection transistor is electrically connected to the first node, and the second electrode of the first element selection transistor is electrically connected to the fifth node. The control terminal of the second element selection transistor is electrically connected to the second element selection signal terminal, the first terminal of the second element selection transistor is electrically connected to the second node, and the second terminal of the second element selection transistor is electrically connected to the fifth node. The control terminal of the third element selection transistor is electrically connected to the third element selection signal terminal, the first terminal of the third element selection transistor is electrically connected to the third node, and the second terminal of the third element selection transistor is electrically connected to the fifth node. The control terminal of the fourth element selection transistor is electrically connected to the fourth element selection signal terminal, the first terminal of the fourth element selection transistor is electrically connected to the fourth node, and the second terminal of the fourth element selection transistor is electrically connected to the fifth node.

7. The light detection structure according to claim 1, wherein, The gear selection circuit includes: a first gear selection sub-circuit to a fourth gear selection sub-circuit; The first gear selection sub-circuit is electrically connected to the first gear selection signal terminal, the fifth node, and the sixth node, respectively, and is configured to provide the signal of the fifth node to the sixth node under the control of the signal of the first gear selection signal terminal; The second gear selection sub-circuit is electrically connected to the second gear selection signal terminal, the fifth node, and the seventh node, respectively, and is configured to provide the signal of the fifth node to the seventh node under the control of the signal of the second gear selection signal terminal; The third gear selection sub-circuit is electrically connected to the third gear selection signal terminal, the fifth node, and the eighth node, respectively, and is configured to provide the signal of the fifth node to the eighth node under the control of the signal of the third gear selection signal terminal. The fourth position selection sub-circuit is electrically connected to the fourth position selection signal terminal, the fifth node, and the ninth node, respectively, and is configured to provide the signal of the fifth node to the ninth node under the control of the signal of the fourth position selection signal terminal.

8. The light detection structure according to claim 7, wherein, The first gear selection sub-circuit includes: a first gear selection transistor; the second gear selection sub-circuit includes: a second gear selection transistor; the third gear selection sub-circuit includes: a third gear selection transistor; and the fourth gear selection sub-circuit includes: a fourth gear selection transistor. The control electrode of the first gear selection transistor is electrically connected to the first gear selection signal terminal, the first electrode of the first gear selection transistor is electrically connected to the fifth node, and the second electrode of the first gear selection transistor is electrically connected to the sixth node. The control electrode of the second-position selection transistor is electrically connected to the second-position selection signal terminal, the first electrode of the second-position selection transistor is electrically connected to the fifth node, and the second electrode of the second-position selection transistor is electrically connected to the seventh node. The control electrode of the third-position selection transistor is electrically connected to the third-position selection signal terminal, the first electrode of the third-position selection transistor is electrically connected to the fifth node, and the second electrode of the third-position selection transistor is electrically connected to the eighth node. The control electrode of the fourth position selection transistor is electrically connected to the fourth position selection signal terminal, the first electrode of the fourth position selection transistor is electrically connected to the fifth node, and the second electrode of the fourth position selection transistor is electrically connected to the ninth node.

9. The light detection structure according to claim 1, wherein, The voltage signal includes: a first voltage signal to a fourth voltage signal; the current conversion device includes: a sampling circuit and a filtering circuit. The sampling circuit is electrically connected to the sixth to thirteenth nodes and the reference signal terminal, respectively. It is configured to sample the signals of the sixth to ninth nodes, generate the first to fourth initial voltage signals corresponding to the current signals, and provide the first to fourth initial voltage signals corresponding to the current signals to the tenth to thirteenth nodes, respectively. The filtering circuit is electrically connected to the tenth to thirteenth nodes, the ground terminal, and the control device, respectively. It is configured to filter the first to fourth initial voltage signals corresponding to the current signal to generate the first to fourth voltage signals corresponding to the current signal, and provide the first to fourth voltage signals corresponding to the current signal to the control device, respectively.

10. The light detection structure according to claim 9, wherein, The sampling circuit includes: a first sampling sub-circuit, a second sampling sub-circuit, a third sampling sub-circuit, and a fourth sampling sub-circuit; The first sampling sub-circuit is electrically connected to the sixth node, the tenth node and the reference signal terminal respectively, and is configured to sample the signal of the sixth node, generate a first initial voltage signal corresponding to the current signal, and provide the first initial voltage signal corresponding to the current signal to the tenth node. The second sampling sub-circuit is electrically connected to the seventh node, the eleventh node and the reference signal terminal respectively, and is configured to sample the signal of the seventh node, generate the second initial voltage signal corresponding to the current signal, and provide the second initial voltage signal corresponding to the current signal to the eleventh node. The third sampling sub-circuit is electrically connected to the eighth node, the twelfth node and the reference signal terminal respectively, and is configured to sample the signal of the eighth node, generate the third initial voltage signal corresponding to the current signal, and provide the third initial voltage signal corresponding to the current signal to the twelfth node. The fourth sampling sub-circuit is electrically connected to the ninth node, the thirteenth node and the reference signal terminal, respectively. It is configured to sample the signal of the ninth node, generate the fourth initial voltage signal corresponding to the current signal, and provide the fourth initial voltage signal corresponding to the current signal to the thirteenth node.

11. The light detection structure according to claim 10, wherein, The first sampling sub-circuit includes: a first operational amplifier, a first sampling resistor, and a first feedback capacitor; the second sampling sub-circuit includes: a second operational amplifier, a second sampling resistor, and a second feedback capacitor; the third sampling sub-circuit includes: a third operational amplifier, a third sampling resistor, and a third feedback capacitor; the fourth sampling sub-circuit includes: a fourth operational amplifier, a fourth sampling resistor, and a fourth feedback capacitor. The non-inverting input terminal of the first operational amplifier is electrically connected to the reference signal terminal, the inverting input terminal of the first operational amplifier is electrically connected to the sixth node, and the output terminal of the first operational amplifier is electrically connected to the tenth node. The first end of the first sampling resistor is electrically connected to the sixth node, and the second end of the first sampling resistor is electrically connected to the tenth node. The first terminal of the first feedback capacitor is electrically connected to the sixth node, and the second terminal of the first feedback capacitor is electrically connected to the tenth node. The non-inverting input of the second operational amplifier is electrically connected to the reference signal terminal, the inverting input of the second operational amplifier is electrically connected to the seventh node, and the output of the second operational amplifier is electrically connected to the eleventh node. The first end of the second sampling resistor is electrically connected to the seventh node, and the second end of the second sampling resistor is electrically connected to the eleventh node. The first terminal of the second feedback capacitor is electrically connected to the seventh node, and the second terminal of the second feedback capacitor is electrically connected to the eleventh node. The non-inverting input of the third operational amplifier is electrically connected to the reference signal terminal, the inverting input of the third operational amplifier is electrically connected to the eighth node, and the output of the third operational amplifier is electrically connected to the twelfth node. The first end of the third sampling resistor is electrically connected to the eighth node, and the second end of the third sampling resistor is electrically connected to the twelfth node. The first terminal of the third feedback capacitor is electrically connected to the eighth node, and the second terminal of the third feedback capacitor is electrically connected to the twelfth node. The non-inverting input of the fourth operational amplifier is electrically connected to the reference signal terminal, the inverting input of the fourth operational amplifier is electrically connected to the ninth node, and the output of the fourth operational amplifier is electrically connected to the thirteenth node. The first end of the fourth sampling resistor is electrically connected to the ninth node, and the second end of the fourth sampling resistor is electrically connected to the thirteenth node. The first terminal of the fourth feedback capacitor is electrically connected to the ninth node, and the second terminal of the fourth feedback capacitor is electrically connected to the thirteenth node. The resistances R1 of the first sampling resistor, R2 of the second sampling resistor, R3 of the third sampling resistor, and R4 of the fourth sampling resistor satisfy: R1 = K R2=K 2 R3= K 3 R3, where K is a positive integer greater than 1.

12. The light detection structure according to any one of claims 9 to 11, wherein, The filtering circuit includes: a first filtering sub-circuit, a second filtering sub-circuit, a third filtering sub-circuit, and a fourth filtering sub-circuit; The first filter sub-circuit is electrically connected to the tenth node, the ground terminal and the control device respectively, and is configured to filter the signal of the tenth node to generate a first voltage signal corresponding to the current signal, and provide the first voltage signal corresponding to the current signal to the control device. The second filter sub-circuit is electrically connected to the eleventh node, the ground terminal and the control device, respectively, and is configured to filter the signal of the eleventh node, generate the second voltage signal corresponding to the current signal, and provide the second voltage signal corresponding to the current signal to the control device. The third filter sub-circuit is electrically connected to the twelfth node, the ground terminal, and the control device, respectively, and is configured to filter the signal of the twelfth node, generate the third voltage signal corresponding to the current signal, and provide the third voltage signal corresponding to the current signal to the control device. The fourth filter sub-circuit is electrically connected to the thirteenth node, the ground terminal, and the control device, respectively. It is configured to filter the signal of the thirteenth node, generate a fourth voltage signal corresponding to the current signal, and provide the fourth voltage signal corresponding to the current signal to the control device.

13. The light detection structure according to claim 12, wherein, The first filter sub-circuit includes: a first filter resistor and a first filter capacitor; the second filter sub-circuit includes: a second filter resistor and a second filter capacitor; the third filter sub-circuit includes: a third filter resistor and a third filter capacitor; the fourth filter sub-circuit includes: a fourth filter resistor and a fourth filter capacitor. The first end of the first filter resistor is electrically connected to the tenth node, the second end of the first filter resistor is electrically connected to the control device and the first end of the first filter capacitor, and the second end of the first filter capacitor is electrically connected to the ground terminal. The first end of the second filter resistor is electrically connected to the eleventh node, the second end of the second filter resistor is electrically connected to the control device and the first end of the second filter capacitor, and the second end of the second filter capacitor is electrically connected to the ground terminal. The first end of the third filter resistor is electrically connected to the twelfth node, the second end of the third filter resistor is electrically connected to the control device and the first end of the third filter capacitor, and the second end of the third filter capacitor is electrically connected to the ground terminal. The first end of the fourth filter resistor is electrically connected to the thirteenth node, the second end of the fourth filter resistor is electrically connected to the control device and the first end of the fourth filter capacitor, and the second end of the fourth filter capacitor is electrically connected to the ground terminal.

14. The light detection structure according to claim 9, wherein, The control device includes: an analog-to-digital converter, a controller, and a level converter; The analog-to-digital conversion element is electrically connected to the filter circuit and is configured to convert the first voltage signal to the fourth voltage signal corresponding to the current signal into the first digital voltage signal to the fourth digital voltage signal corresponding to the current signal. The controller is electrically connected to the analog-to-digital conversion element and is configured to generate a first initial element selection signal to a fourth initial element selection signal and a first initial gear selection signal to a fourth initial gear selection signal, and to generate chromaticity parameters of light according to the first digital voltage signal to the fourth digital voltage signal corresponding to the current signal. The level converter is electrically connected to the controller, the first component selection signal terminal to the fourth component selection signal terminal, and the first gear selection signal terminal to the fourth gear selection signal terminal. It is configured to perform level conversion on the first initial component selection signal to the fourth initial component selection signal to generate the first component selection signal to the fourth component selection signal, and provide the first component selection signal to the fourth component selection signal terminal respectively. It also performs level conversion on the first initial gear selection signal to the fourth initial gear selection signal to generate the first gear selection signal to the fourth gear selection signal, and provide the first gear selection signal to the fourth gear selection signal terminal respectively.

15. The light detection structure according to claim 14, wherein, The analog-to-digital conversion element includes: a signal selector, a signal buffer, and an analog-to-digital converter; The signal selector is electrically connected to the filter circuit and the signal buffer respectively, and is configured to transmit the first voltage signal to the fourth voltage signal corresponding to the current signal to the signal buffer in a time-division manner. The signal buffer is configured to store the first to fourth voltage signals corresponding to the time-division input current signals of the signal selector; The analog-to-digital converter is electrically connected to the signal buffer and is configured to convert the first to fourth voltage signals corresponding to the current signals in the signal buffer into the first to fourth digital voltage signals corresponding to the current signals in a time-division multiplexing manner.

16. The light detection structure according to claim 15, wherein, The voltage value of the signal at the reference signal terminal is constant, and the voltage value of the signal at the reference signal terminal is less than the maximum input voltage value of the analog-to-digital converter and greater than the minimum input voltage value of the analog-to-digital converter.

17. The light detection structure according to claim 14, wherein, The controller includes: eight first interfaces, each configured as a standard general purpose input / output port; The eight first interfaces are electrically connected to the level converter and are configured to transmit the first initial element selection signal to the fourth initial element selection signal and the first initial gear selection signal to the fourth initial gear selection signal, respectively.

18. The light detection structure according to claim 17, wherein, The controller further includes: a first digital register to a fourth digital register; The controller is configured to pre-store a first threshold voltage value and a second threshold voltage value, sequentially determine whether the voltage values ​​of the first to fourth digital voltage signals corresponding to the i-th current signal meet the corresponding threshold conditions, convert the digital voltage signal corresponding to the i-th current signal that meets the corresponding threshold conditions into a full-range digital voltage signal, and store the converted full-range digital voltage signal in the i-th digital register. It is also configured to generate the chromaticity parameters of light based on the full-range digital voltage signals in the first to fourth digital registers. The threshold condition for the first digital voltage signal corresponding to the i-th current signal is greater than the second threshold voltage value. The threshold conditions for the second and third digital voltage signals corresponding to the i-th current signal are greater than the first threshold voltage value and less than the second threshold voltage value. The threshold condition for the fourth digital voltage signal corresponding to the i-th current signal is less than the first threshold voltage value. The first threshold voltage value is greater than the minimum input voltage value of the analog-to-digital converter, and the second threshold voltage value is less than the maximum input voltage value of the mode converter. The difference between the first threshold voltage value and the minimum input voltage value of the analog-to-digital converter is equal to the difference between the maximum output voltage value of the analog-to-digital converter and the second threshold voltage value.

19. The light detection structure according to claim 18, wherein, The controller is configured according to formula V Dcount =V Dj / Gain j Convert the j-th digital voltage signal into a full-range digital voltage signal Dcount. Wherein, the j-th digital voltage signal is the digital voltage signal corresponding to the i-th current signal that satisfies the threshold condition, Gain j Gain is the magnification factor. j = K j V Dcount The voltage value of the full-range digital voltage signal, V Dj Let be the voltage value of the j-th digital voltage signal, where j = 1, 2, 3, or 4.

20. The light detection structure according to claim 14, wherein, The control device further includes: a transmission interface connected to the controller, the transmission interface being configured as a serial interface and set to transmit the chromaticity parameters of the light generated by the controller; The transmission interface includes: I 2 C interface or SPI interface.

21. A display substrate, comprising: Display area and non-display area, wherein the non-display area is provided with a light detection structure as described in any one of claims 1 to 20.

22. The display substrate according to claim 21, wherein, The non-display area includes a border area and a bonding area. The bonding area is located on the side of the border area away from the display area. The photoelectric conversion device in the light detection structure is disposed in the border area, and the current conversion device and control device in the light detection structure are disposed in the bonding area.

23. The display substrate according to claim 22, further comprising: A substrate and four shielded signal lines disposed on the substrate; The photoelectric conversion device includes: a first element selection transistor to a fourth element selection transistor and a first gear selection transistor to a fourth gear selection transistor; The orthographic projection of the i-th shielded signal line on the substrate at least partially overlaps with the orthographic projections of the i-th element selection transistor and the i-th position selection transistor on the substrate.

24. A display device, comprising: The display substrate as described in any one of claims 21 to 23.

25. The display device according to claim 24, further comprising: app; The application is electrically connected to the light detection structure in the display substrate and is configured to acquire the chromaticity parameters of the light.

26. A light detection method, applied in the light detection structure according to any one of claims 1 to 20, the method comprising: The control device generates control signals; The photoelectric conversion device converts incident light of N colors into current signals, and provides the current signals under the control of the control signal; The current conversion device converts the current signal into a voltage signal corresponding to the current signal; The control device generates chromaticity parameters of the light based on the voltage signal corresponding to the current signal. The chromaticity parameters include: brightness, color temperature, and color coordinates.

27. The method according to claim 26, wherein, The photoelectric conversion device converts incident N colors of light into current signals, including: The incident light of the first color is converted into a first current signal and written into the first node; the incident light of the second color is converted into a second current signal and written into the second node; the incident light of the third color is converted into a third current signal and written into the third node; the incident light of the fourth color is converted into a fourth current signal and written into the fourth node. The photoelectric conversion device, under the control of a control signal, provides the current signal to the current conversion device, including: Under the control of the signals from the first element selection signal terminal to the fourth element selection signal terminal, the signals of the first node, the second node, the third node, or the fourth node are provided to the fifth node in a time-division manner; Under the control of the signals from the first gear selection signal terminal to the fourth gear selection signal terminal, the signal of the fifth node is provided to the sixth, seventh, eighth and ninth nodes in a time-division manner; The provision of signals from the first element selection signal terminal to the fourth element selection signal terminal to the fifth node in a time-division manner includes: providing the first node's signal to the fifth node under the control of the first element selection signal terminal; providing the second node's signal to the fifth node under the control of the second element selection signal terminal; providing the third node's signal to the fifth node under the control of the third element selection signal terminal; and providing the fourth node's signal to the fifth node under the control of the fourth element selection signal terminal. The provision of the signal of the fifth node to the sixth, seventh, eighth, and ninth nodes in a time-division manner, under the control of the signals from the first to the fourth gear selection signal terminals, includes: providing the signal of the fifth node to the sixth node under the control of the signal from the first gear selection signal terminal; providing the signal of the fifth node to the seventh node under the control of the signal from the second gear selection signal terminal; providing the signal of the fifth node to the eighth node under the control of the signal from the third gear selection signal terminal; and providing the signal of the fifth node to the ninth node under the control of the signal from the fourth gear selection signal terminal.

28. The method according to claim 27, wherein, The voltage signal includes: a first voltage signal to a fourth voltage signal, and the current conversion device converts the current signal into a voltage signal corresponding to the current signal by: The signals from the sixth to the ninth nodes are sampled to generate the first to fourth initial voltage signals corresponding to the current signals, and the first to fourth initial voltage signals corresponding to the current signals are provided to the tenth to the thirteenth nodes respectively. The first to fourth initial voltage signals corresponding to the current signal are filtered to generate the first to fourth voltage signals corresponding to the current signal, and the first to fourth voltage signals corresponding to the current signal are respectively provided to the control device. The step of sampling the signals from the sixth to the ninth nodes to generate the first to fourth initial voltage signals corresponding to the current signals, and providing the first to fourth initial voltage signals corresponding to the current signals to the tenth to the thirteenth nodes respectively, includes: sampling the signal from the sixth node to generate the first initial voltage signal corresponding to the current signal and providing the first initial voltage signal corresponding to the current signal to the tenth node; sampling the signal from the seventh node to generate the second initial voltage signal corresponding to the current signal and providing the second initial voltage signal corresponding to the current signal to the eleventh node; sampling the signal from the eighth node to generate the third initial voltage signal corresponding to the current signal and providing the third initial voltage signal corresponding to the current signal to the twelfth node; and sampling the signal from the ninth node to generate the fourth initial voltage signal corresponding to the current signal and providing the fourth initial voltage signal corresponding to the current signal to the thirteenth node. The step of filtering the first to fourth initial voltage signals corresponding to the current signal to generate the first to fourth voltage signals corresponding to the current signal, and providing the first to fourth voltage signals corresponding to the current signal to the control device respectively, includes: filtering the signal of the tenth node to generate the first voltage signal corresponding to the current signal and providing the first voltage signal corresponding to the current signal to the control device; filtering the signal of the eleventh node to generate the second voltage signal corresponding to the current signal and providing the second voltage signal corresponding to the current signal to the control device; filtering the signal of the twelfth node to generate the third voltage signal corresponding to the current signal and providing the third voltage signal corresponding to the current signal to the control device; and filtering the signal of the thirteenth node to generate the fourth voltage signal corresponding to the current signal and providing the fourth voltage signal corresponding to the current signal to the control device.

29. The method according to claim 27 or 28, wherein, The control device generates chromaticity parameters of the light based on the voltage signal corresponding to the current signal, including: Convert the first to fourth voltage signals corresponding to the current signal into the first to fourth digital voltage signals corresponding to the current signal; The chromaticity parameters of the light are generated based on the first to fourth digital voltage signals corresponding to the current signal.

30. The method according to claim 29, wherein, The step of generating chromaticity parameters of light based on the first to fourth digital voltage signals corresponding to the current signal includes: The first threshold voltage value and the second threshold voltage value are stored in advance; Sequentially determine whether the voltage values ​​of the first to fourth digital voltage signals corresponding to the i-th current signal meet the corresponding threshold conditions, convert the digital voltage signal corresponding to the i-th current signal that meets the corresponding threshold conditions into a full-range digital voltage signal, and store the converted full-range digital voltage signal in the i-th digital register; The chromaticity parameters of the light are generated based on the full-range digital voltage signals in the first to fourth digital registers. The threshold condition for the first digital voltage signal corresponding to the i-th current signal is greater than the second threshold voltage value. The threshold conditions for the second and third digital voltage signals corresponding to the i-th current signal are greater than the first threshold voltage value and less than the second threshold voltage value. The threshold condition for the fourth digital voltage signal corresponding to the i-th current signal is less than the first threshold voltage value. The first threshold voltage value is greater than the minimum input voltage value of the analog-to-digital converter, and the second threshold voltage value is less than the maximum input voltage value of the mode converter.

31. The method according to claim 30, wherein, The step of converting the digital voltage signal corresponding to the i-th current signal that meets the threshold condition into a full-range digital voltage signal includes: According to formula V Dcount =V Dj / Gain j The j-th digital voltage signal is converted into a full-range digital voltage signal Dcount, where the j-th digital voltage signal is the digital voltage signal corresponding to the i-th current signal that meets the threshold condition, and Gain j Gain is the magnification factor. j = K j V Dcount The voltage value of the full-range digital voltage signal, V Dj Let be the voltage value of the j-th digital voltage signal, where j = 1, 2, 3, or 4.

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