A GPU merging Schul patch method based on peer-to-peer memory access

Abstract

A method for GPU merging Schur's complement based on peer memory access includes: enabling peer memory access between GPU devices; performing diagonal block processing on a sparse matrix, decomposing the underlying matrix on different GPUs, and storing the matrix in a sparse format; numbering the underlying matrix and establishing a mapping relationship between the number and the underlying matrix data storage address; traversing the Schur's complement of the underlying matrix and obtaining a first array based on the number of non-zero elements at each position; sorting all non-zero elements of the Schur's complement of the underlying matrix according to the storage order of the non-zero elements of the upper matrix, extracting the positions of the sorted non-zero elements and the numbers of the matrices in which they are located, and obtaining a second array; querying the first array and the second array, obtaining the storage address of the underlying matrix data based on the number of the underlying matrix, using peer memory access to extract data from the storage address based on the positions of the non-zero elements, and summing all matrix data extracted within the identified summing range.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic design automation (EDA) circuit simulation, and in particular to a method for GPU merging Schur complement based on peer memory access. Background Art

[0002] In the process of transient simulation of circuits, solving large-scale sparse linear equations is the most time-consuming part. At present, when using the diagonal plus edge matrix partitioning method to solve sparse linear equations, it is necessary to add the Schur complement of the bottom matrix to the corresponding position of the upper layer. When using multiple GPUs (Graphics Processing Unit, abbreviation: GPU, graphics processing unit) for solution, the Schur complement of the bottom matrix and the upper matrix are located on different GPUs. If they are copied to the same GPU for accumulation, a large amount of video memory will be consumed. How to reduce the amount of video memory occupied and avoid the inability to simulate due to insufficient video memory is a problem that needs to be solved in this field. Summary of the Invention

[0003] In order to address the shortcomings of the prior art, the purpose of the present invention is to provide a method for GPU merging Schur's complement based on peer-to-peer memory access. Using the peer-to-peer memory access method, the Schur's complement of the underlying matrices located on multiple GPUs is directly accumulated, reducing the usage of video memory, thereby avoiding the inability to simulate due to insufficient video memory.

[0004] To achieve the above-mentioned object, the present invention provides a method for GPU merging Schur patch based on peer-to-peer memory access, comprising the following steps:

[0005] 1) Enable peer-to-peer memory access between GPU devices;

[0006] 2) Diagonally partition the sparse matrix, decompose the underlying matrix on different GPUs, and store the Schur complement of the underlying matrix in a sparse format;

[0007] 3) numbering the underlying matrix and establishing a mapping relationship between the number and the data storage address of the underlying matrix;

[0008] 4) traversing the Schur complement of the underlying matrix, forming a first array according to the number of non-zero elements at each position, calculating a prefix sum array of the first array, and adding 0 to the first position of the prefix sum array to obtain a second array;

[0009] 5) sorting all non-zero elements of the Schur complement of the bottom matrix according to the storage order of the non-zero elements of the upper matrix, taking the positions of the sorted non-zero elements and the numbers of the matrices in which they are located, to obtain a third array;

[0010] 6) querying the second array and the third array, obtaining the storage address of the underlying matrix data according to the number of the underlying matrix, using a peer-to-peer memory access method to retrieve the matrix data from the retrieved storage address according to the position of the non-zero element, and summing all the matrix data retrieved within the identified summation range.

[0011] Furthermore, the sparse format includes: COO format, row compression format and column compression format.

[0012] Furthermore, the step 6) further comprises:

[0013] For each position of the upper matrix, search for an element in the second array, and the adjacent elements identify the summation range;

[0014] For each position in the summing range, the number of the underlying matrix and the position of the non-zero element are searched in the third array, and the storage address of the underlying matrix data is obtained according to the number of the underlying matrix.

[0015] Furthermore, when calculating multiple sparse matrices with the same sparse structure, steps 1) to 5) are performed once, and step 6) is performed repeatedly.

[0016] Furthermore, the step 6) further includes: performing parallel calculation on the sums of different positions of the upper matrix.

[0017] Furthermore, the prefix sum of the first array is equal to the sum of the element at each position in the first array and the elements at all previous positions.

[0018] Furthermore, the step of forming the first array according to the number of non-zero elements at each position further includes: calculating the number of non-zero elements at each position in the underlying matrix column by column to obtain the first array.

[0019] Furthermore, CUDA C++ is used to enable peer-to-peer memory access between multiple GPU devices.

[0020] To achieve the above-mentioned objectives, the present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and runnable on the processor, wherein the processor is configured to execute the computer program stored in the memory to implement the above-mentioned method of GPU merging Schur patching based on peer memory access.

[0021] To achieve the above objectives, the present invention also provides a computer-readable storage medium, wherein the storage medium stores at least one instruction, which is loaded and executed by a processor to implement the above-mentioned method of GPU merging Schur patch based on peer memory access.

[0022] The method for GPU merging Schur patching based on peer-to-peer memory access provided by the present invention has the following beneficial effects compared with the prior art:

[0023] The Schur complements of the underlying matrix are retained on several GPUs used during decomposition. By constructing an auxiliary data structure and adding them using peer-to-peer memory access, parallel calculations can be performed when merging the Schur complements, improving computational efficiency. Using peer-to-peer memory access for calculations effectively conserves video memory and avoids the problem of simulation failure due to insufficient video memory.

[0024] Other features and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0026] Figure 1 Flowchart of a method for GPU merging Schur's patches based on peer-to-peer memory access according to an embodiment of the present invention;

[0027] Figure 2 A schematic diagram of an example code for CUDA C++ programming according to an embodiment of the present invention;

[0028] Figure 3 Schematic diagram of a matrix with diagonal edge partitioning according to an embodiment of the present invention;

[0029] Figure 4 Schematic diagram of the result after decomposition of the underlying matrix on different GPUs according to an embodiment of the present invention;

[0030] Figure 5 A schematic diagram of the Schur complement of the bottom matrix according to an embodiment of the present invention;

[0031] Figure 6 Schematic diagram of element storage of Shure patch on GPU according to an embodiment of the present invention;

[0032] Figure 7 Schematic diagram of element order and ExpandPos array according to an embodiment of the present invention;

[0033] Figure 8 FIG. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0035] Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0036] As used herein, the term "including" and its variations are open-ended, i.e., "including but not limited to." The term "based on" means "based, at least in part, on." The term "one embodiment" means "at least one embodiment," the term "another embodiment" means "at least one additional embodiment," and the term "some embodiments" means "at least some embodiments." Other terms are defined in the following description.

[0037] It should be noted that the concepts of "first" and "second" may be mentioned in the present invention only to distinguish different devices, components or parts, and are not used to limit the order or interdependence of the functions performed by these devices, components or parts.

[0038] It should be noted that the modifications of "one" and "plurality" mentioned in the present invention are illustrative and non-restrictive. Those skilled in the art will understand that unless the context clearly indicates otherwise, they should be understood as "one or more". "Plurality" should be understood as two or more.

[0039] GPUs are multi-core parallel processors with far more processing units than CPUs. Traditionally, GPUs were solely responsible for graphics rendering, leaving the majority of processing to the CPU. Today, GPUs have evolved into multi-core, multi-threaded, programmable processors with powerful computing capabilities and extremely high memory bandwidth. In general computing models, GPUs function as coprocessors for the CPU, achieving high-performance computing through the rational allocation and decomposition of tasks.

[0040] The computational parallelism of solving sparse linear systems of equations is achieved through diagonal and edge-by-edge partitioning. The underlying matrix can be decomposed in parallel on different processors. The Schur complement of the lower-right corner is then added to the upper matrix, which is then decomposed again to obtain the LU decomposition of the entire matrix. The LU decompositions of different underlying matrices are independent of each other and have no dependencies, making them suitable for parallel execution on multiple GPUs.

[0041] In the prior art, when solving sparse linear equations using diagonal matrix partitioning, the Schur complement of the underlying matrix needs to be added to the corresponding position in the upper layer. When solving using multiple GPUs, the Schur complement of the underlying matrix and the upper layer matrix are located on different GPUs. If they are copied to the same GPU for accumulation, a large amount of video memory is consumed. The present invention uses a peer-to-peer memory access method to directly accumulate the Schur complement of the underlying matrix located on multiple GPUs, reducing video memory usage.

[0042] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0043] Figure 1 FIG. 1 is a flow chart of a method for GPU merging Schur's patch based on peer-to-peer memory access according to an embodiment of the present invention. Figure 1 As shown, first, in step 101, the peer-to-peer memory access function between GPU devices is enabled. When peer-to-peer memory access is enabled between different GPU devices, different GPUs can access each other's internal memory data.

[0044] In the embodiment of the present invention, taking the use of CUDA C++ to enable the peer-to-peer memory access function between GPU devices as an example, the peer-to-peer memory access function between different GPU devices is enabled. Figure 2 Schematic diagram of example code for CUDA C++ programming according to an embodiment of the present invention.

[0045] In step 102, the sparse matrix is partitioned diagonally and edge-wise, the underlying matrix is decomposed on different GPUs, and the Schur complement of the underlying matrix is stored in a sparse format.

[0046] Figure 3 Schematic diagram of a matrix after corner-plus-edge block processing is performed on a sparse matrix according to an embodiment of the present invention. Figure 3 As shown, the sparse matrix is processed into the form of matrix A by diagonally adding edges and blocks; Figure 4 Schematic diagram of the bottom matrix according to an embodiment of the present invention, as shown in FIG. Figure 4 As shown, the matrix A includes four underlying matrices, which will be decomposed on different GPUs. The corresponding Schur complements of these four underlying matrices are as follows: Figure 5 As shown, where AA top1 AA top2 AA top3 AA top4 The sum is the upper matrix.

[0047] After decomposing the underlying matrix on different GPUs, the Schur complement is stored in sparse format on these GPUs, with its elements stored as Figure 6 shown.

[0048] In the embodiment of the present invention, the sparse format includes a COO format, a row compression format, and a column compression format (column compression storage is used as an example in this embodiment). The COO format stores the non-zero elements in the matrix in the form of coordinates; the row compression format stores the matrix elements in sequence by row, and the non-zero elements are encoded with index numbers starting from 0; the column compression format stores the matrix elements in sequence by column, and the non-zero elements are also encoded with index numbers starting from 0.

[0049] In step 103, the underlying matrix is numbered, and a mapping relationship between the number and the storage address of the underlying matrix data is established.

[0050] In the embodiment of the present invention, the bottom matrix in step 102 is numbered, AA top1 , AA top2 , AA top3 , AA top4 They are numbered 0, 1, 2, and 3 respectively.

[0051] In step 104, the Schur complement of the underlying matrix is traversed, and the number of non-zero elements at each position is used as an array. The prefix sum array of this array is calculated and 0 is added to the first position to obtain the ExpandIndex array.

[0052] In an embodiment of the present invention, the prefix sum of an array is calculated, that is, the sum of the first n items at each position in the array is calculated respectively, for example, [1, 2, 3, 4], the prefix sum array is [1, 1+2, 1+2+3, 1+2+3+4].

[0053] Traverse the underlying matrix AA top1 , AA top2 , AA top3 , AA top4 , count the number of non-zero elements at each position in all underlying matrices, such as AA top1 AA top2 AA 1op3 AA top4 If all the non-zero elements are in the first row and first column of , then the number of non-zero elements in the first row and first column is 4, and all the non-zero elements are in the first row and first column of , then the number of non-zero elements in the first row and first column is 0. Figure 5 As shown, the number of non-zero elements at each position of all underlying matrices is 4, 0, 1, 1, 4, 1, 2, 2, 4 respectively. Calculating their prefix sums and padding the first position with 0 gives the ExpandIndex array as 0, 4, 4, 5, 6, 10, 11, 13, 15, 19.

[0054] In step 105, all non-zero elements of the Schur complement of the bottom matrix are sorted according to the storage order of the non-zero elements of the upper matrix, and the positions of the sorted non-zero elements and the numbers of the bottom matrix are obtained to obtain the ExpandPos array.

[0055] In the embodiment of the present invention, the underlying matrix AA top1 , AA top2 , AA too3 , AA top4 All non-zero elements of are sorted according to the storage order of non-zero elements in the upper matrix; the positions of all non-zero elements and the numbers of the underlying matrix are taken out to obtain the ExpandPos array. The element order and ExpandPos array are as follows Figure 7 shown.

[0056] In step 106, the ExpandIndex array and the elements of the ExpandIndex array are queried, and the underlying matrix data storage address is obtained according to the number of the underlying matrix. Using the peer memory access method, data is obtained from this storage address according to the position of the non-zero element, and all matrix data obtained within the summation range are summed.

[0057] In this step, for each position in the upper matrix, the ExpandIndex array is queried for an element, with adjacent elements identifying the summation range. For each position in the summation range, the matrix number and the position of the nonzero element are queried in the ExpandPos array. The storage address of the underlying matrix data is retrieved based on the matrix number. Using peer-to-peer memory access, data is retrieved from this storage address based on the position of the nonzero element, and all matrix data retrieved within the summation range are summed. In this step, the sums of different positions in the upper matrix can be calculated in parallel.

[0058] In the embodiment of the present invention, for each position of the upper matrix, the elements corresponding to the bottom matrix are summed. top Take the element in the second row and second column as an example. Its position in the storage is 4. ExpandIndex[4] and ExpandIndex[5] are 6 and 10 respectively. ExpandPos[6-9] are {1,0}, {2,1}, {2,2}, {1,3}, which correspond to element a22 in position 1 of matrix 0, element b22 in position 2 of matrix 1, element c22 in position 2 of matrix 2, and element d22 in position 1 of matrix 3. Take out the four values and add them to the second row and second column. AA top The summation at other positions is similar, and the summation at different positions can be calculated in parallel.

[0059] In step 107 , when calculating multiple sparse matrices with the same sparse structure, steps 101 to 105 only need to be performed once, and step 106 can be repeated.

[0060] In an embodiment of the present invention, an electronic device is further provided. Figure 8 FIG. 1 is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Figure 8 As shown, the electronic device of the present invention includes a processor 801 and a memory 802, wherein:

[0061] The memory 802 stores a computer program. When the computer program is read and executed by the processor 801 , the computer program executes the steps in the embodiment of the method for GPU merging Schur patches based on peer memory access as described above.

[0062] In an embodiment of the present invention, a computer-readable storage medium is further provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of the above-mentioned method embodiment of GPU merging Schur patch based on peer memory access when running.

[0063] In this embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0064] Those skilled in the art will understand that the foregoing descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will be able to modify the technical solutions described in the foregoing embodiments or substitute equivalents for some of the technical features. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A method for GPU merging Schur patch based on peer memory access, characterized in that: The following steps are involved: 1) Enable peer-to-peer memory access between GPU devices; 2) Diagonally partition the sparse matrix, decompose the underlying matrix on different GPUs, and store the Schur complement of the underlying matrix in a sparse format; 3) numbering the underlying matrix and establishing a mapping relationship between the number and the data storage address of the underlying matrix; 4) traversing the Schur complement of the underlying matrix, forming a first array according to the number of non-zero elements at each position, calculating a prefix sum array of the first array, and adding 0 to the first position of the prefix sum array to obtain a second array; 5) sorting all non-zero elements of the Schur complement of the bottom matrix according to the storage order of the non-zero elements of the upper matrix, taking the positions of the sorted non-zero elements and the numbers of the matrices in which they are located, to obtain a third array; 6) querying the second array and the third array, obtaining the storage address of the underlying matrix data according to the number of the underlying matrix, using a peer-to-peer memory access method to retrieve the matrix data from the retrieved storage address according to the position of the non-zero element, and summing all the matrix data retrieved within the identified summation range.

2. The method for GPU merging Schur patch based on peer-to-peer memory access according to claim 1, characterized in that: The sparse format includes: COO format, row compression format and column compression format.

3. The method for GPU merging Schur patch based on peer-to-peer memory access according to claim 1, wherein: Said step 6) further comprises: For each position of the upper matrix, search for an element in the second array, and the adjacent elements identify the summation range; For each position in the summing range, the number of the underlying matrix and the position of the non-zero element are searched in the third array, and the storage address of the underlying matrix data is obtained according to the number of the underlying matrix.

4. The method for GPU merging Schur patch based on peer-to-peer memory access according to claim 1, wherein: When calculating multiple sparse matrices with the same sparse structure, steps 1) to 5) are performed once, and step 6) is performed repeatedly.

5. The method for GPU merging Schur patch based on peer-to-peer memory access according to claim 1, wherein: Said step 6) further comprises: performing parallel calculation on the sums of different positions of the upper matrix.

6. The method for GPU merging Schur patch based on peer-to-peer memory access according to claim 1, characterized in that: The prefix sum of the first array is equal to the sum of the element at each position in the first array and the elements at all previous positions.

7. The method for GPU merging Schur patch based on peer-to-peer memory access according to claim 1, wherein: The step of forming the first array according to the number of non-zero elements at each position further includes: calculating the number of non-zero elements at each position in the underlying matrix column by column to obtain the first array.

8. The method for GPU merging Schur patch based on peer-to-peer memory access according to claim 1, wherein: Use CUDAc++ to enable peer-to-peer memory access between multiple GPU devices.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: The processor is configured to execute the computer program stored in the memory to implement the method for GPU merging Schur's patch based on peer-to-peer memory access according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The storage medium stores at least one instruction, which is loaded and executed by the processor to implement the method for GPU merging Schur's patch based on peer memory access according to any one of claims 1 to 8.

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