A chip communication system and resource management method for wafer system

Abstract

The present invention discloses a chiplet communication system and resource management method in a wafer system. A central processing unit (CPU) sends management request frames via a management interface to manage registered chiplets. At least two chiplets, including a first chiplet and at least one second chiplet, transmit data with the CPU via the management interface, and transmit data between adjacent chiplets via a first control unit. A first processor transmits data between the first chiplet and the first processor via a second control unit, and the first processor processes a first interrupt signal sent by the first chiplet in response to the management request frame. At least one second processor, with a single second chiplet corresponding to a second processor, transmits data between the single second chiplet and the corresponding second processor via the second control unit, and the second processor processes a second interrupt signal when the corresponding second chiplet sends a second interrupt signal in response to the management request frame. This system enables in-band signal transmission and flexible management of in-band resources.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular to a chip communication system and resource management method for use in a wafer system. Background Art

[0002] Wafer-level system integration (WSI) is a new system integration technology for high-computing applications. It achieves exceptional system computing power through high-speed interconnection between chiplets and high-density integration of homogeneous or heterogeneous chiplets. Due to the significant increase in integration density, the chiplet's input / output (I / O) interface resources have become extremely limited, making traditional direct host interfaces unsuitable for internal resource management in wafer-level systems. Summary of the Invention

[0003] The present invention provides a chip communication system and resource management method for a wafer system, so as to solve the problem that the input and output (I / O) interface resources of the chip are limited and the traditional host direct interface is not suitable for internal resource management in the wafer-level system.

[0004] According to one aspect of the present invention, a chiplet communication system for use in a wafer system is provided, comprising:

[0005] The central processing unit is used to send a management request frame through the management interface to manage the registered chiplets;

[0006] At least two core particles, the core particles comprising a first core particle and at least one second core particle, the first core particle and the central processing unit transmit data via a management interface, and adjacent core particles transmit data between each other via a first control unit;

[0007] a first processor, wherein data is transmitted between the first core particle and the first processor via a second control unit, and the first processor is configured to process a first interrupt signal sent by the first core particle according to the management request frame;

[0008] At least one second processor, a single second core particle corresponds to a second processor, data is transmitted between the single second core particle and the corresponding second processor through a second control unit, and the second processor is used to process the second interrupt signal when the corresponding second core particle sends the second interrupt signal according to the management request frame.

[0009] According to another aspect of the present invention, a resource management method is provided, characterized in that it is applied to the chiplet communication system for use in a wafer system according to any embodiment of the present invention, and the method includes:

[0010] The CPU sends a management request frame through the management interface to manage the registered chiplets;

[0011] The first processor processes a first interrupt signal sent by the first chip according to the management request frame;

[0012] The second processor processes the second interrupt signal when the corresponding second core sends the second interrupt signal according to the management request frame.

[0013] The technical solution provided by the embodiment of the present invention is a chip communication system for a wafer system, comprising a central processor, configured to send a management request frame through a management interface to manage registered chiplets; at least two chiplets, the chiplets comprising a first chiplet and at least one second chiplet, the first chiplet and the central processor transmitting data through the management interface, and adjacent chiplets transmitting data through a first control unit; a first processor, the first chiplet and the first processor transmitting data through a second control unit, the first processor being configured to process a first interrupt signal sent by the first chiplet according to the management request frame; at least one second processor, a single second chiplet corresponding to a second processor, a single second chiplet and the corresponding second processor transmitting data through a second control unit, the second processor being configured to process the second interrupt signal when the corresponding second chiplet sends a second interrupt signal according to the management request frame. Through the above technical solution, through the first control unit, the second control unit and the management interface of each chiplet, in-band signal transmission can be realized, in-band resources can be flexibly managed, and the problem of limited input and output (I / O) interface resources of the chiplet and the inability of the traditional host direct interface to be applied to internal resource management in wafer-level systems can be effectively solved.

[0014] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 This is a schematic structural diagram of a chiplet communication system provided in Example 1 of the present invention;

[0017] Figure 2 This is a schematic diagram of a chiplet communication system processing operation provided by an embodiment of the present invention;

[0018] Figure 3This is a flow chart of a resource management method provided in Example 2 of the present invention. DETAILED DESCRIPTION

[0019] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0021] Example 1

[0022] Figure 1 This is a schematic diagram of the structure of a chiplet communication system provided in a first embodiment of the present invention, comprising a central processing unit 11, a first chiplet 12, and at least one second chiplet 13. The central processing unit 11 corresponds to a management interface 110, the first chiplet 12 comprises the management interface 110, a first control unit 120, a first processor 121, and a second control unit 122, and the second chiplet 13 comprises a second processor 131, a second control unit 122, and the first control unit 120. The figure shows only one second chiplet for schematic illustration; depending on actual circumstances, the number of second chiplets may be greater than two. This embodiment is applicable to in-band resource management in wafer-level systems.

[0023] Specifically, the central processing unit 11 is used to send a management request frame through the management interface 110 to manage the registered core particles; the at least two core particles include a first core particle 12 and at least one second core particle 13, the first core particle 12 and the central processing unit 11 transmit data through the management interface 110, and adjacent core particles transmit data through the first control unit 120; the first processor 121, the first core particle 12 and the first processor 121 transmit data through the second control unit 122, and the first processor 121 is used to process the first interrupt signal sent by the first core particle 12 according to the management request frame; at least one second processor 131, a single second core particle 13 corresponds to a second processor 131, a single second core particle 13 and the corresponding second processor 131 transmit data through the second control unit 122, and the second processor 131 is used to process the second interrupt signal when the corresponding second core particle 13 sends the second interrupt signal according to the management request frame.

[0024] In this embodiment, the chip can be a chip of a wafer-level system, where the wafer-level system can also be referred to as a wafer system. The central processing unit 11 can be understood as a processor in a host of the wafer-level system. The management interface 110 can be used for data transmission between the central processing unit 11 and the first chip 12. The management interface 110 can include a high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe) interface or an out-of-band (OOB) interface. The management request frame can be understood as request data from the host requesting management of related chip resources, which may include relevant instructions or commands for managing the chip. The data format of the management request frame can be predefined, such as a management frame format, which can be expressed as an MGR frame format. The central processing unit 11 sends the management request frame through the management interface 110 to manage the registered chip. The wafer-level system can include a first chip 12 and multiple second chips 13. The first chip 12 can be an edge chip, and the second chip 13 can be an internal chip. The first core 12 includes a management interface 110, which is directly connected to the host through the management interface 110. The second core 13 can share the management interface with the first core 12. However, due to resource constraints, the second core 13 does not include the management interface 110 and is therefore not connected to the host. The first control unit 120 can be used for data transmission between adjacent cores, such as C2C. The first core 12 corresponds to the first processor 121, and the second core 13 corresponds to the second processor 131. The second control unit 122 is used to implement interaction between the cores and the corresponding processors, and is used to instruct or configure data transmission by the processors. The second control unit 122 is, for example, a transfer forwarding module (Transfer), which can be represented as Xfer. The first interrupt signal can be understood as a signal initiated by the first core 12 to trigger the first processor 121 to parse and process the management request frame. The second interrupt signal can be understood as a signal initiated by the second core 13 to trigger the second processor 131 to analyze and process the management request frame.

[0025] Specifically, this embodiment is described by taking a wafer-level system including a second chiplet 13 as an example. The CPU 11 transmits data to the first chiplet 12 via the management interface 110. The chiplets are interconnected via the first control unit 120, without the need for fan-out I / O interfaces.

[0026] All corelets to be managed are registered in the management interface 110, including the first corelet 12 and the second corelet 13. The central processor 11 sends a management request frame to the first corelet 12 via the management interface 110. After the first corelet 12 receives the management request frame via the management interface 110, the first corelet 12 sends a first interrupt signal to the first processor 121 via the second control unit 122 based on the management request frame. The first processor 121 then parses the first interrupt signal. If the corelet corresponding to the parsed destination address is the first corelet 12, the parsed data is sent to the second control unit 122 corresponding to the first corelet 12. If the corelet corresponding to the destination address is the second corelet 13, the parsed data is sent to the first control unit 120 for transmission to the second corelet 13. The second corelet 13 then sends a second interrupt signal to the second processor 131 for processing based on the management request frame in the transmitted data. After processing the second interrupt signal, the second processor 131 sends the processed data to the second control unit 122.

[0027] The technical solution provided in the first embodiment of the present invention is a chip communication system for a wafer system, including a central processor 11, which is used to send a management request frame through a management interface 110 to manage registered chiplets; at least two chiplets, the chiplets including a first chiplet 12 and at least one second chiplet 13, the first chiplet 12 and the central processor 11 transmit data through the management interface 110, and adjacent chiplets transmit data through a first control unit 120; a first processor 121, the first chiplet 12 and the first processor 121 transmit data through a second control unit 122, and the first processor 121 is used to process a first interrupt signal sent by the first chiplet 12 according to the management request frame; at least one second processor 131, a single second chiplet 13 corresponds to a second processor 131, and a single second chiplet 13 transmits data to the corresponding second processor 131 through the second control unit 122, and the second processor 131 is used to process the second interrupt signal when the corresponding second chiplet 13 sends the second interrupt signal according to the management request frame. Through the above technical solution, in-band signal transmission can be realized through the first control unit 120, the second control unit 122 of each chip and the management interface 110 of the first chip 12, and flexible management of in-band resources can be achieved, which effectively solves the problem that the input and output (I / O) interface resources of the chip are limited and the traditional host direct interface is not suitable for internal resource management in wafer-level systems.

[0028] In some embodiments, the destination address of the management request frame is a designated second corelet; the first processor is specifically configured to: in response to the first interrupt signal, if it is determined that the destination address is the designated second corelet, forward the management request frame to a second corelet adjacent to the first corelet via the second control unit of the first corelet. This technical solution enables request management of a designated corelet.

[0029] In this embodiment, the destination address can be understood as a chiplet to be managed by the designated central processing unit.

[0030] Specifically, in order to manage a specified core, it is necessary to specify the destination address of a management request frame. When transmitting a management request frame within a core, the first processor responds to a first interrupt signal and parses the first interrupt signal. If it is determined that the core corresponding to the destination address is the second core, the processor sends the parsed data to the second control unit of the first core. The second control unit then sends the parsed data to the first control unit, which then forwards the parsed data to the second core corresponding to the destination address of the specified management request frame through the first control unit. The parsed data includes the management request frame.

[0031] In some embodiments, a single second core is specifically configured to: if the destination address is the core, send a second interrupt signal to the corresponding second processor via the second control unit of the core; if the destination address is not the core, forward the management request frame to a second core adjacent to the core via the first control unit of the core. Through the above technical solution, the wafer-level system can flexibly manage internal resources.

[0032] Specifically, during the process of managing internal resources, for a single second core, if the destination address is the core itself, the second control unit of the core sends a second interrupt signal to the second processor corresponding to the core for resolution. If the destination address is not the core itself, the first control unit of the core forwards the management frame request frame to a second core adjacent to the core.

[0033] For example, for a single internal die, if the destination address is the internal die, the second interrupt signal is sent to the AP corresponding to the internal die through the Xfer interface of the internal die for resolution. If the destination address is not the internal die, the management request frame is forwarded to the internal die adjacent to the internal die through the chip-to-chip (C2C) interconnection on the internal die.

[0034] In some embodiments, a single second processor is specifically configured to: respond to a second interrupt signal sent by a corresponding second core according to the management request frame, execute a corresponding command according to the management request frame and generate a response frame in a second format; and forward the response frame to a second core adjacent to the core or the first core via a second control unit of the corresponding second core. This technical solution enables data transmission within and between cores, laying the foundation for flexible internal resource management in wafer-level systems.

[0035] In this embodiment, the second format may be a predefined format used for responding to a management request frame. The second format may include a response frame (Response Frame, RSP Frame) format.

[0036] Exemplarily, in the process of managing internal resources, for a single second processor, in response to the second interrupt signal sent by the second core particle according to the management request frame, the management request frame is parsed, and after parsing, the corresponding command is executed according to the management request frame and a response frame in the second format is generated, and then the response frame is sent to the first control unit or the management interface through the second control unit of the second core particle, so that the first control unit forwards the response frame to the second core particle adjacent to the current core particle or the management interface forwards the response frame to the first core particle adjacent to the current core particle.

[0037] In some embodiments, the first core is further configured to, upon receiving a response frame, send a third interrupt signal to the first processor via the second control unit of the core. The first processor is further configured to, based on the third interrupt signal, determine that the response frame is a response frame from a second core within the system. This technical solution lays the foundation for further flexible internal resource management in wafer-level systems.

[0038] In this embodiment, the third interrupt signal can be understood as a signal initiated by the first chip to trigger the first processor to determine and process the response frame.

[0039] Specifically, there may be only one first core in each system. For the first core, if the core receives a response frame sent by the second core, a third interrupt signal is sent to the first processor corresponding to the core through the second control unit on the core. The first processor parses the third interrupt signal and determines whether the response frame is a response frame of the second core in the wafer-level system.

[0040] In some embodiments, the first core is further configured to send the response frame to the central processing unit via the management interface. Through the above technical solution, data interaction between the first core and the management interface is effectively achieved.

[0041] Specifically, in order to implement the wafer-level system management of internal resources, the first chip needs to send a response frame to the central processing unit through the management interface to implement the response to the management request frame.

[0042] In some embodiments, the central processing unit is further configured to establish a ring buffer of the command queue in the memory. Through the above technical solution, effective data storage is achieved and a foundation is laid for the wafer-level system to flexibly manage internal resources.

[0043] In this embodiment, the ring buffer can be understood as a data structure for representing a buffer with a fixed size and connected head to tail.

[0044] Exemplarily, the central processing unit establishes a ring buffer of a command queue (Command Queue) and a response queue (Response Queue) in the memory. The ring buffer can be used to store data in MGR Frame and RSP Fram formats. Then the central processing unit can obtain the response frame from the RSPQ in the ring buffer, thereby completing an internal resource management.

[0045] For example, Figure 2 FIG. 1 is a schematic diagram of a chiplet communication system processing operation provided by an embodiment of the present invention. Figure 2 As shown, the wafer-level system includes a system host, an edge die, and three internal dies. The system host includes a central processing unit (Application Processor, AP), a management interface PCIe, and a memory (Double Data Rate, DDR). The DDR includes a ring buffer of established command queues and response queues, where the command queue can be represented by CMDQ and the response queue can be represented by RSPQ. The edge die includes a second control unit Xfer, a management interface PCIe, and a first control unit C2C. The other three internal dies include a second control unit Xfer and two first control units C2C respectively. The edge die is directly connected to the host through PCIe, and the edge die and internal die or the internal dies are interconnected through C2C.

[0046] Register managed chiplets in PCIe, including all edge and internal dies. Predefined transmission data formats are MGR Frame and RSP Frame, and a CMDQ and RSPQ ring buffer is established in the host's memory. The host's access point (AP) controls the CMDQ to generate a management request frame in the MGR frame format. The edge die then reads the management request frame in the CMDQ via PCIe and sends a first interrupt signal to the edge die's AP via its Xfer interface. For example, when managing an internal die, the edge die's AP parses the data and determines the internal die corresponding to the destination address. The parsed data is then sent to the edge die's C2C via the edge die's Xfer interface, which then forwards it to the internal die via the C2C interface. After receiving the data, the internal die determines whether the destination address is the current chiplet. If not, it continues forwarding the data. If it is, it sends a second interrupt signal to the internal die's AP via Xfer interface for parsing. The AP executes the corresponding command based on the management request frame and generates a response frame in the RSP frame format. The chiplet's AP then configures its Xfer interface to forward the response frame. When the Xfer of the edge die receives the response frame, it sends a third interrupt signal to the AP of the edge die. The AP of the edge die analyzes it and determines whether it is the response frame corresponding to the management request frame. If so, the response frame is written to the RSPQ through the PCIe of the edge die for storage and notified to the AP in the host, thereby completing a complete internal resource management command and response.

[0047] Example 2

[0048] Figure 3 This is a flow chart of a resource management method provided in the second embodiment of the present invention, which is applied to a chiplet communication system provided in any embodiment of the present invention. Figure 3 As shown, the method includes:

[0049] S210: The central processing unit sends a management request frame through the management interface to manage the registered chiplets.

[0050] S220: The first processor processes a first interrupt signal sent by the first chiplet according to the management request frame.

[0051] S230: The second processor processes the second interrupt signal when the corresponding second chip sends the second interrupt signal according to the management request frame.

[0052] The technical solution provided by the second embodiment of the present invention is to manage the registered core particles by sending a management request frame through the management interface by the central processing unit; the first processor processes the first interrupt signal sent by the first core particle according to the management request frame; the second processor processes the second interrupt signal when the corresponding second core particle sends the second interrupt signal according to the management request frame. Through the above technical solution, through the first control unit, the second control unit and the management interface of the first core particle of each core particle, in-band signal transmission can be realized, and in-band resources can be flexibly managed, which effectively solves the problem that the input and output (I / O) interface resources of the core particle are limited and the traditional host direct interface cannot be applied to the internal resource management in the wafer-level system.

[0053] In some embodiments, the first processor processes the first interrupt signal sent by the first chiplet according to the management request frame, including:

[0054] In response to the first interrupt signal, the first processor forwards the management request frame to a second chiplet adjacent to the first chiplet through the second control unit of the first chiplet when determining that the destination address of the management request frame is the designated second chiplet.

[0055] The method further includes: the second chip receiving the management request frame performs the following operations:

[0056] If the destination address is the current core particle, a second interrupt signal is sent to the corresponding second processor through the second control unit of the current core particle; if the destination address is not the current core particle, the management request frame is forwarded to the second core particle adjacent to the current core particle through the first control unit of the current core particle.

[0057] In some embodiments, the second processor processes the second interrupt signal when the corresponding second corelet sends the second interrupt signal according to the management request frame, including:

[0058] The second processor responds to the second interrupt signal sent by the corresponding second core particle according to the management request frame, executes the corresponding command according to the management request frame and generates a response frame in a second format;

[0059] forwarding the response frame to a second core particle or the first core particle adjacent to the current core particle through a second control unit of the corresponding second core particle;

[0060] The method further comprises:

[0061] If the first core particle receives the response frame, it sends a third interrupt signal to the first processor via the second control unit of the core particle;

[0062] The first processor determines, according to the third interrupt signal, that the response frame is a response frame of the second core particle in the system;

[0063] The first core particle sends the response frame to the central processing unit through the management interface.

[0064] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0065] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A chip communication system for a wafer system, characterized in that: include: The central processing unit is used to send a management request frame through the management interface to manage the registered chiplets; At least two core particles, the core particles comprising a first core particle and at least one second core particle, the first core particle and the central processing unit transmit data via a management interface, and adjacent core particles transmit data between each other via a first control unit; a first processor, wherein data is transmitted between the first core particle and the first processor via a second control unit, and the first processor is configured to process a first interrupt signal sent by the first core particle according to the management request frame; at least one second processor, a single second core particle corresponding to one second processor, data being transmitted between the single second core particle and the corresponding second processor via a second control unit, the second processor being configured to process the second interrupt signal when the corresponding second core particle sends the second interrupt signal according to the management request frame; The second processor is specifically configured to: In response to a second interrupt signal sent by a corresponding second core particle according to the management request frame, executing a corresponding command according to the management request frame and generating a response frame in a second format; forwarding the response frame to a second core particle or the first core particle adjacent to the current core particle through the first control unit of the corresponding second core particle; The first core is specifically configured to: if a response frame is received, send a third interrupt signal to the first processor via the second control unit of the first core; The first processor is specifically configured to: determine, according to the third interrupt signal, that the response frame is a response frame of a second core particle within the system; The first core is further configured to send the response frame to the central processing unit through the management interface.

2. The chiplet communication system according to claim 1, wherein: The destination address of the management request frame is the designated second core particle; The first processor is specifically configured to: in response to the first interrupt signal, forward the management request frame to a second corelet adjacent to the first corelet through a first control unit of the first corelet when determining that the destination address is a designated second corelet.

3. The chiplet communication system according to claim 2, characterized in that: The single second core particle is specifically used for: If the destination address is the current chiplet, sending a second interrupt signal to the corresponding second processor via the second control unit of the current chiplet; If the destination address is not the current core particle, the management request frame is forwarded to a second core particle adjacent to the current core particle via the first control unit of the current core particle.

4. The chiplet communication system according to claim 1, wherein: The central processing unit is further configured to establish a ring buffer of the command queue in the memory.

5. A resource management method, characterized in that: Applied to the chiplet communication system for use in a wafer system according to any one of claims 1 to 4, the method comprising: The CPU sends a management request frame through the management interface to manage the registered chiplets; The first processor processes a first interrupt signal sent by the first chip according to the management request frame; The second processor responds to the second interrupt signal sent by the corresponding second core particle according to the management request frame, executes the corresponding command according to the management request frame and generates a response frame in a second format; forwarding the response frame to a second core particle or the first core particle adjacent to the current core particle through the first control unit of the corresponding second core particle; The method further comprises: If the first core particle receives the response frame, the first core particle sends a third interrupt signal to the first processor via the second control unit of the first core particle; The first processor determines, according to the third interrupt signal, that the response frame is a response frame of the second core particle in the system; The first core particle sends the response frame to the central processing unit through the management interface.

6. The resource management method according to claim 5, characterized in that: The first processor processes the first interrupt signal sent by the first chip according to the management request frame, including: In response to the first interrupt signal, the first processor forwards the management request frame to a second chiplet adjacent to the first chiplet through the first control unit of the first chiplet when determining that the destination address of the management request frame is the designated second chiplet. The method further includes: the second chip receiving the management request frame performs the following operations: If the destination address is the current core particle, a second interrupt signal is sent to the corresponding second processor through the second control unit of the current core particle; if the destination address is not the current core particle, the management request frame is forwarded to the second core particle adjacent to the current core particle through the first control unit of the current core particle.

Images