Thin film transistor, display substrate and preparation method thereof, and display device

Abstract

This disclosure provides a thin-film transistor, a display substrate, a method for fabricating the same, and a display device. The thin-film transistor includes a substrate, a first metal layer located on one side of the substrate, the first metal layer including a gate, a first insulating layer located on the side of the first metal layer away from the substrate, an active layer located on the side of the first insulating layer away from the substrate, and the active layer including a first semiconductor sublayer and a second semiconductor sublayer. The second semiconductor sublayer is located on the side of the first semiconductor sublayer away from the substrate, and the carrier mobility of the first semiconductor sublayer material is greater than that of the second semiconductor sublayer material. The active layer includes a channel and a first region and a second region located on both sides of the channel. The second metal layer is located on the side of the active layer away from the substrate and includes a first electrode and a second electrode, which are coupled to the first region and the second region, respectively. The embodiments of this disclosure can effectively avoid etching damage to the first semiconductor sublayer and improve device performance.

Description

Technical Field

[0001] This disclosure relates to the field of display device technology, and in particular to a thin-film transistor, a display substrate, a method for fabricating the same, and a display device. Background Technology

[0002] With societal progress and rising living standards, the demand for high-quality display technologies is constantly increasing. In the display industry, thin-film transistor (TFT) technology is considered to have broad application prospects due to its advantages such as high current, low leakage current, and high stability. To improve display performance, further improvements in TFT performance are needed. Among related technologies, back-channel etched (BCE) TFTs still suffer from abnormal characteristics such as negative bias caused by back-channel etching damage. Summary of the Invention

[0003] This disclosure provides a thin-film transistor, a display substrate, a method for fabricating the same, and a display device to solve or alleviate one or more technical problems in the prior art.

[0004] As a first aspect of this disclosure, this disclosure provides a thin-film transistor, including:

[0005] Substrate;

[0006] A first metal layer is located on one side of the substrate, and the first metal layer includes a gate.

[0007] The first insulating layer is located on the side of the first metal layer that is away from the substrate;

[0008] An active layer is located on the side of the first insulating layer away from the substrate. The active layer includes a first semiconductor sublayer and a second semiconductor sublayer stacked together. The second semiconductor sublayer is located on the side of the first semiconductor sublayer away from the substrate. The carrier mobility of the material of the first semiconductor sublayer is greater than that of the material of the second semiconductor sublayer. The active layer includes a channel and a first region and a second region located on both sides of the channel.

[0009] The second metal layer is located on the side of the active layer away from the substrate. The second metal layer includes a first electrode and a second electrode, which are coupled to the first region and the second region, respectively.

[0010] In some possible implementations, the material of the first semiconductor sublayer includes an oxide semiconductor, and the material of the second semiconductor sublayer includes an oxide semiconductor.

[0011] In some possible implementations, the material of the second semiconductor sublayer includes indium gallium zinc oxide.

[0012] Among some possible implementations,

[0013] The thickness of the second semiconductor sublayer located in the channel is 100 angstroms to 400 angstroms, and the thickness of the second semiconductor sublayer is the dimension of the second semiconductor sublayer in the direction perpendicular to the substrate; or,

[0014] The thickness of the second semiconductor sublayer located in the channel is 200 angstroms to 600 angstroms, and the thickness of the second semiconductor sublayer is the dimension of the second semiconductor sublayer in the direction perpendicular to the substrate.

[0015] As a second aspect of the present disclosure, an embodiment of the present disclosure provides a display substrate, the display substrate including a display area and a border area, including:

[0016] Pixel thin-film transistor, wherein the pixel thin-film transistor is a thin-film transistor of any embodiment of the present disclosure, and the pixel thin-film transistor is located in the display area;

[0017] A photosensitive thin-film transistor, wherein the photosensitive thin-film transistor is a thin-film transistor of any embodiment of the present disclosure, and the photosensitive thin-film transistor is located in the border area.

[0018] In some possible implementations, the thickness of the second semiconductor sublayer of the photosensitive thin-film transistor channel is h1, the thickness of the second semiconductor sublayer of the pixel thin-film transistor channel is h2, h1>h2, and the thickness of the second semiconductor sublayer is the dimension of the second semiconductor sublayer in the direction perpendicular to the substrate.

[0019] In some possible implementations, the thickness of the second semiconductor sublayer of the channel of the photosensitive thin film transistor is 200 Å to 600 Å; and / or, the thickness of the second semiconductor sublayer of the channel of the pixel thin film transistor is 100 Å to 400 Å, the thickness of the second semiconductor sublayer being the dimension of the second semiconductor sublayer in the direction perpendicular to the substrate.

[0020] In some possible implementations, the thickness of the second semiconductor sublayer of the channel of the photosensitive thin film transistor is h1, the thickness of the second semiconductor sublayer of the channel of the pixel thin film transistor is h2, the thickness of the first semiconductor sublayer of the channel of the pixel thin film transistor and the thickness of the first semiconductor sublayer of the channel of the photosensitive thin film transistor are both h3, the thickness of the second semiconductor sublayer is the dimension of the second semiconductor sublayer in the direction perpendicular to the substrate, and the thickness of the first semiconductor sublayer is the dimension of the first semiconductor sublayer in the direction perpendicular to the substrate;

[0021] The ratio of h1 / (h1+h3) ranges from 50% to 85%; and / or the ratio of h2 / (h2+h3) ranges from 20% to 80%.

[0022] In some possible implementations, the channel width of the photosensitive thin-film transistor is greater than 10 micrometers.

[0023] In some possible implementations, the first electrode of the photosensitive thin-film transistor includes a plurality of first intercalation portions, and the second electrode of the photosensitive thin-film transistor includes a plurality of second intercalation portions. The first intercalation portions and the second intercalation portions are insulated from each other in the same layer and nested together.

[0024] In some possible implementations, the display substrate also includes:

[0025] The second insulating layer is located on the side of the photosensitive thin-film transistor and the pixel thin-film transistor that is away from the substrate;

[0026] An organic planarization layer is located on the side of the second insulating layer that is away from the substrate;

[0027] The first electrode layer is located on the side of the organic planarization layer away from the substrate;

[0028] The third insulating layer is located on the side of the first electrode layer that is away from the substrate;

[0029] The second electrode layer is located on the side of the third insulating layer away from the substrate, and the second electrode layer is connected to the first electrode of the pixel thin film transistor.

[0030] As a third aspect of the present disclosure, an embodiment of the present disclosure provides a method for manufacturing a display substrate, the display substrate including a display area and a border area, comprising:

[0031] A first metal layer is formed on one side of the substrate. The first metal layer includes the gate of a photosensitive thin-film transistor and the gate of a pixel thin-film transistor. The photosensitive thin-film transistor is located in the border area, and the pixel thin-film transistor is located in the display area.

[0032] A first insulating layer is formed on the side of the first metal layer away from the substrate;

[0033] An active layer and a second metal layer are formed on the side of the first insulating layer away from the substrate. The active layer includes a first semiconductor sublayer and a second semiconductor sublayer stacked together. The second semiconductor sublayer is located on the side of the first semiconductor sublayer away from the substrate. The carrier mobility of the material of the first semiconductor sublayer is greater than that of the material of the second semiconductor sublayer. The active layer includes the active layer of a photosensitive thin film transistor and the active layer of a pixel thin film transistor.

[0034] The second metal layer is located on the side of the active layer away from the substrate, and the second metal layer includes the first and second electrodes of the photosensitive thin film transistor and the first and second electrodes of the pixel thin film transistor.

[0035] In some possible implementations, an active layer and a second metal layer are formed on the side of the first insulating layer facing away from the substrate, including:

[0036] A first semiconductor sublayer of a photosensitive thin-film transistor and a first semiconductor sublayer of a pixel thin-film transistor are formed on the side of the first insulating layer away from the substrate;

[0037] A second semiconductor sub-film for a photosensitive thin-film transistor and a second semiconductor sub-film for a pixel thin-film transistor are formed. The second semiconductor sub-film of the photosensitive thin-film transistor is stacked with a corresponding first semiconductor sub-layer, and the second semiconductor sub-film of the pixel thin-film transistor is stacked with a corresponding first semiconductor sub-layer.

[0038] A second metal thin film is formed on the side of the second semiconductor sub-film away from the substrate. The second metal thin film is etched for the first time to form a first via through the second metal thin film. The orthogonal projection of the first via on the substrate coincides with the orthogonal projection of the channel of the photosensitive thin film transistor on the substrate.

[0039] Plasma surface treatment is performed on the second semiconductor sub-film of the channel of the photosensitive thin film transistor to form the second semiconductor sub-layer of the photosensitive thin film transistor;

[0040] A photoresist layer is formed on the side of the second metal thin film away from the substrate, and a second via is formed in the photoresist layer. The orthogonal projection of the second via on the substrate coincides with the orthogonal projection of the channel of the pixel thin film transistor on the substrate.

[0041] An etching process is used to etch the second metal film at the second via location and the second semiconductor sub-film of the pixel thin film transistor. The remaining second semiconductor sub-film forms the second semiconductor sub-layer of the pixel thin film transistor, and the second metal film forms the first and second electrodes of the photosensitive thin film transistor and the first and second electrodes of the pixel thin film transistor.

[0042] In some possible implementations, the treatment gas for plasma surface treatment is hydrogen or ammonia, the treatment power is 800-2000 W / m2, and the treatment time is 2-10 s.

[0043] As a fourth aspect of the present disclosure, the present disclosure provides a display device including a thin-film transistor of any embodiment of the present disclosure, or including a display substrate of any embodiment of the present disclosure.

[0044] The technical solution of this disclosure can achieve the following beneficial effects: in this thin-film transistor, the second semiconductor sublayer can effectively avoid the etching damage to the first semiconductor sublayer, thereby improving device performance.

[0045] The above overview is for illustrative purposes only and is not intended to be limiting in any way. Further aspects, embodiments, and features of this disclosure will become readily apparent from the accompanying drawings and the following detailed description, in addition to the illustrative aspects, embodiments, and features described above. Attached Figure Description

[0046] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments according to this disclosure and should not be construed as limiting the scope of this disclosure.

[0047] Figure 1 This is a cross-sectional schematic diagram of a thin-film transistor according to an embodiment of the present disclosure;

[0048] Figure 2 This is a cross-sectional schematic diagram of the display substrate according to an embodiment of the present disclosure;

[0049] Figure 3a This is a plan view of the display substrate according to an embodiment of the present disclosure;

[0050] Figure 3b This is a schematic diagram of a photosensitive thin-film transistor detection circuit according to an embodiment of the present disclosure;

[0051] Figure 4a This is a top view of a photosensitive thin-film transistor according to an embodiment of the present disclosure. Figure 1 ;

[0052] Figure 4b This is a top view of a photosensitive thin-film transistor according to an embodiment of the present disclosure. Figure 2 ;

[0053] Figure 4c This is a top view schematic diagram of a pixel thin-film transistor according to an embodiment of the present disclosure;

[0054] Figure 5a This is a schematic diagram of the substrate after the gate and the first insulating layer have been formed in an embodiment of this disclosure;

[0055] Figure 5b This is a schematic diagram of the substrate after the active layer has been formed, according to an embodiment of the present disclosure.

[0056] Figure 5c This is a schematic diagram showing the deposition of a second metal thin film on a substrate according to an embodiment of this disclosure;

[0057] Figure 5d This is a schematic diagram of a first via forming through the second metal thin film on a substrate according to an embodiment of the present disclosure;

[0058] Figure 5e This is a schematic diagram of the second semiconductor sublayer of a substrate formed by plasma surface treatment of a photosensitive thin-film transistor according to an embodiment of the present disclosure;

[0059] Figure 5f This is a schematic diagram of the substrate after the photoresist layer has been removed, according to an embodiment of this disclosure.

[0060] Figure 5g This is a schematic diagram showing the formation of a second via through the second metal thin film on the substrate according to an embodiment of the present disclosure;

[0061] Figure 5h This is a schematic diagram of the second semiconductor sublayer on the display substrate in an embodiment of the present disclosure, showing the formation of pixel thin-film transistors. Detailed Implementation

[0062] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this disclosure. Therefore, the drawings and description are to be considered exemplary in nature and not restrictive.

[0063] Figure 1 This is a schematic cross-sectional view of a thin-film transistor according to an embodiment of the present disclosure. (Refer to...) Figure 1 As shown, this embodiment of the present disclosure provides a thin-film transistor, which includes a substrate 100, a first metal layer 200, a first insulating layer 300, an active layer 400, and a second metal layer 500. The first metal layer 200 is located on one side of the substrate 100 and includes a gate 210. The first insulating layer 300 is located on the side of the first metal layer 200 opposite to the substrate 100.

[0064] Reference Figure 1 As shown, the active layer 400 is located on the side of the first insulating layer 300 facing away from the substrate 100. The active layer 400 includes a first semiconductor sublayer 410 and a second semiconductor sublayer 420 stacked together, with the second semiconductor sublayer 420 located on the side of the first semiconductor sublayer 410 facing away from the substrate 100. The carrier mobility of the material in the first semiconductor sublayer 410 is greater than that in the second semiconductor sublayer 420. The active layer 400 includes a channel 401 and a first region 402 and a second conductive region 403 located on both sides of the channel 401. A second metal layer 500 is located on the side of the active layer 400 facing away from the substrate 100, and the second metal layer 500 includes a first electrode 510 and a second electrode 520, which are coupled to the first region 402 and the second region 403, respectively.

[0065] like Figure 1 As shown, the channel 401 of the second semiconductor sublayer 420 is etched and damaged, resulting in the dimension of the channel 401 in the direction perpendicular to the substrate 100 being smaller than the dimensions of the first region 402 and the second region 403 in the direction perpendicular to the substrate 100. The etch damage to the second semiconductor sublayer 420 with low carrier mobility has a smaller impact on performance. The first semiconductor sublayer 410 is not damaged due to the protection of the second semiconductor sublayer 420, thereby preventing the second semiconductor sublayer 420 with high carrier mobility from becoming abnormal.

[0066] In the thin-film transistor of this embodiment, an active layer 400 is stacked with a first semiconductor sublayer 410 and a second semiconductor sublayer 420, with the second semiconductor sublayer 420 located on the side of the first semiconductor sublayer 410 facing away from the substrate 100. The carrier mobility of the material of the first semiconductor sublayer 410 is greater than that of the material of the second semiconductor sublayer 420. A second metal layer 500 is located on the side of the active layer 400 facing away from the substrate 100, and the second metal layer 500 includes a first electrode 510 and a second electrode 520, which are coupled to a first region 402 and a second region 403, respectively. Therefore, during the etching process to form the first electrode 510 and the second electrode 520, the second semiconductor sublayer 420 can protect the first semiconductor sublayer 410, preventing damage to the first semiconductor sublayer 410 caused by the etching process to form the first electrode 510 and the second electrode 520, thus improving device performance. It also avoids the negative bias and other abnormal characteristics of the first semiconductor sublayer 410 with a high carrier mobility caused by back channel etching damage, which is beneficial to improving the yield of thin film transistors.

[0067] It should be noted that the specific values ​​of the carrier mobility of the first semiconductor sublayer 410 material and the carrier mobility of the second semiconductor sublayer 420 material are not limited here, as long as the carrier mobility of the first semiconductor sublayer 410 material is greater than that of the second semiconductor sublayer 420 material.

[0068] In one embodiment, the substrate 100 can be a rigid substrate. For example, a rigid substrate can be a glass substrate or a polymethyl methacrylate substrate. Alternatively, the substrate 100 can also be a flexible substrate. For example, a flexible substrate can be any of a polyethylene terephthalate substrate, a polyimide substrate, or ultrathin glass. The material of the substrate 100 is not limited herein and can be selected according to the actual application.

[0069] Exemplarily, the first insulating layer 300 is located on the side of the first metal layer 200 facing away from the substrate 100, and the first insulating layer 300 is a gate insulating layer GI. The first insulating layer 300 may include at least one of the following: silicon oxide and silicon nitride. The first insulating layer 300 may be formed as a single-layer structure or a multilayer structure having at least two layers. For example, as Figure 1 As shown, the first insulating layer 300 includes a silicon oxide insulating layer and a silicon nitride insulating layer, with the silicon oxide insulating layer disposed close to the active layer 400. The first insulating layer 300 can have good insulation properties and is formed between the first electrode 510, the second electrode 520, and the gate 210. The specific material of the first insulating layer 300 is not limited here and can be set according to actual application requirements.

[0070] Exemplarily, the first metal layer 200 includes a single layer or multiple layers of composite materials formed from one or more of molybdenum, molybdenum-niobium alloy, aluminum, aluminum-neodymium alloy, titanium, and copper. For example, the gate 210 can be a stacked structure of copper and titanium metal layers. The material of the gate 210 can include metal, and the shape of the gate 210 can be a cube or a cylinder. When the shape of the gate 210 is a cube, the orthographic projection of the gate 210 onto the substrate 100 is rectangular. This disclosure does not specifically limit the shape, material, or thickness of the gate 210.

[0071] For example, the second metal layer 500 may be a single layer or a multilayer composite layer formed of one or more of the following materials: molybdenum, molybdenum-niobium alloy, aluminum, aluminum-neodymium alloy, titanium, and copper. For instance, the first electrode 510 and the second electrode 520 may be a stacked structure of a molybdenum-niobium alloy layer and a copper metal layer. The thin-film transistor may also include a passivation layer covering the side of the first electrode 510 and the second electrode 520 away from the substrate 100, and the passivation layer may be a stacked structure of silicon nitride and silicon oxide.

[0072] In one embodiment, the first semiconductor sublayer 410 is made of an oxide semiconductor, and the second semiconductor sublayer 420 is also made of an oxide semiconductor. Exemplarily, the oxide semiconductor can be indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium zinc oxide (IZO), or similar materials. This disclosure does not specifically limit the oxide semiconductor material; it can be chosen according to actual usage requirements. Exemplarily, the active layer 400 can be cubic or cylindrical, etc. When the active layer 400 is cubic, its orthogonal projection onto the substrate 100 is rectangular.

[0073] In this embodiment of the present disclosure, both the first semiconductor sublayer 410 and the second semiconductor sublayer 420 are made of oxide semiconductors. Moreover, the carrier mobility of the first semiconductor sublayer 410 is greater than that of the second semiconductor sublayer 420. Using a high-mobility oxide semiconductor material as the channel in the first semiconductor sublayer 410 can improve the performance of the thin-film transistor. Furthermore, using a lower-mobility oxide semiconductor material in the second semiconductor sublayer 420 can effectively prevent the etching of the first electrode 510 and the second electrode 520 from damaging the first semiconductor sublayer 410, thereby improving the performance of the thin-film transistor and avoiding damage caused by back channel etching that could lead to abnormal characteristics such as negative bias in the thin-film transistor.

[0074] For example, the orthographic projection of the first semiconductor sublayer 410 on the substrate 100 coincides with the orthographic projection of the second semiconductor sublayer 420 on the substrate 100. The first electrode 510 and the second electrode 520 are respectively attached to the edges of the first semiconductor sublayer 410 and the second semiconductor sublayer 420, and the first electrode 510 and the second electrode 520 are coupled to the first region and the second region on both sides.

[0075] In one embodiment, the material of the second semiconductor sublayer 420 includes indium gallium zinc oxide. The material of the first semiconductor sublayer 420 can be configured as needed, as long as the carrier mobility of the first semiconductor sublayer 410 is greater than that of the second semiconductor sublayer 420. For example, the materials of the first semiconductor sublayer 410 and the second semiconductor sublayer 420 can be the same. The carrier mobility of the first semiconductor sublayer 410 can be made greater than that of the second semiconductor sublayer 420 by adjusting the atomic content within the materials. Alternatively, the materials of the first semiconductor sublayer 410 and the second semiconductor sublayer 420 can be different.

[0076] In one embodiment, the thin-film transistor can serve as a pixel thin-film transistor (Pixel TFT). When the thin-film transistor serves as a pixel thin-film transistor, the thickness of the second semiconductor sublayer 420 located in the channel 401 needs to be appropriately reduced. During the etching process to form the first electrode 510 and the second electrode 520, the thickness of the second semiconductor sublayer 420 is simultaneously reduced by controlling the etching liquid and the etching time, thereby reducing light absorption and further improving stability.

[0077] In one embodiment, when the thin-film transistor is used as a pixel thin-film transistor, the thickness of the second semiconductor sublayer 420 located in the channel 401 is 100 Å to 400 Å, and the thickness of the second semiconductor sublayer 420 is its dimension in the direction perpendicular to the substrate 100. Exemplarily, the thickness of the second semiconductor sublayer 420 located in the channel 401 can be 100 Å, 200 Å, 300 Å, or 400 Å. The specific value of the thickness of the second semiconductor sublayer 420 located in the channel 401 is not limited here and can be set according to actual usage requirements.

[0078] In this embodiment, the thickness of the second semiconductor sublayer 420 located in the channel 401 is set to 100 Å-400 Å. The second semiconductor sublayer 420 can not only protect the first semiconductor sublayer 410 and improve device performance, but also reduce light absorption and further improve stability.

[0079] In one embodiment, the thin-film transistor can be used as a photosensitive thin-film transistor (Sensor TFT). When the thin-film transistor is used as a photosensitive thin-film transistor, the second semiconductor sublayer 420 can increase the thickness of the light-absorbing layer, and can be combined with etching and plasma processing processes to further enhance the photosensitive characteristics of the thin-film transistor.

[0080] In one embodiment, when the thin-film transistor is used as a photosensitive thin-film transistor, the thickness of the second semiconductor sublayer 420 located in the channel 401 is 200 Å to 600 Å, and the thickness of the second semiconductor sublayer 420 is its dimension in the direction perpendicular to the substrate 100. Exemplarily, the thickness of the second semiconductor sublayer 420 located in the channel 401 can be 200 Å, 300 Å, 400 Å, 500 Å, or 600 Å. The specific value of the thickness of the second semiconductor sublayer 420 located in the channel 401 is not limited here and can be set according to actual usage requirements.

[0081] In this embodiment, the thickness of the second semiconductor sublayer 420 located in the channel 401 is 200 angstroms to 600 angstroms. The second semiconductor sublayer 420 can not only protect the first semiconductor sublayer 410, but also increase the thickness of the light absorption layer, thereby further improving the photosensitive characteristics of the thin film transistor.

[0082] Figure 2 This is a schematic cross-sectional view of a display substrate according to an embodiment of this disclosure. (Refer to...) Figure 2 As shown, this embodiment of the present disclosure provides a display substrate 1, which includes a display area AA and a border area BB. The display substrate 1 includes pixel thin-film transistors 10 and photosensitive thin-film transistors 20. The pixel thin-film transistor 10 is a thin-film transistor according to any embodiment of the present disclosure, and is located in the display area AA. The photosensitive thin-film transistor 20 is a thin-film transistor according to any embodiment of the present disclosure, and is located in the border area BB.

[0083] In this embodiment of the display substrate 1, a pixel thin-film transistor 10 is disposed in the display area AA, which is a thin-film transistor as described in any of the above embodiments. A photosensitive thin-film transistor 20 is disposed in the frame area BB, which is a thin-film transistor as described in any of the above embodiments. This effectively prevents damage to the first semiconductor sublayer 420 caused by the etching of the first electrode 510 and the second electrode 520, improving device performance and product yield. Simultaneously, the second semiconductor sublayer 420 in the photosensitive thin-film transistor 20 can increase the thickness of the light absorption layer. Combined with the plasma surface treatment process after etching of the first electrode 510 and the second electrode 520, the photosensitive characteristics are further enhanced, improving the ambient light detection effect.

[0084] For example, the gate 210 of the pixel thin film transistor 10 and the gate 210 of the photosensitive thin film transistor 20 are disposed in the same layer, the first semiconductor sublayer 410 of the pixel thin film transistor 10 and the first semiconductor sublayer 410 of the photosensitive thin film transistor 20 are disposed in the same layer, the second semiconductor sublayer 420 of the pixel thin film transistor 10 and the second semiconductor sublayer 420 of the photosensitive thin film transistor 20 are disposed in the same layer, and the first electrode 510 and the second electrode 520 of the pixel thin film transistor 10 are disposed in the same layer as the first electrode 510 and the second electrode 520 of the photosensitive thin film transistor 20.

[0085] Figure 3a This is a plan view of the display substrate according to an embodiment of the present disclosure. Figure 3b This is a schematic diagram of a photosensitive thin-film transistor detection circuit according to an embodiment of this disclosure. (Refer to...) Figure 3a As shown, exemplarily, the photosensitive thin-film transistors 20 can be used for ambient light detection, and the number of photosensitive thin-film transistors 20 is four. For example, if the display substrate 1 is square, the photosensitive thin-film transistors 20 are disposed in two opposite border areas of the display substrate 1. The number of photosensitive thin-film transistors 20 is not limited here and can be set according to actual usage requirements.

[0086] Reference Figure 3b As shown, the ambient light detection circuit includes a photosensitive thin-film transistor 20 and a pixel thin-film transistor 10, with the pixel thin-film transistor 10 acting as a switch. The second terminal 520 of the photosensitive thin-film transistor 20 and the first terminal 510 of the pixel thin-film transistor 10 are coupled together, and a capacitor C is connected to the coupling point between the second terminal 520 of the photosensitive thin-film transistor 20 and the first terminal 510 of the pixel thin-film transistor 10.

[0087] For example, before ambient light detection, both the photosensitive thin-film transistor 20 and the pixel thin-film transistor 10 are turned on. Figure 3b The voltage at point V0 is the same as the voltage Vdd, which is Va. The photosensitive thin-film transistor 20 and the pixel thin-film transistor 10 are turned off, and the Vdd voltage is adjusted to Vb. Due to the leakage current of the photosensitive thin-film transistor 20, the capacitor C charges, and the voltage at point V0 changes from Va to Vb. Ambient light accelerates this change. After a period of time, the ambient light intensity is recognized by reading the change in the voltage at point V0 after turning on the pixel thin-film transistor 10.

[0088] Exemplarily, both the pixel thin-film transistor 10 and the photosensitive thin-film transistor 20 are disposed on the substrate 100. The display substrate 1 includes a plurality of first switching units disposed on the substrate 100. For example, one first switching unit may be disposed in a sub-pixel region, and the first switching units may be arranged in an array. The first switching units may be configured to control the light emission brightness of the sub-pixel region. Specifically, the first light unit includes at least one pixel thin-film transistor 10, which is disposed on the substrate. By turning the pixel thin-film transistor 10 on and off, the first switching unit can control the light emission brightness of the sub-pixel region, thereby realizing the display function of the display substrate.

[0089] For example, the display substrate 1 includes a plurality of second switching units disposed on the substrate 100. The second switching units are disposed in the bezel area. Specifically, the second switching unit includes a pixel thin-film transistor 10 and a photosensitive thin-film transistor 20. The pixel thin-film transistor 10 is located in the light-shielding area. The ambient light detection function is realized by the cooperation of the pixel thin-film transistor 10 and the photosensitive thin-film transistor 20.

[0090] In one embodiment, the display substrate can be an organic light-emitting diode (OLED) display panel or a quantum dot light-emitting diode (QLED) display panel.

[0091] For example, the channel 401 of the photosensitive thin-film transistor 20 can be subjected to plasma surface treatment (HPlasma). After plasma surface treatment, the indium gallium zinc oxide (IGNOW) of the photosensitive thin-film transistor 20 increases the number of shallow and deep donor defects (oxygen vacancies). When illuminated, the donor defects release electrons to the conduction band, thus the current of the photosensitive thin-film transistor 20 changes with the illumination. After the second semiconductor sublayer 420 of the photosensitive thin-film transistor is subjected to plasma surface treatment, the current of the photosensitive thin-film transistor changes significantly with illumination, and the photosensitivity is improved.

[0092] For example, the second semiconductor sublayer 420 is made of indium gallium zinc oxide (IGZO), which has a bandgap of approximately 3 eV. By performing plasma surface treatment on the IGZO, shallow donor defects and oxygen vacancies are increased. Due to the limited change in the material bandgap, the Fermi level shifts towards the inverted band. For example, the second semiconductor sublayer 420 of the photosensitive thin-film transistor 20 undergoes plasma surface treatment, resulting in a lower oxygen content in the second semiconductor sublayer 420 compared to the second semiconductor sublayer 420 of the pixel thin-film transistor 10. In other words, the oxygen vacancies in the second semiconductor sublayer 420 of the photosensitive thin-film transistor 20 are increased.

[0093] Reference Figure 2 As shown, in one embodiment, the thickness of the second semiconductor sublayer 420 of the channel 401 of the photosensitive thin-film transistor 20 is h1, and the thickness of the second semiconductor sublayer 420 of the channel 401 of the pixel thin-film transistor 10 is h2, where h1 > h2. The thickness of the second semiconductor sublayer 420 is the dimension of the second semiconductor sublayer 420 in the direction perpendicular to the substrate 100. The thickness of the second semiconductor sublayer 420 of the pixel thin-film transistor 10 can be appropriately reduced by controlling the etching liquid and etching time to reduce light absorption and further improve stability. A thicker second semiconductor sublayer 420 of the channel 401 of the photosensitive thin-film transistor can increase the thickness of the light absorption layer.

[0094] In one embodiment, the thickness of the second semiconductor sublayer 420 of the channel 401 of the photosensitive thin-film transistor 20 is 200 Å to 600 Å, and the thickness of the second semiconductor sublayer 420 is its dimension in the direction perpendicular to the substrate 100. Exemplarily, the thickness of the second semiconductor sublayer 420 of the channel 401 of the photosensitive thin-film transistor 20 is 200 Å, 300 Å, 400 Å, 500 Å, or 600 Å. The specific value of the thickness of the second semiconductor sublayer 420 of the channel 401 of the photosensitive thin-film transistor 20 is not limited here and can be set according to actual application requirements.

[0095] In one embodiment, the thickness of the second semiconductor sublayer 420 of the channel 401 of the pixel thin-film transistor 10 is 100 Å to 400 Å, and the thickness of the second semiconductor sublayer 420 is its dimension in the direction perpendicular to the substrate 100. Exemplarily, the thickness of the second semiconductor sublayer 420 of the channel 401 of the pixel thin-film transistor 10 is 100 Å, 200 Å, 300 Å, or 400 Å. The specific value of the thickness of the second semiconductor sublayer 420 of the channel 401 of the pixel thin-film transistor 10 is not limited here and can be set according to actual usage requirements.

[0096] In one embodiment, the thickness of the second semiconductor sublayer 420 of the channel 401 of the photosensitive thin film transistor 20 is 200 Å to 600 Å, and the thickness of the second semiconductor sublayer 420 of the channel 401 of the pixel thin film transistor 10 is 100 Å to 400 Å. The thickness of the second semiconductor sublayer 420 is the dimension of the second semiconductor sublayer 420 in the direction perpendicular to the substrate 100.

[0097] In one embodiment, the thickness of the first semiconductor sublayer 410 of the channel 401 of the pixel thin-film transistor 10 is equal to the thickness of the first semiconductor sublayer 410 of the channel 401 of the photosensitive thin-film transistor 20. For example, the thickness of the first semiconductor sublayer 410 of the channel of the pixel thin-film transistor 10 and the thickness of the first semiconductor sublayer 410 of the channel of the photosensitive thin-film transistor 20 are 100 angstroms to 400 angstroms. The thickness of the first semiconductor sublayer 410 can be 100 angstroms, 200 angstroms, 300 angstroms, or 400 angstroms. The specific value of the thickness of the first semiconductor sublayer 410 is not limited here and can be set according to actual usage requirements.

[0098] Reference Figure 2 As shown, in one embodiment, the thickness of the second semiconductor sublayer 420 of the channel 401 of the photosensitive thin-film transistor 20 is h1, and the thickness of the first semiconductor sublayer 410 of the channel of the photosensitive thin-film transistor 20 is h3. The thickness of the second semiconductor sublayer 420 is its dimension in the direction perpendicular to the substrate 100, and the thickness of the first semiconductor sublayer 410 is its dimension in the direction perpendicular to the substrate 100. The ratio h1 / (h1+h3) ranges from 50% to 85%. By setting the relationship between the thicknesses of the second semiconductor sublayer 420 and the first semiconductor sublayer 410 of the channel 401 of the photosensitive thin-film transistor 20, the photosensitive thin-film transistor 20 can have better photosensitivity and better ambient light detection performance.

[0099] Reference Figure 2 As shown, in one embodiment, the thickness of the second semiconductor sublayer 420 of the channel 401 of the pixel thin-film transistor 10 is h2, and the thickness of the first semiconductor sublayer 410 of the channel of the pixel thin-film transistor 10 is h3. The thickness of the second semiconductor sublayer 420 is its dimension in the direction perpendicular to the substrate, and the thickness of the first semiconductor sublayer 410 is its dimension in the direction perpendicular to the substrate. The ratio h2 / (h2+h3) ranges from 20% to 80%. By setting the relationship between the thicknesses of the second semiconductor sublayer 420 and the first semiconductor sublayer 410 of the channel of the pixel thin-film transistor 10, the pixel thin-film transistor 10 can avoid damage to the first semiconductor sublayer 410, improve device performance, and also reduce light absorption, thus improving stability.

[0100] Reference Figure 2As shown, in one embodiment, the thickness of the second semiconductor sublayer 420 of the channel 401 of the photosensitive thin film transistor 20 is h1, the thickness of the second semiconductor sublayer 420 of the channel 401 of the pixel thin film transistor 10 is h2, the thickness of the first semiconductor sublayer 410 of the channel of the pixel thin film transistor 10 and the thickness of the first semiconductor sublayer 410 of the channel of the photosensitive thin film transistor 20 are both h3, the ratio of h1 / (h1+h3) ranges from 50% to 85%, and the ratio of h2 / (h2+h3) ranges from 20% to 80%.

[0101] Figure 4a This is a top view of a photosensitive thin-film transistor according to an embodiment of the present disclosure. Figure 1 , refer to Figure 4a As shown, the width W of the channel 401 of the photosensitive thin-film transistor 20 is greater than 10 micrometers.

[0102] For example, the main characterization index of the photosensitive thin-film transistor 20 is its responsivity. The responsivity of the photosensitive thin-film transistor 20 is greater than 0.1 A / W, and the off-state current of the photosensitive thin-film transistor 20 is less than 1E-10, which can reduce noise. The responsivity of the photosensitive thin-film transistor 20 is proportional to the width W of the channel 401 of the photosensitive thin-film transistor 20. In this embodiment, the width W of the channel 401 of the photosensitive thin-film transistor 20 is set to be greater than 10 micrometers, which can ensure the responsivity of the photosensitive thin-film transistor 20.

[0103] Figure 4b This is a top view of a photosensitive thin-film transistor according to an embodiment of the present disclosure. Figure 2 , refer to Figure 4b As shown, the first electrode 510 of the photosensitive thin film transistor 20 includes a plurality of first intercalation portions 511, and the second electrode 520 of the photosensitive thin film transistor 20 includes a plurality of second intercalation portions 521. The first intercalation portions 511 and the second intercalation portions 521 are insulated from each other in the same layer and are nested together.

[0104] The first electrode 510 and the second electrode 520 of the photosensitive thin film transistor 20 in this embodiment are configured as intercalation structures, with the first intercalation portion 511 and the second intercalation portion 521 being insulated in the same layer and nested together. This increases the width of the channel 401 of the photosensitive thin film transistor 20, thereby further improving the responsivity of the photosensitive thin film transistor 20.

[0105] For example, Figure 4b The first electrode 510 of the photosensitive thin film transistor 20 shown includes three spaced-apart first intercalation portions 511, and the second electrode 520 of the photosensitive thin film transistor 20 includes two second intercalation portions 521. The two second intercalation portions 521 are located between adjacent first intercalation portions 511. In this way, the width of the channel 401 of the photosensitive thin film transistor is greatly increased, thereby greatly improving the responsivity of the photosensitive thin film transistor 20.

[0106] Figure 4c This is a top view schematic diagram of a pixel thin-film transistor according to an embodiment of the present disclosure. (Refer to...) Figure 4c As shown, the width of the channel 401 of the pixel thin-film transistor 10 is not limited here and can be set according to actual use.

[0107] Reference Figure 2 As shown, in one embodiment, the display substrate 1 further includes a second insulating layer 30, an organic planarization layer 40, a first electrode layer 50, a third insulating layer 60, and a second electrode layer 70. The second insulating layer 30 is located on the side of the photosensitive thin-film transistor 20 and the pixel thin-film transistor 10 facing away from the substrate 100. The organic planarization layer 40 is located on the side of the second insulating layer facing away from the substrate. The first electrode layer 50 is located on the side of the organic planarization layer 40 facing away from the substrate 100. The third insulating layer 60 is located on the side of the first electrode layer 50 facing away from the substrate 100. The second electrode layer 70 is located on the side of the third insulating layer 60 facing away from the substrate 100, and the second electrode layer 70 is connected to the first electrode 510 of the pixel thin-film transistor 10.

[0108] This disclosure provides a method for fabricating a display substrate. The display substrate 1 includes a display area AA and a border area BB. The method includes: forming a first metal layer 200 on one side of a substrate 100. The first metal layer 200 includes the gate 210 of a photosensitive thin-film transistor 20 and the gate 210 of a pixel thin-film transistor 10. The photosensitive thin-film transistor 20 is located in the border area BB, and the pixel thin-film transistor 10 is located in the display area AA. A first insulating layer 300 is formed on the side of the first metal layer 200 facing away from the substrate 100. An active layer 400 and a second metal layer 500 are formed on the side of the first insulating layer 300 facing away from the substrate 100. The active layer 400 includes a first semiconductor sublayer 410 and a second semiconductor sublayer 420 stacked together. The second semiconductor sublayer 420 is located on the side of the first semiconductor sublayer 410 facing away from the substrate 100. The carrier mobility of the material of the first semiconductor sublayer 410 is greater than that of the material of the second semiconductor sublayer 420. The active layer 400 includes the active layer of the photosensitive thin-film transistor 20 and the active layer of the pixel thin-film transistor 10. The second metal layer 500 is located on the side of the active layer 400 away from the substrate 100, and the second metal layer 500 includes the first electrode 510 and the second electrode 520 of the photosensitive thin-film transistor 20 and the first electrode 510 and the second electrode 520 of the pixel thin-film transistor 10.

[0109] In one embodiment, an active layer 400 and a second metal layer 500 are formed on the side of the first insulating layer 300 facing away from the substrate 100, including:

[0110] A first semiconductor sublayer 410 of a photosensitive thin-film transistor 20 and a first semiconductor sublayer 410 of a pixel thin-film transistor 10 are formed on the side of the first insulating layer 300 facing away from the substrate 100.

[0111] A second semiconductor sub-film of a photosensitive thin-film transistor 20 and a second semiconductor sub-film of a pixel thin-film transistor 10 are formed. The second semiconductor sub-film of the photosensitive thin-film transistor 20 is stacked with the corresponding first semiconductor sub-layer 410, and the second semiconductor sub-film of the pixel thin-film transistor 10 is stacked with the corresponding first semiconductor sub-layer 410.

[0112] A second metal thin film is formed on the side of the second semiconductor sub-film away from the substrate 100. The second metal thin film is etched for the first time to form a first via K1 that penetrates the second metal thin film. The orthogonal projection of the first via K1 on the substrate 100 coincides with the orthogonal projection of the channel 401 of the photosensitive thin film transistor 20 on the substrate 100.

[0113] Plasma surface treatment is performed on the second semiconductor sub-film of the channel 401 of the photosensitive thin film transistor 20 to form the second semiconductor sub-layer 420 of the photosensitive thin film transistor 20.

[0114] A photoresist layer PR is formed on the side of the second metal thin film away from the substrate 100. A second via K2 is formed on the photoresist layer PR. The orthogonal projection of the second via K2 on the substrate 100 coincides with the orthogonal projection of the channel 401 of the pixel thin film transistor 10 on the substrate 100.

[0115] The second metal film at the second via K2 position and the second semiconductor sub-film of the pixel thin film transistor 10 are etched using an etching process. The remaining second semiconductor sub-film forms the second semiconductor sub-layer 420 of the pixel thin film transistor 10, and the second metal film forms the first electrode 510 and the second electrode 520 of the photosensitive thin film transistor 20, as well as the first electrode 510 and the second electrode 520 of the pixel thin film transistor 10.

[0116] In some possible implementations, the treatment gas for plasma surface treatment is hydrogen or ammonia, the treatment power is 800-2000 W / m2, and the treatment time is 2-10 s.

[0117] The following is combined with Figure 2 This disclosure details the fabrication process of the display substrate. It is understood that the term "patterning" as used herein, when referring to an inorganic or metallic material, includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; when referring to an organic material, it includes processes such as mask exposure and development. Evaporation, deposition, coating, and plating as mentioned herein are all mature fabrication processes in related technologies.

[0118] A first metal layer 200 is formed on one side of the substrate 100. The first metal layer 200 includes the gate 210 of a photosensitive thin-film transistor 20 and the gate 210 of a pixel thin-film transistor 10. The photosensitive thin-film transistor 20 is located in the border region BB, and the pixel thin-film transistor 10 is located in the display region AA. Exemplarily, a first metal thin film is deposited on one side of the substrate 100, and the first metal thin film is patterned to form the gate 210 of the photosensitive thin-film transistor 20 and the gate 210 of the pixel thin-film transistor 10, such as... Figure 5a As shown. Figure 5a This is a cross-sectional schematic diagram of the gate and the first insulating layer after they have been formed according to an embodiment of the present disclosure.

[0119] A first insulating layer 300 is formed on the side of the first metal layer 200 facing away from the substrate 100. Exemplarily, a first insulating film can be deposited on the side of the first metal layer 200 facing away from the substrate 100, and the first insulating layer 300 can be formed by patterning. Exemplarily, a silicon nitride insulating film is deposited on the side of the first metal layer 200 facing away from the substrate 100, and a silicon nitride insulating layer 310 is formed by patterning. A silicon oxide insulating film is deposited on the side of the silicon nitride insulating layer 310 facing away from the substrate 100, and a silicon oxide insulating layer 320 is formed by patterning, such as... Figure 5a As shown.

[0120] An active layer 400 is formed on the side of the first insulating layer 300 facing away from the substrate 100. Exemplarily, a first semiconductor thin film can be deposited on the side of the first insulating layer 300 facing away from the substrate 100, and the first semiconductor thin film can be patterned to form the first semiconductor sublayer 410 of the photosensitive thin-film transistor 20 and the first semiconductor sublayer 410 of the pixel thin-film transistor 10, such as... Figure 5b As shown. Figure 5b This is a cross-sectional schematic diagram of the active layer after it has been formed according to an embodiment of this disclosure.

[0121] A second semiconductor film is deposited on the side of the first semiconductor sublayer 410 of the photosensitive thin-film transistor 20 and the first semiconductor sublayer 410 of the pixel thin-film transistor 10 facing away from the substrate 100. The second semiconductor film is patterned to form the second semiconductor sublayer 420' of the photosensitive thin-film transistor 20 and the second semiconductor sublayer 420' of the pixel thin-film transistor 10. The second semiconductor sublayer 420' of the photosensitive thin-film transistor 20 is stacked with the corresponding first semiconductor sublayer 410, and the second semiconductor sublayer 420' of the pixel thin-film transistor 10 is stacked with the corresponding first semiconductor sublayer 410. Figure 5b As shown.

[0122] A second metal thin film 500 is deposited on the side of the second semiconductor sub-film 420' of the photosensitive thin film transistor 20 and the second semiconductor sub-film 420' of the pixel thin film transistor 10 that is away from the substrate 100, such as Figure 5c As shown. Figure 5c This is a schematic diagram showing the deposition of a second metal thin film on a substrate according to an embodiment of this disclosure.

[0123] A first photoresist layer PR1 is deposited on the side of the second metal thin film 500 facing away from the substrate 100. A first etching process is performed on the second metal thin film 500 and the first photoresist layer PR1 to form a first via K1 penetrating the second metal thin film 500. The orthographic projection of the first via K1 onto the substrate 100 coincides with the orthographic projection of the channel 401 of the photosensitive thin-film transistor 20 onto the substrate 100. Figure 5d As shown. Figure 5d This is a schematic diagram of a first via forming through a second metal thin film on a display substrate according to an embodiment of the present disclosure.

[0124] Plasma surface treatment is performed on the second semiconductor sub-film 420' of the channel 401 of the photosensitive thin-film transistor 20 to form the second semiconductor sub-layer 420 of the photosensitive thin-film transistor 20, thereby improving the photosensitivity of the corresponding second semiconductor sub-layer 420 of the photosensitive thin-film transistor 20, such as... Figure 5e As shown. Figure 5e This is a schematic diagram of the second semiconductor sublayer for forming a photosensitive thin-film transistor using plasma surface treatment of the substrate, as shown in an embodiment of this disclosure. The first photoresist layer PR1 is removed, as follows... Figure 5f As shown, Figure 5f This is a schematic diagram of the substrate after the first photoresist layer has been removed, according to an embodiment of this disclosure.

[0125] For example, plasma surface treatment can be performed using a chemical vapor deposition (PEVCD) device, with hydrogen or ammonia as the treatment gas, a treatment power of 800-2000 W / m², and a treatment time of 2-10 s. It should be noted that nitrogen or inert argon can be used to dilute the treatment gas during plasma surface treatment, and the treatment power or time can be increased according to actual treatment needs. Other parameters of plasma surface treatment are not specifically limited and can be set according to actual usage requirements.

[0126] A second photoresist layer PR2 is formed on the side of the second metal thin film 500 facing away from the substrate 100. The second photoresist layer PR2 covers the first via K1. A second via K2 is formed in the second photoresist layer PR2 through an etching process. The second via K2 penetrates the second metal thin film 500. The orthographic projection of the second via K2 onto the substrate 100 coincides with the orthographic projection of the channel 401 of the pixel thin film transistor 10 onto the substrate 100. An etching process is used to etch the second metal thin film 500 at the location of the second via K2 and the second semiconductor sub-film 420' of the pixel thin film transistor 10. The remaining second semiconductor sub-film 420' forms the second semiconductor sub-layer 420 of the pixel thin film transistor 10, as shown below. Figure 5g As shown. Figure 5gThis is a schematic diagram of a second via forming through the second metal thin film on a display substrate according to an embodiment of the present disclosure.

[0127] For example, the second semiconductor sub-film of the pixel thin-film transistor 10 is appropriately thinned by controlling the etching solution and etching time to form the second semiconductor sub-layer 420 of the pixel thin-film transistor 10. A patterned etching process is used to form the first electrode 510 and second electrode 520 of the photosensitive thin-film transistor 20 and the first electrode 510 and second electrode 520 of the pixel thin-film transistor 10 on the second metal thin-film transistor 500. The second photoresist layer is then removed. Figure 5h As shown. Figure 5h This is a schematic diagram of the second semiconductor sublayer on the display substrate in an embodiment of the present disclosure, showing the formation of pixel thin-film transistors.

[0128] A second insulating layer 30 is formed on the side of the photosensitive thin-film transistor 20 and the pixel thin-film transistor 10 facing away from the substrate 100. Exemplarily, a silicon oxide thin film layer is deposited on the side of the active layer 400 and the second metal layer 500 facing away from the substrate 100, and a silicon oxide insulating layer is formed by a patterning process. A silicon nitride thin film layer is deposited on the side of the silicon oxide insulating layer facing away from the substrate 100, and a silicon nitride insulating layer is formed by a patterning process, such as... Figure 2 As shown.

[0129] An organic resin film is deposited on the side of the second insulating layer 30 facing away from the substrate 100, and an organic planarization layer 40 is formed by patterning. A metal film is deposited on the side of the organic planarization layer 40 facing away from the substrate 100, and a first electrode layer 50 is formed by patterning. A silicon nitride or silicon oxide film is deposited on the side of the first electrode layer 50 facing away from the substrate 100, and a third insulating layer 60 is formed by patterning. Vias are etched into the third insulating layer 60. A metal film is deposited on the side of the third insulating layer 60 facing away from the substrate 100, and a second electrode layer 70 is formed by patterning. The second electrode layer 70 is connected to the first electrode 510 of the pixel thin-film transistor 10 through the vias, such as... Figure 2 As shown.

[0130] Another embodiment of this disclosure provides a display device, including a thin-film transistor of any embodiment of this disclosure, or including a display substrate of any embodiment of this disclosure.

[0131] The display device in this disclosure can be any product or component with display and touch functions, such as a smartphone, wearable smartwatch, smart glasses, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, in-vehicle display, e-book, biometric device such as smart skin device, soft robot and biomedical device.

[0132] The thin-film transistor, display substrate, and other components of the display device described above can be derived from various technical solutions known now and in the future to those skilled in the art, and will not be described in detail here.

[0133] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0134] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0135] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0136] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0137] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this disclosure. To simplify this disclosure, the components and arrangements of specific examples have been described above. Of course, these are merely examples and are not intended to limit this disclosure. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0138] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this disclosure, and these should all be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, the display substrate comprising a display area and a border area, characterized in that, include: Pixel thin-film transistors are located in the display area; A photosensitive thin-film transistor is located in the frame region; The pixel thin-film transistor and the photosensitive thin-film transistor each include: a substrate; a first metal layer located on one side of the substrate, the first metal layer including a gate; a first insulating layer located on the side of the first metal layer opposite to the substrate; an active layer located on the side of the first insulating layer opposite to the substrate, the active layer including a first semiconductor sublayer and a second semiconductor sublayer stacked thereon, the second semiconductor sublayer being located on the side of the first semiconductor sublayer opposite to the substrate, the carrier mobility of the first semiconductor sublayer material being greater than the carrier mobility of the second semiconductor sublayer material, the active layer including a channel and a first region and a second region located on both sides of the channel; and a second metal layer located on the side of the active layer opposite to the substrate, the second metal layer including a first electrode and a second electrode, the first electrode and the second electrode being coupled to the first region and the second region, respectively. Wherein, the thickness of the second semiconductor sublayer of the channel of the photosensitive thin film transistor is h1, the thickness of the second semiconductor sublayer of the channel of the pixel thin film transistor is h2, h1>h2, and the thickness of the second semiconductor sublayer is the dimension of the second semiconductor sublayer in the direction perpendicular to the substrate.

2. The display substrate according to claim 1, characterized in that, The thickness of the second semiconductor sublayer of the channel of the photosensitive thin film transistor is 200 Å to 600 Å; and / or, the thickness of the second semiconductor sublayer of the channel of the pixel thin film transistor is 100 Å to 400 Å, the thickness of the second semiconductor sublayer being the dimension of the second semiconductor sublayer in the direction perpendicular to the substrate.

3. The display substrate according to claim 1, characterized in that, The thickness of the second semiconductor sublayer of the channel of the photosensitive thin film transistor is h1, the thickness of the second semiconductor sublayer of the channel of the pixel thin film transistor is h2, the thickness of the first semiconductor sublayer of the channel of the pixel thin film transistor and the thickness of the first semiconductor sublayer of the channel of the photosensitive thin film transistor are both h3, the thickness of the second semiconductor sublayer is the dimension of the second semiconductor sublayer in the direction perpendicular to the substrate, and the thickness of the first semiconductor sublayer is the dimension of the first semiconductor sublayer in the direction perpendicular to the substrate; The ratio of h1 / (h1+h3) ranges from 50% to 85%; and / or the ratio of h2 / (h2+h3) ranges from 20% to 80%.

4. The display substrate according to claim 1, characterized in that, The channel width of the photosensitive thin-film transistor is greater than 10 micrometers.

5. The display substrate according to claim 1, characterized in that, The first electrode of the photosensitive thin-film transistor includes a plurality of first intercalation portions, and the second electrode of the photosensitive thin-film transistor includes a plurality of second intercalation portions. The first intercalation portions and the second intercalation portions are insulated from each other in the same layer and are nested together.

6. The display substrate according to claim 1, characterized in that, The display substrate further includes: The second insulating layer is located on the side of the photosensitive thin-film transistor and the pixel thin-film transistor that is away from the substrate; An organic planarization layer is located on the side of the second insulating layer opposite to the substrate; The first electrode layer is located on the side of the organic planarization layer opposite to the substrate; The third insulating layer is located on the side of the first electrode layer that is away from the substrate; The second electrode layer is located on the side of the third insulating layer opposite to the substrate, and the second electrode layer is connected to the first electrode of the pixel thin film transistor.

7. The display substrate according to claim 1, characterized in that, The material of the first semiconductor sublayer includes an oxide semiconductor, and the material of the second semiconductor sublayer includes an oxide semiconductor.

8. The display substrate according to claim 7, characterized in that, The material of the second semiconductor sublayer includes indium gallium zinc oxide.

9. The display substrate according to claim 1, characterized in that, The thickness of the second semiconductor sublayer located in the channel is 100 angstroms to 400 angstroms, and the thickness of the second semiconductor sublayer is the dimension of the second semiconductor sublayer in the direction perpendicular to the substrate; or... The thickness of the second semiconductor sublayer located in the channel is 200 angstroms to 600 angstroms, and the thickness of the second semiconductor sublayer is the dimension of the second semiconductor sublayer in the direction perpendicular to the substrate.

10. A method for preparing a display substrate, characterized in that, The display substrate includes a display area and a border area, including: A first metal layer is formed on one side of the substrate. The first metal layer includes the gate of a photosensitive thin-film transistor and the gate of a pixel thin-film transistor. The photosensitive thin-film transistor is located in the border area, and the pixel thin-film transistor is located in the display area. A first insulating layer is formed on the side of the first metal layer opposite to the substrate; An active layer and a second metal layer are formed on the side of the first insulating layer away from the substrate. The active layer includes a first semiconductor sublayer and a second semiconductor sublayer stacked together. The second semiconductor sublayer is located on the side of the first semiconductor sublayer away from the substrate. The carrier mobility of the material of the first semiconductor sublayer is greater than that of the material of the second semiconductor sublayer. The active layer includes the active layer of the photosensitive thin film transistor and the active layer of the pixel thin film transistor. The second metal layer is located on the side of the active layer opposite to the substrate, and the second metal layer includes the first and second electrodes of the photosensitive thin film transistor and the first and second electrodes of the pixel thin film transistor.

11. The method for preparing a display substrate according to claim 10, characterized in that, An active layer and a second metal layer are formed on the side of the first insulating layer opposite to the substrate, including: The first semiconductor sublayer of the photosensitive thin-film transistor and the first semiconductor sublayer of the pixel thin-film transistor are formed on the side of the first insulating layer opposite to the substrate; The second semiconductor sub-film of the photosensitive thin film transistor and the second semiconductor sub-film of the pixel thin film transistor are formed, wherein the second semiconductor sub-film of the photosensitive thin film transistor is stacked with the corresponding first semiconductor sub-layer, and the second semiconductor sub-film of the pixel thin film transistor is stacked with the corresponding first semiconductor sub-layer. A second metal thin film is formed on the side of the second semiconductor sub-film away from the substrate. The second metal thin film is etched for the first time to form a first via through the second metal thin film. The orthographic projection of the first via on the substrate coincides with the orthographic projection of the channel of the photosensitive thin film transistor on the substrate. Plasma surface treatment is performed on the second semiconductor sub-film of the channel of the photosensitive thin film transistor to form the second semiconductor sub-layer of the photosensitive thin film transistor; A photoresist layer is formed on the side of the second metal thin film facing away from the substrate, and a second via is formed in the photoresist layer. The orthogonal projection of the second via on the substrate coincides with the orthogonal projection of the channel of the pixel thin film transistor on the substrate. The second metal film at the second via location and the second semiconductor sub-film of the pixel thin film transistor are etched using an etching process. The remaining second semiconductor sub-film forms the second semiconductor sub-layer of the pixel thin film transistor, and the second metal film forms the first and second electrodes of the photosensitive thin film transistor and the first and second electrodes of the pixel thin film transistor.

12. The method for preparing a display substrate according to claim 11, characterized in that, The treatment gas for plasma surface treatment is hydrogen or ammonia, with a treatment power of 800-2000 W / m2 and a treatment time of 2-10s.

13. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 9.

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