Configurable multi-function jammer cancellation device implementation architecture

Abstract

The application provides a configurable multifunctional interference cancellation equipment implementation architecture, belongs to the technical field of electromagnetic compatibility, radio frequency and digital signal processing, and solves the problem of how to configure multifunctional combinable interference cancellation function equipment; the architecture comprises an ARM core, an FPGA core, a multi-path zero intermediate frequency chip, a multi-channel radio frequency link and a radio frequency coupling link connected in sequence, and the FPGA core is further connected with the multi-channel radio frequency link and the radio frequency coupling link; the ARM core is used for system control and parameter calculation, and the FPGA core is used for signal processing; the multi-path zero intermediate frequency chip is used for generating and transmitting radio frequency signals and receiving the radio frequency signals in cooperation with the multi-channel radio frequency link; the radio frequency coupling link is used for coupling and radio frequency modulation of the radio frequency signals; different interference cancellation links are formed through software configuration of the architecture; the application can configure multiple different interference cancellation links on the basis of unified hardware, and therefore can be widely used in multiple scenes requiring interference cancellation function.

Description

Technical Field

[0001] This invention belongs to the fields of electromagnetic compatibility, radio frequency and digital signal processing technology, specifically a configurable multi-functional interference cancellation device implementation architecture. Background Technology

[0002] With the development of information technology, the demand for information interaction is also increasing, leading to a growing number of radio frequency (RF) transceivers installed on the same information platform. Under the constraints of limited platform size and spectrum resources, RF sensors inevitably generate mutual coupling interference through their antennas. When there are few RF sensors, transmission and reception isolation can be achieved through traditional filtering methods; however, when a large number of RF sensors are used simultaneously, especially when their frequency bands are close or overlap, the RF interference problem cannot be eliminated by traditional methods.

[0003] To address this type of radio frequency interference problem, those skilled in the art have proposed interference cancellation solutions based on adaptive filtering technology. After years of research, interference cancellation technology has evolved into various approaches, including radio frequency interference cancellation, digital interference cancellation, and adaptive near-field nulling. These approaches differ in their implementation, but their core principle is to construct appropriate adaptive filters to achieve mutual cancellation of interference signals.

[0004] With the rapid development of integrated circuit technology, software-defined radio (SDR) architecture is being increasingly widely used in the field of radio communication. SDR architecture is software-centric, building a general-purpose radio platform, providing a signal processing framework for algorithm encapsulation, and offering a user interface that allows different functions to be implemented through software control rather than hardware modifications.

[0005] Since various interference cancellation technologies have similar cores, implementing configurable, multi-functional interference cancellation devices from a software-defined radio architecture has become a more reasonable choice. As a result, those skilled in the art have begun to design related architectures, hoping to implement different interference cancellation functions in a software configuration manner, or even combine different interference cancellation functions into a stronger interference cancellation effect. Summary of the Invention

[0006] Based on the current state of the background technology, the purpose of this invention is to provide an interference cancellation device architecture that is multifunctional, highly reusable, and allows for the configuration or combination of various interference cancellation capabilities as needed. The architecture of this invention can be configured with a variety of different interference cancellation links on a unified hardware basis, and therefore can be widely applied in various scenarios that require interference cancellation functions.

[0007] The present invention employs the following technical solutions to achieve its objective:

[0008] A configurable, multi-functional interference cancellation device architecture is disclosed, comprising an ARM core, an FPGA core, a multi-channel zero-IF chip, a multi-channel radio frequency (RF) link, and an RF coupling link connected sequentially. The FPGA core is also connected to the multi-channel RF link and the RF coupling link. The ARM core is used for system control and parameter calculation, and the FPGA core is used for signal processing. The multi-channel zero-IF chip, in conjunction with the multi-channel RF link, is used to generate and transmit RF signals, as well as receive RF signals. The RF coupling link is used for RF signal coupling and RF modulation. Different interference cancellation links are formed by software configuration of each component in the architecture.

[0009] Furthermore, the ARM core is used for interference cancellation link configuration and adaptive filtering calculation;

[0010] The configuration process of the ARM core for the interference cancellation link is as follows: receiving the interference cancellation configuration requirements issued by the control computer, calculating the link construction method of the hardware resources of the multi-functional interference cancellation device; configuring the FPGA core and the multi-channel zero intermediate frequency chip through the high-speed bus, and configuring the multi-channel RF link and the RF coupling link through the serial data line;

[0011] The adaptive filtering calculation process of the ARM core is as follows: initiating sampling of the useful signal and the reference signal, completing the timing synchronization of the useful signal and the reference signal through the autocorrelation algorithm; obtaining the adaptive filtering coefficients through the adaptive filtering algorithm, and sending them to the FPGA core for execution.

[0012] Furthermore, the FPGA core is used for data acquisition and as an adaptive filter; the data acquisition process works with the ARM core to sample the useful signal and the reference signal; the adaptive filter consists of a time delay unit, an FIR filter, and an adder; the FPGA core is used to perform the following processes:

[0013] The FPGA core receives adaptive filtering coefficients from the ARM core, configures a delay in the delay unit, configures adaptive filtering coefficients in the FIR filter, and configures the signal index for addition in the adder. The useful signal and the reference signal pass through the delay unit and the FIR filter, and through the adder, synthesize the canceled signal according to the hardware link configuration, and then output it to the outside.

[0014] Furthermore, the multi-channel zero-IF chip is used to configure frequency and bandwidth parameters under the control of the FPGA core. The specific process is as follows: converting the output baseband signal into a radio frequency signal for transmission, and converting the received radio frequency signal into a baseband signal.

[0015] The multi-channel RF link includes a preamplifier link corresponding to the received RF signal and a power amplifier corresponding to the transmitted RF signal; the multi-channel RF link is used to: amplify the received RF signal and suppress the noise figure of the RF signal; amplify the transmitted RF signal to make it meet the power requirements for RF interference cancellation.

[0016] Furthermore, the radio frequency coupling link is used to: construct an auxiliary receiving channel through coupling during digital interference cancellation, construct an auxiliary transmitting branch during radio frequency interference cancellation, complete the modulation and cancellation of radio frequency signals during radio frequency interference cancellation, and serve as a direct channel for adaptive null traps and digital interference cancellation functions.

[0017] In summary, due to the adoption of this technical solution, the beneficial effects of this invention are as follows:

[0018] The interference cancellation device architecture proposed in this invention can be directly configured as a radio frequency interference cancellation link based on an auxiliary transmit branch, a radio frequency interference cancellation link based on radio frequency amplitude and phase adjustment, a digital interference cancellation link based on an auxiliary receive branch, a digital interference cancellation link based on a baseband signal, and a beam adaptive near-field null interference cancellation link.

[0019] Therefore, the architecture of this invention has the ability to construct multiple interference cancellation links, and different interference cancellation functions can be implemented through specific configurations. These can be combined to form a stronger interference cancellation effect, achieving the characteristics of multi-functionality and high reusability, making it extremely suitable for various scenarios that require interference cancellation. Attached Figure Description

[0020] Figure 1 This is a schematic diagram illustrating the principle of the interference cancellation device implementation architecture of the present invention;

[0021] Figure 2 This is a schematic diagram of the basic unit structure of a multi-channel radio frequency link;

[0022] Figure 3 This is a schematic diagram of the basic safety and power structure of a radio frequency coupling link;

[0023] Figure 4 This is a schematic diagram of a radio frequency interference cancellation link based on an auxiliary transmit branch;

[0024] Figure 5 This is a schematic diagram of a radio frequency interference cancellation link based on radio frequency amplitude and phase adjustment.

[0025] Figure 6 This is a schematic diagram of a digital interference cancellation link based on an auxiliary receiving branch;

[0026] Figure 7 This is a schematic diagram of a digital interference cancellation link based on baseband signals;

[0027] Figure 8 This is a schematic diagram of a beam-adaptive near-field null interference cancellation link. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0029] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0030] Example 1

[0031] A configurable, multi-functional interference cancellation device implementation architecture. Figure 1 The structure and principle of the architecture are illustrated. This architecture includes an ARM core, an FPGA core, multiple zero-IF chips, a multi-channel RF link, and an RF coupling link connected sequentially. The FPGA core is also connected to the multi-channel RF link and the RF coupling link. The ARM core is used for system control and parameter calculation, while the FPGA core is used for signal processing. The multiple zero-IF chips, in conjunction with the multi-channel RF link, are used to generate and transmit RF signals, as well as receive RF signals. The RF coupling link is used for RF signal coupling and modulation. Different interference cancellation links are formed through software configuration of each component in the architecture.

[0032] This embodiment will describe in detail the components of the above architecture. In this embodiment, the number of multiple zero-IF chips and the number of channels in the multi-channel RF link can be adjusted according to actual needs.

[0033] First, the ARM core can implement interference cancellation link configuration and adaptive filtering calculation functions.

[0034] The steps for configuring the interference cancellation link function are as follows:

[0035] (1) Receive interference cancellation configuration requirements issued by the control computer, which may include specific parameters such as the type of interference cancellation applied and the number of links to be configured;

[0036] (2) A link construction method for calculating the hardware resources of a multi-functional interference cancellation device;

[0037] (3) Configure the FPGA core and multiple zero-IF chips through the high-speed bus, and configure the multi-channel RF link and RF coupling link through the serial data line.

[0038] The steps for adaptive filtering calculation are as follows:

[0039] (1) Initiate sampling of the useful signal and the reference signal;

[0040] (2) Timing synchronization between the useful signal and the reference signal is achieved through autocorrelation algorithm;

[0041] (3) Use adaptive filtering algorithms such as recursive least squares or least mean squares algorithm to obtain adaptive filtering coefficients;

[0042] (4) Send the adaptive filtering coefficients to the FPGA core for execution.

[0043] In this embodiment, the FPGA core implements data acquisition and adaptive filtering. The data acquisition function works with the ARM core to sample the useful signal and the reference signal. The adaptive filter consists of a time delay unit, an FIR filter, and an adder, and its functional implementation steps are as follows:

[0044] (1) The FPGA core receives the adaptive filtering coefficients sent by the ARM core, configures the delay in the delay unit, configures the filtering coefficients in the FIR filter, and configures the signal indexes to be added in the adder.

[0045] (2) The useful signal and the reference signal pass through a time delay unit and an FIR filter, and are then combined by an adder according to the hardware link configuration to form a canceled signal before being output to the outside.

[0046] In this embodiment, the multi-channel zero-IF chip is controlled by the FPGA core to configure its frequency, bandwidth, and other related parameters, and its functions are as follows:

[0047] (1) Convert the output baseband signal into a radio frequency signal for transmission;

[0048] (2) Convert the received radio frequency signal into a baseband signal.

[0049] In this embodiment, the multi-channel RF link includes a preamplifier for the received signal and a power amplifier for the transmitted signal, and its function is as follows:

[0050] (1) Amplify the received signal and suppress the noise figure;

[0051] (2) Amplify the transmitted signal to meet the power requirements for radio frequency interference cancellation.

[0052] The basic unit of a multi-channel RF link, such as Figure 2As shown, a multi-functional interference cancellation device may contain basic units of multiple radio frequency links.

[0053] In this embodiment, the function of the radio frequency coupling link includes:

[0054] (1) An auxiliary receiving channel is constructed through coupling during the digital interference cancellation process;

[0055] (2) Constructing an auxiliary transmission branch during the radio frequency interference cancellation process;

[0056] (3) Modulation and cancellation of radio frequency signals are completed during the radio frequency interference cancellation process;

[0057] (4) As a direct channel for adaptive zero trap and digital interference cancellation functions.

[0058] The basic unit of a radio frequency coupling link is as follows Figure 3 As shown, a multifunctional interference cancellation device may contain basic units of multiple radio frequency coupling links.

[0059] Example 2

[0060] Based on Example 1, the architecture of the present invention can achieve different interference cancellation functions through software configuration. This example details five different configuration methods.

[0061] I. Radio Frequency Interference Cancellation Link Based on Auxiliary Transmitter Branch

[0062] like Figure 4 As shown, in this link, the FPGA core collects the transmitted baseband signal and the baseband signal received through the receiving link, calculates the weight of the adaptive filter, and configures it for the auxiliary transmitting branch; after being converted into radio frequency signals by multiple zero-IF chips, it is amplified by an amplifier and then coupled to the receiving channel through a directional coupler to complete the elimination of the transmitted radio frequency signal.

[0063] II. Radio Frequency Interference Cancellation Link Based on Radio Frequency Amplitude and Phase Adjustment

[0064] like Figure 5 As shown, in this link, the FPGA core collects the transmitted baseband signal and the baseband signal received through the receiving link, calculates the weight of the adaptive filter, and configures it to the vector modulator of the RF coupling link. The RF signal coupled from the transmit channel is modulated in amplitude and phase by the vector modulator and then coupled to the receive channel to complete the interference cancellation process.

[0065] III. Digital Interference Cancellation Link Based on Auxiliary Receiver Branch

[0066] like Figure 6As shown, in this link, the radio frequency coupling link couples the transmitted radio frequency signal to the auxiliary receiving channel through a directional coupler, and calculates the adaptive filtering weight together with the received radio frequency signal. The weight is then configured to the adaptive filter in the FPGA core to complete the interference cancellation process. The result is then output to the interfered device for further processing.

[0067] IV. Digital Interference Cancellation Link Based on Baseband Signal

[0068] like Figure 7 As shown, in this link, the FPGA core collects the transmitted baseband signal and the baseband signal received through the receiving link, calculates the weight of the adaptive filter, and configures it to the adaptive filter in the FPGA core to complete the cancellation process of interference signals in the received baseband signal.

[0069] V. Beam Adaptive Near-Field Null Interference Cancellation Link

[0070] like Figure 8 As shown, in this link, the FPGA core collects the transmitted baseband signal and the baseband signal received through the receiving link, calculates the weight of the adaptive filter, and configures it for amplitude and phase modulation operation of the transmitting array, so that the electric field reaching the receiver position when the transmitting array transmits forms a null trap, thus completing the interference cancellation process.

Claims

1. A configurable, multi-functional interference cancellation device implementation architecture, characterized in that: The architecture includes an ARM core, an FPGA core, a multi-channel zero-IF chip, a multi-channel RF link, and an RF coupling link connected in sequence. The FPGA core is also connected to the multi-channel RF link and the RF coupling link. The ARM core is used for system control and parameter calculation, and the FPGA core is used for signal processing. The multi-channel zero-IF chip, in conjunction with the multi-channel RF link, is used to generate and transmit RF signals, as well as to receive RF signals. The RF coupling link is used for RF signal coupling and RF modulation. By configuring the software of each component in the architecture, different interference cancellation links are formed; The ARM core is used for interference cancellation link configuration and adaptive filtering calculation; The configuration process of the ARM core for the interference cancellation link is as follows: receiving the interference cancellation configuration requirements issued by the control computer, calculating the link construction method of the hardware resources of the multi-functional interference cancellation device; configuring the FPGA core and the multi-channel zero intermediate frequency chip through the high-speed bus, and configuring the multi-channel RF link and the RF coupling link through the serial data line; The adaptive filtering calculation process of the ARM core is as follows: initiating sampling of the useful signal and the reference signal, completing the timing synchronization of the useful signal and the reference signal through the autocorrelation algorithm; obtaining the adaptive filtering coefficients through the adaptive filtering algorithm, and sending them to the FPGA core for execution; The radio frequency coupling link is used to: construct an auxiliary receiving channel through coupling during digital interference cancellation, construct an auxiliary transmitting branch during radio frequency interference cancellation, complete the modulation and elimination of radio frequency signals during radio frequency interference cancellation, and serve as a direct channel for adaptive null traps and digital interference cancellation functions.

2. The configurable multi-functional interference cancellation device implementation architecture according to claim 1, characterized in that: The FPGA core is used for data acquisition and as an adaptive filter; the data acquisition process works with the ARM core to sample the useful signal and the reference signal; the adaptive filter consists of a time delay unit, an FIR filter, and an adder; the FPGA core is used to perform the following processes: The FPGA core receives adaptive filtering coefficients from the ARM core, configures a delay in the delay unit, configures adaptive filtering coefficients in the FIR filter, and configures the signal index for addition in the adder. The useful signal and the reference signal pass through the delay unit and the FIR filter, and through the adder, synthesize the canceled signal according to the hardware link configuration, and then output it to the outside.

3. The configurable multi-functional interference cancellation device implementation architecture according to claim 1, characterized in that: The multi-channel zero-IF chip is used to configure frequency and bandwidth parameters under the control of the FPGA core. The specific process is as follows: converting the output baseband signal into a radio frequency signal for transmission, and converting the received radio frequency signal into a baseband signal. The multi-channel RF link includes a preamplifier link corresponding to the received RF signal and a power amplifier corresponding to the transmitted RF signal; the multi-channel RF link is used to: amplify the received RF signal and suppress the noise figure of the RF signal; amplify the transmitted RF signal to make it meet the power requirements for RF interference cancellation.

4. The configurable multi-functional interference cancellation device implementation architecture according to claim 1, characterized in that: By configuring the architecture in software, a radio frequency interference cancellation link based on the auxiliary transmission branch is formed; In this link, the FPGA core collects the transmitted baseband signal and the baseband signal received through the receiving link, calculates the weight of the adaptive filter, and configures it for the auxiliary transmitting branch; after being converted into radio frequency signals by the multi-channel zero intermediate frequency chip, it is amplified by the amplifier and then coupled to the receiving channel through the directional coupler to complete the elimination of the transmitted radio frequency signal.

5. The configurable multi-functional interference cancellation device implementation architecture according to claim 1, characterized in that: By configuring the architecture in software, a radio frequency interference cancellation link based on radio frequency amplitude and phase adjustment is formed; In this link, the FPGA core collects the transmitted baseband signal and the baseband signal received through the receiving link, calculates the weight of the adaptive filter, and configures it to the vector modulator of the RF coupling link. The RF signal coupled from the transmitting channel is modulated in amplitude and phase by the vector modulator and then coupled to the receiving channel to complete the interference cancellation process.

6. The configurable multi-functional interference cancellation device implementation architecture according to claim 1, characterized in that: By configuring the architecture in software, a digital interference cancellation link based on the auxiliary receiving branch is formed; In this link, the radio frequency coupling link couples the transmitted radio frequency signal to the auxiliary receiving channel through a directional coupler, and calculates the adaptive filtering weight together with the received radio frequency signal. The weight is then assigned to the adaptive filter in the FPGA core to complete the interference cancellation process. The result is then output to the interfered device for further processing.

7. The configurable multi-functional interference cancellation device implementation architecture according to claim 1, characterized in that: By configuring the architecture in software, a digital interference cancellation link based on baseband signals is formed; In this link, the FPGA core collects the transmitted baseband signal and the baseband signal received through the receiving link, calculates the weight of the adaptive filter, and configures it to the adaptive filter in the FPGA core to complete the cancellation process of interference signals in the received baseband signal.

8. The configurable multi-functional interference cancellation device implementation architecture according to claim 1, characterized in that: By configuring the architecture in software, a beam-adaptive near-field null interference cancellation link is formed; In this link, the FPGA core collects the transmitted baseband signal and the baseband signal received through the receiving link, calculates the weight of the adaptive filter, and configures it for amplitude and phase modulation operation of the transmitting array, so that the electric field reaching the receiver position when the transmitting array transmits forms a null trap, thus completing the interference cancellation process.

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