Multi-queue organization and scheduling method, system, storage medium and electronic device

Abstract

The application provides a multi-queue organization and scheduling method, system, storage medium and electronic device. The multi-queue organization and scheduling method comprises the following steps: writing data packets into a queue in a URAM memory space based on the state of the queue; and scheduling the queue according to the time difference of the data packets stored in the queue. In the application, a multi-queue organization and scheduling method is provided. Different data packets are sequentially written into a queue according to the queuing requirements, and the queue is selected based on an output control request to meet the scheduling of the multi-queue, so that the complex network queue can be efficiently managed.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of computers, and relates to a multi-queue organization and scheduling method, system, storage medium and electronic device. BACKGROUND

[0002] Multi-queue scheduling can be divided into priority scheduling and non-priority scheduling. Priority scheduling, that is, the order of scheduling needs to be determined according to the priority of each queue; non-priority scheduling, there is no priority between queues, and usually each queue needs to be scheduled fairly to ensure the fairness of scheduling.

[0003] With the development of networks, network queues are becoming more and more complex, and multi-queue scheduling based on complex networks can ensure the fairness of scheduling, but will reduce the efficiency of scheduling and occupy more resources. SUMMARY

[0004] The present application aims to provide a multi-queue organization and scheduling method, system, storage medium and electronic device, to solve the technical problems of low efficiency and complex management of multi-queue organization and scheduling in the prior art under complex networks.

[0005] In a first aspect, the present application provides a multi-queue organization and scheduling method, which comprises: writing a data packet into a queue in a URAM memory space based on the state of the queue; and scheduling the queue according to the time difference of storing the data packet into the queue.

[0006] In an implementation form of the first aspect, the writing of the data packet into the queue in the URAM memory space based on the state of the queue comprises: obtaining a head pointer and a tail pointer of the queue to check the state of the queue; when the state of the queue is empty, writing the current data packet into the queue and updating the head pointer and the tail pointer of the queue; when the state of the queue is not empty and the length of the queued data packet is greater than the available space of the current entry, adding the next entry to the queue and sequentially writing the queued data packet into the queue.

[0007] In an implementation form of the first aspect, before the data packet is written into the queue, it further comprises: obtaining the length of the data packet to determine whether the queue has enough space to store the data packet; when the length of the data packet is greater than the available space of the queue, discarding the data packet; otherwise, writing the data packet into the queue.

[0008] In an implementation form of the first aspect, the available space of the queue comprises: when the queue is a guaranteed queue, the available space is the available space of the entry where the queue is located, the free list FIFO and the free list FIFO remaining entries of the guaranteed queue; when the queue is a non-guaranteed queue, the available space is the available space of the entry where the queue is located and the free list FIFO remaining entries.

[0009] In an implementation form of the first aspect, the scheduling the queue according to the time difference of storing the data packet into the queue comprises: reading the head pointer and the tail pointer of the queue based on the queue number of the current queue; and outputting the data packet in the queue in the first-in first-out order to schedule the queue.

[0010] In an implementation form of the first aspect, the outputting the data packet in the queue in the first-in first-out order comprises: determining the state of the queue according to the number of the queue; when the queue is empty after a conflict and a de-listing, if the de-listing length of the data packet is less than the available length of the queue, updating the head pointer of the queue with the next cell count in the current entry in the queue; otherwise, updating the number of entries from the free list FIFO to the head pointer of the queue, and clearing the cell count in the current entry; when the queue is empty after a de-listing without a conflict or the de-listing length of the data packet is less than the available length of the queue, updating the head pointer of the queue with the next cell count in the current entry in the queue.

[0011] In an implementation form of the first aspect, the length of the entry is 4 KB, and when the de-listing length of the data packet is greater than or equal to the available length in the 4 KB entry or the queue is empty after the data packet exits the queue and the queue has no conflict, the current entry where the queue is located is released and the current entry is written into the free list FIFO or the free list FIFO of the guaranteed queue.

[0012] In a second aspect, the present application provides a multi-queue organization and scheduling system, comprising: a queue management module configured to write a data packet into a queue in a URAM memory space based on the state of the queue; and a traffic management output module configured to schedule the queue according to a time difference of storing the data packet into the queue.

[0013] In a third aspect, the present application provides a computer readable storage medium having a computer program stored thereon, wherein the program, when executed by an electronic device, implements the multi-queue organization and scheduling method of any one of the first aspect.

[0014] In a fourth aspect, the present application provides an electronic device, comprising a processor and a memory; the memory is configured to store a computer program; the processor is configured to execute the computer program stored in the memory, so that the electronic device executes the multi-queue organization and scheduling method according to any one of the first aspect of the present application.

[0015] As described above, the multi-queue organization and scheduling method, system, storage medium and electronic device provided by the present application have the following beneficial effects:

[0016] In the present application, different data packets are stored in queues based on the state of the queues, the queues are divided into guaranteed queues and non-guaranteed queues based on the queue manager, and the data packets are dragged and dropped through shared memory to improve memory space, and the queues are selected based on the output control request to meet the scheduling of multiple queues, thereby realizing efficient management of complex network queues. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 A flowchart of the multi-queue organization and scheduling method according to the embodiment of the present application is shown.

[0018] Figure 2 A flowchart of the data packet writing into the queue according to the embodiment of the present application is shown.

[0019] Figure 3 A flowchart of the multi-queue scheduling according to the embodiment of the present application is shown.

[0020] Figure 4 A flowchart of the signal processing method according to the embodiment of the present application is shown.

[0021] Figure 5 A flowchart of the multi-queue scheduling according to another embodiment of the present application is shown.

[0022] Figure 6 A structural diagram of the multi-queue organization and scheduling system according to the embodiment of the present application is shown.

[0023] Figure 7 An architecture diagram of the multi-queue organization and scheduling according to the embodiment of the present application is shown.

[0024] Figure 8 A structural diagram of the electronic device according to the embodiment of the present application is shown.

[0025] ELEMENT NUMBER EXPLANATION

[0026] 100 multi-queue organization and scheduling system

[0027] 10 queue management module

[0028] 20 flow management output module

[0029] 30 URAM memory space

[0030] 81 processing unit

[0031] 82 memory

[0032] 821 random access memory

[0033] 822 cache memory

[0034] 823 storage system

[0035] 824 programs / utilities

[0036] 8251 program modules

[0037] 83 bus

[0038] 84 input / output interface

[0039] 851 network adapter

[0040] 81 processing unit

[0041] 82 memory

[0042] 821 random access memory

[0043] 822 cache memory

[0044] 823 storage system

[0045] 824 programs / utilities

[0046] 8251 program modules

[0047] 83 bus

[0048] 84 input / output interface

[0049] 85 network adapter

[0050] S1-S2 steps

[0051] S11-S12 steps

[0052] S21-S22 steps

[0053] S221-S222 steps DETAILED DESCRIPTION

[0054] Following make the embodiment of the present application through the specific concrete example, the person skilled in the art can easily understand the other advantages and efficacy of the present application from the disclosure of the present specification. The present application can also be implemented or applied by another different specific embodiment, and the details in the present specification can be variously modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following examples and features in the examples can be combined with each other without conflict.

[0055] It should be noted that the diagrams provided in the following examples only illustrate the basic concept of the present application in a schematic manner, and only the components related to the present application are shown in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component can be a random change in the number, shape and size, and the component layout pattern can be more complex.

[0056] The embodiment of the present application provides a multi-queue organization and scheduling method, system, storage medium and electronic device. Different data packets are stored in queues based on the state of the queues, the queues are divided into guaranteed queues and non-guaranteed queues based on a queue manager, and the queues are selected based on an output control request, so as to realize efficient management of complex network queues.

[0057] In the following, the technical solutions in the embodiments of the present application will be described in detail with reference to the drawings in the embodiments of the present application.

[0058] As Figure 1 described, in an embodiment, the multi-queue organization and scheduling method described in the present application includes the following steps:

[0059] Step S1, write the data packet into the queue in the URAM memory space based on the state of the queue.

[0060] Specifically, the data packet is stored in the packet buffer area, and the packet descriptor of the queue management module corresponding to the data packet is generated based on the queue number of the queue and the length of the data packet. Among them, the queue manager in the queue management module supports 256 queues, that is, the queue number of the queue is from 0 to 255.

[0061] Specifically, in the present embodiment, the internal storage space of the URAM memory space is 2MB, which can configure a maximum of 64 guaranteed queues, wherein the guaranteed buffer size of each guaranteed queue is 16KB. That is, the value range of the guaranteed queue number is 0~64.

[0062] It should be noted that in the URAM memory space, in addition to the guaranteed queue, the remaining memory except the memory occupied by the guaranteed queue is shared by other queues.

[0063] Specifically, the memory of the URAM memory space is composed of 512 entries, each entry has a memory size of 4KB, and each entry is divided into 64B granularity units for writing / reading of the data packets in each queue. That is, the memory of any entry is divided into 64 unit cells with a size of 64B.

[0064] As shown in FIG. 1, in an embodiment, the queue-based state writes the data packet into the queue in the URAM memory space, including the following steps: Figure 2

[0065] Step S11, obtaining the head pointer and the tail pointer of the queue to check the state of the queue.

[0066] Specifically, any of the queues is associated with a head pointer and a tail pointer. As shown in Table 1 below.

[0067] Table 1: Head pointer / tail pointer format of the queue

[0068] bit 15 bit 14:6 bit 5:0 used: all 4KB used ptr: 4KB entry pointer wd_cnt: 64B cell count within 4KB

[0069] Wherein, the {ptr, wd_cnt} in the head pointer points to the first unqueued unit cell in the URAM memory space entry, and the {ptr, wd_cnt} in the tail pointer points to the queued unit cell in the URAM memory space entry. For the head pointer, if the used bit has been set, it indicates that there is no available unit cell in the current entry to read, and for the tail pointer, if the used bit has been set, it indicates that there is no available unit cell in the current entry to use.

[0070] Specifically, when the {used, ptr, wd_cnt} of the head pointer in the queue and the {used, ptr, wd_cnt} of the tail pointer are the same, it indicates that the current queue is empty.

[0071] Step S12, when the state of the queue is empty, the current data packet is written into the queue and the head pointer and the tail pointer of the queue are updated; when the state of the queue is not empty and the length of the queued data packet is greater than the available space of the current entry, the next entry is added to the queue, and the queued data packet is sequentially written into the queue.

[0072] Specifically, when the {used, ptr, wd_cnt} of the head pointer and the {used, ptr, wd_cnt} of the tail pointer are the same, the queue is empty, the ptr of the tail pointer in the current queue points to the entry number when the data packet enters the queue, and the available space of the queue in the current entry is “~wd_cnt+1”.

[0073] ​The head pointer of the queue is updated by {1'd0, new entry number, 6'd0}, and the tail pointer is updated to the new cell count and entry number.

[0074] Specifically, when the state of the queue is empty, the free list FIFO is read to obtain a new entry and store the entry into the queue, and if the packet length is greater than the available space of the obtained new entry, the free list FIFO is read again to continue obtaining an entry.

[0075] Specifically, when the state of the queue is not empty and the length of the queued packet is greater than the available space of the current entry, the linked list is updated, and the next entry is stored into the queue through the linked list.

[0076] Further, when the length of the queued packet is greater than 4 KB plus the available space of the current entry, the free list FIFO is read to obtain a new entry and store the entry into the queue, and the linked list is updated.

[0077] It should be noted that when the packet is written into the queue, if the length of the packet is greater than one 4 KB entry and not greater than two 4 KB entries, the queue will generate two write requests, otherwise, only one write request is generated.

[0078] In an embodiment, before the packet is written into the queue, the length of the packet is obtained to determine whether the queue has enough space to store the packet.

[0079] Specifically, the length of the packet is obtained according to the generated packet descriptor based on the queue management module. When the length of the packet is greater than the available space of the queue, the packet is discarded; otherwise, the packet is written into the queue.

[0080] Specifically, the available space of the queue includes: when the queue is a guaranteed queue, the available space is the available space of the entry where the queue is located, the free list FIFO and the free list FIFO of the guaranteed queue; when the queue is a non-guaranteed queue, the available space is the available space of the entry where the queue is located and the free list FIFO. The space of any of the entries is 4 KB.

[0081] The free list FIFO is the available 4 KB entry number of the shared memory of the guaranteed queue and the non-guaranteed queue, and the shared memory in the URAM memory space is allocated through the free list FIFO.

[0082] In particular, the free list of the guarantee queue uses a read / write pointer to track the available 4KB entries of each guarantee queue, and each guarantee queue can use at most 4 4KB entries. The format of the read / write pointer of the free list of the guarantee queue is shown in Table 2.

[0083] Table 2: Format of the read / write pointer of the free list of the guarantee queue

[0084] bit 2:0 read / write ptr: 4KB entry number

[0085] wherein the number of available 4KB entries of any guarantee queue is equal to 4-(read_ptr-write_ptr).

[0086] In particular, a plurality of entries are stored in the same guarantee queue by a linked list.

[0087] Step S2, scheduling the queue according to the time difference of storing the data packet to the queue.

[0088] In particular, according to the output control request, the queue number corresponding to the output control request is obtained, and the queue is scheduled.

[0089] As shown in Figure 3 the scheduling of the queue according to the time difference of storing the data packet to the queue includes the following steps:

[0090] Step S21, reading the head pointer and the tail pointer of the queue based on the queue number of the current queue.

[0091] In particular, the ptr in the head pointer of the queue refers to the current entry number of dequeuing, and the available read length in the current entry number is "64 minus wd_cnt". If the free list of the queue is updated after the data packet exits the queue, the settings of the head pointer and the tail pointer of the queue are the same, and the queue is empty.

[0092] Step S22, outputting the data packet in the queue in the order of first-in first-out to schedule the queue.

[0093] In particular, the dequeuing of the data packet is performed in the order of writing the data packet to the queue to schedule the queue.

[0094] It should be noted that enqueue is an operation of adding an element to the end of the queue. This means that the newly added element will become the next element to be processed, i.e. the element that enters the queue first will be processed first. Dequeue is an operation of removing an element from the head of the queue and returning its value. When the queue is not empty, the dequeue operation will return the element that was inserted into the queue first.

[0095] In an embodiment, as shown in FIG. 2, a time slot diagram of data packets when enqueueing / dequeueing is shown. Figure 4

[0096] At a frequency of 300 MHz, the rate of data transmission can reach 50 MBps, i.e. it takes 6 cycles to complete the enqueueing / dequeueing of a data packet, i.e. the data packet is processed from global time slot 0 and continues to global time slot 5.

[0097] Specifically, as shown in FIG. 3, when data packet A is enqueued from global time slot 0, data packet B is dequeued from global time slot 0 at the same time. Figure 4

[0098] It should be noted that for data packet A, if it needs to read another free list FIFO, it needs to continue to enqueue the data packet A from global time slot 0, otherwise, a new data packet is enqueued from global time slot 0; similarly, for data packet B, if it needs to read another free list FIFO, it needs to continue to dequeue the data packet B from global time slot 0, otherwise, a new data packet is dequeued.

[0099] As shown in FIG. 4, in an embodiment, the step of outputting the data packets in the queue in order comprises the following steps: Figure 5

[0100] Step S221, judging the state of the queue according to the number of the queue.

[0101] Specifically, if the number of the queue is the same as the number of the queue being written, it is considered that there is a conflict between the queue and the queue being written, otherwise, there is no conflict.

[0102] Step S222, when the queue has a conflict and is empty after being dequeued, if the length of the data packet is less than the available length of the queue, updating the head pointer of the queue with the next cell count in the current entry in the queue; otherwise, updating the number of entries from the free list FIFO to the head pointer of the queue and clearing the cell count in the current entry; when the queue has no conflict and is empty after being dequeued or the length of the data packet is less than the available length of the queue, updating the head pointer of the queue with the next cell count in the current entry in the queue.

[0103] ​​​Specifically, the length of the entry is 4KB, the current entry where the queue is located is released and written into the free list FIFO or the free list FIFO of the guarantee queue when the length of the data packet is greater than or equal to the available length in the 4KB entry when the data packet exits the queue, or the queue is empty and there is no conflict in the queue after the data packet exits the queue.

[0104] In combination Figure 4 and Figure 7 As shown in the figure, before normal data packets are queued into the queue, the data packets are stored in a packet buffer, and a packet descriptor of the data packet is generated, then the data packets are sequentially written into the queue in the URAM memory space based on a write control request, a read control request is made based on an output control instruction, and the queue which needs to be read is obtained based on the read control request, and the data packets are outputted according to the time difference of the data packets stored in the queue.

[0105] Wherein, {Q#, addr, len} represents the number and length of the queue written, and {Q#, len} represents the length of the queue.

[0106] The protection scope of the multi-queue organization and scheduling method described in the embodiments of the present application is not limited to the execution order of the steps listed in the embodiments, and any scheme realized by adding, replacing or deleting steps of the prior art according to the principle of the present application is included in the protection scope of the present application.

[0107] The present application also provides a multi-queue organization and scheduling system, as shown in Figure 6 The multi-queue organization and scheduling system 100 described in the present application comprises:

[0108] A queue management module 10 is configured to write data packets into the queue in the URAM memory space 30 based on the state of the queue; and a traffic management output module 20 is configured to schedule the queue according to the time difference of the data packets stored in the queue.

[0109] Specifically, in an embodiment, as shown in Figure 7 The data packets are stored in a packet buffer before being queued, the queue management module 10 generates a packet descriptor of the data packet based on the number of the queue and the length of the data packet, and writes the data packet into the queue in the URAM memory space 30 based on the state of the queue, and the traffic management output module 20 schedules the queue according to the first-in-first-out order based on an output control instruction.

[0110] It should be noted that the specific working principle of the multi-queue organization and scheduling system of the present application can refer to the above description of the working principle of the multi-queue organization and scheduling method, and therefore will not be repeated here.

[0111] It should be noted that the division of the above modules is only a logical functional division, and all or part of them can be integrated into one physical entity or physically separated in actual implementation. These modules can all be implemented in the form of software called by a processing element; all can be implemented in the form of hardware; or part of the modules can be implemented in the form of software called by a processing element, and part of the modules can be implemented in the form of hardware. For example, the x module can be a separately arranged processing element, or can be integrated in a certain chip of the above device, in addition, it can also be stored in the form of program code in the memory of the above device, and the function of the above x module is called and executed by a certain processing element of the above device. The implementation of other modules is similar. In addition, all or part of these modules can be integrated together or independently implemented. The processing element described herein can be an integrated circuit with signal processing capability. In the implementation process, each step of the above method or each of the above modules can be completed by the integrated logic circuit of the hardware in the processor element or the instructions in the form of software.

[0112] For example, the above modules can be one or more integrated circuits configured to implement the above method, such as one or more application specific integrated circuits (ASICs), or one or more digital signal processors (DSPs), or one or more field programmable gate arrays (FPGAs), etc. For another example, when a certain module above is implemented in the form of program code called by a processing element, the processing element can be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call program code. For another example, these modules can be integrated together to implement in the form of system on a chip (SOC).

[0113] The embodiments of the present application further provide a computer readable storage medium. Those skilled in the art can understand that all or part of the steps of the methods described above can be instructed by a program to complete the processor, and the program can be stored in the computer readable storage medium. The storage medium is a non-transitory medium, for example, random access memory, read only memory, flash memory, hard disk, solid state disk, magnetic tape, floppy disk, optical disc and any combination thereof. The storage medium can be any available medium accessible by a computer or a data storage device such as a server, data center and the like, which includes one or more available media sets. The available medium can be a magnetic medium (for example, floppy disk, hard disk, magnetic tape), an optical medium (for example, digital video disc (DVD)) or a semiconductor medium (for example, solid state disk (SSD)) and the like.

[0114] The embodiments of the present application further provide an electronic device, comprising: a processor and a memory.

[0115] Specifically, the memory is used to store a computer program; the memory includes: ROM, RAM, disk, U disk, memory card or optical disc and various media that can store program codes.

[0116] The processor is used to execute the computer program stored in the memory, so that the electronic device executes the camera abnormality detection method described above.

[0117] Preferably, the processor can be a general processor, including a central processing unit (CPU), a network processor (NP) and the like; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0118] As shown in Figure 8 The sub-device of the present application is in the form of a general computing device. The components of the electronic device can include but are not limited to: one or more processors or processing units 81, memory 82, bus 83 connecting different system components including memory 82 and processing unit 81.

[0119] Bus 83 represents one or more of several possible bus structures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor or local bus using any of a variety of bus structures. Examples of such architectures include, but are not limited to, Industry Standard Architecture (ISA), Micro Channel Architecture (MCA), Enhanced ISA (EISA), Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

[0120] Electronic device typically includes a variety of computer system readable media. Such media can be any available media that is accessible by the electronic device and includes both volatile and non-volatile media, removable and non-removable media.

[0121] Memory 82 can include computer system readable media in the form of volatile memory, such as random access memory (RAM) 821 and / or cache memory 822. Electronic device can further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 823 can be provided for reading from and writing to a non-removable, non-volatile magnetic media (e.g., a "hard drive"). Figure 8 not shown, a magnetic hard disk drive for reading from and writing to non-removable, non-volatile magnetic media (e.g., a "hard drive"). Although not specifically shown, such can Figure 8 In such a case, each drive can be connected to bus 83 by one or more data media interfaces. Memory 82 can include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the application.

[0122] Program / utility 824, having a set (at least one) of program modules 8251, can be stored in memory 82 by way of example, such program modules 8241 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data, each or some combination thereof, can include implementation of a networking environment. Program modules 8251 generally carry out the functions and / or methodologies of embodiments of the application as described herein.

[0123] The electronic device can also communicate with one or more external devices such as a keyboard or a pointing device, displays, etc.; other devices that enable a user to interact with the electronic device; and / or any devices (e.g., network card, modem, etc.) that enable the electronic device to communicate with one or more other computing devices. Such communication can occur via Input / Output (I / O) interface 84. Still yet, the electronic device can communicate with one or more networks, such as a local area network (LAN), a wide area network (WAN), and / or the Internet, through network adapter 85. As Figure 8 illustrated, network adapter 85 communicates with the other components of the electronic device via bus 83. It should be understood that although not shown, other hardware and / or software components could be used in conjunction with the electronic device. These include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc.

[0124] The above-mentioned various figures correspond to the description of the flow or structure, and the part not described in detail in a certain flow or structure can refer to the related description of other flows or structures.

[0125] In summary, the present application stores different data packets into the queue based on the state of the queue, divides the queue into guaranteed queue and non-guaranteed queue based on the queue manager, and drags and drops the data packets through the shared memory to improve the memory space, selects the queue based on the output control request to meet the scheduling of multiple queues, so as to realize the efficient management of complex network queue. Therefore, the present application effectively overcomes the shortcomings in the prior art and has high industrial utilization value.

[0126] The above-mentioned embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought of the present application should be covered by the claims of the present application.

Claims

1. A method of multi-queue organization and scheduling, characterized by, The method comprises: writing the data packet into the queue in the URAM memory space based on the state of the queue; scheduling the queue according to the time difference of the data packet storage to the queue, comprising: reading the head pointer and tail pointer of the queue based on the queue number of the current queue; and outputting the data packet in the queue in the first-in first-out order to schedule the queue; outputting the data packet in the queue in the first-in first-out order comprises: judging the state of the queue according to the number of the queue; when the queue is empty after a conflict and off the list, if the data packet off the list length is less than the available length of the queue, updating the head pointer of the queue with the next cell count in the current entry in the queue; otherwise, updating the entry number from the free list FIFO to the head pointer of the queue, and clearing the cell count in the current entry; when the queue is empty after off the list without conflict or the data packet off the list length is less than the available length of the queue, updating the head pointer of the queue with the next cell count in the current entry in the queue.

2. The method of multi-queue organization and scheduling according to claim 1, characterized in that, The writing of the data packet into the queue in the URAM memory space based on the state of the queue comprises: obtaining the head pointer and tail pointer of the queue to check the state of the queue; when the state of the queue is empty, writing the current data packet into the queue and updating the head pointer and tail pointer of the queue; when the state of the queue is not empty and the length of the queued data packet is greater than the available space of the current entry, adding the next entry to the queue and sequentially writing the queued data packet into the queue.

3. The method of multi-queue organization and scheduling according to claim 2, characterized in that, Before writing the data packet into the queue, it further comprises: obtaining the length of the data packet to determine whether the queue has enough space to store the data packet; when the length of the data packet is greater than the available space of the queue, discarding the data packet; otherwise, writing the data packet into the queue.

4. The method of multi-queue organization and scheduling according to claim 3, characterized in that, The available space of the queue comprises: when the queue is a guaranteed queue, the available space is the available space of the entry where the queue is located, the remaining entries of the free list FIFO of the guaranteed queue and the free list FIFO; when the queue is a non-guaranteed queue, the available space is the available space of the entry where the queue is located and the remaining entries of the free list FIFO.

5. The method of multi-queue organization and scheduling according to claim 1, characterized in that, The length of the entry is 4KB, when the length of the data packet is greater than or equal to the available length in the 4KB entry after the data packet exits the queue, or the queue is empty and the queue has no conflict after the data packet exits the queue, releasing the current entry where the queue is located and writing the current entry into the free list FIFO or the free list FIFO of the guaranteed queue.

6. A multi-queue organization and scheduling system, characterized by, The system comprises: a queue management module for writing a data packet into the queue in the URAM memory space based on the state of the queue; The traffic management output module is configured to schedule the queue according to a time difference of storing the data packet into the queue, including: reading a head pointer and a tail pointer of the queue based on a queue number of the queue; and outputting the data packet in the queue in a first-in first-out order to schedule the queue. The outputting the data packet in the queue in the first-in first-out order includes judging a state of the queue according to the queue number. When the queue is empty after a conflict and a de-queue, if a de-queue length of the data packet is less than an available length of the queue, a head pointer of the queue is updated by a next cell count in a current entry in the queue; otherwise, an entry number from a free list FIFO to the head pointer of the queue is updated, and a cell count in the current entry is cleared. When the queue is empty after a de-queue without a conflict or the de-queue length of the data packet is less than the available length of the queue, the head pointer of the queue is updated by the next cell count in the current entry in the queue.

7. A computer-readable storage medium having stored thereon a computer program, characterized in that, The program is executed by the electronic device to implement the multi-queue organization and scheduling method of any one of claims 1-5.

8. An electronic device, comprising: The electronic device includes a processor and a memory. The memory is configured to store a computer program. The processor is configured to execute the computer program stored in the memory, so that the electronic device executes the multi-queue organization and scheduling method of any one of claims 1-5.

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