A method and device for dynamically combining and transmitting multi-core data in a multi-core chip

Abstract

The present invention belongs to the field of automotive software technology and specifically discloses a method and device for dynamically combining and transmitting multi-core data in a multi-core chip. The method comprises the following steps: receiving data from at least one process within a counting period and accumulating the number of received data groups; comparing the number of groups with a predefined first threshold; if the number of groups is greater than the first threshold, combining the multiple received data groups into an IPCF data sequence; and issuing an interrupt request to the multi-core chip to transmit the IPCF data sequence. The present invention has the advantage of improving CPU operating efficiency and the efficiency of cross-core data transmission.

Description

Technical Field

[0001] The present invention relates to the field of automotive software technology, and in particular to a method and device for dynamically combining and transmitting multi-core data in a multi-core chip. Background Art

[0002] The processors used in automotive electronic control units (ECUs) are becoming increasingly powerful. Chip designers and manufacturers are increasingly introducing multi-core processors, creating a need for inter-core data communication. Furthermore, if multiple cores employ different system architectures, a more complex and efficient inter-core data communication protocol is required to define the communication process.

[0003] Currently, the AUTOmotive Open System ARchitecture (AUTOSAR) is becoming the most mainstream software architecture in the automotive electronics field. This architecture is basically divided into three layers: the application software layer (AppL), the real-time runtime environment (RTE), and the basic software layer (BSW). However, the existing architecture does not specify a protocol for inter-core data communication in multi-core processors. Existing technologies generally use interrupt-triggered methods based on shared memory (Shared Memory) or other high-speed bus protocols for data transmission.

[0004] When using a SharedMemory-based interrupt trigger method to transmit data, relatively high transmission efficiency can be achieved in scenarios with small amounts of data. However, since interrupts require immediate CPU response, when the amount of data is large, the CPU main process will be frequently interrupted, resulting in low CPU operating efficiency.

[0005] In the case of using other high-speed bus protocols to transmit data, the need to perform corresponding conversions between multiple bus protocols may easily lead to the defect of low data transmission efficiency. Summary of the Invention

[0006] The present invention proposes a method and device for dynamically combining and transmitting multi-core data in a multi-core chip, which can improve the operating efficiency of the CPU and the efficiency of data transmission.

[0007] The present invention provides a method for dynamically combining and transmitting multi-core data in a multi-core chip. When a first core sends data to other cores in the multi-core chip, the method comprises the following steps:

[0008] receiving data from at least one process within a counting period and accumulating the number of groups of received data;

[0009] Comparing the number of groups with a predefined first threshold, and if the number of groups is greater than the first threshold, merging the received multiple groups of data into one IPCF data sequence;

[0010] An interrupt request is made to the multi-core chip to send the IPCF data sequence.

[0011] The above method further includes defining a data buffer, where the data buffer is used to store the IPCF data sequence.

[0012] In the above method, the size of the data buffer is at least twice the size of the IPCF data sequence.

[0013] In the above method, for each group of data received, the data is initialized according to the source core ID, destination core ID, destination process direction and CPU data load of the data to obtain a structured data PDU, wherein the CPU data load is positively correlated with the number of groups.

[0014] In the above method, merging the received multiple sets of data into an IPCF data sequence includes:

[0015] Converting each group of the data PDUs into IPCF data suitable for transmission in the IPCF;

[0016] The plurality of IPCF data are sequentially connected to form the IPCF data sequence.

[0017] In the above method, the IPCF data sequence is one-dimensional structured data.

[0018] In the above method, when other cores in the multi-core chip receive the data from the first core, the following steps are included:

[0019] Receiving the IPCF data sequence by interruption;

[0020] Splitting the IPCF data sequence according to the source core ID, the destination core ID, and the destination process direction included in the IPCF data sequence to obtain a plurality of IPCF data;

[0021] Converting the plurality of IPCF data into the data PDU;

[0022] The data PDU is sent to the corresponding process according to the destination core ID and the destination process direction.

[0023] Accordingly, the present invention further proposes a multi-core chip, comprising: a plurality of cores and an IPCF hardware unit, wherein each of the plurality of cores comprises:

[0024] A software sending interface for packaging data from the software into structured data PDUs;

[0025] A software receiving interface, configured to receive structured data PDUs and convert them into a data format suitable for the software;

[0026] An IPCF interface unit receives the data PDUs from the software sending interface and converts a plurality of the data PDUs into an IPCF data sequence, or converts the received IPCF data sequence into a plurality of data PDUs and sends the data PDUs to the software receiving interface;

[0027] The IPCF hardware unit is connected to the IPCF interface units of the multiple cores respectively, and the IPCF data sequence is transmitted between the multiple cores.

[0028] In the above chips,

[0029] The software sending interface includes:

[0030] An application software sending interface, used to package data from the application software into structured data PDUs; and

[0031] Basic software sending interface, used to package data from the basic software into structured data PDUs;

[0032] The software receiving interface includes:

[0033] An application software receiving interface, configured to receive structured data PDUs and convert them into a data format suitable for the corresponding application software; and

[0034] The basic software receiving interface is used to receive structured data PDUs and convert them into a data format suitable for the corresponding basic software;

[0035] The IPCF interface unit receives the data PDU from the basic software sending interface and converts multiple data PDUs into IPCF data sequences, or converts the received IPCF data sequences into multiple data PDUs and sends the data PDUs to the basic software receiving interface.

[0036] The above chip further includes a data buffer, which is used to store the IPCF data sequence.

[0037] Accordingly, the present invention also provides a computer program product, which includes computer instructions. When the computer instructions are executed, the above method is implemented.

[0038] Compared with the prior art, the present invention accumulates the number of groups (or packets) of data that need to be sent from the first core to other cores in a unit of time, and compares the number of groups with a predefined threshold. If the number of groups exceeds the threshold, it is considered that the data is sent frequently and it is not suitable to adopt a solution of sending a group of data in one interrupt. Then the solution is modified to merge multiple groups of data, and the merged data is converted again into a data format supported by IPCF (Inter-Platform Communication Framework) hardware, so that the data in the first core can be sent to other cores through IPCF hardware. Thus, with the support of IPCF hardware driver, a cross-core data transmission protocol based on a predefined threshold (WATERMARK) is realized, and at the same time, it can prevent CPU interrupts from being triggered frequently, effectively utilize the cache (buffer) space of IPCF, and avoid causing excessive CPU data load. At the same time, it complies with the AutoSAR design specifications and can be transplanted in different projects. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a flow chart of a method for dynamically combining and transmitting multi-core data in a multi-core chip according to the present invention;

[0040] Figure 2 It is a block diagram of a multi-core data dynamic combination transmission device in a multi-core chip of the present invention;

[0041] Figure 3 It is a schematic diagram of the hardware structure of an electronic device in the present invention. DETAILED DESCRIPTION

[0042] The following is an explanation of the embodiments of the present invention by specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Although the description of the present invention will be introduced in conjunction with the preferred embodiment, this does not mean that the features of this invention are limited to this embodiment. On the contrary, the purpose of introducing the invention in conjunction with the embodiment is to cover other options or modifications that may be extended based on the claims of the present invention. In order to provide a deep understanding of the present invention, the following description will contain many specific details. The present invention can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of the present invention, some specific details will be omitted in the description. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0043] It should be noted that in this specification, similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures and is defaulted to the same definition.

[0044] It should also be stated that the methods and processes in the present invention are numbered for ease of reference, rather than to limit the order of precedence. If there is a sequence between the steps, the written description shall prevail.

[0045] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0046] As described in the background, AUTOSAR is an existing automotive electronics software standard jointly established by global automakers, component suppliers, and other electronics, semiconductor, and software systems companies. Members maintain a development partnership. Since 2003, these partner companies have worked together to develop an open, standardized software architecture for the automotive industry. The AutoSAR software architecture is primarily divided into three layers: the application software layer (AppL), the real-time runtime environment (RTE), and the basic software layer (BSW). The Inter-Platform Communication Framework (IPCF) is a subsystem that allows applications (including application software and basic software) to run on multiple homogeneous or heterogeneous processing cores, located on the same or different chips, and running different operating systems. However, data exchange between different cores can only be achieved through interrupts based on shared memory or by directly using existing bus protocols. Both approaches suffer from low efficiency.

[0047] The present invention further adds a control protocol based on the shared memory interrupt mode to control the frequency of interrupt generation, thereby reducing the situation where the multi-core CPU is forced to enter the interrupt mode and improving the operating efficiency of the CPU.

[0048] Figure 1 The flowchart of the method for dynamic combination transmission of multi-core data in a multi-core chip of the present invention is shown. Figure 2 This is a block diagram of a multi-core data dynamic combination transmission device in a multi-core chip in the present invention. Figure 1 and Figure 2 The technical solution of the present invention will be described in detail.

[0049] like Figure 2 As shown, a multi-core data dynamic combination transmission device in a multi-core chip includes an application software sending interface 1, an application software receiving interface 2, a basic software sending interface 3, a basic software receiving interface 4, and an IPCF interface unit 5.

[0050] like Figure 1 As shown, when the first core 10 (refer to Figure 2When data is sent from one core to another core (such as the second core 11) in the multi-core chip, the transmission method includes the following steps:

[0051] S11, within the counting period, the application software sending interface 1 and the basic software sending interface 3 receive data from at least one process. For example, the application software sending interface 1 may receive data from the application software 6, or the basic software sending interface 3 may receive data from the basic software 8, or the application software sending interface 1 and the basic software sending interface 3 may receive data from the application software 6 and the basic software 8 respectively, or even more. Synchronously, a counter may also be set in the device to accumulate the number of groups (or packets) of received data when the application software sending interface 1 and the basic software sending interface 3 start working. The counting period may generally be about 1 second. Moreover, the counting period may be calculated by the multi-core data dynamic combination transmission device in the multi-core chip. For example, a cycle counter may be defined to determine the counting period by recording a timestamp. Preferably, the counting period may be selected based on the hardware performance of the multi-core chip. For example, according to the hardware specification of the chip, if the maximum number of interrupts supported per unit time (e.g., second) is M, then the counting period may be set to a multiple of 1 second, and, at the same time, the predefined first threshold may also be set to M or an integer multiple of M accordingly.

[0052] For each group of data received, the application software sending interface 1 and the basic software sending interface 3 can respectively initialize the data according to the source core ID of the data (for example, the ID from the first core 10), the destination core ID (for example, the ID of the second core 11), the destination process direction (for example, the application software 6 in the second core 11) and the CPU data load to obtain a structured data PDU. The CPU data load is the load value of the CPU caused by the inter-core data transmission when the data is initialized. In some embodiments, the CPU data load can be a mapping of the number of data groups to indicate the heavy situation of data transmission. For example, when the number of data groups is 0, the CPU data load is 0; when the number of data groups is M / 2, the CPU data load is 50%; when the number of data groups is M, the CPU data load is 100%. This can be used as a reference value in subsequent steps to assist in evaluating whether the real-time CPU data load is overloaded. Accordingly, a mapping relationship may exist between the predefined first threshold M (this value is used in the subsequent step S12) and the CPU data load. The CPU data load corresponding to the first threshold M is the CPU data load threshold. In some embodiments, the CPU data load may be used as a judgment basis. When the CPU data load exceeds the threshold, the step of merging data needs to be performed. For example, in the previous example, when the CPU data load is greater than or equal to 100%, the step of merging data needs to be performed.

[0053] S12, in some embodiments, the number of groups can be directly compared with a predefined first threshold value without having to be mapped to a CPU data load. If the number of groups is greater than the first threshold value, the received multiple groups of data are merged into an IPCF data sequence. For example, if the predefined first threshold value is M, then when the accumulated number of groups is less than M, the protocol described in the present invention is not triggered, and the technical solution of proposing an interrupt for one group of data in the prior art can continue to be used to transmit data across cores. When the accumulated number of groups is greater than M, the protocol of the present invention is triggered, i.e., multiple groups of data are merged. Specifically, the IPCF interface unit 5 receives the structured data PDUs sent by the application software sending interface 1 and the basic software sending interface 3 respectively, and accumulates the number of these data PDUs. When the number is greater than M, each group of structured data PDUs is converted into IPCF data suitable for transmission in IPCF. In most cases, the data structure of the IPCF data is a one-dimensional structure. For example, it can be converted into a one-dimensional array, and then multiple one-dimensional arrays (IPCF data) are connected to directly form an IPCF data sequence. Because structured data PDUs already include information such as the data source and destination, one-dimensional arrays can be directly concatenated without further packaging. Furthermore, on the receiving end, this information can be used as a segmentation marker to identify the boundary between two data sets, allowing the receiving end to simply and clearly re-split the data.

[0054] S13: Propose an interrupt request to the multi-core chip to send the IPCF data sequence.

[0055] At the second core 11 end, the data sent by the first core 10 is also received in an interrupt manner. After the IPCF interface unit 5 receives the IPCF data sequence from the IPCF hardware unit 9, the unpacking order of the data packet is exactly opposite to the packaging processing process at the first core 10 end. The IPCF interface unit 5 of the second core 11 divides the IPCF data sequence according to the source core ID, destination core ID, and destination process direction included in the IPCF data sequence to obtain multiple IPCF data sequences; then the obtained IPCF data sequence is converted into a data PDU; finally, the data PDU is sent to the corresponding process according to the destination core ID and the destination process direction.

[0056] In addition, the method further includes defining a data buffer (not shown), wherein the data buffer is used to store the IPCF data sequence. In order to prevent data conflicts, the size of the data buffer is at least twice the size of the IPCF data sequence.

[0057] like Figure 2As shown, a multi-core data dynamic combination transmission device in a multi-core chip includes an application software sending interface 1, an application software receiving interface 2, a basic software sending interface 3, a basic software receiving interface 4, and an IPCF interface unit 5. Each core (for example, the first core 10 and the second core 11) includes the above five interfaces as well as application software 6, PduR 7, and basic software 8.

[0058] Application software 6, PduR (PDU Router) 7, and basic software 8 correspond to the three layers of the AutoSAR software architecture: the application software layer (AppL), the real-time runtime environment (RTE), and the basic software layer (BSW), representing the software running in each layer. The multi-core data dynamic combination and transmission device proposed in this invention is connected to PduR 7. As a typical functional module in the RTE, PduR 7 is responsible for accurately directing data from application software 6 and basic software 8 to the target process (i.e., application software 6 and basic software 8 on another core).

[0059] Multiple IPCF interface units 5 can be connected to the IPCF hardware unit 9, and data is transmitted (or received and sent) between the IPCF interface unit 5 and the IPCF hardware unit 9 via a fixed communication method. The specific communication method to be used is determined by the IPCF hardware unit 9. That is, when designing the chip, the IPCF hardware unit 9 is designed to have a certain communication method or communication interface (i.e., what data structure is required to communicate with it), and the IPCF interface unit 5 can select one of them. As mentioned above, the IPCF interface unit 5 usually merges data into a one-dimensional array. The IPCF interface unit 5 and the IPCF hardware unit 9 together serve as communication channels between different cores, and can transmit data between different cores, such as the first core 10 and the second core 11. When transmitting data, the communication protocol used can be determined as described in steps S11-S13 above, depending on the number of groups of data to be transmitted, whether to directly use the existing interrupt method or to use the interrupt method after merging the data. Alternatively, in some embodiments, a method of merging and then interrupting the transmission can be used for all.

[0060] In general, data is sent from the application software 6 and basic software 8 of the first core 10. The PduR 7 of the first core 10 distributes the data to the corresponding interfaces: data sent by the application software 6 is distributed to the application software sending interface 1, and data sent by the basic software 8 is distributed to the basic software sending interface 3. The application software sending interface 1 packages the data from the application software 6 into structured data PDUs, and the basic software sending interface 3 packages the data from the basic software 8 into structured data PDUs. All structured data PDUs are then transmitted to the IPCF interface unit 5. The IPCF interface unit 5 converts the multiple data PDUs into one-dimensional data (IPCF data sequence), forming an IPCF data sequence suitable for transmission within the IPCF hardware unit 9. The IPCF data sequence is then transmitted to the second core 11 through the IPCF interface unit 5 of the first core 10, the IPCF hardware unit 9, and the IPCF interface unit 5 of the second core 11.

[0061] In the second core 11, the IPCF data sequence is converted and split through the reverse process to transmit the data to the predetermined process. Specifically, the IPCF interface unit 5 of the second core 11 reassembles the IPCF data sequence into data PDUs, then transmits the data PDUs to the corresponding application software receiving interface 2 and basic software receiving interface 4 of the second core 11. The application software receiving interface 2 and basic software receiving interface 4 of the second core 11 (data receiver) further split the data PDUs into individual PDUs corresponding to the designated processes and transmit them accordingly.

[0062] In the above embodiment, the frequency of interruptions is determined by a simple counting method. When the interruption frequency is high, the data is merged and multiple data blocks are transmitted in one interruption, which greatly reduces the time spent by the processor to respond to the interruption, improves the operating efficiency of the CPU, and also improves the transmission efficiency of data across cores.

[0063] The embodiment of the method provided by the present invention can be run in a variety of electronic devices, for example, the electronic device can be an onboard computer or an onboard controller. Figure 3 A schematic diagram of the basic hardware structure of the electronic device 100 is given.

[0064] like Figure 3 As shown, the electronic device 100 includes at least a main processor 101 and a storage medium 103. Depending on actual usage requirements, the electronic device 100 may further include a coprocessor 102, an I / O unit 104, a network communication unit 105, and some other expansion units 106. The optional nature of the coprocessor 102, the I / O unit 104, the network communication unit 105, and other expansion units 106 is indicated in the figure by dotted lines.

[0065] The main processor 101 and / or the coprocessor 102 are used to execute computer instructions stored in the storage medium 103 to implement the method proposed in the present invention. The main processor 101 is the control center of the electronic device 100 and is typically a general-purpose processor (e.g., Intel's various series of CPUs) that can perform logical processing and arithmetic calculations in a relatively balanced manner. The main processor 101 uses various interfaces to connect the various parts of the entire electronic device 100. By running or executing software programs stored in the storage medium 103 and calling data stored in the storage medium 103, the main processor 101 implements various functions of the electronic device 100, thereby monitoring the electronic device 100 as a whole.

[0066] The coprocessor 102 is typically a dedicated processor (e.g., a user-programmable embedded microprocessor) that implements a single function. For example, the coprocessor 102 may be a graphics processing unit (GPU) dedicated to processing graphics and images. The main processor 101 does not directly process information related to graphics and images, but instead provides data from other units to the coprocessor 102 or sends management instructions to the coprocessor 102 to instruct the coprocessor 102 to obtain data from other units. After the coprocessor 102 processes the data, the main processor 101 receives the processing results from the coprocessor 102 so that it can subsequently make other decisions based on the processing results. For different professional fields, the coprocessor 102 can also be a signal processor, a network communication processor, a complex computing processor, etc. Typically, the hardware implementation basis of the coprocessor 102 is a digital signal processing (DSP) chip, or a complex programmable logic device (CPLD), a field programmable gate array (FPGA), or other application-specific integrated circuits (ASICs).

[0067] The storage medium 103 may include internal memory and external memory, or may also include volatile memory and non-volatile memory, or may also include magnetic storage devices, solid-state memory, flash memory, floppy disks, and hard disks. The storage medium 103 may be used to store an operating system (e.g., which may be executed by the main processor 101) and data generated during the operation of the operating system, software programs of application software and data generated during the operation of the application software, and software programs of dedicated modules (e.g., which may be executed by a coprocessor 102) and data generated during the operation of the program. For example, in one embodiment of the present invention, the main processor 101 executes various functional applications and data processing by running a monitoring program stored in the storage medium 103. In some embodiments, the storage medium 103 may also be a remote memory (relative to a memory in the conventional sense) remote from the main processor 101. These remote memories may be connected to the main processor 101 or a coprocessor 102 via a network connection (e.g., via a network communication device 105). Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0068] The I / O (Input / Output) unit 104 includes an information input device and an information output device, which enables a user to interact with the electronic device 100. The input device can be used to receive input digital or character information, and can specifically include: a keyboard, a mouse, a joystick, a touch input device, or a trackball. The output device can be used to output / display the processing results processed by the electronic device 100. The processing results can be generated based on the information input by the input device. Specifically, the output device can include: a liquid crystal display (LCD), an organic light-emitting diode (OLED), etc.

[0069] The network communication unit 105 enables communication between the electronic device 100 and various remote devices through a wired / wireless network connection, thereby enabling the electronic device 100 to exchange data with a remote device (e.g., the remote storage device described above). Alternatively, the electronic device 100 can also connect to a server through the network communication unit 105, thereby enabling the electronic device 100 to interact with the server as part of a larger system.

[0070] Other expansion units 106 include a variety of peripheral components and interfaces thereof, so that the electronic device 100 can interact with a variety of devices. For example, through a Bluetooth interface, it can be connected to a Bluetooth headset, so that the audio played by the electronic device 100 can be received by the Bluetooth headset. As another example, through a bus interface (such as an RS-485 bus), the electronic device 100 can be connected to some sensors, so as to obtain some monitoring data to assist the electronic device 100 in implementing specific functions. In various embodiments, other expansion interfaces 106 can exist alone or be integrated with other components of the electronic device 100. At the same time, other expansion interfaces 106 are optional, and their optional properties are represented in the figure with dotted lines.

[0071] The present invention also provides a computer-readable storage medium having instructions stored therein. When the instructions are executed, the computer is caused to execute the method described above.

[0072] The present invention also provides a computer program product, which includes computer instructions. When the computer instructions are executed, the computer is enabled to perform the method described above.

[0073] In the description provided herein, numerous specific details are described. However, it is understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0074] Similarly, it should be understood that in order to streamline the present invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the claims, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Accordingly, the claims that follow the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the present invention.

[0075] Those skilled in the art will appreciate that the modules in the devices of the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and further may be divided into a plurality of submodules or subunits or subcomponents. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device so disclosed may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0076] Furthermore, those skilled in the art will appreciate that although some embodiments described herein include certain features included in other embodiments but not other features, combinations of features from different embodiments are intended to be within the scope of the present invention and to form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.

Claims

1. A method for dynamically combining and transmitting multi-core data in a multi-core chip, the multi-core chip comprising: The first core and the second core are characterized in that when the first core sends data to the second core in a shared memory manner, the method includes the following steps: receiving a plurality of groups of data from at least one process within a counting period, and accumulating the number of groups of received data, wherein the accumulated number of groups is used to calculate the frequency of interruption; Comparing the number of groups with a predefined first threshold, wherein the predefined first threshold corresponds to a threshold of CPU data load; If the number of groups is less than the first threshold, the multiple groups of data are sent to other cores respectively in a manner of interrupting one group of data at a time; If the number of groups is greater than the first threshold, it is considered that the data is sent frequently and it is not suitable to adopt the solution of sending one group of data in one interrupt, so the received multiple groups of data are merged into one IPCF data sequence, and the IPCF data sequence is sent to other cores in a one-time interrupt manner; The received multiple sets of data are merged into an IPCF data sequence, including: The data PDUs are respectively converted into IPCF data suitable for transmission in the IPCF, and a plurality of the IPCF data are sequentially connected to form the IPCF data sequence.

2. The method according to claim 1, wherein It also includes defining a data buffer, where the data buffer is used to store the IPCF data sequence.

3. The method according to claim 2, wherein The size of the data buffer is at least twice the size of the IPCF data sequence.

4. The method according to claim 1, wherein For each group of the data received, the data is initialized according to the source core ID, destination core ID, destination process direction and CPU data load of the data to obtain a structured data PDU, wherein the CPU data load is positively correlated with the number of groups.

5. The method according to claim 1, wherein The IPCF data sequence is one-dimensional data.

6. The method according to claim 1, wherein When other cores in the multi-core chip receive the data from the first core, the following steps are included: Receiving the IPCF data sequence by interruption; Splitting the IPCF data sequence according to the source core ID, the destination core ID, and the destination process direction included in the IPCF data sequence to obtain a plurality of IPCF data; Converting the plurality of IPCF data into the data PDU; The data PDU is sent to the corresponding process according to the destination core ID and the destination process direction.

7. A multi-core chip, comprising: Multiple cores and an IPCF hardware unit, wherein each of the multiple cores includes: A software sending interface for packaging data from the software into structured data PDUs; A software receiving interface, configured to receive structured data PDUs and convert them into a data format suitable for the software; The IPCF interface unit receives the data PDU from the software sending interface and converts multiple data PDUs into an IPCF data sequence, or converts the received IPCF data sequence into multiple data PDUs and sends the data PDUs to the software receiving interface, wherein when the first core sends data to the second core in a shared memory manner, the IPCF interface unit: receiving a plurality of groups of data from at least one process within a counting period, and accumulating the number of groups of received data, wherein the accumulated number of groups is used to calculate the frequency of interruption; Comparing the number of groups with a predefined first threshold, wherein the predefined first threshold corresponds to a threshold of CPU data load; If the number of groups is less than the first threshold, the multiple groups of data are sent to other cores respectively in a manner of interrupting one group of data at a time; If the number of groups is greater than the first threshold, it is considered that the data is sent frequently and it is not suitable to adopt the solution of sending one group of data in one interrupt, so the received multiple groups of data are merged into one IPCF data sequence, and the IPCF data sequence is sent to other cores in a one-time interrupt manner; The received multiple sets of data are merged into an IPCF data sequence, including: Converting the data PDUs into IPCF data suitable for transmission in the IPCF, and sequentially connecting a plurality of the IPCF data to form the IPCF data sequence; The IPCF hardware unit is connected to the IPCF interface units of the multiple cores respectively, and the IPCF data sequence is transmitted between the multiple cores.

8. The chip according to claim 7, wherein: The software sending interface includes: An application software sending interface, used to package data from the application software into structured data PDUs; and Basic software sending interface, used to package data from the basic software into structured data PDUs; The software receiving interface includes: An application software receiving interface, configured to receive structured data PDUs and convert them into a data format suitable for the corresponding application software; and The basic software receiving interface is used to receive structured data PDUs and convert them into a data format suitable for the corresponding basic software; The IPCF interface unit receives the data PDU from the basic software sending interface and converts multiple data PDUs into IPCF data sequences, or converts the received IPCF data sequences into multiple data PDUs and sends the data PDUs to the basic software receiving interface.

9. The chip according to claim 7, wherein: The chip further includes a data buffer, which is used to store the IPCF data sequence.

10. A computer program product, characterized in that The computer program product comprises computer instructions, and when the computer instructions are executed, the method according to any one of claims 1 to 6 is implemented.

Images