Pixel driving method, pixel driving circuit and display device

Abstract

The present disclosure provides a pixel driving method and circuit, and a display device. The pixel driving method comprises: receiving image data; determining a data voltage signal for a target pixel based on pixel data for the target pixel in the image data; in response to a first enable signal being active, driving the target pixel in a first display mode, in the first display mode, the data voltage signal is updated at a first frequency, and the data voltage signal is provided for the target pixel, so that a driving voltage of the target pixel is determined as a voltage difference between the data voltage signal and a common voltage signal; in response to a second enable signal being active, driving the target pixel in a second display mode, in the second display mode, the data voltage signal is updated at a second frequency, and the data voltage signal is adjusted according to the pixel data for the target pixel, so that the driving voltage of the target pixel is determined as a maximum driving voltage or a minimum driving voltage, and the second frequency is lower than the first frequency.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a pixel driving method, a pixel driving circuit, and a display device. Background Technology

[0002] For battery-powered computing devices such as wearables, mobile phones, and tablets, battery life typically requires charging or replacement. Therefore, there is usually a need to reduce power consumption and extend battery life for these devices. Wearable devices, such as smartwatches, are particularly vulnerable due to their small size, making it difficult to accommodate large-capacity batteries. Consequently, power consumption control is often a more pressing issue for these devices. Summary of the Invention

[0003] In view of this, the present disclosure provides a pixel driving method, a pixel driving circuit, a display device, and a computing device that can alleviate, reduce, or even eliminate the above-mentioned problems.

[0004] According to one aspect of this disclosure, a pixel driving method is provided, comprising: receiving image data, the image data including pixel data for at least one pixel; determining a data voltage signal for a target pixel based on the pixel data for a target pixel in the image data; driving the target pixel in a first display mode in response to a first enable signal being active, wherein in the first display mode, the data voltage signal is updated at a first frequency and a data voltage signal is provided to the target pixel, such that the driving voltage of the target pixel is determined as the voltage difference between the data voltage signal and a common voltage signal, wherein the common voltage signal is a reference voltage signal shared by all pixels; driving the target pixel in a second display mode in response to a second enable signal being active, wherein in the second display mode, the data voltage signal is updated at a second frequency, the data voltage signal is adjusted according to the pixel data for the target pixel, and an adjusted data voltage signal is provided to the target pixel, such that the driving voltage of the target pixel is determined as a maximum driving voltage or a minimum driving voltage, wherein the second frequency is lower than the first frequency.

[0005] In some embodiments, the pixel data for the target pixel includes at least one valid data bit, and wherein adjusting the data voltage signal according to the pixel data for the target pixel and providing the adjusted data voltage signal to the target pixel such that the driving voltage of the target pixel is determined to be a maximum driving voltage or a minimum driving voltage includes: adjusting the data voltage signal in response to the highest valid data bit among the at least one valid data bit being a first value, such that the driving voltage of the target pixel is determined to be a maximum driving voltage; and adjusting the data voltage signal in response to the highest valid data bit among the at least one valid data bit being a second value, such that the driving voltage of the target pixel is determined to be a minimum driving voltage.

[0006] In some embodiments, adjusting the data voltage signal such that the driving voltage of the target pixel is determined to be the maximum driving voltage includes: during the initialization period, determining the data voltage signal as a first voltage signal and sequentially providing an effective initialization control signal to each pixel; during the display period, determining the data voltage signal to be opposite to the common voltage signal and providing a continuously effective display control signal to the target pixel, such that the driving voltage of the target pixel is determined to be the voltage difference between the data voltage signal and the common voltage signal.

[0007] In some embodiments, adjusting the data voltage signal such that the driving voltage of the target pixel is determined to be the minimum driving voltage includes: during the initialization period, determining the data voltage signal as the second voltage signal and sequentially providing an effective initialization control signal to each pixel; during the display period, providing a zero-difference voltage signal to the target pixel, the zero-difference voltage signal being the same as the common voltage signal, and providing a continuously effective display control signal to the target pixel such that the driving voltage of the target pixel is determined to be the voltage difference between the zero-difference voltage signal and the common voltage signal.

[0008] In some embodiments, determining a data voltage signal for a target pixel based on pixel data for a target pixel in image data includes: buffering pixel data for a preset number of pixels in image data; and converting the buffered pixel data for the target pixel into a data voltage signal for the target pixel according to a preset digital-to-analog conversion rule.

[0009] In some embodiments, caching image data includes: in response to the number of valid data bits in pixel data for a preset number of pixels being greater than a first threshold, compressing the pixel data for the preset number of pixels according to a preset compression rule, such that the number of valid data bits in the compressed pixel data is not greater than the first threshold.

[0010] In some embodiments, converting the pixel data for the target pixel in the cached pixel data into a data voltage signal for the target pixel includes: decompressing the compressed pixel data; and converting the pixel data for the target pixel in the decompressed pixel data into a data voltage signal for the target pixel.

[0011] In one embodiment, caching image data includes: in response to the number of valid data bits in pixel data for a preset number of pixels being less than a first threshold, padding the pixel data for the preset number of pixels according to a first preset padding rule, such that the number of valid data bits in the padded image data is equal to the first threshold.

[0012] In some embodiments, converting the pixel data for the target pixel in the cached pixel data into a data voltage signal for the target pixel includes: in response to the number of valid data bits in the pixel data for the target pixel electrode being less than a second threshold, padding the image data for the target pixel electrode according to a second preset padding rule, such that the number of valid data bits in the padded pixel data is equal to the second threshold.

[0013] In some embodiments, converting the pixel data for a target pixel in the cached pixel data into a data voltage signal for the target pixel further includes: in response to receiving pixel data for at least two pixels per clock cycle, reallocating the pixel data for at least two pixels into at least two sets of pixel data for different pixels.

[0014] In some embodiments, the image processing method further includes: in a first display mode, in response to receiving an instruction to switch to a second display mode, writing enable data for the second display mode into a mode register, and after a first preset time interval, enabling a second enable signal based on the enable data in the mode register.

[0015] In some embodiments, the image processing method further includes: in a second display mode, in response to receiving new image data, activating a data voltage buffer; writing a data voltage signal determined based on the new image data into the data voltage buffer; and after a second preset time interval, deactivating the data voltage buffer.

[0016] In some embodiments, the image processing method further includes: in a second display mode, in response to receiving an instruction to switch to a first display mode, writing enable data for the first display mode to a mode register and enabling a data voltage buffer; writing a data voltage signal to the data voltage buffer; after a third preset time interval, disabling the data voltage buffer; and enabling a first enable signal based on the enable data in the mode register.

[0017] In some embodiments, the image processing method further includes: in a first display mode, when the number of valid data bits in the pixel data for the target pixel meets a first preset condition, in response to receiving an enable signal for a low-quality display mode, using a low-quality display mode, wherein in the low-quality display mode, in response to the highest valid data bit in the pixel data for the target pixel being a first value, the pixel data for the target pixel is set to a maximum value, and in response to the highest valid data bit in the pixel data for the target pixel being a second value, the pixel data for the target pixel is set to a minimum value.

[0018] In some embodiments, the image processing method further includes: in a first display mode, when the number of valid data bits in the pixel data for the target pixel meets a second preset condition, making a second enable signal valid before the screen is turned on.

[0019] In some embodiments, the image processing method further includes: in a first display mode, when the number of valid data bits in the pixel data for the target pixel meets a third preset condition, adjusting the data voltage signal for the target pixel according to a preset binding point voltage, wherein the preset binding point voltage is used to specify the data voltage signal corresponding to at least one gray level.

[0020] In some embodiments, receiving image data includes: receiving initialization image data after the device is powered on and initialized, and before the screen is turned on, and determining an initialization voltage signal for each pixel based on the initialization image data.

[0021] In some embodiments, receiving image data includes: selecting a first interface or a second interface to receive image data based on a preset interface rule, according to the display mode and / or the number of valid data bits in the pixel data, wherein the first interface and the second interface have different data transmission rates.

[0022] According to another aspect of this disclosure, a pixel driving circuit is provided, comprising: a data interface configured to: receive image data, the image data including pixel data for at least one pixel; a data processing circuit configured to: determine a data voltage signal for a target pixel based on the pixel data for a target pixel in the image data; and a pixel electrode driving circuit including a first charging circuit and a second charging circuit, wherein the first charging circuit is configured to: drive the target pixel in a first display mode in response to a first enable signal being active, update the data voltage signal at a first frequency in the first display mode, and provide the data voltage signal to the target pixel such that the driving voltage of the target pixel is determined as the voltage difference between the data voltage signal and a common voltage signal, wherein the common voltage signal is a reference voltage signal shared by all pixels; and wherein the second charging circuit is configured to: drive the target pixel in a second display mode in response to a second enable signal being active, update the data voltage signal at a second frequency in the second display mode, adjust the data voltage signal according to the pixel data for the target pixel, and provide the adjusted data voltage signal to the target pixel such that the driving voltage of the target pixel is determined as a maximum driving voltage or a minimum driving voltage, wherein the second frequency is lower than the first frequency.

[0023] In some embodiments, the pixel data for the target pixel includes at least one valid data bit, and wherein the second charging circuit includes: a latch configured to latch the most valid data bit among the at least one valid data bit; and a mode selection circuit configured to: adjust a data voltage signal in response to the most valid data bit among the at least one valid data bit being a first value, such that the driving voltage of the target pixel is determined to be a maximum driving voltage, and adjust the data voltage signal in response to the most valid data bit among the at least one valid data bit being a second value, such that the driving voltage of the target pixel is determined to be a minimum driving voltage.

[0024] In some embodiments, the data processing circuit includes: a buffer circuit configured to buffer pixel data for a preset number of pixels in image data; and a digital-to-analog converter circuit configured to convert the buffered pixel data for a target pixel into a data voltage signal for the target pixel.

[0025] In some embodiments, the pixel driving circuit further includes a data voltage buffer configured to buffer the data voltage signal in a second display mode.

[0026] According to another aspect of this disclosure, a display device is provided, including a pixel driving circuit as described in the foregoing aspect; a liquid crystal panel including a plurality of pixels and configured to receive a data voltage signal from the pixel driving circuit; and a backlight panel configured to provide backlight for the liquid crystal panel.

[0027] These and other aspects of this disclosure will be apparent from the embodiments described below, and will be elucidated with reference to the embodiments described below. Attached Figure Description

[0028] Further details, features, and advantages of this disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0029] Figure 1 An example flowchart of a pixel-driving method according to some embodiments of the present disclosure is illustrated schematically;

[0030] Figure 2 An example circuit diagram of a pixel circuit according to some embodiments of the present disclosure is illustrated schematically;

[0031] Figure 3A and 3B The schematic illustration shows the operating state of a pixel circuit according to some embodiments of the present disclosure in a first display mode;

[0032] Figure 4A , 4B4C and 4D schematically illustrate the operating state of pixel circuitry according to some embodiments of the present disclosure in a second display mode;

[0033] Figure 5A and 5B An example driving timing diagram for driving pixel circuitry according to some embodiments of the present disclosure is illustrated schematically;

[0034] Figure 6 An example circuit diagram of a pixel charging circuit for charging a pixel circuit according to some embodiments of the present disclosure is shown schematically;

[0035] Figure 7A , 7B 7C, 7D, and 7E schematically illustrate a transmission protocol for example data formats of image data according to some embodiments of the present disclosure;

[0036] Figure 8A , 8B 8C and 8D schematically illustrate example processing flows for various data formats according to some embodiments of the present disclosure;

[0037] Figure 9A , 9B 9C schematically illustrates an example flowchart of mode switching or image data updating according to some embodiments of the present disclosure;

[0038] Figure 10 An exemplary internal mode switching diagram of a pixel driving circuit according to some embodiments of the present disclosure is illustrated schematically;

[0039] Figure 11 This illustration schematically depicts an exemplary data processing flow in conjunction with Idle mode according to some embodiments of the present disclosure;

[0040] Figure 12 An example flowchart illustrating a display process according to some embodiments of the present disclosure is shown schematically;

[0041] Figure 13 An example flowchart illustrating a display process according to some embodiments of the present disclosure is shown schematically;

[0042] Figure 14 An exemplary internal mode switching diagram of a mating interface according to some embodiments of the present disclosure is illustrated schematically;

[0043] Figure 15 An example table illustrating recommended interface configurations according to some embodiments of this disclosure is shown schematically;

[0044] Figure 16 An example block diagram of a pixel driving circuit according to some embodiments of the present disclosure is shown schematically;

[0045] Figure 17A An exemplary block diagram of a display device according to some embodiments of the present disclosure is shown schematically;

[0046] Figure 17B A schematic diagram of a display device according to some embodiments of the present disclosure is shown as an example;

[0047] Figure 18 An example block diagram of a computing device according to some embodiments of the present disclosure is illustrated schematically. Detailed Implementation

[0048] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the described embodiments are merely a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments described in this disclosure without creative effort are within the scope of protection of this disclosure. Those skilled in the art will understand that the embodiments described below are intended to explain this disclosure and should not be considered as limitations on this disclosure. Unless otherwise specified, where specific technologies or conditions are not explicitly described in the following embodiments, those skilled in the art can understand them according to commonly used technologies or conditions in the art or according to the product manual.

[0049] In the description of this specification, references to terms such as "one embodiment," "another embodiment," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples, without contradiction. Additionally, it should be noted that in this specification, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0050] As those skilled in the art will understand, although the steps of the methods in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order unless the context clearly indicates otherwise. Additional or alternatively, multiple steps may be combined into a single step, and / or a single step may be broken down into multiple steps. Furthermore, other method steps may be inserted between steps. Inserted steps may represent improvements to the method described herein, or may be unrelated to the method. Moreover, a given step may not be fully completed before the next step begins.

[0051] Figure 1 An example flowchart of a pixel driving method 100 according to some embodiments of the present disclosure is illustrated schematically. Figure 1 As shown, the pixel driving method 100 may include steps 110 to 140. Exemplarily, the pixel driving method 100 may be executed by a computing device including a display screen, for example, by a driving device in the computing device for driving the display screen. The driving device may be embodied as a circuit structure independent of or integrated with other devices, and may or may not have a separate package structure. For example, the driving device may be implemented as a structure such as a driver IC (Integrated Circuit). Generally, the driving device may be used to receive image data from a system end and provide driving signals to some or all pixels in the display screen based on the image data to display the corresponding image. The system end may refer to devices such as a central control unit (CPU), a microcontroller (MCU), or a dedicated graphics processing unit (GPU), which may transmit image data to the driving device according to a preset data format and corresponding transmission protocol based on stored images, received images, or generated images. See below for reference. Figure 1 Steps 110 to 140 are explained in detail.

[0052] In step 110, image data is received. The image data may include pixel data for at least one pixel. Exemplarily, the image data may be provided by a controller, central processing unit, or graphics processor in a computing device, for example, via a data bus or other type of transmission line to the pixel driving device. The image data may be data conforming to a preset data protocol format, and may include pixel data for individual pixels or portions of pixels in the display screen. Exemplarily, multiple sets of image data may be received at a preset frequency, wherein each set of image data may represent a frame in a video.

[0053] In step 120, a data voltage signal for the target pixel can be determined based on the pixel data for the target pixel in the image data. Pixel data for a pixel may include the pixel value of that pixel. For example, for a monochrome image, the pixel data may reflect the grayscale of the pixel; for a color image, the pixel data may reflect the brightness corresponding to the R (red), G (green), and B (blue) values ​​of the pixel, respectively. Exemplarily, a conversion relationship between pixel data and the data voltage signal can be preset. This conversion relationship can be expressed in various ways, such as through lookup tables, curves, or function expressions, so that the corresponding data voltage signal can be determined based on the pixel data according to the conversion relationship. Optionally, before determining the data voltage signal according to the preset conversion relationship, the pixel data can be processed as needed to meet different requirements for data transmission, data storage, data processing, and display effects. Such embodiments will be described in detail below.

[0054] In step 130, in response to the first enable signal being active, the target pixel can be driven in a first display mode. In the first display mode, the data voltage signal can be updated at a first frequency, and a data voltage signal can be provided to the target pixel, such that the driving voltage of the target pixel is determined as the voltage difference between the data voltage signal and a common voltage signal, wherein the common voltage signal is a reference voltage signal shared by all pixels. Generally, the pixel circuitry of each pixel may include a storage capacitor, one end of which can be connected to the common voltage signal and the other end of which can be connected to the data voltage signal. The voltage difference between the two can charge the storage capacitor, thereby enabling the pixel to display a corresponding brightness. Here, "connection" should be understood to encompass both direct and indirect connections; that is, the storage capacitor can be directly connected to the common voltage signal and the data voltage signal, or it can be connected to one or both of these signals through other intermediate circuit elements. In other statements of this disclosure, unless otherwise indicated, the term "connection" should also be understood in a similar manner.

[0055] Furthermore, by way of example, the update frequency of the data voltage signal can be controlled by the pixel driving circuit, or it can depend on the frequency of the image data received by the pixel driving circuit.

[0056] In step 140, in response to the second enable signal being active, the target pixel can be driven in a second display mode. In the second display mode, the data voltage signal can be updated at a second frequency, the data voltage signal is adjusted according to the pixel data for the target pixel, and the adjusted data voltage signal is provided to the target pixel, such that the driving voltage of the target pixel is determined to be either the maximum driving voltage or the minimum driving voltage, wherein the second frequency is lower than the first frequency. For example, the data voltage signal can be adjusted based on some or all of the valid bits in the pixel data for the target pixel, such that the difference between the adjusted data voltage signal and the common voltage signal is at its maximum or minimum value. Thus, when charging the storage capacitor in the pixel using the adjusted data voltage signal and the common voltage signal, a maximum or minimum driving voltage can be obtained. Alternatively, the data voltage signal can be adjusted based on some or all of the valid bits in the pixel data for the target pixel, such that the difference between the adjusted data voltage signal and the common voltage signal (and the zero-difference voltage signal) is at its maximum value. Thus, when charging the storage capacitor in the pixel using the adjusted data voltage signal and the common voltage signal, a maximum driving voltage can be obtained, while when charging the storage capacitor in the pixel using the zero-difference voltage signal and the common voltage signal, a minimum driving voltage can be obtained; and so on. For example, the minimum driving voltage can be zero. Therefore, in the second display mode, the pixel brightness can be at its highest or lowest. Optionally, depending on the pixel's control mode, when driving the pixel with zero voltage, the pixel brightness can be at its highest or lowest. For example, in normally black mode, the pixel brightness can be at its lowest when driven with zero voltage; in normally white mode, the pixel brightness can be at its highest when driven with zero voltage. This can be designed according to specific application requirements.

[0057] For example, the first frequency and the second frequency can be preset. The first frequency can be a frequency commonly used by the display device, such as 60Hz or other approximate frequencies, such as any frequency from 60Hz to 85Hz, which can meet the display requirements of conventional dynamic images. The second frequency can be a frequency of low-frequency display mode, such as 1Hz or other approximate frequencies, such as 2Hz, 0.5Hz, etc., which can be used for displaying static images and can significantly reduce power consumption compared to the first frequency.

[0058] Furthermore, by way of example, the pixel driving circuit may enable the first or second enable signal in response to an instruction to use the first or second display mode, or the pixel driving circuit may enable the first or second enable signal according to specific display requirements. Further by way of example, the instruction to use the first or second display mode may be generated internally by the pixel driving circuit or received from an external circuit. For example, a user may select to use the first or second display mode via a physical or virtual button on the computing device, and subsequently, the computing device may generate a corresponding instruction based on the user's selection and provide it to the pixel driving circuit; or, the computing device may automatically determine whether to use the first or second display mode based on current requirements, generate a corresponding instruction, and provide it to the pixel driving circuit; or, the pixel driving circuit may automatically determine whether to use the first or second display mode based on the image data to be displayed and generate a corresponding instruction; and so on.

[0059] In related technologies, only one display mode at a single frequency is often supported, such as the first display frequency described above. Alternatively, although the related circuitry supports multiple display modes at various frequencies, only one frequency can be selected during use. However, the pixel driving method 100 can support display modes at different frequencies (e.g., a 60Hz mode and a 1Hz mode, or other combinations of the first and second frequencies), and charge the pixels in different ways in the two modes. Specifically, different enabling signals can be used to employ different charging methods in different display modes. In the first display mode, a data voltage signal can be provided to the pixel, allowing the pixel to be charged through the voltage difference between the data voltage signal and a common voltage signal. In the second display mode, a determined data voltage signal can be adjusted based on the pixel data, and the adjusted data voltage signal can be provided to the pixel, allowing the pixel to be charged through the maximum or minimum driving voltage. Thus, enabling signals for different display modes can be provided, for example, by manual switching or automatic switching when certain conditions are met, and the data voltage can be updated at different frequencies and the pixels can be charged in different ways in different display modes. In this way, it is not necessary to maintain a high-frequency display state continuously, thereby helping to reduce overall power consumption. Specifically, the high-frequency first display mode can meet the needs of conventional displays, while the low-frequency second display mode can meet the needs of low-power displays. In addition, in the low-frequency second display mode, the driving voltage of each pixel is determined to be the maximum or minimum driving voltage, that is, each pixel only has two display states: white and black. This can realize simpler processing logic and help to further reduce power consumption.

[0060] As mentioned above, the need to reduce power consumption and extend battery life is often more pronounced for wearable devices such as smartwatches. Therefore, the pixel driving method provided in this disclosure can be applied to such devices. According to experiments, by using the technical solution provided in this disclosure, the power consumption of wearable devices such as smartwatches can be significantly reduced, typically by one to two orders of magnitude.

[0061] In some embodiments, Figure 1 The pixel driving method 100 shown can be used in conjunction with Figure 2 The pixel circuit 200 shown is used, that is, the pixel driving method 100 can be used to drive the pixel circuit 200. However, it should be understood that the pixel circuit 200 is merely exemplary, and other similar pixel circuits can actually be used.

[0062] like Figure 2 As shown, the pixel circuit 200 may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a second transistor M5, and two inverters connected end-to-end. The two inverters connected end-to-end can form a Static Random Access Memory (SRAM) to store voltage signals that control the on / off state of M3 and M4. The switching of M1 and M2 can be determined by the Gate A signal. When Gate A is high, M1 is on and M2 is off, and the Source signal can be input to node 1 (i.e., to the SRAM) via M1. When the Gate A signal is low, M1 is off and M2 is on, isolating the SRAM from the Source signal; changes in the Source signal will not affect the voltage signal in the SRAM. When the GateB signal is high, when the voltage signal in the SRAM causes M3 to turn off and M4 to turn on, the storage capacitor P in the pixel circuit 200 can be connected to the Source via M5; when the voltage signal in the SRAM causes M3 to turn on and M4 to turn off, the storage capacitor P can be connected to the FRP via M5. Figure 2 The Source signal can be considered as the data voltage signal provided to the pixel circuit by the driving device, as mentioned earlier. FRP can be considered as a zero-difference voltage signal, which can be a long black voltage signal in this circuit. VCOM can be considered as a common voltage signal. In addition, GateA and GateB are control signals. GateA can be considered as an initialization control signal, which can be used for progressive initialization; GateB can be considered as a display control signal, which can be used for progressive display.

[0063] Below, in conjunction with Figure 3A and 3BThe operation of the pixel circuit 200 according to some embodiments of the present disclosure is described in a first display mode. As mentioned above, the first display mode can be a display mode at a conventional frequency, such as a 60Hz mode or other approximate frequency mode.

[0064] Figure 3A The initialization phase of the first display mode is shown. As shown in the figure, Gate A is high, at which time M1 is on and M2 is off. A low level (L) is written through the Source signal. This L level is then inverted for the first time by the inverter between nodes 1 and 2 to a high level (H). This high level turns on M4, and simultaneously inverts it a second time by the inverter between nodes 3 and 4 to a low level (L), but neither inverter is actually on. Gate B is low, at which time M5 is off, therefore no data is written to the storage capacitor P, and no pixels are displayed.

[0065] Figure 3B The diagram illustrates the display stage of the first display mode. As shown, Gate A is low, at which point M2 is on, M1 is off, and both inverters are on, maintaining a level cycle that keeps M4 continuously on. Gate B is high, at which point M5 is on. Therefore, data can be continuously written via the Source signal and then written to the storage capacitor P via M4 and M5. The Source signal and VCOM signal across storage capacitor P create a voltage difference, allowing the pixels to display normally.

[0066] For example, in the first display mode, it can be achieved through Figure 5A The driving timing shown is 500A to drive the pixel circuit 200. Figure 5A The diagram illustrates the column start signal STV, data voltage signal Source, common voltage signal VCOM, long black voltage signal FRP, initialization control signals GateA1 to GateAn for pixels 1 to n, and display control signals GateB1 to GateBn for pixels 1 to n, where n ≥ 1. As shown, in the first display mode, the first frame can be used for initialization, and from the second frame onwards, it can be used for normal display. The process from initialization to normal display is only repeated when power is restored or the frame rate changes. Specifically, during the initialization phase of the first display mode, Source is low, and GateA1 to GateAn are sequentially set to high, i.e., each pixel circuit is initialized sequentially. During the display phase of the first display mode, image data is written to the pixel circuits of each pixel through Source, and GateB1 to GateBn are sequentially set to high, i.e., corresponding image data is written to each pixel circuit in sequence to display the frame image. For example, in a 60Hz mode, the duration of each frame can be approximately 16.7ms.

[0067] Below, in conjunction with Figure 4A , 4B The 4C and 4D descriptions refer to the operating state of the pixel circuit 200 in a second display mode according to some embodiments of the present disclosure. For ease of description, in relation to... Figures 4A-4D In the described embodiments, it is assumed that the pixel circuit 200 is a pixel circuit in a normally black mode. For a normally white mode, it can be driven similarly, wherein the correspondence between the driving voltage and the pixel grayscale (or pixel brightness) needs to be adjusted. As mentioned above, the second display mode can be a low-frequency display mode, such as a 1Hz mode or other approximate frequency mode. In some embodiments, the second display mode can be further divided into a White mode and a Black mode. In the White mode, the pixel driving voltage is determined to be the maximum driving voltage, and the highest brightness is displayed. In the Black mode, the pixel driving voltage is determined to be the minimum driving voltage (e.g., zero voltage), and the lowest brightness (e.g., complete black) is displayed.

[0068] Figure 4A The initialization phase of the White mode in the second display mode is shown. This phase is similar to the initialization phase of the first display mode. As shown in the figure, Gate A is high. At this time, M1 is on and M2 is off. A low level (L) is written through the Source signal. The L level is then inverted to a high level (H) by the inverter between nodes 1 and 2. This high level turns M4 on. Simultaneously, it is inverted to a low level (L) by the inverter between nodes 3 and 4, but neither inverter is turned on. Gate B is low. At this time, M5 is off, so no data is written to the storage capacitor P, and no pixel is displayed.

[0069] Figure 4B The display stage of White mode in the second display mode is shown. As shown, Gate A is low, at which time M2 is on, M1 is off, and both inverters are on, maintaining a level cycle, so that M4 is continuously on. Gate B is high, at which time M5 is on. Therefore, data can be continuously written through the Source signal and written to the storage capacitor P via M4 and M5. The Source signal and VCOM signal across the storage capacitor P form a voltage difference, and the pixel is displayed normally. In some embodiments, when displaying a static image, the system does not continuously write image data. For the pixel circuit, the Source data of the previous frame can be written to the storage capacitor P through M4 and M5. This Source data can be stored in a buffer device, which will be described below.

[0070] Figure 4AThe diagram illustrates the initialization phase of the Black mode in the second display mode. As shown, Gate A is high, at which point M1 is on and M2 is off. An H level is written via the Source signal, which turns on M3. This H level is then inverted to L level for the first time by the inverter between nodes 1 and 2, and then inverted to H level a second time by the inverter between nodes 3 and 4, but neither inverter is turned on. Gate B is low, at which point M5 is off, therefore no data is written to the storage capacitor P, and no pixels are displayed.

[0071] Figure 4B The diagram illustrates the display stage of Black mode in the second display mode. As shown, Gate A is low, at which point M2 is on, M1 is off, and both inverters are on, maintaining a level cycle that keeps M3 continuously on. Gate B is high, at which point M5 is on. Therefore, the FRP signal can be written to the storage capacitor P via M3 and M5. The voltage difference between the FRP signal and the VCOM signal across storage capacitor P is zero, and the pixel displays black. In some embodiments, when displaying a static image, the system does not continuously write image data. For the pixel circuit, in the next frame, it can continue to be initialized to Black mode by the high level of the Source signal, and the FRP signal can be written to storage capacitor P via M3 and M5. When there is an image update, the system writes new image data.

[0072] For example, in the second display mode, it is possible to... Figure 5B The driving timing 500B shown is used to drive the pixel circuit 200. Figure 5BThe diagram illustrates the column start signal STV, the data voltage signal Source (Black) in Black mode, the data voltage signal Source (White) in White mode, the common voltage signal VCOM, the long black voltage signal FRP, the initialization control signals GateA1 to GateAn for pixels 1 to n, and the display control signals GateB1 to GateBn for pixels 1 to n, where n ≥ 1. As shown in the figure, in the second display mode, a portion of each frame can be used for initialization, and the remaining time can be used for normal display. Taking the 1Hz mode as an example, each frame lasts 1 second, with the first 16.7ms used for initialization and the remaining time used for normal display. It should be understood that the length of the initialization phase can be set according to requirements, and it can be equal to or different from the frame length of the first display mode. Specifically, during the initialization phase of the Black mode in the second display mode, Source is high, and GateA1 to GateAn are sequentially set to high, thus initializing each pixel circuit in turn. During the display phase of the Black mode, pixels are charged via FRP and VCOM, and GateB1 to GateBn remain high, continuously providing FRP signals to the pixel circuits to ensure the relevant pixels continuously display black. During the initialization phase of the White mode in the second display mode, Source is low, and GateA1 to GateAn are sequentially set to high, thus initializing each pixel circuit in turn. During the display phase of the White mode, image data is written to the pixel circuits of each pixel via Source, and GateB1 to GateBn remain high, continuously writing the corresponding Source signal to each pixel circuit to display the frame image. Because the second display mode involves selecting between Black and White modes for pixels, the process from initialization to normal display must be repeated at the beginning of each frame.

[0073] It should be understood that the above description refers to transistors with control level high active. In fact, transistors with control level low active can also be used. In this case, the relevant drive signals can be set to the opposite of those described above.

[0074] In some embodiments, the pixel data for the target pixel may include at least one valid data bit. The data format of the image data will be described in detail below with examples, and will not be repeated here. In this embodiment, step 140 may include: adjusting a data voltage signal in response to the highest valid data bit among the at least one valid data bit being a first value, such that the driving voltage of the target pixel is determined to be a maximum driving voltage; and adjusting the data voltage signal in response to the highest valid data bit among the at least one valid data bit being a second value, such that the driving voltage of the target pixel is determined to be a minimum driving voltage. For example, when the highest valid data bit in the pixel data is 1, the data voltage signal can be adjusted to determine the driving voltage of the target pixel to be a maximum driving voltage; for example, the data voltage signal can be adjusted to make the target pixel display in the White mode described above. When the highest valid data bit in the pixel data is 0, the data voltage signal can be adjusted to determine the driving voltage of the target pixel to be a minimum driving voltage (e.g., zero); for example, the data voltage signal can be adjusted to make the target pixel display in the Black mode described above. Therefore, the target pixel can be displayed at its highest or lowest brightness based solely on the value of the most significant bit of the pixel data. This helps reduce the amount of data processing, simplifies the processing logic, and thus helps to further reduce power consumption.

[0075] In some embodiments, the driving voltage of a target pixel can be determined as the maximum driving voltage or the minimum driving voltage in the following ways. Specifically, to determine the driving voltage of the target pixel as the maximum driving voltage, during the initialization period, the data voltage signal can be determined as the first voltage signal, and valid initialization control signals are provided to each pixel sequentially. Subsequently, during the display period, the data voltage signal can be determined to be opposite to the common voltage signal, and a continuously valid display control signal is provided to the target pixel, so that the driving voltage of the target pixel is determined as the voltage difference between the data voltage signal and the common voltage signal. To determine the driving voltage of the target pixel as the minimum driving voltage, during the initialization period, the data voltage signal can be determined as the second voltage signal, and valid initialization control signals are provided to each pixel sequentially. Subsequently, during the display period, a zero-difference voltage signal, which is the same as the common voltage signal, can be provided to the target pixel, and a continuously valid display control signal is provided to the target pixel, so that the driving voltage of the target pixel is determined as the voltage difference between the zero-difference voltage signal and the common voltage signal.

[0076] Still for reference Figures 4A-4DTaking the described pixel circuit as an example, the case where the target pixel's driving voltage is determined to be the maximum driving voltage can be the White mode mentioned earlier. In White mode, during the initialization period, the data voltage signal can be determined to be low, and during the display period, the data voltage signal can be determined to be opposite to the common voltage signal, for example, as... Figure 5B As shown in the Source (White) signal. The target pixel's driving voltage is determined to be the minimum driving voltage in the Black mode mentioned earlier. In Black mode, during the initialization period, the data voltage signal can be set to a high level, for example, as... Figure 5B As shown in the Source (Black) signal, a long black voltage signal, identical to the common voltage signal, can be provided during the display period, for example, as... Figure 5B The FRP signal shown is the same as that of VCOM. Furthermore, exemplarily, it can be as follows: Figure 5B As shown in GateA1 to GateAn, each pixel is provided with a valid initialization control signal during the initialization period, and as shown in GateB1 to GateBn, each pixel is provided with a continuously valid display control signal during the display period.

[0077] In the above embodiments, the data voltage signal can be adjusted, and the adjusted data voltage signal can be used to set the pixels to display at maximum or minimum brightness during the initialization period. Furthermore, by keeping the display control signal active during the display period, each pixel can continuously display at maximum or minimum brightness. Therefore, the display status of each pixel (i.e., displaying maximum or minimum brightness) can be conveniently controlled within each cycle.

[0078] In some embodiments, it can be achieved by means of Figure 6 The pixel charging circuit 600 shown is used to charge the pixels. For example... Figure 6 As shown, the pixel charging circuit 600 includes two charging paths 610 and 620. Charging path 610 can be used to charge the pixel circuit in a first display mode, and charging path 620 can be used to charge the pixel circuit in a second display mode.

[0079] like Figure 6As shown, the pixel charging circuit 600 can receive a data voltage signal Source', which can be generated based on pixel data in step 120 described above. When the first enable signal EN_1 is valid and the second enable signal EN_2 is invalid, the pixel circuit can be driven in a first display mode. At this time, the Source' signal is transmitted to the first charging path 610 via transistor T1, and then provided to the corresponding pixel circuit as the Source signal, written into the storage capacitor of the pixel circuit, so that the Source signal and the VCOM signal form a voltage difference across the storage capacitor, causing the pixel to display the corresponding brightness. In some embodiments, the voltage difference can be proportional to the pixel brightness. For example, Figure 6 An example drive timing 611 for the first charging path 610 is also schematically shown. As shown, VCOM can vary between 4.5V and 0V, and the Source signal can be determined as a series of voltage signals based on the image data, such as 3V, 4.5V, 0V, 4.5V, and 1.5V as shown in the figure. Thus, the charging voltage of the storage capacitor can be determined as the difference ΔV between the two.

[0080] When the first enable signal EN_1 is invalid and the second enable signal EN_2 is valid, the pixel circuit can be driven in the second display mode. At this time, the Source' signal is transmitted to the second charging path 620 via transistor T2. To determine whether the pixel driving voltage should be determined to be the maximum or minimum value in the second display mode, the value of the most significant bit of the pixel data can be latched to each pixel. Optionally, the value of the most significant bit can be taken from the Source' signal, the corresponding pixel data in the image data, the corresponding pixel data in the processed image data, etc. For example, when the most significant bit is 1, T3 is turned on, driving the pixel circuit in White mode (still taking the normally black mode as an example), where the Source' signal is adjusted to the Source signal, so that there is a maximum voltage difference between the Source signal and the VCOM signal. For example, Figure 6 An example drive timing 621 for the second charging path 620 in White mode is also schematically shown. As shown, Source' can be adjusted to Source to charge the storage capacitor of the pixel circuit with a maximum voltage difference of 4.5V, allowing the pixel to display maximum brightness. When the most significant bit is 0, T4 is turned on, driving the pixel circuit in Black mode, where the Source' signal is adjusted to Source signal, allowing the storage capacitor of the pixel circuit to be charged through the voltage difference between the long black voltage signal FRP and VCOM. Exemplarily, Figure 6An example drive timing 622 for the second charging path 620 in Black mode is also schematically shown. As shown, VCOM is the same as FRP, causing the voltage across the storage capacitor to be zero, thus making the pixel display black.

[0081] For the sake of brevity, Figure 6 In this diagram, the pixel circuit is not fully shown; only its Source, VCOM, and Gate terminals are schematically illustrated. It should be understood that the pixel circuit may have the same or similar structure as described in the preceding embodiments and may be driven as described in the preceding embodiments.

[0082] In some embodiments, reference Figure 1 Step 120 described may include: caching pixel data for a preset number of pixels in the image data; and converting the pixel data for the target pixel in the cached pixel data into a data voltage signal for the target pixel according to a preset digital-to-analog conversion rule. Since the interface data transmission rate and the internal data processing rate of the driving device may differ (for example, the data transmission rate may be higher than the data processing rate), the received image data can be cached for subsequent processing and use. Optionally, the preset digital-to-analog conversion rule may be a preset digital-to-analog conversion function, a preset lookup table, etc. The digital-to-analog conversion process can convert digital signals to analog signals (i.e., data voltage signals) based on the valid data bits in the pixel data. The converted analog signal can be input to the display screen and determine the grayscale color of the display screen.

[0083] In some embodiments, during the caching of image data, in response to the number of valid data bits in pixel data for a preset number of pixels exceeding a first threshold, the pixel data for the preset number of pixels can be compressed according to a preset compression rule, so that the number of valid data bits in the compressed pixel data does not exceed the first threshold. To save storage space and reduce the pressure on the data transmission rate inside the driving device, the pixel data can be compressed in units of a preset number of pixels. The preset number can be, for example, 2, 3, 4, or other preset values, and the first threshold can be 36 bits or other values. It is understood that the preset number and the first threshold can be set according to specific application requirements. For example, different preset numbers can be set for different data formats of image data, and the first threshold can be set according to the processing capability inside the driving circuit.

[0084] In the above embodiments, during the process of converting the cached pixel data into a data voltage signal, the compressed pixel data can be decompressed, and the pixel data for the target pixel in the decompressed pixel data can be converted into a data voltage signal for the target pixel.

[0085] In some embodiments, during the caching of image data, in response to the number of valid data bits in the pixel data for a preset number of pixels being less than a first threshold, the pixel data for the preset number of pixels can be padded according to a first preset padding rule, so that the number of valid data bits in the padded image data is equal to the first threshold. To ensure that pixel data has the same or similar format during storage, transmission, and processing within the driving device, and to facilitate unified management, when the number of valid data bits in the pixel data for a preset number of pixels is less than the first threshold, it can be padded to the first threshold. The first preset padding rule can be set to pad with 0, or it can be set to other padding methods according to specific application requirements.

[0086] In the above embodiments, during the process of converting the cached pixel data into a data voltage signal, in response to the number of valid data bits in the pixel data used for the target pixel electrode being less than a second threshold, the image data used for the target pixel electrode can be padded according to a second preset padding rule, so that the number of valid data bits in the padded pixel data is equal to the second threshold. For example, the second preset padding rule can be preset according to application requirements, for example, it can be set through relevant registers, such as padding with 0s, 1s, MSB (most significant bit), Green LSB (least significant green bit), etc. For example, a padding control signal EPF can be generated based on the register setting result to specify how padding is performed.

[0087] In the above embodiments, during the process of converting the cached pixel data into a data voltage signal, in response to receiving pixel data for at least two pixels per clock cycle, the pixel data for at least two pixels can be reallocated into at least two sets of pixel data for different pixels. For example, when the number of valid data bits in the pixel data for one pixel is too low, in order to unify the number of clock signals when receiving image data of different data formats and improve transmission efficiency, pixel data for two or more pixels can be received within one clock cycle and cached and processed as a whole. In this example, to ensure that pixel data can be provided to the correct pixel, the two or more pixel data can be reallocated into two or more independent sets of pixel data before generating the data voltage signal.

[0088] Below, as an example, for reference Figures 7A to 7E This document briefly introduces several data formats applicable to the technical solutions provided in this disclosure. It should be understood that the data formats shown in the accompanying drawings are merely illustrative, and other types of data formats can be designed and used based on the technical solutions provided in this disclosure.

[0089] As shown in the figure, the data format can consist of CMD (Control Message) and DATA (Data Message). CMD can be used to specify information such as the data protocol type, while DATA can be used to transmit image data. For example, one byte can include 9 bits, where the first byte can be used to transmit CMD, and DATA can be transmitted starting from the second byte. The first bit in each byte can be used for error correction or other functions, without transmitting actual data. The effective data bits used for data transmission can be different for different data formats.

[0090] Specifically, Figure 7A The diagram illustrates the 700A transmission protocol with a 24-bit data format. In this 24-bit format, each pixel's data can consist of 8 bits of red, 8 bits of green, and 8 bits of blue data, and can be transmitted in 3-byte chunks. Figure 7B The diagram illustrates the 700B transmission protocol with an 18-bit data format. In the 18-bit data format, the pixel data for each pixel can consist of 6 bits of red, 6 bits of green, and 6 bits of blue data, and can also be transmitted in 3 bytes, but there are 2 free bits in each byte. Figure 7C The diagram illustrates the 700C transmission protocol with a 16-bit data format. In the 16-bit data format, the pixel data for each pixel can consist of 5 bits of red, 6 bits of green, and 5 bits of blue data, and can be transmitted in 2 bytes. Figure 7D The diagram illustrates a 700D transmission protocol with a 6-bit data format. In this 6-bit format, each pixel's data can consist of 2 bits of red, 2 bits of green, and 2 bits of blue data. Two different protocol types have been designed for the 6-bit data format, such as... Figure 7D As shown in the upper part, pixel data for each pixel can be transmitted continuously without any idle spaces, thus improving data transmission efficiency; as Figure 7D As shown in the lower half, only one pixel's data can be transmitted within a single byte, leaving the other two bits idle. While this sacrifices some data transmission efficiency, it helps reduce the complexity of data processing. One of these two protocol types can be selected based on the system's data transmission requirements. Figure 7E The diagram illustrates the 700E transmission protocol with a 3-bit data format. In this 3-bit data format, each pixel's data can consist of 1 bit of red, 1 bit of green, and 1 bit of blue data. Two different protocol types are also designed for the 3-bit data format, such as... Figure 7EAs shown in the upper part, only two pixels of pixel data can be transmitted in one byte, with the other two bits left idle; for example... Figure 7E As shown in the lower half, pixel data for each pixel can be transmitted continuously without any idle bits. Similar to the 6-bit data format, the two protocol types each have different advantages, and one protocol type can be selected based on the data transmission requirements of the system.

[0091] For example, in accordance with the different needs and characteristics of the first and second display modes described above, in the first display mode, a similar... Figure 7A , Figure 7B , Figure 7C The data format shown has a higher number of valid data bits to present richer image details and provide a display effect that meets general needs; while in the second display mode, a similar format can be used preferentially. Figure 7D , Figure 7E The data format shown has a lower number of valid data bits to reduce data transmission volume, simplify data processing logic, and further reduce overall power consumption. However, depending on the actual application requirements, a data format with fewer valid data bits can also be used in the first display mode, or a data format with more valid data bits can be used in the second display mode.

[0092] For different data formats, the processing can be performed according to the scheme described in the preceding embodiments to ultimately generate the corresponding data voltage signal. For example, Figures 8A to 8D The reference is shown schematically. Figures 7A to 7E The data processing flow describes the data format.

[0093] For ease of understanding, the following assumptions are used to describe the process. Figures 8A to 8DThe data processing flow is shown below. The pixel driving device can take the form of a driver IC. The system can write image data to the driver IC according to one of the aforementioned data formats. The driver IC can receive image data and perform multi-level data processing, finally writing the data to the corresponding pixel circuit through the Source. For the driver IC, data transmission can be performed in 24-bit units, that is, 24 bits of data can be received per clock cycle (per CLK). If 1 bit of data is received per rising edge of the clock, then each clock cycle should include at least 24 rising edges of the clock. Inside the driver IC, data processing can consist of three modules: compression / decompression (MC / MD), data mapping, and digital-to-analog conversion (D / A). For the MC / MD module, data processing is allowed in units of at least one pixel's pixel data, with 36 bits of valid data. That is, when the number of valid data bits of at least one pixel's pixel data exceeds 36 bits, the pixel data needs to be compressed; when the number of valid data bits is less than 36 bits, the pixel data needs to be padded, for example, by padding with 0s. D / A data acquisition and processing can be performed in 24-bit units. Therefore, the data mapping module can pad pixel data that is less than 24 bits. As mentioned earlier, the padding rules can be set as needed, such as padding with 0, padding with 1, padding with MSB, padding with Green LSB, etc.

[0094] Figure 8A The schematic diagram illustrates the processing flow of the 800A for 24-bit data format. As shown, the IC interface can receive image data at 1 pixel / CLK. For the 24-bit data format, that is, 24 valid data bits are received per CLK, without any padding. Within the MC / MD, image data exists at 2 pixels / CLK (i.e., 48 valid data bits). 3 / 4 compression is required to compress the pixel data from 48 bits to 36 bits, which is then stored in GRAM. After decompression, it is restored to 48 valid data bits. The data mapping module receives 1 pixel of data at a time, i.e., 24 valid data bits, without padding. It can directly enter the D / A module for digital-to-analog conversion, generating the corresponding data voltage signal, and providing it to the display panel.

[0095] Figure 8BThe schematic diagram illustrates the processing flow of the 18-bit data format 800B. As shown, the IC interface can receive image data at 1 pixel / CLK. For the 18-bit data format, this means receiving 18 valid data bits per CLK, padded to 24 bits. Within the MC / MD, image data exists at 2 pixels / CLK (i.e., 36 valid data bits). No data compression or decompression is required; the image data can be directly input to the data mapping module via this module. The data mapping module receives 1 pixel of data at a time, i.e., 18 valid data bits, which are padded to 24 bits. The padded data then enters the D / A module for digital-to-analog conversion, generating the corresponding data voltage signal, which is then provided to the display panel. For the 16-bit data format, the processing flow is similar to that of 18-bit, only the number of padded bits differs, and will not be described further here.

[0096] Figure 8C The diagram illustrates the processing flow of the 800C for 6-bit data format. As shown, the IC interface can receive image data at 1 pixel / CLK. For the 6-bit data format, this means receiving 6 valid data bits per CLK, padded with 0s to reach 24 bits. Within the MC / MD, image data exists at 2 pixels / CLK (i.e., 12 valid data bits), requiring no data compression or decompression, and can be padded to 36 bits. The data mapping module receives 1 pixel of data each time, i.e., 18 bits of data (including 12 valid data bits), which needs to be padded to 24 bits. The padded data enters the D / A module for digital-to-analog conversion, generating the corresponding data voltage signal, and providing it to the display panel. For the 6-bit data format, considering its primary application in the low-frequency second display mode, to reduce processing complexity and because the data voltage signal is determined only based on the value of the most significant data bit in the second display mode, the padding operation can be completed simply by padding with 0s.

[0097] Figure 8DThe diagram illustrates the processing flow of a 3-bit data format 800D. As shown, for the 3-bit data format, for data transmission efficiency, the IC interface can receive image data at 2 pixels / CLK, i.e., 6 valid data bits per CLK, padded to 24 bits. Within the MC / MD, image data exists at 4 pixels / CLK (i.e., 12 valid data bits), without the need for data compression and decompression, and can be padded to 36 bits. The data mapping module receives 2 pixels of data each time, i.e., 18 bits of data (including 12 valid data bits), which needs to be padded to 24 bits. Since the padded 24 bits actually contain pixel data for two pixels, to ensure that the pixel data can be provided to the corresponding pixels, the padded data needs to be redistributed into two sets of pixel data. Optionally, during redistribution, the second most significant bit of each pixel data can be set to the value of the most significant bit. The redistributed pixel data can then sequentially enter the D / A module for digital-to-analog conversion, generating corresponding data voltage signals, and providing them to the display panel. For 3-bit data formats, similar to 6-bit data formats, padding can be accomplished simply by adding 0s.

[0098] In some embodiments, a mode switching instruction can be provided to switch between a first display mode and a second display mode.

[0099] For example, in the first display mode, in response to receiving an instruction to switch to the second display mode, enable data for the second display mode can be written to the mode register. After a first preset time interval, a second enable signal can be enabled based on the enable data in the mode register. Similar to the embodiments mentioned above, the instruction to switch to the second display mode can be received from the system side. For example, a user can manually select to switch to the second display mode, or the system side can automatically determine to switch to the second display mode under certain circumstances. Based on this manual or automatic switching operation, an instruction to switch to the second display mode can be sent to the pixel driving circuit. The mode register can write corresponding enable data in response to receiving the relevant switching instruction. Subsequently, a first enable signal or a second enable signal can be provided to a pixel charging circuit such as those described in the embodiments above based on the enable data stored in the mode register. The first preset time interval can be set according to specific application requirements and can serve as a buffer time to help avoid circuit processing errors.

[0100] Taking 60Hz mode and 1Hz mode as examples, Figure 9AAn example flow 900A for switching from 60Hz mode to 1Hz mode is illustrated schematically. As shown, in 60Hz mode, optionally, a color format can be set. For example, as described in the previous embodiments, the corresponding data format can be set based on CMD information in the image data received from the system or based on other relevant instructions, so as to select an appropriate processing flow according to the characteristics and requirements of the data format. This has been described in detail in the previous embodiments and will not be repeated here. After setting the color format, optionally, image data (2C / 3C data) can be received. When a command to switch to 1Hz mode is received, enable data for 1Hz mode can be written to the mode register, and after a 50ms time interval, the system switches to 1Hz mode and enables the second enable signal.

[0101] For example, in the second display mode, in response to receiving new image data, a data voltage buffer can be activated, a data voltage signal determined based on the new image data can be written into the data voltage buffer, and the data voltage buffer can be deactivated after a second preset time interval. As mentioned above, the second display mode can be used for displaying static images; therefore, in this mode, the system may not continuously provide image data to the pixel driving circuit. Thus, in the second display mode, after generating the corresponding data voltage signal based on the image data, the generated data voltage signal can be stored in the data voltage buffer, so that the data voltage signal can be provided or updated based on the data in the data voltage buffer during each display cycle. This buffering mechanism helps reduce the data transmission pressure between the system and the pixel driving circuit, as well as within the pixel driving circuit, in the second display mode, and reduces unnecessary data processing operations within the pixel driving circuit.

[0102] Taking the 1Hz mode as an example, Figure 9B The schematic diagram illustrates the processing flow 900B when receiving new image data in 1Hz mode. As shown, in 1Hz mode, upon receiving new image data, a data voltage buffer (e.g., GRAM for buffering data voltage signals) can be activated. After a 1ms delay, receiving new image data can begin. Optionally, the color format (e.g., the data format of the image data) can be set according to CMD information or additional instructions. Subsequently, a corresponding data voltage signal can be generated based on the new image data and written to the data voltage buffer. If no mode switching instruction is received, the 1Hz mode can be maintained according to the enable data stored in the status register. After the new image data reception and processing are complete, the data voltage buffer can be deactivated after a 50ms time interval.

[0103] For example, in the second display mode, in response to receiving an instruction to switch to the first display mode, enable data for the first display mode can be written to the mode register, and the data voltage buffer can be enabled. Subsequently, a data voltage signal can be written to the data voltage buffer. After a third preset time interval, the data voltage buffer is disabled, and the first enable signal is enabled based on the enable data in the mode register. Similar to the embodiments mentioned above, the instruction to switch to the first display mode can be received from the system side. The system side can send the instruction to switch to the first display mode to the pixel driving circuit based on manual or automatic switching operations. The pixel driving circuit can write enable data for the first display mode to the mode register based on receiving the instruction, so as to prepare to switch to the first display mode. To reduce the complexity of the processing logic, in this case, the image data update process in the second display mode described above can be followed. That is, the data voltage buffer can be enabled, and the data voltage signal generated based on the image data can be stored in the data voltage buffer. At this time, the stored data voltage signal can be generated based on new image data or the data voltage signal corresponding to previous image data. Subsequently, the first display mode can be switched according to the enable data in the mode register, and the first enable signal can be made active.

[0104] Taking 60Hz mode and 1Hz mode as examples, Figure 9C An example flow 900C for switching from 1Hz mode to 60Hz mode is illustrated. As shown, in 1Hz mode, in response to receiving a command to switch to 60Hz, enable data for 60Hz mode can be written to the mode register, and the data voltage buffer can be enabled to store the data voltage signal generated based on the image data. Optionally, the color format can be set as described in the previous embodiments. After setting the color format, image data (2C / 3C data) can optionally be received. Subsequently, the 60Hz mode can be switched according to the enable data in the mode register, and the data voltage buffer is disabled after a 50ms time interval.

[0105] As mentioned earlier, the first display mode can be used to meet conventional display needs. Therefore, in some embodiments, when the pixel driving circuit is powered on, it can directly enter the first display mode and continuously write and update image data in the first display mode. When it is necessary to display static images or when there is a need to reduce power consumption, it can be manually or automatically switched to the second display mode. In the second display mode, image data can be updated at a low frequency, and it can be switched back to the first display mode when needed. For example, Figure 10A schematic diagram 1000 illustrates the mode switching within the pixel driving circuit. As shown, in the power-off state, the pixel driving circuit can enter a sleep state in response to a power-on operation. In the sleep state, the pixel driving circuit can return to the power-off state in response to a power-off operation; when the sleep time is long or in response to a related state switching operation, the pixel driving circuit can enter a deep sleep state; when image data is received from the system or a related command is received, the pixel driving circuit can switch to a first display mode (e.g., 60Hz mode). In the deep sleep state, when data signals or commands are received from the system, the pixel driving circuit can switch back to the sleep state. In the sleep state, some circuit functions can be disabled; in the deep sleep state, more circuit functions can be disabled, thereby reducing unnecessary power consumption. In the first display mode (e.g., 60Hz mode), as described above, image data can be received and data voltage signals and other driving signals can be provided to the pixel circuit based on the image data; it can also switch to a second display mode (e.g., 1Hz mode) in response to a related switching command. Furthermore, when image data is no longer displayed or in response to a related command, the pixel driving circuit can also switch back to the sleep state from the first display mode. In the second display mode (e.g., 1Hz mode), as described above, image data can be received and data voltage signals and other drive signals can be provided to the pixel circuit based on the image data. It can also switch to the first display mode (e.g., 1Hz mode) in response to a relevant switching command. Furthermore, when image data is no longer displayed or in response to a relevant command, the pixel drive circuit can also switch back to a sleep state from the second display mode.

[0106] As mentioned in the previous embodiments, in the first display mode, to provide richer image details and meet general display requirements, a data format with more effective data bits can be used, such as the 24-bit, 18-bit, and 16-bit data formats described above. In the second display mode, considering its display characteristics, to reduce data volume and power consumption, a data format with fewer effective data bits can be used, such as the 6-bit and 3-bit data formats described above. However, in some practical applications, due to limitations in motherboard speed, to avoid stuttering, there may be a need to use a data format with fewer effective data bits in the first display mode. Since data formats with fewer effective data bits, such as 6-bit and 3-bit, are generally used in the second display mode in general designs, as described above, in the second display mode, the pixel driving voltage can be ultimately determined as the maximum or minimum driving voltage based on the value of the highest effective data bit. Therefore, to reduce data processing complexity, zero-padding is generally used by default when performing padding operations. However, in this case, when using data formats with fewer effective data bits in the first display mode, there will be a problem of insufficient pixel brightness.

[0107] For example, suppose that inside the pixel driving circuit, when the number of valid data bits in the pixel data is less than 24 bits, it needs to be padded to 24 bits. Taking an 18-bit data format as an example, with valid data bits R(111111)G(111111)B(111111), if padded with 0, the padded data becomes R(11111100)G(11111100)B(11111100). After passing through the D / A module, the corresponding grayscale is R252 G252 B252. If padded with 1, it becomes R(11111111)G(11111111)B(11111111), and after passing through the D / A module, the corresponding grayscale is R255 G255 B255. Therefore, through different padded methods, the final maximum grayscale brightness range is 252~255, with basically no brightness difference. Taking the 6-bit data format as an example, with the effective data bits being R(11)G(11)B(11), as a data format with a small number of effective data bits, only zero padding is used for padding. That is, the padded data is R(11000000)G(11000000)B(11000000). After passing through the D / A module, the corresponding grayscale is R192 G192 B192. That is, the maximum grayscale brightness that can be achieved is only 192 grayscale levels, which is seriously insufficient in visual brightness, only 60% of the normal brightness. Similarly, the 3-bit data format has the same problem.

[0108] In some embodiments, to address the aforementioned insufficient brightness problem, in a first display mode, when the number of valid data bits in the pixel data for the target pixel meets a first preset condition, a low-quality display mode can be used in response to receiving an enable signal for a low-quality display mode. In the low-quality display mode, in response to the highest valid data bit in the pixel data for the target pixel being a first value, the pixel data for the target pixel is set to its maximum value; and in response to the highest valid data bit in the pixel data for the target pixel being a second value, the pixel data for the target pixel is set to its minimum value. Exemplarily, the first preset condition may refer to the number of valid data bits being lower than a preset threshold, or it may refer to the number of valid data bits being equal to a preset value. For example, the first preset condition may refer to the number of valid data bits being 6, i.e., the 6-bit data format mentioned above, or the first preset condition may be set to other conditions as needed. The low-quality display mode can be an independently set display mode, or it can be implemented directly using the IC's Idle mode. Optionally, when image data processing and display require a low-quality display mode, the low-quality display mode can be enabled via a relevant enable signal. This enable signal can be transmitted using a separate instruction or CMD information within the image data. In low-quality display mode, pixel data can be reset to its maximum or minimum value (i.e., all 1s or all 0s) based solely on the highest bit value, corresponding to a grayscale of 255 or 0, thus avoiding brightness loss.

[0109] Continuing with the previous example, for R, G, or B sub-pixels within a pixel, the pixel data bits written after padding are 8 bits. At this point, the highest bit, D7, can be checked. If D7 is 1, the possible data range is 10000000~11111111, corresponding to grayscale levels 128~255. In this case, the IC displays grayscale level 255. If D7 is 0, the possible data range is 00000000~01111111, corresponding to grayscale levels 0~127. In this case, the IC displays grayscale level 0. In this display mode, a maximum of 8 colors can be displayed. However, with a 6-bit data format, 64 colors can normally be displayed. Normally, displaying 8 colors only requires a 3-bit data format. Therefore, to achieve the same display effect, the 6-bit data format increases the amount of data on the motherboard. To solve this problem, when writing image data in 6-bit data format in conjunction with low-quality display mode, the value of the second most significant bit can be directly set to the value of the most significant bit, for example, D6=D7. This satisfies both the motherboard's requirement for low data volume and the requirement of not sacrificing display brightness.

[0110] Figure 11 An example procedure 1100 for data processing in conjunction with Idle mode is illustrated. For example... Figure 11As shown, when receiving image data in 6-bit data format, the pixel data of the 6 valid data bits can be padded to 24 bits. For example, to reduce the data volume on the driver circuit motherboard, D6 can be directly set to D7. Subsequently, according to the instructions in the CMD information, the Idle mode can be entered via the enable signal. In Idle mode, based on the value of D7, it is determined whether the pixel displays 255 gray levels or 0 gray levels; that is, the pixel data is set to all 1s or all 0s. The set pixel data can pass through the data mapping module, and then through the D / A conversion module to generate the corresponding data voltage signal. This data voltage signal can then be used... Figure 6 Branch 610 of the pixel charging circuit shown is provided to the pixel circuit, causing the pixel to display the highest or lowest brightness.

[0111] In some embodiments, to address the aforementioned insufficient brightness problem, in the first display mode, when the number of valid data bits in the pixel data used for the target pixel meets a second preset condition, the second enable signal can be made active before the screen is turned on. For example, the second preset condition may refer to the number of valid data bits being lower than a preset threshold, or it may refer to the number of valid data bits being equal to a preset value. For instance, the second preset condition may refer to the number of valid data bits being 3, i.e., the 3-bit data format mentioned above. Alternatively, the first preset condition can also be set to other conditions as needed. Normally, after receiving image data in the first display mode, a corresponding data voltage signal is generated based on the image data according to the process described in the preceding embodiments, and the generated data voltage signal is used to drive the corresponding pixel to display the image. To address the brightness loss problem caused by using a 3-bit data format in the first display mode, after generating the data voltage signal, the system can switch to the second display mode, i.e., drive the corresponding pixel through the charging path of the second display mode, and then turn on the screen in the second display mode. Since the pixel driving voltage is determined to be the maximum or minimum driving voltage in the second display mode, the pixel will exhibit maximum or minimum brightness without any brightness loss. Optionally, after the current image has finished displaying, you can switch back to the first display mode to continue receiving image data.

[0112] Figure 12An example flow 1200 illustrating how a second display mode avoids the aforementioned brightness loss problem is illustrated. As shown, continuing with 60Hz and 1Hz modes as examples, after the device is powered on, the circuitry is initialized and then prepared to enter 60Hz mode. In response to receiving a relevant display command or receiving image data in a format such as 3-bit data, the drive circuitry can stop sleeping and begin processing the image data, generating a corresponding data voltage signal. After a 120ms delay (during which the corresponding data processing operation can be completed), the device can switch to 1Hz mode for screen display, thereby avoiding the brightness loss problem that occurs when using 3-bit data formats at 60Hz.

[0113] In some embodiments, to address the aforementioned insufficient brightness problem, in the first display mode, when the number of valid data bits in the pixel data used for the target pixel meets a third preset condition, the data voltage signal used for the target pixel is adjusted according to a preset binding point voltage. The preset binding point voltage is used to specify the data voltage signal corresponding to at least one gray level. As analyzed above, when a data format with a low number of valid data bits is used in the first display mode, the gray level corresponding to the padded pixel data cannot reach the maximum gray level (e.g., 255), resulting in brightness loss. Therefore, some or all of the binding point voltages in the gray level-brightness curve (gamma curve) can be adjusted to increase the overall brightness within a reasonable range to compensate for the aforementioned brightness loss. Optionally, the gamma 255 binding point voltage can be adjusted to improve brightness. However, since the binding point voltage has an adjustment range and cannot be increased indefinitely, although this method is beneficial for improving brightness, the improvement effect is often limited. Experimental verification shows that for the pixel circuit and pixel driving circuit mentioned in the embodiments of this disclosure, the brightness can be increased from 60% to 80%. Optionally, when this scheme is adopted, a corresponding adjusted preset binding point voltage can be provided at the same time as providing image data, or the adjusted preset binding point voltage can be stored in the driving circuit and enabled as needed.

[0114] Generally, in related technologies, the device typically enters the display state after powering on and completing the initialization of the internal registers of the driving circuit. However, as described above, in some embodiments of this disclosure, the driving of the pixel circuit includes an initialization phase and a display phase. When the system completes the initialization of the driving circuit and performs driving initialization on the display screen with random signals, the display screen will display a distorted image, i.e., a snowy screen problem occurs upon startup. This degrades the user experience. In some embodiments, to improve this problem, after the device is powered on and initialized, but before the screen lights up, initialization image data can be received, and initialization voltage signals for each pixel can be determined based on the initialization image data. Optionally, the initialization image data can be separate initialization image data, or it can be the first frame of image data in the normally received image data.

[0115] Figure 13 The illustration schematically depicts example process 1300 taken to avoid the snowy startup issue. As shown, after the device is powered on, the device circuitry can be initialized via initialization code, and then prepared to enter 60Hz mode. After terminating sleep mode and receiving image data (2C / 3C), the screen can be turned on after 120ms. Within this 120ms, corresponding data voltage signals can be generated based on the image data and provided to the corresponding pixels to prepare for the display of the corresponding image.

[0116] As mentioned above, in some embodiments of this disclosure, various data formats such as 24-bit, 28-bit, 16-bit, 6-bit, and 3-bit can be supported. For different data formats, due to the different number of bits, the overall data transmission volume for a single frame of an image will differ at the same resolution, and the required transmission time will also differ even with the same transmission rate. Specifically, the data transmission volume is directly proportional to the resolution and data format, while the overall data transmission rate (i.e., the data write rate) depends on the data interface rate and is inversely proportional to the time required for that interface to transmit 1 bit of data. Therefore, the image data write rate F = 1-bit transmission time * number of bits in the data format * X * Y (where X and Y are the resolution). Thus, for high-bit-volume data formats, when the data interface transmission rate is too low, it will affect the smoothness of the screen refresh, causing screen stuttering; for low-bit-volume data formats, when the data interface transmission rate is too high, although it will not affect the screen display effect, it will cause redundant consumption of interface resources and interface power consumption, which is not conducive to overall power consumption control.

[0117] To avoid the aforementioned problems, in some embodiments, a first interface and a second interface with different data transmission rates can be provided in the driving circuit. The first interface or the second interface can be selected to receive the image data based on the display mode and / or the number of valid data bits in the pixel data, according to preset interface rules. For example, preset interface rules can specify which interface to use under what circumstances. For instance, a first interface with a higher transmission rate can be used when the number of valid data bits in the pixel data is higher than a certain threshold, and a second interface with a lower transmission rate can be used when the number of valid data bits is lower than that threshold. Alternatively, as mentioned above, a first display mode is typically used for regular display needs, while a second display mode is typically used for displaying static images or low-frequency refresh rate images. Therefore, it can be configured to use the first interface in the first display mode and the second interface in the second mode. Alternatively, both can be considered together to select a suitable interface, and so on. For example, the first interface can be, for example, a MIPI interface with a rate of several hundred Mbps to 1 Gbps, and the second interface can be, for example, an SPI interface with a rate of tens of Mbps. Alternatively, other interface combinations can be selected according to specific application requirements, or more than two interface options can be provided.

[0118] Figure 14 The diagram illustrates an example state switching process 1400 via different interfaces. As shown, in sleep mode, the system can enter 60Hz mode via the CMD mode of the MIPI interface. The MIPI interface supports both CMD and VIDEO modes. In CMD mode, the system can send commands, parameters, and data to the pixel driver circuit via CMD+DATA to control its behavior. In VIDEO mode, the system can send data to the pixel driver circuit as a real-time pixel stream. In 60Hz mode, the image can be updated via the CMD mode of the MIPI interface, and the system can enter 1Hz mode via either the MIPI or SPI interface. In 1Hz mode, the system can enter 60Hz mode via either the MIPI or SPI interface, and image data can be updated via either the MIPI or SPI interface.

[0119] Figure 15Table 1500 illustrates the application recommendations for MIPI and SPI interfaces. As shown in the table, the MIPI interface can be used in VIDEO or CMD mode, supporting various data formats in 60Hz and 1Hz modes. The SPI interface (using SPI4W as an example) can be used in CMD mode, supporting data formats in 1Hz mode. In 60Hz mode, it supports various data formats, but common 3-bit and 6-bit data formats are not recommended due to significant brightness loss. For 6-bit data formats used in conjunction with Idle mode, it can be used provided the motherboard supports sending 3-bit data in a 2-2-2 format. For 3-bit data formats used with Gamma-bound voltage adjustment, brightness can be increased to 80%, and it can be used under certain conditions (e.g., when brightness requirements are not high).

[0120] According to some embodiments of this disclosure, a pixel driving circuit is also provided. Figure 16 An example block diagram of a pixel driving circuit 1600 is schematically shown. As shown, the pixel driving circuit 1600 may include a data interface 1610, a data processing circuit 1620, and a pixel charging circuit 1630.

[0121] Specifically, the data interface 1610 can be configured to: receive image data, the image data including pixel data for at least one pixel; the data processing circuit 1620 can be configured to: determine a data voltage signal for a target pixel based on the pixel data for the target pixel in the image data; the pixel charging circuit 1630 can include a first charging circuit and a second charging circuit. The first charging circuit can be configured to: drive the target pixel in a first display mode in response to a first enable signal being active, in the first display mode updating the data voltage signal at a first frequency and providing a data voltage signal to the target pixel, such that the driving voltage of the target pixel is determined as the voltage difference between the data voltage signal and a common voltage signal, wherein the common voltage signal is a reference voltage signal shared by all pixels; the second charging circuit can be configured to: drive the target pixel in a second display mode in response to a second enable signal being active, in the second display mode updating the data voltage signal at a second frequency, adjusting the data voltage signal according to the pixel data for the target pixel, and providing an adjusted data voltage signal to the target pixel, such that the driving voltage of the target pixel is determined as a maximum driving voltage or a minimum driving voltage, wherein the second frequency is lower than the first frequency. Exemplarily, the first charging circuit and the second charging circuit can respectively be as follows: Figure 6 The charging paths 610 and 620 shown can also be in other similar forms.

[0122] In some embodiments, the pixel data for the target pixel may include at least one valid data bit, and wherein the second charging circuit may include: a latch configured to latch the most valid data bit among the at least one valid data bit; and a mode selection circuit configured to: adjust a data voltage signal in response to the most valid data bit among the at least one valid data bit being a first value, such that the driving voltage of the target pixel is determined to be a maximum driving voltage, and adjust the data voltage signal in response to the most valid data bit among the at least one valid data bit being a second value, such that the driving voltage of the target pixel is determined to be a minimum driving voltage.

[0123] In some embodiments, the data processing circuit includes: a buffer circuit configured to buffer pixel data for a preset number of pixels in image data; and a digital-to-analog converter circuit configured to convert the buffered pixel data for a target pixel into a data voltage signal for the target pixel.

[0124] In some embodiments, the pixel driving circuit further includes a data voltage buffer configured to buffer data voltage signals in a second display mode. Exemplarily, in the second display mode, when new image data is received, the data voltage buffer can be activated and a data voltage signal generated based on the new image data can be written to it; when an instruction to switch to the first display mode is received, the data voltage buffer can be activated and a data voltage signal can be written to it. This has been described in the preceding embodiments and will not be repeated here.

[0125] It should be understood that the pixel driving circuit 1600 may have the same or similar implementation methods and advantages as the pixel driving method 100 described above, and will not be repeated here.

[0126] According to some embodiments of the present disclosure, a display device is also provided, which may include a pixel driving circuit 1600; a liquid crystal panel including a plurality of pixels and configured to receive data voltage signals from the pixel driving circuit; and a backlight panel configured to provide backlight for the liquid crystal panel. Figure 17A An exemplary block diagram of a display device 1700A according to some embodiments of the present disclosure is shown schematically. Figure 17A As shown, the display device 1700A may include a pixel driving circuit 1600, a liquid crystal panel 1701, and a backlight panel 1702. Exemplarily, the liquid crystal panel 1701 may include a color filter substrate, an array substrate, and a liquid crystal layer between them. For each pixel unit, the degree of deflection of the liquid crystal molecules can be controlled by applying an electric field to the array substrate, thereby displaying a corresponding brightness. Optionally, the backlight panel 1702 may employ various types of direct-lit or edge-lit backlight structures, and this disclosure does not specifically limit it.

[0127] For example, Figure 17BA schematic diagram of a display device 1700B according to some embodiments of the present disclosure is shown as an example. As shown, the display device 1700B may include a liquid crystal panel 1710 and a pixel driving circuit 1720. A backlight may be located below the liquid crystal panel 1710. Figure 17B Not shown in the diagram. Optionally, in addition to liquid crystal display devices, the pixel driving circuit provided in this disclosure can also be applied to other suitable types of display devices. The pixel driving circuit 1720 can be the pixel driving circuit described in the various embodiments above, and can perform the pixel driving method described in the various embodiments above to drive the display screen 1710. The pixel driving circuit 1720 can be implemented, for example, in the form of a driver IC, and can be fixed on the circuit board 1730. Exemplarily, the circuit board 1730 can be a general printed circuit board (PCB) or a flexible circuit board (FPC). The driver IC can be fixed on the circuit board 1730 using COF (Chip On Film) technology, etc.

[0128] In addition, according to some embodiments of this disclosure, a computing device is also provided, which may include pixel driving circuitry 1600.

[0129] For example, Figure 18 An exemplary block diagram of a computing device 1800 according to some embodiments of the present disclosure is illustrated. As shown, the computing device 1800 may include a display screen 1810, a pixel driving device 1820, and a processor 1830. Exemplarily, the pixel driving device 1820 may receive various display-related instructions and data from the processor through a suitable interface, and provide data voltage signals to individual pixels in the display screen based on these instructions and data to drive the corresponding pixels to display corresponding brightness. The pixel driving device 1820 may be the pixel driving circuit described in the various embodiments above, and may execute the pixel driving methods described in the various embodiments above. The display screen 1810 may be, for example, an LCD (Liquid Crystal Display) or other type of display screen. The processor 1830 may be a CPU (central processing unit), an MCU (Microcontroller Unit), or other form of processor.

[0130] It should be understood that the above-described display device and computing device may also have the same or similar implementation methods and advantages as the pixel driving method 100 described above, and will not be repeated here.

[0131] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims. Furthermore, in the claims, the word "comprising" does not exclude other elements or steps, and "a" or "an" does not exclude multiple. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used for profit.

Claims

1. A pixel driving method, comprising: Receive image data, the image data including pixel data for at least one pixel; Based on the pixel data for the target pixel in the image data, a data voltage signal for the target pixel is determined; In response to a first enable signal being active, the target pixel is driven in a first display mode. In the first display mode, the data voltage signal is updated at a first frequency, and the data voltage signal is provided to the target pixel, such that the driving voltage of the target pixel is determined as the voltage difference between the data voltage signal and a common voltage signal, wherein the common voltage signal is a reference voltage signal shared by all pixels. In response to a second enable signal being active, the target pixel is driven in a second display mode. In the second display mode, the data voltage signal is updated at a second frequency, the data voltage signal is adjusted according to pixel data for the target pixel, and an adjusted data voltage signal is provided to the target pixel, such that the driving voltage of the target pixel is determined to be either a maximum driving voltage or a minimum driving voltage, wherein the second frequency is lower than the first frequency. Wherein, the pixel data for the target pixel includes at least one valid data bit, and wherein adjusting the data voltage signal according to the pixel data for the target pixel and providing the adjusted data voltage signal to the target pixel, such that the driving voltage of the target pixel is determined to be a maximum driving voltage or a minimum driving voltage, includes: In response to the highest valid data bit in the at least one valid data bit being a first value, the data voltage signal is adjusted such that the driving voltage of the target pixel is determined to be the maximum driving voltage; In response to the highest valid data bit in the at least one valid data bit being a second value, the data voltage signal is adjusted such that the driving voltage of the target pixel is determined to be the minimum driving voltage.

2. The method according to claim 1, wherein, The step of adjusting the data voltage signal so that the driving voltage of the target pixel is determined to be the maximum driving voltage includes: During the initialization period, the data voltage signal is determined as the first voltage signal, and effective initialization control signals are provided to each pixel in sequence; During the display period, the data voltage signal is determined to be opposite to the common voltage signal, and a continuously effective display control signal is provided to the target pixel, such that the driving voltage of the target pixel is determined to be the voltage difference between the data voltage signal and the common voltage signal.

3. The method according to claim 1, wherein, The step of adjusting the data voltage signal so that the driving voltage of the target pixel is determined to be the minimum driving voltage includes: During the initialization period, the data voltage signal is determined as the second voltage signal, and effective initialization control signals are provided to each pixel in sequence; During the display period, a zero-difference voltage signal is provided to the target pixel, the zero-difference voltage signal being the same as the common voltage signal, and a continuously effective display control signal is provided to the target pixel, such that the driving voltage of the target pixel is determined to be the voltage difference between the zero-difference voltage signal and the common voltage signal.

4. The method according to claim 1, wherein, The step of determining the data voltage signal for the target pixel based on the pixel data for the target pixel in the image data includes: Cache pixel data for a preset number of pixels in the image data; According to the preset digital-to-analog conversion rules, the pixel data in the cached pixel data used for the target pixel is converted into a data voltage signal used for the target pixel.

5. The method according to claim 4, wherein, The cached image data includes: In response to the fact that the number of valid data bits in the pixel data for a preset number of pixels is greater than a first threshold, the pixel data for the preset number of pixels is compressed according to a preset compression rule so that the number of valid data bits in the compressed pixel data is not greater than the first threshold.

6. The method according to claim 5, wherein, The step of converting the pixel data for the target pixel in the cached pixel data into a data voltage signal for the target pixel includes: Decompress the compressed pixel data; The pixel data for the target pixel in the decompressed pixel data is converted into a data voltage signal for the target pixel.

7. The method according to claim 4, wherein, The cached image data includes: In response to the fact that the number of valid data bits in the pixel data for a preset number of pixels is less than a first threshold, the pixel data for the preset number of pixels is padded according to a first preset padding rule, so that the number of valid data bits in the padded image data is equal to the first threshold.

8. The method according to claim 7, wherein, The step of converting the pixel data for the target pixel in the cached pixel data into a data voltage signal for the target pixel includes: In response to the fact that the number of valid data bits in the pixel data for the target pixel electrode is less than a second threshold, the image data for the target pixel electrode is padded according to a second preset padding rule, so that the number of valid data bits in the padded pixel data is equal to the second threshold.

9. The method according to claim 8, wherein, The step of converting the pixel data for the target pixel in the cached pixel data into a data voltage signal for the target pixel also includes: In response to receiving pixel data for at least two pixels per clock cycle, the pixel data for the at least two pixels is reallocated into at least two sets of pixel data for different pixels.

10. The method according to claim 1, further comprising: In the first display mode, in response to receiving an instruction to switch to the second display mode, enable data for the second display mode is written to the mode register, and after a first preset time interval, the second enable signal is made valid based on the enable data in the mode register.

11. The method according to claim 1, further comprising: In the second display mode, in response to receiving new image data, the data voltage buffer is activated; The data voltage signal determined based on the new image data is written into the data voltage buffer; After a second preset time interval, the data voltage buffer is turned off.

12. The method according to claim 1, further comprising: In the second display mode, in response to receiving an instruction to switch to the first display mode, enable data for the first display mode is written to the mode register, and the data voltage buffer is enabled; Write the data voltage signal into the data voltage buffer; After a third preset time interval, the data voltage buffer is turned off; Based on the enable data in the mode register, the first enable signal is made valid.

13. The method according to claim 1, further comprising: In the first display mode, when the number of valid data bits in the pixel data used for the target pixel meets a first preset condition, in response to receiving an enable signal for the low-quality display mode, the low-quality display mode is used. In the low-quality display mode, in response to the highest valid data bit in the pixel data for the target pixel being a first value, the pixel data for the target pixel is set to a maximum value, and in response to the highest valid data bit in the pixel data for the target pixel being a second value, the pixel data for the target pixel is set to a minimum value.

14. The method according to claim 1, further comprising: In the first display mode, when the number of valid data bits in the pixel data used for the target pixel meets the second preset condition, the second enable signal is made valid before the screen is turned on.

15. The method according to claim 1, further comprising: In the first display mode, when the number of valid data bits in the pixel data for the target pixel meets the third preset condition, the data voltage signal for the target pixel is adjusted according to the preset binding point voltage, wherein the preset binding point voltage is used to specify the data voltage signal corresponding to at least one gray level.

16. The method according to claim 1, wherein, The received image data includes: After the device is powered on and initialized, and before the screen lights up, it receives initialization image data and determines initialization voltage signals for each pixel based on the initialization image data.

17. The method according to claim 1, wherein, The received image data includes: According to preset interface rules, a first interface or a second interface is selected to receive the image data based on the display mode and / or the number of valid data bits in the pixel data, wherein the first interface and the second interface have different data transmission rates.

18. A pixel driving circuit, comprising: The data interface is configured to receive image data, the image data including pixel data for at least one pixel; The data processing circuit is configured to: determine a data voltage signal for the target pixel based on pixel data for the target pixel in the image data; The pixel electrode driving circuit includes a first charging circuit and a second charging circuit. The first charging circuit is configured to: drive the target pixel in a first display mode in response to a first enable signal being active; update the data voltage signal at a first frequency in the first display mode; and provide the data voltage signal to the target pixel, such that the driving voltage of the target pixel is determined as the voltage difference between the data voltage signal and a common voltage signal, wherein the common voltage signal is a reference voltage signal shared by all pixels. The second charging circuit is configured to: drive the target pixel in a second display mode in response to a second enable signal being active; update the data voltage signal at a second frequency in the second display mode; adjust the data voltage signal according to pixel data for the target pixel; and provide the adjusted data voltage signal to the target pixel, such that the driving voltage of the target pixel is determined to be either the maximum driving voltage or the minimum driving voltage; wherein the second frequency is lower than the first frequency. Wherein, the pixel data for the target pixel includes at least one valid data bit, and wherein the second charging circuit includes: A latch is configured to latch the most significant data bit among the at least one significant data bits; The mode selection circuit is configured to: adjust the data voltage signal in response to the highest valid data bit among the at least one valid data bits being a first value, such that the driving voltage of the target pixel is determined to be a maximum driving voltage; and adjust the data voltage signal in response to the highest valid data bit among the at least one valid data bits being a second value, such that the driving voltage of the target pixel is determined to be a minimum driving voltage.

19. The pixel driving circuit according to claim 18, wherein, The data processing circuit includes: A buffer circuit is configured to buffer pixel data for a preset number of pixels in the image data; The digital-to-analog converter circuit is configured to convert the pixel data for the target pixel in the cached pixel data into a data voltage signal for the target pixel.

20. The pixel driving circuit according to claim 18, further comprising: A data voltage buffer is configured to buffer the data voltage signal in the second display mode.

21. A display device, comprising: The pixel driving circuit according to claim 18; A liquid crystal panel includes a plurality of pixels and is configured to receive data voltage signals from the pixel driving circuit. A backlight panel is configured to provide backlighting for the liquid crystal panel.

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