Interrupt handling systems, components, devices, methods, apparatuses, and storage media

Abstract

The present disclosure provides an interrupt processing system, component, device, method, apparatus and storage medium, wherein the interrupt processing system comprises: a first register for recording masking status information of each interrupt vector; a second register for recording the corresponding relationship between the interrupt event and the interrupt vector; a third register for recording the masking status information of each interrupt event, wherein the masking status information in the third register is obtained synchronously from the first register according to the corresponding relationship in the second register; and a control circuit for determining whether to send an interrupt request of the first interrupt event to the host after the first interrupt event is generated, according to the masking status information of the first interrupt event recorded in the third register, wherein the interrupt request carries the interrupt vector information corresponding to the first interrupt event. Based on the interrupt processing system provided by the present disclosure, multiple interrupt events can be configured to correspond to the same interrupt vector, thereby reducing the physical resource requirements of the interrupt vector.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to an interrupt processing system, an electronic component, an electronic device, an interrupt configuration method, an interrupt configuration device, an electronic device, and a readable storage medium. Background Art

[0002] Interrupt technology is one of the important technologies in modern computer systems. As a method of communication between the CPU and its external devices, interrupt technology enables system software with serial operation characteristics to schedule various components in the system more reasonably, make full use of CPU resources, improve system efficiency, and realize more complex system functions.

[0003] In a system based on the PCIe bus, two interrupt modes, MSI (Message Signaled Interrupt) and MSIX (Message Signaled Interrupt eXtended), are usually supported. In the MSI / MSIX mode, each function (functional module) of the slave is assigned a certain number of interrupt vectors. Each function needs to bind the assigned interrupt vectors to the interrupt events it supports one by one, and then use the interrupt vectors to report the corresponding interrupt events to the host. In the MSI mode, each function of the slave can be assigned up to 32 interrupt vectors, while in the MSIX mode, each function of the slave can be assigned up to 2048 interrupt vectors, which can basically meet the number of interrupt vectors required by any function.

[0004] However, for each interrupt vector assigned to it, each function needs to deploy a register of at least 128 bits (or 97 bits) in length within the function for the configuration and use of the corresponding interrupt vector. This places high physical resource requirements on the slave, especially when the slave supports many functions and each function supports multiple interrupt events. This will cause a heavy physical resource burden on the slave and increase the control complexity and circuit delay of the slave. Summary of the invention

[0005] The purpose of the present disclosure is to provide an interrupt processing system, component, device, method, apparatus and storage medium, aiming to reduce the demand of interrupt technology on physical resources.

[0006] According to one aspect of the present disclosure, there is provided an interrupt processing system, the system comprising:

[0007] The first register is used to record the mask status information of each interrupt vector;

[0008] The second register is used to record the corresponding relationship between the interrupt event and the interrupt vector;

[0009] A third register is used to record the masking status information of each interrupt event; the masking status information in the third register is synchronously obtained from the first register according to the corresponding relationship in the second register;

[0010] A control circuit is used to determine whether to send an interrupt request of the first interrupt event to the host after a first interrupt event is generated, based on the masking status information of the first interrupt event recorded in the third register, wherein the interrupt request carries interrupt vector information corresponding to the first interrupt event.

[0011] In a feasible implementation of the present disclosure, the first register, the second register, the third register and the control circuit are all located in the slave machine.

[0012] In a feasible implementation of the present disclosure, the length of the first register corresponds to the number of interrupt vectors allocated to the slave, and the length of the third register corresponds to the number of interrupt events supported by the slave.

[0013] In a feasible implementation of the present disclosure, the second register is specifically used to record an interrupt vector number corresponding to each interrupt event.

[0014] In a feasible implementation of the present disclosure, each interrupt event corresponds to a second register, and each second register is specifically used to record an interrupt vector number corresponding to the corresponding interrupt event.

[0015] In a feasible implementation of the present disclosure, the control circuit is further used to synchronize the masking status information in the first register to the third register according to the corresponding relationship between the interrupt event and the interrupt vector after the second register is configured with the corresponding relationship.

[0016] In a feasible implementation of the present disclosure, the control circuit is specifically configured to: if the masking status information of the first interrupt event indicates that the first interrupt event is not masked by the host, send an interrupt request of the first interrupt event to the host.

[0017] In a feasible implementation of the present disclosure, the system further includes:

[0018] The fourth register is used to record the suspension status information of each interrupt event;

[0019] The fifth register is used to record the suspension status information of each interrupt vector;

[0020] The control circuit is also specifically used for: if the masking status information of the first interrupt event indicates that the first interrupt event is masked by the host, then setting the suspension status information of the first interrupt event in the fourth register to a first preset value, and according to the corresponding relationship in the second register, synchronizing the first preset value of the first interrupt event in the fourth register to the fifth register, and according to the first preset value recorded in the fifth register, reporting the suspension message of the corresponding interrupt vector to the host.

[0021] In a feasible implementation of the present disclosure, the fourth register and the fifth register are both located in the slave device.

[0022] In a feasible implementation of the present disclosure, the length of the fourth register corresponds to the number of interrupt events supported by the slave, and the length of the fifth register corresponds to the number of interrupt vectors allocated to the slave.

[0023] In a feasible implementation of the present disclosure, the system further includes a sixth register for recording interrupt status information of an interrupt event, wherein the interrupt status information of an interrupt event indicates whether the interrupt event has occurred and has not been processed by the host.

[0024] In a feasible implementation of the present disclosure, the sixth register is located in the slave device.

[0025] In a feasible implementation of the present disclosure, the system also includes the host, which is used to query the sixth register after receiving the interrupt request / suspend message based on the interrupt vector information carried in the interrupt request / suspend message and the correspondence between the interrupt vector and the interrupt event stored in the host.

[0026] According to another aspect of the present disclosure, an electronic component is also provided, which includes the interrupt processing system described in any of the above embodiments. In some usage scenarios, the product form of the electronic component is a graphics card; in other usage scenarios, the product form of the electronic component is a component including a CPU motherboard and a graphics card.

[0027] According to another aspect of the present disclosure, an electronic device is also provided, which includes the above-mentioned electronic component. In some usage scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some usage scenarios, the product form of the electronic device is a personal computer, a game console, etc.

[0028] According to another aspect of the present disclosure, there is also provided an interrupt configuration method, the method comprising:

[0029] Receiving a first configuration of a first register, wherein the first configuration is used to configure mask state information of each interrupt vector;

[0030] receiving a second configuration of a second register, wherein the second configuration is used to configure a correspondence between an interrupt event and an interrupt vector;

[0031] According to the corresponding relationship in the second register, the masking status information in the first register is configured to a third register, and the third register is used to record the masking status information of each interrupt event.

[0032] In a feasible implementation of the present disclosure, the first register, the second register and the third register are all located in the slave.

[0033] In a feasible implementation of the present disclosure, the method further includes:

[0034] A third configuration of a first storage unit is received, wherein the third configuration is used to configure a correspondence between an interrupt event of a slave and an interrupt vector, and the first storage unit is located in a host.

[0035] In a feasible implementation of the present disclosure, the method further includes:

[0036] The data bits corresponding to each interrupt event in the fourth register are initialized to a second preset value, where the second preset value indicates that the corresponding interrupt event is not suspended.

[0037] In a feasible implementation of the present disclosure, the fourth register is located in the slave device.

[0038] According to another aspect of the present disclosure, there is also provided an electronic device, the electronic device comprising a memory and a processor;

[0039] The memory is used to store application programs;

[0040] The processor is used to run the application stored in the memory to implement the interrupt configuration method described in the first aspect or any feasible implementation manner of the first aspect.

[0041] According to another aspect of the present disclosure, a computer-readable storage medium is further provided, wherein an application is stored in the computer-readable storage medium, and when the application is executed by a processor, the interrupt configuration method described in the first aspect or any feasible implementation manner of the first aspect is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of the structure of an interrupt processing system provided by an embodiment of the present disclosure;

[0043] Figure 2A schematic diagram of the structure of an interrupt processing system provided by another embodiment of the present disclosure;

[0044] Figure 3 A schematic diagram of the structure of an interrupt processing system provided by another embodiment of the present disclosure;

[0045] Figure 4 A schematic diagram of the structure of an interrupt processing system provided by another embodiment of the present disclosure;

[0046] Figure 5 A flowchart of an interrupt configuration method provided by an embodiment of the present disclosure;

[0047] Figure 6 A schematic diagram of the structure of an interrupt configuration device provided by an embodiment of the present disclosure;

[0048] Figure 7 It is a structural block diagram of an electronic device proposed in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] Before introducing the embodiments of the present disclosure, it should be noted that:

[0050] Some embodiments of the present disclosure are described as processing flows. Although the various operation steps of the flow may be given sequential step numbers, the operation steps therein may be implemented in parallel, concurrently or simultaneously.

[0051] In the embodiments of the present disclosure, the terms "first", "second", etc. may be used to describe various features, but these features should not be limited by these terms. These terms are used only to distinguish one feature from another.

[0052] The term “and / or” may be used in embodiments of the present disclosure. “And / or” includes any and all combinations of one or more of the associated features listed.

[0053] It should be understood that when describing the connection or communication relationship between two components, unless it is explicitly stated that the two components are directly connected or directly communicating, the connection or communication between the two components can be understood as direct connection or communication, or as indirect connection or communication through an intermediate component.

[0054] In order to make the technical solutions and advantages of the embodiments of the present disclosure more clearly understood, the exemplary embodiments of the present disclosure are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0055] In a system based on the PCIe (peripheral component interconnect express) bus, the host (also referred to as the host) and the slave (also referred to as the EP) are connected via a PCIe Link. A slave may include one or more functions, which may be understood as functional modules, such as encoding modules, decoding modules, encryption modules, decryption modules, etc. These functional modules may be physical functional modules or may be virtualized functional modules based on virtualization technology, which is not limited in the present disclosure. It should be noted that, relative to the host, the slave itself (and the EP) belongs to the slave corresponding to the host, and the function in the slave may actually be understood as the slave corresponding to the host. Therefore, the "slave" described in the present disclosure below may generally be understood as a function, but may also be understood as an actual slave (EP).

[0056] The above systems usually support two interrupt modes, MSI and MSIX. In the MSI / MSIX mode, each function of the slave is assigned a certain number of interrupt vectors. Each function needs to bind the assigned interrupt vectors to the interrupt events it supports one by one, and then use the interrupt vectors to report the corresponding interrupt events to the host. In the MSI mode, each function of the slave can be assigned up to 32 interrupt vectors. However, with the increase in system functionality, complexity, and the number of peripherals, the number of interrupt events supported by some functions has far exceeded 32, which has resulted in 32 interrupt vectors no longer being able to meet the needs of the function. Therefore, PCIe proposed an extended mode of MSI, MSIX. In the MSIX mode, each function of the slave can be assigned up to 2048 interrupt vectors.

[0057] On the surface, MSIX can already support the need for a function to have thousands of interrupt events. However, for each interrupt vector assigned to each function, a register of at least 128 bits (or 97 bits) in length needs to be deployed in the function for the configuration and use of the corresponding interrupt vector, which places high physical resource requirements on the slave, especially when the slave supports many functions and each function supports multiple interrupt events, which will cause a great physical resource burden on the slave and increase the control complexity and circuit delay of the slave.

[0058] In order to reduce the demand for physical resources of interrupt technology, the present disclosure provides an interrupt processing system. Figure 1 As shown, the interrupt processing system includes:

[0059] The first register is used to record the mask status information of each interrupt vector;

[0060] The second register is used to record the corresponding relationship between the interrupt event and the interrupt vector;

[0061] The third register is used to record the mask status information of each interrupt event; the mask status information in the third register is synchronously obtained from the first register according to the corresponding relationship in the second register;

[0062] The control circuit is used to determine whether to send an interrupt request of the first interrupt event to the host after the first interrupt event is generated, according to the masking status information of the first interrupt event recorded in the third register, and the interrupt request carries the interrupt vector information corresponding to the first interrupt event.

[0063] The present disclosure can be applied to the MSI mode. In the MSI mode, the function of the slave machine will be assigned an MSI vector, and the interrupt vector described in the present disclosure can be understood as the MSI vector in the MSI mode. In addition, the present disclosure can also be applied to the MSIX mode. In the MSIX mode, the function of the slave machine will be assigned an entry, and the interrupt vector described in the present disclosure can be understood as the entry in the MSIX mode. It should be noted that the present disclosure can also be applied to other interrupt modes, and the interrupt vector in the present disclosure can be interpreted accordingly based on the interrupt mode applied by the present disclosure.

[0064] The first register is used to record the masking status information of each interrupt vector, and the masking status information of each interrupt vector indicates whether the host masks the interrupt vector. For example, if the host does not want to process a certain interrupt vector of a function temporarily, the host can set the masking status information of the interrupt vector in the first register to a first preset value (for example, the first preset value is equal to 1), thereby masking the interrupt vector. It should be noted that, since the interrupt vector has a corresponding relationship with the interrupt event, the host's masking of a certain interrupt vector is actually the masking of the corresponding interrupt event. In actual applications, the host can set the masking status information of the corresponding interrupt vector to the first preset value in order to mask a certain / certain interrupt events of a function. In MSI / MSIX mode, the masking status information of the interrupt vector can be understood as the mask bit in MSI / MSIX mode.

[0065] Each function may support one or more interrupt events. The interrupt events supported by different functions are usually not exactly the same. The present disclosure does not limit which interrupt events each function supports.

[0066] The control circuit in the present disclosure may be a circuit generated by synthesizing and placing and routing RTL (Register-Transfer Level) codes in sequence. Specifically, according to the functions to be implemented by the control circuit in the present disclosure, RTL codes that can implement the corresponding functions may be written based on a hardware description language (such as Verilog), and then the RTL codes may be synthesized and placed and routed in sequence to obtain the control circuit in the present disclosure. Alternatively, the control circuit in the present disclosure may also be a general-purpose processor, which stores codes or instructions for implementing the corresponding functions, and the general-purpose processor implements the corresponding functions (i.e., the functions to be implemented by the control circuit in the present disclosure) by executing the codes or instructions stored therein.

[0067] In the present disclosure, on the one hand, the masking status information of each interrupt vector is recorded by the first register, so that the host can configure whether the interrupt vector is masked or not in the first register; and when the control circuit sends an interrupt request corresponding to the first interrupt event to the host, the interrupt request carries the interrupt vector corresponding to the first interrupt event; it can be seen that the host can continue to use the interrupt vector masking scheme and interrupt vector processing scheme in the MSI / MSIX mode, and the present disclosure can have better compatibility for the host side.

[0068] On the other hand, the correspondence between the interrupt event and the interrupt vector is recorded through the second register, and based on the correspondence, the mask status information in the first register is synchronized to the third register, thereby forming the mask status information of the corresponding interrupt event; after the first interrupt event is generated, the control circuit determines whether to send an interrupt request of the first interrupt event to the host according to the mask status information of the first interrupt event recorded in the third register; based on the above system, an interrupt vector can be bound to multiple interrupt events, and based on the correspondence recorded in the second register, the mask status information of an interrupt vector can be synchronized to the multiple interrupt events bound to it, so the function can support a large number of interrupt events while allocating a small number of interrupt vectors, thereby reducing the demand for physical resources of the interrupt technology.

[0069] In some specific embodiments, the first register, the second register, the third register and the control circuit are all located in the slave. More specifically, the first register, the second register, the third register and the control circuit can all be located in the function of the slave. For example, in a system based on a PCIe bus, one or more slaves are included, and each slave includes one or more functions. Then, each function of each slave is provided with a first register, a second register, a third register and a control circuit; or, a part of the functions of each slave is provided with a first register, a second register, a third register and a control circuit; or, a part or all of the functions of a part of the slaves are provided with a first register, a second register, a third register and a control circuit. Based on the interrupt processing system proposed in the present disclosure, the demand for physical resources of the slave by the interrupt technology can be reduced.

[0070] In some specific implementations, the length of the first register corresponds to the number of interrupt vectors assigned to the slave, and the length of the third register corresponds to the number of interrupt events supported by the slave. More specifically, the length of the first register corresponds to the number of interrupt vectors assigned to the function, and the length of the second register corresponds to the number of interrupt events supported by the function.

[0071] In specific implementation, if the present disclosure is applied to the MSI mode, such as Figure 2 As shown, function is assigned N interrupt vectors, the length of the first register is N bits, each bit of the first register corresponds to an interrupt vector vector, and is used to store the mask status information of the interrupt vector vector. Wherein, N is a positive integer greater than 0. For example, Figure 2 If the 3rd and 5th bits of the first register are 1, it means that the 3rd and 5th interrupt vectors of the function are blocked by the host. Figure 2 The control circuit is not shown.

[0072] like Figure 2 As shown, function supports M interrupt events, the length of the third register is M bits, each bit of the third register corresponds to an interrupt event, and is used to store the mask status information of the interrupt event. Wherein, M can be a positive integer greater than, equal to, or less than N, and usually M is greater than N. For example, Figure 2 If the 4th, 5th, 9th, 10th and 15th bits of the third register are all 1, it means that the 4th interrupt event, the 5th interrupt event, the 9th interrupt event, the 10th interrupt event and the 15th interrupt event of the function are masked by the host.

[0073] Each interrupt vector assigned to a function has a unique number. For example, Figure 2 The N interrupt vectors shown are numbered 1, 2...N. The second register is specifically used to record the interrupt vector number corresponding to each interrupt event. Each interrupt event corresponds to a second register, and each second register is specifically used to record the interrupt vector number corresponding to the corresponding interrupt event. In short, in the present disclosure, each data bit in the third register corresponds to an interrupt event, and each interrupt event corresponds to a second register, and each second register stores an interrupt vector number. Therefore, there is a corresponding relationship between the interrupt event corresponding to the second register and the interrupt vector recorded by the second register.

[0074] Specifically, the second register is used to record the binary number of the interrupt vector number. For example, the binary number recorded in the second register corresponding to the first interrupt event is 0001, indicating that the interrupt vector corresponding to the first interrupt event is the first interrupt vector. For example, the binary number recorded in the second register corresponding to the second interrupt event is also 0001, indicating that the interrupt vector corresponding to the second interrupt event is also the first interrupt vector. For example, the binary number recorded in the second register corresponding to the fourth interrupt event is 0011, indicating that the interrupt vector corresponding to the fourth interrupt event is the third interrupt vector. Figure 2 The dotted line in , represents the corresponding relationship between the second register and the interrupt event (or the data bit of the interrupt event in the third register).

[0075] exist Figure 2 In the interrupt processing system shown in the figure, since a small number of interrupt vectors (for example, within 30) can be used to meet the large number of interrupt events required by the function, the length of the second register corresponding to each interrupt event will not be too long (for example, no more than 5 bits); in addition, in the third register, each interrupt event only corresponds to one data bit of the third register; it can be seen that in Figure 2 In the interrupt processing system shown, each interrupt event requires only a small number of data bits, which is much smaller than the interrupt vector's requirement for register data bits.

[0076] In specific implementation, if the disclosure is applied to MSIX mode, such as Figure 3As shown, function is assigned N interrupt vectors, the length of the first register is divided into N segments, each segment of the first register corresponds to an interrupt vector entry, and is used to store the relevant information of the interrupt vector entry. The relevant information of each interrupt vector entry includes: mask status information, message address (message address) and message data (message data). Among them, N is a positive integer greater than 0, and the message address and message data of each interrupt vector are pre-configured by the host. For example, Figure 3 If the mask status information in the second section and the mask status information in the third section of the first register are both 1, it means that the second interrupt vector and the third interrupt vector of the function are masked by the host. Figure 3 The control circuit is not shown.

[0077] like Figure 3 As shown, function supports M interrupt events, the length of the third register is M bits, each bit of the third register corresponds to an interrupt event, and is used to store the mask status information of the interrupt event. Wherein, M can be a positive integer greater than, equal to, or less than N, and usually M is greater than N. For example, Figure 3 If the 3rd, 4th, 5th, 6th and 7th bits of the third register are all 1, it means that the 3rd interrupt event, the 4th interrupt event, the 5th interrupt event, the 6th interrupt event and the 7th interrupt event of the function are masked by the host.

[0078] Each interrupt vector assigned to a function has a unique number. For example, Figure 3 The N interrupt vectors shown are numbered 1, 2...N. The second register is specifically used to record the interrupt vector number corresponding to each interrupt event. Each interrupt event corresponds to a second register, and each second register is specifically used to record the interrupt vector number corresponding to the corresponding interrupt event. In short, in the present disclosure, each data bit in the third register corresponds to an interrupt event, and each interrupt event corresponds to a second register, and each second register stores an interrupt vector number. Therefore, there is a corresponding relationship between the interrupt event corresponding to the second register and the interrupt vector recorded by the second register.

[0079] Specifically, the second register is used to record the binary number of the interrupt vector number. For example, the binary number recorded in the second register corresponding to the first interrupt event is 0001, indicating that the interrupt vector corresponding to the first interrupt event is the first interrupt vector. For example, the binary number recorded in the second register corresponding to the second interrupt event is also 0001, indicating that the interrupt vector corresponding to the second interrupt event is also the first interrupt vector. For example, the binary number recorded in the second register corresponding to the fifth interrupt event is 0010, indicating that the interrupt vector corresponding to the fifth interrupt event is the second interrupt vector.

[0080] exist Figure 3 In the interrupt processing system shown in FIG. 1 , since a small number of interrupt vectors can be used to meet the large number of interrupt events required by the function, the length of the second register corresponding to each interrupt event will not be too long; in addition, in the third register, each interrupt event only corresponds to one data bit of the third register; it can be seen that in Figure 3 In the interrupt processing system shown, each interrupt event requires only a small number of data bits, which is much smaller than the interrupt vector's requirement for register data bits.

[0081] It should be noted that, in the above specific implementation, there are multiple second registers, each of which corresponds to an interrupt event. However, the present disclosure is not limited thereto, and there may be only one second register, which may be divided into multiple sections, each of which corresponds to an interrupt event (in other words, each section corresponds to a data bit in the third register), for recording the corresponding relationship between the interrupt event and the corresponding interrupt vector.

[0082] It should also be noted that in Figure 2 and Figure 3 In the specific implementation shown, the number of data bits of the first register (i.e., the number of bits of the first register) is equal to the number of interrupt vectors assigned to the function, and the number of data bits of the third register (i.e., the number of bits of the third register) is equal to the number of interrupt events supported by the function. However, the present disclosure is not limited to this, and the number of interrupt vectors assigned to the function should be less than or equal to the number of data bits of the first register, and the number of interrupt events supported by the function should be less than or equal to the number of data bits of the third register. For example, if the number of data bits of the first register in the function is N, the number of interrupt vectors assigned to the function by the host should not exceed N, wherein each interrupt vector corresponds to a data bit in the first register. For example, if the number of data bits of the third register in the function is M, the number of interrupt events supported by the function should not exceed M, wherein each interrupt event corresponds to a data bit in the third register.

[0083] In some specific implementations, the control circuit is further configured to synchronize the masking status information in the first register to the third register according to the corresponding relationship after the second register is configured with the corresponding relationship between the interrupt event and the interrupt vector.

[0084] In specific implementation, when the corresponding relationship between the interrupt event and the interrupt vector has been configured in the second register, if the shielding status information has also been configured in the first register, such as Figure 2 or Figure 3 As shown, the control circuit synchronizes the masking status information in the corresponding data bit / corresponding data segment in the first register to the corresponding data bit in the third register of the second register according to the interrupt vector number recorded in each second register. Figure 2 As shown, the control circuit synchronizes the mask status information 0 in the first data bit in the first register to the first data bit in the third register according to the interrupt vector number 0001 recorded in the first second register; the control circuit synchronizes the mask status information 0 in the first data bit in the first register to the second data bit in the third register according to the interrupt vector number 0001 recorded in the second second register; the control circuit synchronizes the mask status information 0 in the second data bit in the first register to the third data bit in the third register according to the interrupt vector number 0010 recorded in the third second register; the control circuit synchronizes the mask status information 1 in the third data bit in the first register to the fourth data bit in the third register according to the interrupt vector number 0011 recorded in the fourth second register, and the synchronization method for the remaining data bits is similar.

[0085] In addition, when the correspondence between interrupt events and interrupt vectors has been configured in the second register, if the masking status information has not been configured in the first register at this time, the control circuit can also synchronize the initial masking status information (i.e., the default value) in the corresponding data bit / corresponding data segment in the first register to the corresponding data bit of the second register in the third register according to the interrupt vector number recorded in each second register.

[0086] In addition, after the correspondence between the interrupt event and the interrupt vector has been configured in the second register, if the mask status information in the first register is updated, the mask status information in the corresponding data bit / corresponding data segment in the first register is synchronized to the corresponding data bit of the second register in the third register according to the interrupt vector number recorded in each second register; or only the updated mask status information is synchronized to the corresponding data bit in the third register.

[0087] In the present disclosure, the control circuit is used to send an interrupt request to the host. Specifically, after a first interrupt event is generated, if the masking status information of the first interrupt event indicates that the first interrupt event is not masked by the host, the interrupt request of the first interrupt event is sent to the host. The first interrupt event is any one of the one or more interrupt events supported by the function.

[0088] by Figure 2 Taking the interrupt processing system in the MSI mode shown as an example, after the first interrupt event is generated (assuming that the first interrupt event is the 6th interrupt event), the control circuit checks the 6th bit in the third register. Since the 6th bit in the third register is equal to 0, it means that the 6th interrupt event is not masked by the host, so the control circuit generates an interrupt request for the 6th interrupt event. When the control circuit generates an interrupt request for the 6th interrupt event, it generates an interrupt request according to the interrupt vector number 0100 recorded in the second register corresponding to the 6th interrupt event. The interrupt request includes message data and interrupt vector number 0100, wherein message data is pre-configured by the host to the function. Then the control circuit writes the interrupt request containing message data and interrupt vector number 0100 to the MSIMessageAddress in the host memory space, and MSIMessage Address is also pre-configured by the host to the function.

[0089] by Figure 3 Taking the interrupt processing system in the MSIX mode shown as an example, after the first interrupt event is generated (assuming that the first interrupt event is the second interrupt event), the control circuit checks the second bit in the third register. Since the second bit in the third register is equal to 0, it means that the second interrupt event is not masked by the host, so the control circuit generates an interrupt request for the second interrupt event. When the control circuit generates an interrupt request for the second interrupt event, according to the interrupt vector number 0001 recorded in the second register corresponding to the second interrupt event, the control circuit queries a section of space corresponding to the interrupt vector number 0001 in the first register (i.e., the first section in the first register), the control circuit reads the message address and message data from the first section of the first register, and generates an interrupt request according to the interrupt vector number 0001 and the message data, and then the control circuit writes the interrupt request containing the message data and the interrupt vector number 0001 to the messageaddress of the host memory space.

[0090] In some specific embodiments, Figure 4 As shown, the interrupt handling system also includes:

[0091] The fourth register is used to record the suspension status information of each interrupt event;

[0092] The fifth register is used to record the suspension status information of each interrupt vector;

[0093] The control circuit is also specifically used for: if the shielding status information of the first interrupt event indicates that the first interrupt event is shielded by the host, the suspension status information of the first interrupt event in the fourth register is set to the first preset value, and according to the corresponding relationship in the second register, the first preset value of the first interrupt event in the fourth register is synchronized to the fifth register, and according to the first preset value recorded in the fifth register, the suspension message of the corresponding interrupt vector is reported to the host. Among them, the first preset value indicates that the interrupt request of the corresponding interrupt event / interrupt vector needs to be sent to the host for processing, but has not yet been sent to the host. In the MSI / MSIX mode, the shielding status information can be understood as the pending bit in the MSI / MSIX mode.

[0094] In the present disclosure, the suspend state information has two forms: a first preset value and a second preset value. For example, the first preset value is equal to 1, and the second preset value is equal to 0. When the suspend state information is equal to 1, it means that the interrupt request of the corresponding interrupt event / interrupt vector needs to be sent to the host for processing, but has not yet been sent to the host. The suspend state information usually defaults to 0, that is, the initial value is 0.

[0095] In some specific implementations, the fourth register and the fifth register are both located in the slave. More specifically, the fourth register and the fifth register are both located in the function of the slave. For example, in a system based on a PCIe bus, including one or more slaves, each slave including one or more functions, each function of each slave is provided with a fourth register and a fifth register; or, a part of the functions of each slave is provided with a fourth register and a fifth register; or, a part or all of the functions of a part of the slaves are provided with a fourth register and a fifth register. Based on the interrupt processing system proposed in the present disclosure, the demand for physical resources of the slave by the interrupt technology can be reduced.

[0096] In some specific implementations, the length of the fourth register corresponds to the number of interrupt events supported by the slave, and the length of the fifth register corresponds to the number of interrupt vectors allocated to the slave. More specifically, the length of the fourth register corresponds to the number of interrupt events supported by the function, and the length of the fifth register corresponds to the number of interrupt vectors allocated to the function.

[0097] In specific implementation, if the present disclosure is applied to the MSI mode, such as Figure 2 As shown, function supports M interrupt events, the length of the fourth register is M bits, and each bit of the fourth register corresponds to an interrupt event and is used to store the suspension status information of the interrupt event. Figure 2 As shown, function is allocated N interrupt vectors, the length of the fifth register is N bits, each bit of the fifth register corresponds to an interrupt vector vector, and is used to store the suspension state information of the interrupt vector vector.

[0098] by Figure 2 Taking the interrupt processing system in the MSI mode shown as an example, after the first interrupt event is generated (assuming that the first interrupt event is the fourth interrupt event), the control circuit checks the fourth bit in the third register. Since the fourth bit in the third register is equal to 1, it means that the fourth interrupt event is masked by the host. Therefore, the control circuit sets the fourth bit in the fourth register to 1, indicating that the interrupt request of the fourth interrupt event needs to be sent to the host for processing, but it has not been sent to the host yet. Then, the control circuit updates the third bit in the fifth register from 0 to 1 according to the interrupt vector number 0011 recorded in the fourth second register. Then, the control circuit reports a suspend message to the host, and the suspend message is used to indicate that the third bit of the fifth register is 1.

[0099] by Figure 3 Taking the interrupt processing system in the MSIX mode shown as an example, after the first interrupt event is generated (assuming that the first interrupt event is the fifth interrupt event), the control circuit checks the fifth bit in the third register. Since the fifth bit in the third register is equal to 1, it means that the fifth interrupt event is blocked by the host. Therefore, the control circuit sets the fifth bit of the fourth register to 1, indicating that the interrupt request of the fifth interrupt event needs to be sent to the host for processing, but it has not been sent to the host yet. Then, the control circuit updates the second bit in the fifth register from 0 to 1 according to the interrupt vector number 0010 recorded in the fifth second register. Then, the control circuit reports a suspend message to the host, which is used to indicate that the second bit of the fifth register is 1.

[0100] It should be noted that in Figure 2 and Figure 3In the specific implementation shown, the number of data bits of the fourth register (i.e., the number of bits of the fourth register) is equal to the number of interrupt events supported by the function, and the number of data bits of the fifth register (i.e., the number of bits of the fifth register) is equal to the number of interrupt vectors assigned to the function. However, the present disclosure is not limited to this, and the number of interrupt vectors assigned to the function should be less than or equal to the number of data bits of the fifth register, and the number of interrupt events supported by the function should be less than or equal to the number of data bits of the fourth register. For example, if the number of data bits of the fifth register in the function is N, the number of interrupt vectors assigned to the function by the host should not exceed N, wherein each interrupt vector corresponds to a data bit in the fifth register. For example, if the number of data bits of the fourth register in the function is M, the number of interrupt events supported by the function should not exceed M, wherein each interrupt event corresponds to a data bit in the fourth register. In addition, in the specific implementation of the present disclosure, the number of data bits of the first register is usually equal to the number of data bits of the fifth register, and the number of data bits of the third register is usually equal to the number of data bits of the fourth register.

[0101] It should also be noted that the suspension status information of each interrupt vector is recorded through the fifth register, and the control circuit sends a suspension message to the host according to the suspension status information recorded in the fifth register, so that a part of the circuits in the control circuit of the present invention can continue to use the interrupt vector masking scheme in the MSI / MSIX mode, thereby having better compatibility.

[0102] In some specific embodiments, Figure 4 As shown, the interrupt processing system also includes a sixth register, which is used to record the interrupt status information of the interrupt event, and the interrupt status information of the interrupt event indicates whether the interrupt event has occurred and has not been processed by the host. The sixth register is located in the slave, and more specifically, the sixth register is located in the function of the slave.

[0103] In specific implementation, each interrupt event may correspond to a sixth register, and each sixth register is used to record the interrupt status information of the corresponding interrupt event. Alternatively, only one sixth register is set in the function, and each interrupt event corresponds to a data bit in the sixth register, and the data bit is used to record the interrupt status information of the corresponding interrupt event.

[0104] In some specific embodiments, Figure 4As shown, the interrupt processing system also includes a host, which is used to query the sixth register according to the interrupt vector information carried in the interrupt request / suspend message and the corresponding relationship between the interrupt vector and the interrupt event stored in the host after receiving the interrupt request / suspend message. The host and the slave can be connected through a bus (such as a PCIE bus).

[0105] In the present disclosure, the host queries the sixth register according to the corresponding relationship, so as to determine which interrupt event corresponding to the interrupt vector information has occurred. Figure 2 Taking the interrupt processing system shown as an example, assuming that the interrupt vector number included in the interrupt request received by the host is 0100, the host queries the interrupt events corresponding to the interrupt vector number 0100 according to the corresponding relationship between the interrupt vector and the interrupt event, including the 6th interrupt event, the 7th interrupt event and the 8th interrupt event. Then the host queries the sixth register corresponding to the 6th interrupt event, the sixth register corresponding to the 7th interrupt event and the sixth register corresponding to the 8th interrupt event in the function, or queries the data bit corresponding to the 6th interrupt event, the data bit corresponding to the 7th interrupt event and the data bit corresponding to the 8th interrupt event in the sixth register of the function, so as to determine which interrupt event corresponding to the interrupt vector 0100 has occurred, and then the corresponding interrupt event can be processed.

[0106] Alternatively, in some other specific implementations, after receiving an interrupt request / suspend message, the host queries the sixth register based on the corresponding relationship in the temporary configuration table in the host and the interrupt vector information carried in the interrupt request / suspend message, thereby determining which interrupt event corresponding to the interrupt vector information has occurred.

[0107] Alternatively, in some other specific implementations, the host does not need to pre-record or store the correspondence between the interrupt vector and the interrupt event. After receiving the interrupt request / suspend message, the host directly queries the sixth register to determine which interrupt event corresponding to the interrupt vector information has occurred.

[0108] The above specific implementation methods all belong to the case where one interrupt vector corresponds to multiple interrupt events. When one interrupt vector corresponds to only one interrupt event, after receiving the interrupt request / suspend message, the host may not query the sixth register, but may directly determine which interrupt event has occurred based on the interrupt request / suspend message.

[0109] The disclosed embodiment also provides an electronic component, which includes the interrupt processing system described in any of the above embodiments. In some usage scenarios, the product form of the electronic component is a graphics card; in other usage scenarios, the product form of the electronic component is a component including a CPU motherboard and a graphics card.

[0110] The disclosed embodiments also provide an electronic device, which includes the above-mentioned electronic components. In some usage scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some usage scenarios, the product form of the electronic device is a personal computer, a game console, a workstation, a server, etc.

[0111] The embodiment of the present disclosure also provides an interrupt configuration method, which is derived from the same inventive concept as the above-mentioned interrupt processing system, and the relevant parts can be referenced to each other. Figure 5 As shown, the interrupt configuration method includes the following steps:

[0112] S510: Receive a first configuration of a first register, where the first configuration is used to configure masking state information of each interrupt vector;

[0113] S520: Receive a second configuration for a second register, where the second configuration is used to configure a correspondence between an interrupt event and an interrupt vector;

[0114] S530: According to the corresponding relationship in the second register, the masking status information in the first register is configured to the third register, and the third register is used to record the masking status information of each interrupt event.

[0115] The first configuration operation on the first register may come from the host, or may also come from a user (such as a programmer). Similarly, the second configuration operation on the second register may come from the host, or may also come from a user (such as a programmer). The present disclosure does not limit the order of steps S510 and S520.

[0116] In some specific implementations, the first register, the second register, and the third register are all located in the slave.

[0117] In some specific implementations, the interrupt configuration method further includes: receiving a third configuration for the first storage unit, the third configuration being used to configure a correspondence between an interrupt event of the slave and an interrupt vector, and the first storage unit is located in the host.

[0118] In the present disclosure, the first storage unit is located in the host, and the user also needs to configure the correspondence between the interrupt vector and the interrupt event to the host, specifically to the first storage unit in the host, so that the first storage unit stores the correspondence between the interrupt vector and the interrupt event.

[0119] In some specific implementations, the interrupt configuration method further includes: initializing the data bits corresponding to each interrupt event in the fourth register to a second preset value, the second preset value indicating that the corresponding interrupt event is not suspended. The fourth register is located in the slave.

[0120] In the present disclosure, each interrupt event corresponds to a data bit in the fourth register, and each data bit is used to record the suspension status information of the corresponding interrupt event. If the suspension status information is the first preset value, it means that the corresponding interrupt event has occurred, but the corresponding interrupt request has not been sent to the host, that is, the corresponding interrupt event is suspended; if the suspension status information is the first preset value, it means that the corresponding interrupt event is not suspended.

[0121] The embodiment of the present disclosure also provides an interrupt configuration device, which is derived from the same inventive concept as the above-mentioned interrupt processing system and interrupt configuration method, and the relevant parts can be referenced to each other. Figure 6 As shown, the interrupt configuration device includes:

[0122] A first receiving module 610, configured to receive a first configuration of a first register, the first configuration being used to configure masking state information of each interrupt vector;

[0123] A second receiving module 620, configured to receive a second configuration of a second register, wherein the second configuration is used to configure a correspondence between an interrupt event and an interrupt vector;

[0124] The configuration module 630 is used to configure the masking status information in the first register to the third register according to the corresponding relationship in the second register, and the third register is used to record the masking status information of each interrupt event.

[0125] In some specific implementations, the first register, the second register, and the third register are all located in the slave.

[0126] In some specific embodiments, Figure 6 As shown, the interrupt configuration device also includes:

[0127] The third receiving module 640 is used to receive a third configuration of the first storage unit, where the third configuration is used to configure the correspondence between the interrupt event of the slave and the interrupt vector, and the first storage unit is located in the host.

[0128] In some specific implementations, the interrupt configuration device further includes:

[0129] The initialization module 650 is used to initialize the data bits corresponding to each interrupt event in the fourth register to a second preset value, where the second preset value indicates that the corresponding interrupt event is not suspended. The fourth register is located in the slave.

[0130] See also Figure 7 , Figure 7 It is a structural block diagram of an electronic device proposed in an embodiment of the present disclosure, wherein the electronic device 700 includes a processor 710, a memory 720, and one or more applications, wherein the one or more applications are stored in the memory 720 and configured to be executed by one or more processors 710, and the one or more programs are configured to execute the above-mentioned interrupt configuration method.

[0131] The processor 710 may include one or more processing cores. The processor 710 uses various interfaces and lines to connect the various parts of the entire electronic device 700, and executes various functions and processes data of the electronic device 700 by running or executing instructions, programs, code sets or instruction sets stored in the memory 720, and calling data stored in the memory 720. Optionally, the processor 710 can be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), and programmable logic array (Programmable Logic Array, PLA). The processor 710 can integrate one or a combination of a central processing unit (Central Processing Unit, CPU), a graphics processor (Graphics Processing Unit, GPU) and a modem. Among them, the CPU mainly processes the operating system, user interface and application programs; the GPU is responsible for rendering and drawing display content; and the modem is used to process wireless communications. It can be understood that the above-mentioned modem may not be integrated into the processor 710, but may be implemented separately through a communication chip.

[0132] The memory 720 may include a random access memory (RAM) or a read-only memory (Read-Only Memory). The memory 720 may be used to store instructions, programs, codes, code sets or instruction sets. The memory 720 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above-mentioned various method embodiments, etc. The data storage area may also store data created by the electronic device 700 during use, etc.

[0133] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0134] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram and the combination of processes and / or blocks in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the process in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0135] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0136] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0137] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit its protection scope. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the field should understand that after reading the present invention, those skilled in the art can still make various changes, modifications or equivalent substitutions to the specific implementation methods of the invention, but these changes, modifications or equivalent substitutions are all within the protection scope of the pending claims of the invention.

[0138] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0139] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. An interrupt processing system, the system comprising: The first register is used to record the mask status information of each interrupt vector; The second register is used to record the corresponding relationship between the interrupt event and the interrupt vector; The third register is used to record the mask status information of each interrupt event; The masking state information in the third register is synchronously obtained from the first register according to the corresponding relationship in the second register; a control circuit, configured to determine, after a first interrupt event is generated, whether to send an interrupt request of the first interrupt event to a host according to the masking status information of the first interrupt event recorded in the third register, wherein the interrupt request carries interrupt vector information corresponding to the first interrupt event; The control circuit is further configured to synchronize the masking state information in the first register to the third register according to the corresponding relationship between the interrupt event and the interrupt vector after the second register is configured with the corresponding relationship; The first register, the second register, the third register and the control circuit are all located in the slave.

2. The system according to claim 1, wherein the length of the first register corresponds to the number of interrupt vectors allocated to the slave, and the length of the third register corresponds to the number of interrupt events supported by the slave.

3. The system according to claim 1, wherein the second register is specifically used to record an interrupt vector number corresponding to each interrupt event.

4. The system according to claim 3, wherein each interrupt event corresponds to one of the second registers, and each of the second registers is specifically used to record an interrupt vector number corresponding to the corresponding interrupt event.

5. According to the system according to any one of claims 1 to 4, the control circuit is specifically used to: if the masking status information of the first interrupt event indicates that the first interrupt event is not masked by the host, send an interrupt request of the first interrupt event to the host.

6. The system according to claim 5, further comprising: The fourth register is used to record the suspension status information of each interrupt event; The fifth register is used to record the suspension status information of each interrupt vector; The control circuit is also specifically used for: if the masking status information of the first interrupt event indicates that the first interrupt event is masked by the host, then setting the suspension status information of the first interrupt event in the fourth register to a first preset value, and according to the corresponding relationship in the second register, synchronizing the first preset value of the first interrupt event in the fourth register to the fifth register, and according to the first preset value recorded in the fifth register, reporting the suspension message of the corresponding interrupt vector to the host. 7 . The system according to claim 6 , wherein the fourth register and the fifth register are both located in the slave device.

8. The system according to claim 6, wherein the length of the fourth register corresponds to the number of interrupt events supported by the slave, and the length of the fifth register corresponds to the number of interrupt vectors allocated to the slave.

9. The system according to any one of claims 1 to 4, further comprising a sixth register for recording interrupt status information of an interrupt event, wherein the interrupt status information of an interrupt event indicates whether the interrupt event has occurred and has not been processed by the host.

10. The system according to claim 9, wherein the sixth register is located in the slave.

11. The system according to claim 9 further comprises the host, which is used to query the sixth register after receiving an interrupt request / suspend message according to the interrupt vector information carried in the interrupt request / suspend message and the correspondence between the interrupt vector and the interrupt event stored in the host.

12. An electronic assembly comprising the system according to any one of claims 1 to 11.

13. An electronic device comprising the electronic component according to claim 12.

14. An interrupt configuration method, the method comprising: Receiving a first configuration of a first register, wherein the first configuration is used to configure mask state information of each interrupt vector; receiving a second configuration of a second register, wherein the second configuration is used to configure a correspondence between an interrupt event and an interrupt vector; The control circuit configures the masking status information in the first register to a third register according to the corresponding relationship in the second register, and the third register is used to record the masking status information of each interrupt event; The control circuit, the first register, the second register and the third register are all located in the slave.

15. The method according to claim 14, further comprising: A third configuration of a first storage unit is received, wherein the third configuration is used to configure a correspondence between an interrupt event of a slave and an interrupt vector, and the first storage unit is located in a host.

16. The method according to claim 14, further comprising: The data bits corresponding to each interrupt event in the fourth register are initialized to a second preset value, where the second preset value indicates that the corresponding interrupt event is not suspended. The method according to claim 16 , wherein the fourth register is located in the slave device.

18. An electronic device, comprising a memory and a processor; The memory is used to store application programs; The processor is used to run the application stored in the memory to implement the interrupt configuration method according to any one of claims 14 to 17.

19. A computer-readable storage medium, wherein an application is stored in the computer-readable storage medium, and when the application is executed by a processor, the interrupt configuration method according to any one of claims 14 to 17 is implemented.

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