A semiconductor device and a manufacturing method thereof

Abstract

The application provides a semiconductor device and a manufacturing method thereof, the semiconductor device comprising: a substrate, a source, a drain, a gate and a channel structure arranged on one side of the substrate, the channel structure comprising a plurality of nanosheet formed stacks, and the gate surrounding the nanosheet. In the application, the substrate can comprise a first substrate and a second substrate arranged in sequence, wherein the first substrate is a semiconductor material, and the second substrate is an insulating material, that is, the substrate of the application is a semiconductor-on-insulator substrate, so that the performance of the GAAFET can be optimized. The semiconductor device provided by the application comprises an isolation structure arranged between the channel structure and the second substrate, and the isolation structure extends to the source and the drain in a direction parallel to the plane where the substrate is located, so that effective isolation is formed between the substrate, the gate, the drain and the source, and the parasitic channel leakage of the substrate is inhibited by using the isolation structure, thereby reducing the off-state leakage current of the device under a shorter gate length and improving the overall performance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] With the development of semiconductor technology, the feature size of integrated circuits continues to shrink. Traditional triple-gate or double-gate Fin Field-Effect Transistors (FinFETs) are limited at nodes below 3 nanometers (nm). Since Nanosheet-Gate all-round Fin Field-Effect Transistors (Nanosheet-GAAFETs) have broken through the 3 nm node limitation, they have received widespread attention and research.

[0003] Nanosheet-GAAFET is a novel device featuring a gate-around structure and horizontal nanosheets (NS) as the conductive channel. In terms of gate control, the gate-around structure offers superior gate control compared to FinFET devices, effectively suppressing short-channel effects. Regarding current drive, Nanosheet-GAAFET exhibits bulk inversion carriers, and the increased effective gate width and vertical nanosheet stacking design significantly enhance the device's current drive performance.

[0004] Currently, Nanosheet-GAAFETs can be divided into two categories based on substrate material: GAAFETs based on bulk silicon substrates (Bulk-Si) and GAAFETs based on silicon-on-insulators (SOI). Compared to GAAFETs based on bulk silicon substrates, GAAFETs based on SOI can effectively simplify the manufacturing process and suppress leakage current in Bulk-Si, thus showing great application potential.

[0005] However, GAAFETs based on silicon-on-insulator still suffer from leakage problems due to parasitic channels at the bottom, which reduces the device performance of GAAFETs based on silicon-on-insulator. Summary of the Invention

[0006] In view of this, the purpose of this application is to provide a semiconductor device and a method for manufacturing the same, which can suppress parasitic channel leakage current, reduce device off-state leakage current, and improve the overall performance of the device.

[0007] This application provides a semiconductor device, the semiconductor device comprising: The substrate includes a first substrate and a second substrate stacked sequentially, wherein the first substrate is a semiconductor material and the second substrate is an insulating material; A source, a drain, and a channel structure are disposed on one side of the substrate, the channel structure being located between the source and the drain, and the channel structure comprising a stack of multiple nanosheets. An isolation structure is disposed between the channel structure and the second substrate, and extends to the source and the drain in a direction parallel to the plane of the substrate; A gate, which surrounds the nanosheet.

[0008] As one possible implementation, in a direction parallel to the plane of the substrate, one side of the isolation structure is in contact with the source electrode, and the other side of the isolation structure is in contact with the drain electrode.

[0009] In one possible implementation, the substrate includes a third substrate located on the side of the second substrate away from the first substrate, wherein the third substrate does not overlap with the source and the drain, and the material of the third substrate is a semiconductor material; The third substrate is covered by the isolation structure, and the third substrate, the source, and the drain are separated by the isolation structure.

[0010] In one possible implementation, the substrate includes a third substrate located on the side of the second substrate away from the first substrate, the third substrate not overlapping the source and the drain, and the material of the third substrate being a semiconductor material; the isolation structure includes a first isolation structure and a second isolation structure; The third substrate is located between the channel structure and the second substrate. A first isolation structure is provided between the third substrate and the source electrode, and a second isolation structure is provided between the third substrate and the drain electrode.

[0011] As one possible implementation, in a direction parallel to the plane of the substrate, the first isolation structure and the second isolation structure include a first sidewall near the channel structure, and the first sidewall and the sidewall of the channel structure are flush in a direction perpendicular to the plane of the substrate.

[0012] As one possible implementation, the isolation structure includes a first isolation portion and a second isolation portion, wherein the first isolation portion is located on the side of the second isolation portion away from the substrate; In a direction parallel to the plane of the substrate, the first isolation portion includes a second sidewall away from the channel structure, and the second isolation portion includes a third sidewall away from the channel structure. The second sidewall and the third sidewall are not flush in a direction perpendicular to the plane of the substrate, and the third sidewall is disposed on the side of the second sidewall near the source or the drain.

[0013] As one possible implementation, the isolation structure is made of a low-k dielectric material.

[0014] This application provides a method for manufacturing a semiconductor device, the method comprising: A substrate is provided, and a plurality of stacked structures consisting of alternating layers of a first semiconductor layer and a second semiconductor layer are formed on one side of the substrate; the substrate includes a first substrate, a second substrate and a third substrate stacked sequentially, wherein the first substrate and the third substrate are semiconductor materials and the second substrate is an insulating material; The stacked structure and a portion of the thickness of the third substrate are etched to form a source region and a drain region, with a channel region between the source region and the drain region; The third substrate located in the source region and the drain region is etched away. On a plane parallel to the substrate, all or part of the third substrate is etched away in the direction toward the channel region to form a groove. The groove completely or partially separates the stacked structure and the second substrate. The groove is filled with insulating material to form an isolation structure; A source and a drain are formed in the source region and the drain region, respectively. An isolation structure is disposed between the stacked structure and the second substrate. The isolation structure extends to the source and the drain in a direction parallel to the plane of the substrate. The first semiconductor layer is replaced with a gate, which surrounds the second semiconductor layer, and a stack of multiple second semiconductor layers forms a channel structure.

[0015] As one possible implementation, the etching removal of the third substrate located in the source region and the drain region, wherein all or part of the third substrate is etched away in a plane parallel to the substrate, along a direction toward the channel region, to form a groove, includes: The third substrate located in the source region and the drain region is removed by anisotropic etching process; On a plane parallel to the substrate, an isotropic etching process is used to etch away all or part of the third substrate along the direction toward the channel region, forming a groove.

[0016] As one possible implementation, the method further includes, prior to etching away the third substrate located in the source region and the drain region: In a direction parallel to the plane of the substrate, a portion of the first semiconductor layer is etched away to form an inward recess; A protective sidewall is formed in the inward recess, and the protective sidewall covers a portion of the third substrate; The method of etching away the third substrate located in the source region and the drain region using anisotropic etching technology includes: The third substrate, which is not covered by the protective sidewall, is removed by etching using anisotropic etching technology in the source region and the drain region. The step of filling the groove with insulating material to form an isolation structure includes: An insulating material is filled into the groove, and an isolation structure is formed by self-aligned etching. The isolation structure includes a first isolation portion and a second isolation portion, wherein the first isolation portion is located on the side of the second isolation portion away from the substrate. In a direction parallel to the plane of the substrate, the first isolation portion includes a second sidewall away from the channel region, the second isolation portion includes a third sidewall away from the channel region, the second sidewall and the third sidewall are not flush in a direction perpendicular to the plane of the substrate, the third sidewall is flush with the sidewall of the protective sidewall, and the third sidewall is disposed on the side of the second sidewall near the source region or the drain region.

[0017] This application provides a semiconductor device comprising: a substrate; a source, a drain, a gate, and a channel structure disposed on one side of the substrate; the channel structure being located between the source and the drain; and the channel structure comprising a stack of multiple nanosheets; with the gate surrounding the nanosheets. Thus, a basic GAAFET is constructed through the substrate, source, drain, gate, and channel structure. In this application, the substrate may include a first substrate and a second substrate stacked sequentially, wherein the first substrate is a semiconductor material and the second substrate is an insulating material; that is, the substrate of this application is a semiconductor-on-insulator substrate, which optimizes the performance of the GAAFET. The semiconductor device provided in this application includes an isolation structure disposed between the channel structure and the second substrate. The isolation structure extends to the source and drain in a direction parallel to the plane of the substrate, thus forming effective isolation between the substrate, gate, drain, and source. This isolation structure suppresses parasitic channel leakage current of the semiconductor substrate near the channel structure in GAAFET fabricated on a semiconductor-on-insulator substrate, thereby reducing the off-state leakage current of the device with a shorter gate length and improving the overall performance of the device. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of a cross-sectional structure of a GAAFET based on silicon-on-insulator is shown. Figure 2 A three-dimensional structural schematic diagram of a semiconductor device provided in an embodiment of this application is shown; Figure 3 and Figure 4 Provided for the embodiments of this application Figure 1 The diagram shows cross-sectional structures of a semiconductor device in various directions. Figure 5 This is a schematic diagram of another cross-sectional structure provided in an embodiment of this application; Figure 6 This is another schematic diagram of a cross-sectional structure provided in an embodiment of this application; Figure 7 A schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application is shown; Figure 8- Figure 32 A schematic diagram of the structure of a semiconductor device manufactured according to the manufacturing method of the semiconductor device provided in the embodiments of this application is shown. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0021] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0022] This application is described in detail with reference to the schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not according to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0023] Currently, Nanosheet-GAAFETs can be divided into two categories based on substrate material: GAAFETs based on bulk silicon substrates (Bulk-Si) and GAAFETs based on silicon-on-insulator (SOI).

[0024] In bulk silicon-based GAAFETs, the stacked nanosheets have thick sub-fins at the bottom, resulting in significant leakage current. To address this, the bulk silicon substrate typically employs heavily doped wells with doping types opposite to those of the source or drain to suppress parasitic channel leakage at the bottom of the source or drain and gate. However, in 5nm and below process nodes, the suppression capability of heavily doped wells for parasitic channel leakage decreases. Furthermore, bulk silicon-based GAAFETs may also experience leakage current issues due to bandgap tunneling (BTBT) between the source and drain via heavily doped wells.

[0025] GAAFETs based on silicon-on-insulator (SiI) have abundant substrate materials, so they do not require heavily doped wells or shallow trench isolation (STI) processes to form isolation media in the substrate, which greatly simplifies the manufacturing process, results in high process stability, and can improve the electrical stability of the manufactured GAAFETs by utilizing SiI.

[0026] The substrate material of the silicon-on-insulator (SAAFET) includes a bottom silicon layer, an insulating layer, and a top silicon layer 10 stacked sequentially. The top silicon layer 10 is covered by a channel structure, with the source and drain electrodes located on opposite sides of the top silicon layer 10. (Reference) Figure 1 As shown, as the gate length gradually decreases, the top silicon becomes a parasitic channel, leading to leakage problems and reducing the device performance of GAAFETs based on silicon-on-insulator.

[0027] Based on this, this application provides a semiconductor device. The substrate of this application includes a first substrate and a second substrate stacked together, which is a semiconductor-on-insulator (SIA) substrate, thus optimizing the performance of the GAAFET. The semiconductor device provided in this application includes an isolation structure disposed between the channel structure and the second substrate. In a direction parallel to the plane of the substrate, the isolation structure extends to the source and drain, thereby forming effective isolation between the substrate, gate, drain, and source. This isolation structure suppresses parasitic channel leakage current of the semiconductor substrate near the channel structure when fabricating a GAAFET on an SIA substrate, thereby reducing the off-state leakage current of the device with a shorter gate length and improving the overall performance of the device.

[0028] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0029] See Figure 2 The figure is a three-dimensional structural schematic diagram of a semiconductor device provided in an embodiment of this application.

[0030] The semiconductor device provided in this embodiment includes a substrate 110, a source 131, a drain 132, a channel structure, a gate 160, and an isolation structure 200.

[0031] In embodiments of this application, substrate 110 includes a first substrate 111, a second substrate 112, and a third substrate 113 stacked sequentially, wherein the third substrate 113 is located on the side of the second substrate 112 away from the first substrate 111, as shown in the reference. Figure 3 or Figure 4 As shown, the first substrate 111 and the third substrate 113 are semiconductor materials, such as silicon or germanium. The second substrate 112 is an insulating material, such as silicon oxide. The substrates of this application are semiconductor-on-insulator substrates, which can improve the performance of GAAFETs.

[0032] As an example, if the first substrate 111 is silicon, the second substrate 112 is silicon oxide, and the third substrate 113 is silicon, then the substrate 110 can be a silicon-on-insulator (SOI) substrate.

[0033] In the embodiments of this application, a source 131, a drain 132, and a channel structure are disposed on one side of the substrate 110. The channel structure is disposed between the source 131 and the drain 132. The channel structure includes a stack of multiple nanosheets. The channel structure is obtained by removing the first semiconductor layer 121 from the stacked structure. The stacked structure is composed of alternating layers of the first semiconductor layer 121 and the second semiconductor layer 122. That is, the nanosheets in the channel structure are the second semiconductor layer 122 in the stacked structure. (Refer to...) Figure 3 and Figure 4 As shown, where, Figure 3 Provided for the embodiments of this application Figure 2 The diagram shows a cross-sectional view of the semiconductor device in the YY direction. Figure 4 Provided for the embodiments of this application Figure 2 The diagram shows a cross-sectional structure of the semiconductor device in the XX direction, which is parallel to the fin lines of the fins. The diagram shows a cross-sectional structure in the YY direction, which is perpendicular to the fin lines of the fins.

[0034] In the embodiments of this application, there is a gap between the multiple nanosheets in the channel structure, and the gap is filled with a gate 160, that is, the gate 160 surrounds the nanosheets to form a ring gate structure.

[0035] In the embodiments of this application, an isolation structure 200 is disposed between the channel structure and the second substrate 112. The isolation structure 200 and the second substrate 112 are in direct contact, and the isolation structure 200 extends to the source 131 and the drain 132 in a direction parallel to the plane of the substrate 110. This forms an effective isolation between the substrate 110, the channel structure, the gate 160, the drain 132, and the source 131. The isolation structure 200 is used to suppress parasitic channel leakage current of the substrate 110, thereby reducing the device's off-state leakage current and improving the overall device performance.

[0036] Since the third substrate 113 has source 131 and drain 132 on both sides, and the third substrate 113 is covered by gate 160, the third substrate 113 forms a parasitic channel. Therefore, reducing the leakage current caused by the parasitic channel can isolate the third substrate 113 from the source 131 and drain 132, or simultaneously isolate the third substrate 113, gate 160, source 131 and drain 132.

[0037] In some embodiments, the third substrate 113 can be removed during the manufacturing process, i.e., in the final manufactured semiconductor device, the substrate 110 only includes the first substrate 111 and the second substrate 112, as shown in the reference. Figure 5 As shown, Figure 5 Provided for the embodiments of this application Figure 2 The schematic diagram of the cross-sectional structure of the semiconductor device in the XX direction shows that by removing the third substrate 113, the parasitic channel formed by the third substrate 113 can be removed, thereby avoiding leakage current caused by the parasitic channel.

[0038] The morphology of the isolation structure 200 for suppressing parasitic channel leakage is described in detail below using three examples: The first possible implementation is to completely remove the third substrate 113, that is, the isolation structure 200 is located between the gate 160 and the second substrate 112, and the two sidewalls of the isolation structure 200 are in contact with the source 131 and the drain 132 respectively. In this case, the isolation structure 200 is a single structure. Figure 5 As shown, in a direction parallel to the plane of the substrate 110, one side of the isolation structure 200 is in contact with the source 131, and the other side of the isolation structure 200 is in contact with the drain 130. Thus, the source 131 and the drain 132 are separated by the isolation structure 200, which is non-conductive and does not have a third substrate 113, thereby completely avoiding parasitic channel leakage.

[0039] A second possible implementation involves removing a portion of the third substrate 113. In the direction perpendicular to the plane of substrate 110, the third substrate 113 is only disposed in the region overlapping with the channel structure, and the third substrate 113 does not overlap with the source 131 and drain 132. The third substrate 113 is separated from the source 131 and drain 132 by the isolation structure 200, and the third substrate 113 is covered by the isolation structure 200. (Refer to...) Figure 6 As shown, Figure 6 Provided for the embodiments of this application Figure 2The diagram shows a cross-sectional structure of the semiconductor device in the XX direction. In this case, the isolation structure 200 is an integral structure. Thus, the isolation structure 200 completely isolates the third substrate 113, gate 160, source 131 and drain 132, thereby reducing the leakage current caused by the parasitic channel.

[0040] A third possible implementation involves removing a portion of the third substrate 113. In a direction perpendicular to the plane of substrate 110, the third substrate 113 is only disposed in the region overlapping with the channel structure. The third substrate 113 is located between the channel structure and the second substrate 112, meaning one surface of the third substrate 113 contacts the gate 160, and the third substrate 113 does not overlap with the source 131 or the drain 132. The isolation structure 200 may include a first isolation structure and a second isolation structure. A first isolation structure is disposed between the third substrate 113 and the source 131, and a second isolation structure is disposed between the third substrate 113 and the drain 132. (Refer to...) Figure 4 As shown. In this way, the isolation structure 200 completely isolates the third substrate 113, the source 131 and the drain 132, thereby reducing the leakage current caused by the parasitic channel.

[0041] In some embodiments, in a direction parallel to the plane of the substrate 110, both the first isolation structure and the second isolation structure include a first sidewall near the channel structure, and the first sidewall and the sidewall of the channel structure are flush in a direction perpendicular to the plane of the substrate 110. That is, the isolation structure 200 is equivalent to the inner sidewall 206 between adjacent nanosheets, which makes the process of forming the isolation structure 200 simpler and easier to control.

[0042] It should be noted that the positions of the first isolation structure and the second isolation structure can be interchanged. That is, a second isolation structure is disposed between the third substrate 113 and the source 131, and a first isolation structure is disposed between the third substrate 113 and the drain 132. In addition, the first isolation structure and the second isolation structure can be symmetrical structures, thereby avoiding device performance degradation caused by the first isolation structure and the second isolation structure.

[0043] In the embodiments of this application, whether the isolation structure 200 is a single structure or includes two structures, the isolation structure 200 includes two parts: a first isolation part 210 and a second isolation part 220. The first isolation part 210 is located on the side of the second isolation part 220 away from the substrate 110. That is, the first isolation part 210 is closer to the gate 160, and the second isolation part 220 is closer to the second substrate 112.

[0044] In a direction parallel to the plane of substrate 110, the first isolation portion 210 includes a second sidewall away from the channel structure, and the second isolation portion 220 includes a third sidewall away from the channel structure. The second and third sidewalls are not flush in a direction perpendicular to the plane of substrate 110, and the third sidewall is disposed on the side of the second sidewall closer to the source 131 or drain 132. That is, the second isolation portion 220 protrudes towards the source 131 or drain 132 relative to the first isolation portion 210, thereby causing the isolation structure 200 to extend towards the source 131 or drain 132. This is because, in order to protect the channel structure, the isolation structure 200 forms this special structure with uneven sidewalls before the formation of the inner sidewall 206. This allows for the suppression of leakage current by increasing the process of forming the isolation structure 200 without affecting other process steps, thereby minimizing the manufacturing cost of the device.

[0045] In some embodiments, the maximum thickness of the isolation structure 200 can be the initial thickness of the third substrate 113, and the thickness range of the isolation structure 200 can be 1-100 nm. The width of the isolation structure 200 along the XX direction can be 1-100 nm.

[0046] In the embodiments of this application, the material of the isolation structure 200 is an insulating material, for example, the isolation structure 200 is a low-k dielectric material.

[0047] As an example, the low-k dielectric material can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, doped silicon nitride, and doped silicon oxide.

[0048] In the embodiments of this application, the material of the inner wall 206 may be one or more of silicon oxide, silicon nitride, aluminum oxide, silicon oxynitride, silicon oxycarbide, boron nitride, and air. The use of air as the material of the inner wall 206 means that an air cavity can be formed at the location of the inner wall 206, thereby achieving the function of the inner wall 206.

[0049] As an example, the material of the high-k dielectric layer 150 can be HfO2 or HfSiO2. x HfON, HfSiON, HfAlO x HfLaO x Al2O3, ZrO2, ZrSiO x One or a combination of Ta2O5 or La2O3.

[0050] In embodiments of this application, the semiconductor device further includes a second sidewall 205, an isolation layer 207, a top dielectric layer 170, and a contact electrode 180.

[0051] The second sidewall 205 is disposed on the side of the channel structure away from the substrate 110, and the gate 160 is located between the second sidewalls 205. The isolation layer 207 is disposed on the side of the source 131 or drain 132 away from the substrate 110, and the second sidewall 205 and the gate 160 are located between the isolation layers 207.

[0052] The top dielectric layer 170 covers the isolation layer 207, the second sidewall 205 and the gate 160. The top dielectric layer 170 has a contact electrode 180 for electrically leading out the source 131 or the drain 132.

[0053] Therefore, the semiconductor device provided in this application includes: a substrate, a source, a drain, a gate, and a channel structure disposed on one side of the substrate. The channel structure is located between the source and the drain, and the channel structure includes a stack of multiple nanosheets. The gate surrounds the nanosheets, thus forming a basic GAAFET through the substrate, source, drain, gate, and channel structure. In this application, the substrate may include a first substrate, a second substrate, and a third substrate stacked sequentially. The first substrate is a semiconductor material, the second substrate is an insulating material, and the third substrate is also a semiconductor material. The third substrate can be partially or completely removed. That is, the substrate of this application is a semiconductor-on-insulator substrate, which can optimize the performance of the GAAFET. The semiconductor device provided in this application includes an isolation structure disposed between the channel structure and the second substrate. The isolation structure extends to the source and drain in a direction parallel to the plane of the substrate, thereby forming an effective isolation between the substrate, gate, drain and source. This isolation structure is used to suppress parasitic channel leakage current of the semiconductor substrate near the channel structure when fabricating GAAFET on a semiconductor-on-insulator substrate, thereby reducing the off-state leakage current of the device with a shorter gate length and improving the overall performance of the device.

[0054] Based on the semiconductor device provided in the above embodiments, this application also provides a method for manufacturing a semiconductor device, and its working principle will be described in detail below with reference to the accompanying drawings.

[0055] See Figure 7 The figure is a schematic flowchart of a semiconductor device manufacturing method provided in an embodiment of this application.

[0056] The method for manufacturing a semiconductor device provided in this application includes the following steps: S101, a substrate 110 is provided, and a stacked structure consisting of alternating layers of a first semiconductor layer 121 and a second semiconductor layer 122 is formed on one side of the substrate 110, with reference to... Figure 8A and Figure 8B As shown.

[0057] In embodiments of this application, substrate 110 includes a first substrate 111, a second substrate 112, and a third substrate 113 stacked sequentially, wherein the first substrate 111 and the third substrate 113 are semiconductor materials, such as silicon or germanium. The second substrate 112 is an insulating material, such as silicon oxide. The substrate of this application is a semiconductor-on-insulator substrate, which can improve the performance of GAAFETs compared to bulk silicon substrates including heavily doped wells.

[0058] As an example, if the first substrate 111 is silicon, the second substrate 112 is silicon oxide, and the third substrate 113 is silicon, then the substrate 110 can be a silicon-on-insulator (SOI) substrate.

[0059] In embodiments of this application, a stacked structure consisting of alternating layers of a first semiconductor layer 121 and a second semiconductor layer 122 can be formed on one side of the substrate 110, as shown in the reference. Figure 8A and Figure 8B As shown, where, Figure 8A Provided for the embodiments of this application Figure 2 The diagram shows a cross-sectional view of the semiconductor device in the YY direction. Figure 8B Provided for the embodiments of this application Figure 2 The diagram shows a cross-sectional structure of the semiconductor device in the XX direction, which is parallel to the fin lines of the fins. The diagram shows a cross-sectional structure in the YY direction, which is perpendicular to the fin lines of the fins.

[0060] The first semiconductor layer 121 and the second semiconductor layer 122 can be formed using an epitaxial process.

[0061] Specifically, depending on the device type, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 can be the same. For example, the material of the first semiconductor layer 121 can be silicon-germanium, and the material of the second semiconductor layer 122 can be silicon or germanium. Alternatively, depending on the device type, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 can be different. For example, for a P-type semiconductor device, the material of the first semiconductor layer 121 can be silicon, and the material of the second semiconductor layer 122 can be silicon-germanium. For an N-type semiconductor device, the material of the first semiconductor layer 121 can be silicon-germanium, and the material of the second semiconductor layer 122 can be silicon.

[0062] In practical applications, silicon oxide may be formed on the substrate 110. The stacked structure can be formed after the silicon oxide on the substrate 110 is removed and the substrate 110 is cleaned.

[0063] S102, etching is performed on the stacked structure and a portion of the thickness of the third substrate 113 to form the source region 101 and the drain region 102, reference. Figure 13 Show.

[0064] In the embodiments of this application, the stacked structure and a portion of the thickness of the third substrate 113 can be etched to form the source region 101 and the drain region 102. The channel region 103 is located between the source region 101 and the drain region 102. The source region 101 and the drain region 102 are formed by etching the stacked structure and then etching the portion of the thickness of the third substrate 113. Thus, the third substrate 113 in the channel region 103 may subsequently form a parasitic channel. (Refer to...) Figure 13 As shown.

[0065] The specific process flow for forming the source region 101 and the drain region 102 is as follows: S1021, Inner wall transfer process, reference Figure 9A and Figure 9B As shown.

[0066] In the embodiments of this application, a self-aligned inner sidewall transfer process is used to form the first sidewall 201. The material of the first sidewall 201 is silicon nitride. The specific formation process is as follows: a sacrificial layer 202 is covered on the stacked structure. The material of the sacrificial layer 202 can be polycrystalline silicon or amorphous silicon. Part of the sacrificial layer 202 is etched away using photolithography to form a pattern. Silicon nitride material is deposited. Then, anisotropic etching is used to etch away the remaining sacrificial layer 202, so that only the first sidewall 201 on the stacked structure remains. The first sidewall 201 plays the role of a hard mask in the subsequent photolithography for forming fins.

[0067] S1022, forming fins, see reference. Figure 10A and Figure 10B As shown.

[0068] In the embodiments of this application, the stacked structure can be etched using an etching process to form multiple periodically distributed fins, as shown in the reference. Figure 10A and Figure 10B As shown, etching is performed using the first sidewall 201 as a mask to form a fin with a stacked structure. The upper part of the fin is the channel region 103 formed by the stacked structure, and the lower part of the fin is the third substrate 113, forming a structure as shown. Figure 10A The fin shown is not only a multilayer structure but also includes a third substrate 113. The etching process can be anisotropic etching. The fin will be used to form nanosheets for semiconductor devices. Although Figure 10A A fin is shown, and it should be understood that any suitable number and shape of fins can be used in practical applications.

[0069] In practical applications, after the fins are formed, the first sidewall 201 can be removed. The specific etching process can be dry etching or wet etching.

[0070] S1023, forming a dummy gate 204, reference. Figure 11A and Figure 11B As shown.

[0071] In the embodiments of this application, a dummy gate stack is formed on the exposed fin in a direction horizontal to the fin line, i.e., the XX direction. The dummy gate stack is a multilayer structure, including a gate insulating dielectric layer (not shown), a dummy gate 204, and a hard mask layer (not shown). The dummy gate stack can be formed using processes such as thermal oxidation, chemical vapor deposition, or sputtering. The dummy gate stack spans the stack structure above the fin, and multiple dummy gates are periodically distributed along the fin line direction. The material of the dummy gate 204 can be polycrystalline silicon or amorphous silicon. The material of the hard mask layer can be oxides, carbides, organic materials, etc.

[0072] S1024, forming the second sidewall 205, see reference. Figure 12 As shown.

[0073] In the embodiments of this application, second sidewalls 205 can be provided on both sides of the dummy gate stack along the fin direction, i.e., the XX direction. The thickness of the second sidewalls 205 on both sides is the same. (Refer to...) Figure 12 As shown, Figure 12 Provided for the embodiments of this application Figure 2 The diagram shows a cross-sectional view of the semiconductor device along the XX direction. The material of the second sidewall 205 can be a dielectric material with isolation properties, such as silicon nitride or doped silicon oxide.

[0074] In the embodiments of this application, after forming the dummy gate 204 and the second sidewall 205, the dummy gate 204 and the second sidewall 205 can be used as masks to perform source / drain etching on the stacked structure and a portion of the thickness of the third substrate 113 through an etching process, specifically, source / drain etching is performed on the fins. Wherein, the source region 101 and the drain region 102 no longer have a stacked structure after etching, and a portion of the thickness of the third substrate 113 of the source region 101 and the drain region 102 is also etched, as shown in the reference. Figure 13 As shown, Figure 13 Provided for the embodiments of this application Figure 2 The diagram shows a cross-sectional view of the semiconductor device along the XX direction.

[0075] S1025, forming a concave structure 401, reference. Figure 14 As shown.

[0076] In the embodiments of this application, selective etching is performed on the first semiconductor layer 121 in the stacked structure located in the channel region 103 along a first direction, i.e., along the XX direction, parallel to the plane where the substrate 110 is located. That is, only the first semiconductor layer 121 is etched, without damaging the second semiconductor layer 122. Along the XX direction, the portion of the first semiconductor layer 121 that is missing from the second semiconductor layer 122 forms an inward recess, which is a concave structure 401. In other words, pull-back etching is performed, and a portion of the first semiconductor layer 121 is etched away from the source region 101 and the drain region 102 toward the channel region 103. (Refer to...) Figure 14 As shown, Figure 14 Provided for the embodiments of this application Figure 2 The diagram shows a cross-sectional view of the semiconductor device along the XX direction.

[0077] S1026, forming a protective sidewall 501, reference Figure 15A and Figure 15B As shown.

[0078] In the embodiments of this application, after the first semiconductor layer 121 is etched, a dielectric material is deposited on the stacked structure located in the channel region 103, i.e. the periphery of the fin, to form a protective sidewall 501. The protective sidewall 501 covers the dummy gate 204, the second sidewall 205, the sidewall of the stacked structure, and the third substrate 113.

[0079] Then, anisotropic etching is used to etch and remove the protective sidewalls 501 located in the source region 101 and the drain region 102, exposing the third substrate 113 located in the source region 101 and the drain region 102. Figure 16A and Figure 16B As shown.

[0080] S103, the third substrate 113 located in the source region 101 and the drain region 102 is etched away. On a plane parallel to the substrate 110, all or part of the third substrate 113 is etched away in the direction toward the channel region 103 to form a groove 502.

[0081] In embodiments of this application, the third substrate 113 located in the source region 101 and drain region 102 can be removed by etching. Specifically, an anisotropic etching process can be used to remove the third substrate 113 located in the source region 101 and drain region 102. During the etching process of removing the third substrate 113 located in the source region 101 and drain region 102, since the protective sidewall 501 covers the third substrate 113 located in the channel region 103, the third substrate 113 located in the channel region 103 can be retained. (Refer to...) Figure 17 As shown, Figure 17 Provided for the embodiments of this application Figure 2 The diagram shows a cross-sectional view of the semiconductor device along the XX direction.

[0082] On a plane parallel to the substrate 110, all or part of the third substrate 113 is etched away along the direction toward the channel region 103 to form a groove 502. Specifically, an isotropic etching process can be used, and the etching depth is determined according to the morphology of the pre-designed isolation structure 200.

[0083] One possible implementation is to etch away all of the third substrate 113, meaning the channel region 103 does not have the third substrate 113, and a groove 502 is formed between the second substrate 112 and the stacked structure. Figure 18 As shown, Figure 18 Provided for the embodiments of this application Figure 2 The diagram shows a cross-sectional view of the semiconductor device along the XX direction.

[0084] A second possible implementation involves removing a portion of the third substrate 113, retaining a portion of the thickness of the third substrate 113 in the channel region 103. The third substrate 113 contacts the second substrate 112, and a groove 502 exists between the third substrate 113 and the stacked structure, meaning the third substrate 113 and the stacked structure are not in direct contact. Along the XX direction, the groove 502 penetrates the stacked structure. (Refer to...) Figure 19 As shown, Figure 19 Provided for the embodiments of this application Figure 2 The diagram shows a cross-sectional view of the semiconductor device along the XX direction.

[0085] A third possible implementation involves removing a portion of the third substrate 113. The full thickness of the third substrate 113 is retained in the channel region 103. The surface of the third substrate 113 contacts both the stacked structure and the second substrate 112, and the sidewalls of the third substrate 113 are flush with the sidewalls of the stacked structure. The groove 502 is formed by the protective sidewall 501, the third substrate 113, and the second substrate 112 surrounding it. (Refer to...) Figure 20 As shown, Figure 20 Provided for the embodiments of this application Figure 2 The diagram shows a cross-sectional view of the semiconductor device along the XX direction. The groove 502 includes a first groove and a second groove. The opening of the first groove faces one of the source region 101 and the drain region 102, and the opening of the second groove faces the other of the source region 101 and the drain region 102. The first groove and the second groove are symmetrical.

[0086] S104, filling the groove 502 with insulating material to form an isolation structure 200, reference. Figure 21-23 As shown.

[0087] In the embodiments of this application, after etching to obtain the groove 502, insulating material can be filled into the groove 502, and self-aligned anisotropic etching can be used to remove the insulating material outside the groove 502, thereby forming an isolation structure 200. Specifically, the process for filling the insulating material can be physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0088] The morphology of the groove 502 is different, and the morphology of the isolation structure 200 obtained by filling it is also different.

[0089] One possible implementation is to completely remove the groove 502 formed by the third substrate 113, and fill the surface of the isolation structure 200 formed by the insulating material to contact the stacked structure and the second substrate 112 respectively. The two sidewalls of the isolation structure 200 contact the subsequently formed source 131 and drain 132 respectively. At this time, the isolation structure 200 is a single structure. (Refer to...) Figure 21 As shown, Figure 21 Provided for the embodiments of this application Figure 2 The schematic diagram shows the cross-sectional structure of the semiconductor device in the XX direction. That is, in the direction perpendicular to the plane where the substrate 110 is located, the sidewall of the isolation structure 200 and the sidewall of the protective sidewall 501 are flush.

[0090] A second possible implementation involves removing a portion of the thickness of the third substrate 113 to form the groove 502. The surface of the isolation structure 200, filled with insulating material, contacts the stacked structure. The third substrate 113 is covered by the isolation structure 200, and the two sidewalls of the isolation structure 200 contact the subsequently formed source 131 and drain 132, respectively. In this case, the isolation structure 200 is a single, integrated structure. (Refer to...) Figure 22 As shown, Figure 22 Provided for the embodiments of this application Figure 2 The schematic diagram of the cross-sectional structure of the semiconductor device shown in the XX direction shows that, in the direction perpendicular to the plane where the substrate 110 is located, the sidewall of the isolation structure 200 and the sidewall of the protective sidewall 501 are flush.

[0091] A third possible implementation involves removing a portion of the groove 502 formed by the third substrate 113, including the first groove and the second groove. Insulating materials are then filled into the first and second grooves respectively, forming a first isolation structure and a second isolation structure. For example, a first isolation structure is provided between the third substrate 113 and the source region 101, and a second isolation structure is provided between the third substrate 113 and the drain region 102, as shown in the reference. Figure 23 As shown, Figure 23Provided for the embodiments of this application Figure 2 The diagram shows a cross-sectional view of the semiconductor device along the XX direction.

[0092] In the embodiments of this application, whether the isolation structure 200 is a single structure or includes two structures, the isolation structure 200 is disposed between the stacked structure and the second substrate 112, and the isolation structure 200 includes two parts, a first isolation part 210 and a second isolation part 220. The first isolation part 210 is located on the side of the second isolation part 220 away from the substrate 110. That is, the first isolation part 210 is closer to the gate 160, and the second isolation part 220 is closer to the second substrate 112.

[0093] In a direction parallel to the plane of the substrate 110, the first isolation portion 210 includes a second sidewall away from the channel region 103, and the second isolation portion 220 includes a third sidewall away from the channel region 103. The second and third sidewalls are not flush in a direction perpendicular to the plane of the substrate 110. The third sidewall is flush with the sidewall of the protective sidewall 501 and is disposed on the side of the second sidewall near the source region 101 or the drain region 102. That is, the second isolation portion 220 protrudes towards the source region 101 or the drain region 102 relative to the first isolation portion 210, thereby causing the isolation structure 200 to extend towards the source region 101 or the drain region 102.

[0094] In the embodiments of this application, after filling the groove 502 with insulating material and forming the isolation structure 200 by self-aligning etching, the protective sidewall 501 can be etched to form an inner sidewall 206 between adjacent second semiconductor layers 122. The inner sidewall 206 is flush with the second semiconductor layer 122 in a direction perpendicular to the plane of the substrate 110. That is, the concave structure 401 formed by etching in S1025 is filled by the inner sidewall 206. The material of the inner sidewall 206 can be one or more of silicon oxide, silicon nitride, aluminum oxide, silicon oxynitride, silicon oxycarbide, boron nitride, and air. The use of air as the material of the inner sidewall 206 means that an air cavity can be formed at the location of the inner sidewall 206, thereby achieving the function of the inner sidewall 206.

[0095] During the removal of part of the protective sidewall 501, the isolation structure 200 maintains its original morphology. Thus, after the inner sidewall 206 is formed, the portion of the second isolation portion 220 protruding into the source region 101 or drain region 102 is exposed. (Refer to...) Figures 24-26 As shown, Figures 24-26 Provided for the embodiments of this application Figure 2 The diagram shows a cross-sectional view of the semiconductor device along the XX direction.

[0096] S105, source 131 and drain 132 are formed in source region 101 and drain region 102, respectively, for reference. Figure 27-Figure 2 As shown in Figure 9.

[0097] In the embodiments of this application, after etching the stacked structure to form the source region 101 and the drain region 102, and forming the isolation structure 200, source 131 and drain 132 can be formed in the source region 101 and drain region 102 respectively using an epitaxial process. The isolation structure 200 extends to the source 131 and drain 132 in a direction parallel to the plane of the substrate 110. (Refer to...) Figure 27 , Figure 28 and Figure 29B As shown, Figure 27 , Figure 28 and Figure 29B Provided for the embodiments of this application Figure 2 The diagram shows a cross-sectional view of the semiconductor device along the XX direction.

[0098] Specifically, the source and drain materials may differ for different types of semiconductor devices. For P-type semiconductor devices, the source and drain materials are P-type doped silicon-germanium, such as boron-doped germanium-silicon (SiGe:B), where source 131 or drain 132 is P-type doped silicon-germanium. For N-type semiconductor devices, the source and drain materials are N-type doped silicon, such as phosphorus-doped silicon or phosphorus-doped silicon carbide (Si:P or SiC:P).

[0099] In embodiments of this application, after forming the source 131 and drain 132, the dummy gate 204 can be removed, see reference. Figure 27 , Figure 28 and Figure 29B As shown.

[0100] In embodiments of this application, an isolation layer 207 can be deposited on the surfaces of the dummy gate 204, source 131, and drain 132 to prevent short circuits between the dummy gate 204 and the source 131 or drain 132 in subsequent steps. The isolation layer 207 is then subjected to a chemical mechanical polishing process to planarize it. Then, as... Figure 27 , Figure 28 and Figure 29B As shown, the dummy gate 204 formed by the aforementioned polycrystalline silicon or amorphous silicon is etched or etched away by selective etching or etching processes, that is, the dummy gate 204 is removed.

[0101] S106, replace the first semiconductor layer 121 with the gate 160, refer to Figure 27-Figure 2 As shown in Figure 9.

[0102] In embodiments of this application, the first semiconductor layer 121 can be replaced with the gate 160, see reference. Figure 27-Figure 2 As shown in Figure 9.

[0103] The specific process flow is as follows: S1061, Remove the first semiconductor layer 121 of the channel region 103, reference Figure 27-Figure 2 As shown in Figure 9.

[0104] In embodiments of this application, the first semiconductor layer 121 of the channel region 103 can be removed, i.e., a nanosheet channel release process can be performed, so as to form a plurality of gaps 402 to be filled between the second semiconductor layers 122, see reference. Figure 27-Figure 2 As shown in Figure 9.

[0105] Specifically, the first semiconductor layer 121 in the stacked structure located in the channel region 103 can be selectively etched to release the nanosheet channel. That is, the stacked structure exposed by the fins is processed to remove the first semiconductor layer 121 of each layer, which is the sacrificial layer, to release the nanosheets formed by the second semiconductor layer 122.

[0106] In the embodiments of this application, there are several possible ways to achieve nanosheet channel release for different types of devices: In a first possible implementation, for both P-type and N-type semiconductor devices, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon-germanium. The silicon-germanium is selectively removed, leaving the second semiconductor layer 122, i.e., silicon, to form a silicon-laminated nanosheet stack device. In the selective removal process, an etchant that selectively etches silicon-germanium at a faster rate than silicon can be used.

[0107] In a second possible implementation, for a P-type semiconductor device, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon. Silicon is selectively removed, leaving the second semiconductor layer 122, i.e., silicon-germanium, to form a silicon-germanium stacked nanosheet device. In the selective removal process, an etchant that selectively etches silicon at a faster rate than silicon-germanium can be used.

[0108] In a third possible implementation, for N-type semiconductor devices, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon-germanium. The silicon-germanium is selectively removed, leaving the second semiconductor layer 122, i.e., silicon, to form a silicon-stacked nanosheet device. In the selective removal process, an etchant that selectively etches silicon-germanium at a faster rate than silicon can be used.

[0109] S1062, a high-k dielectric layer 150 is formed on the surface of the second semiconductor layer 122, refer to Figure 30- Figure 32 As shown.

[0110] In embodiments of this application, after removing the first semiconductor layer 121, a high-k dielectric layer 150 can be formed on the surface of the second semiconductor layer 122, with the high-k dielectric layer 150 surrounding the surface of the second semiconductor layer 122. Specifically, the material of the high-k dielectric layer 150 can be HfO2 or HfSiO2. x HfON, HfSiON, HfAlO x HfLaO x Al2O3, ZrO2, ZrSiO x One or a combination of Ta2O5 or La2O3.

[0111] In embodiments of this application, the high-k dielectric layer 150 may further include an interface oxide layer (IL) (not shown).

[0112] S1063, fill the gate 160 in multiple gaps 402 to be filled, refer to Figure 30- Figure 32 As shown.

[0113] In the embodiments of this application, after the nanosheet channel is released, there are multiple gaps 402 to be filled between the multiple second semiconductor layers 122. A gate 160 can be filled into these gaps 402, and the gate 160 surrounds the second semiconductor layers 122, forming a gate-ring structure. The stack of multiple second semiconductor layers 122 forms a channel structure, i.e., a nanosheet channel for a semiconductor device, as shown in Figure 30-. Figure 32 As shown.

[0114] In embodiments of this application, the gate 160 may further include a multilayer structure such as a diffusion barrier layer, a work function layer, and a conductive filling layer (not shown).

[0115] In practical applications, in addition to forming the gate 160 in the gap 402 to be filled, the gate 160 also covers the space after the isolation layer 207 and the dummy gate 204 is removed. The gate 160 covered by the isolation layer 207 can be chemically mechanically polished to perform planarization.

[0116] In embodiments of this application, after forming the gate 160, dielectric deposition can be performed on the top of the semiconductor device away from the substrate 110 to form a top dielectric layer 170, as shown in the reference. Figures 3-6 As shown.

[0117] In the embodiments of this application, contact hole etching is performed in the top dielectric layer 170, etching down to the surface of the source 131 or drain 132, and metal material is deposited in the contact holes to form the contact electrodes 180 of the source 131 or drain 132. (Refer to...) Figures 3-6 As shown, subsequent processes include multi-layer back-end interconnection and passivation protection.

[0118] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. In particular, structural embodiments are generally similar to method embodiments and are therefore described simply; relevant details can be found in the descriptions of the method embodiments.

[0119] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: The substrate includes a first substrate and a second substrate stacked sequentially, wherein the first substrate is a semiconductor material and the second substrate is an insulating material; A source, a drain, and a channel structure are disposed on one side of the substrate, the channel structure being located between the source and the drain, and the channel structure comprising a stack of multiple nanosheets. An isolation structure is disposed between the channel structure and the second substrate. In a direction parallel to the plane of the substrate, the isolation structure extends to the source and the drain. The isolation structure includes a first isolation structure and a second isolation structure. In a direction parallel to the plane of the substrate, the first isolation structure contacts the source and the second isolation structure contacts the drain. A gate, the gate surrounding the nanosheet; The substrate further includes a third substrate located on the side of the second substrate away from the first substrate. The third substrate does not overlap with the source and the drain. The material of the third substrate is a semiconductor material. The third substrate is separated from the source and the drain by the isolation structure.

2. The semiconductor device according to claim 1, characterized in that, The third substrate is located between the channel structure and the second substrate. A first isolation structure is provided between the third substrate and the source electrode, and a second isolation structure is provided between the third substrate and the drain electrode.

3. The semiconductor device according to claim 1, characterized in that, In a direction parallel to the plane of the substrate, the first isolation structure and the second isolation structure include a first sidewall near the channel structure, the first sidewall and the sidewall of the channel structure being flush in a direction perpendicular to the plane of the substrate.

4. The semiconductor device according to any one of claims 1-3, characterized in that, The isolation structure includes a first isolation portion and a second isolation portion, wherein the first isolation portion is located on the side of the second isolation portion away from the substrate; In a direction parallel to the plane of the substrate, the first isolation portion includes a second sidewall away from the channel structure, and the second isolation portion includes a third sidewall away from the channel structure. The second sidewall and the third sidewall are not flush in a direction perpendicular to the plane of the substrate, and the third sidewall is disposed on the side of the second sidewall near the source or the drain.

5. The semiconductor device according to any one of claims 1-3, characterized in that, The isolation structure is made of a low-k dielectric material.

6. A method for manufacturing a semiconductor device, characterized in that, The method includes: A substrate is provided, and a plurality of stacked structures consisting of alternating layers of a first semiconductor layer and a second semiconductor layer are formed on one side of the substrate; the substrate includes a first substrate, a second substrate and a third substrate stacked sequentially, wherein the first substrate and the third substrate are semiconductor materials and the second substrate is an insulating material; The stacked structure and a portion of the thickness of the third substrate are etched to form a source region and a drain region, with a channel region between the source region and the drain region; The third substrate located in the source region and the drain region is etched away. On a plane parallel to the substrate, all or part of the third substrate is etched away in the direction toward the channel region to form a groove. The groove completely or partially separates the stacked structure and the second substrate. The groove is filled with insulating material to form an isolation structure; A source and a drain are formed in the source region and the drain region, respectively. An isolation structure is disposed between the stacked structure and the second substrate. The isolation structure extends to the source and the drain in a direction parallel to the plane of the substrate. The first semiconductor layer is replaced with a gate, which surrounds the second semiconductor layer, and a stack of multiple second semiconductor layers forms a channel structure.

7. The manufacturing method according to claim 6, characterized in that, The etching process removes the third substrate located in the source region and the drain region. On a plane parallel to the substrate, etching is performed along a direction towards the channel region to remove all or part of the third substrate, forming a groove. The third substrate located in the source region and the drain region is removed by anisotropic etching process; On a plane parallel to the substrate, an isotropic etching process is used to etch away all or part of the third substrate along the direction toward the channel region, forming a groove.

8. The manufacturing method according to claim 7, characterized in that, Before etching away the third substrate located in the source region and the drain region, the method further includes: In a direction parallel to the plane of the substrate, a portion of the first semiconductor layer is etched away to form an inward recess; A protective sidewall is formed in the inward recess, and the protective sidewall covers a portion of the third substrate; The method of etching away the third substrate located in the source region and the drain region using anisotropic etching technology includes: The third substrate, which is not covered by the protective sidewall, is removed by etching using anisotropic etching technology in the source region and the drain region. The step of filling the groove with insulating material to form an isolation structure includes: An insulating material is filled into the groove, and an isolation structure is formed by self-aligned etching. The isolation structure includes a first isolation portion and a second isolation portion, wherein the first isolation portion is located on the side of the second isolation portion away from the substrate. In a direction parallel to the plane of the substrate, the first isolation portion includes a second sidewall away from the channel region, the second isolation portion includes a third sidewall away from the channel region, the second sidewall and the third sidewall are not flush in a direction perpendicular to the plane of the substrate, the third sidewall is flush with the sidewall of the protective sidewall, and the third sidewall is disposed on the side of the second sidewall near the source region or the drain region.

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