Persistent storage device and method of operation thereof

Abstract

Persistent storage devices and methods of operation thereof. In some embodiments, a persistent storage device includes processing circuitry, a cache, and a persistent storage device. The processing circuitry can be configured to perform a method including receiving a first write request according to a first protocol, saving a data payload of the first write request in a first portion of the cache, receiving a second write request according to a second protocol, and saving a data payload of the second write request in a second portion of the cache.

Description

[0001] This application claims priority and benefit to U.S. Provisional Application No. 63 / 417,940, filed October 20, 2022, entitled “Cache Line Access Prioritized Caching SLC-TLC Hybrid NAND Flash for SSDs That Support Cache Line and Page I / O Granularity Accesses,” and U.S. Patent Application No. 18 / 163,208, filed February 1, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] One or more aspects of embodiments of the present disclosure relate to data storage devices, and more specifically, to systems and methods for persistent storage devices having dual interfaces. Background Technology

[0003] Persistent storage devices can provide storage for host computers. Such storage devices can communicate with host computers using different interfaces, and different interfaces can handle different amounts of data.

[0004] The aspects disclosed herein are related to the overall technical environment. Summary of the Invention

[0005] According to embodiments of the present disclosure, a persistent storage device is provided, the persistent storage device comprising: a processing circuit; a cache; and a persistent storage unit, the processing circuit being configured to perform a method comprising: receiving a first write request according to a first protocol; storing the data payload of the first write request in a first portion of the cache; receiving a second write request according to a second protocol; and storing the data payload of the second write request in a second portion of the cache.

[0006] In some embodiments, the first write request includes a caching hint instructing the persistent storage device to perform caching.

[0007] In some embodiments: a first protocol addresses data units at a first granularity; a second protocol addresses data units at a second granularity different from the first granularity; and the method further includes: receiving a third write request, the third write request including a data payload and a cache hint, the cache hint instructing the persistent storage device to abandon caching; and storing the data payload of the third write request in the persistent storage device.

[0008] In some embodiments: the persistent storage device includes a first storage medium and a second storage medium, the first storage medium having a higher read latency than the second storage medium; the data load of the third write request is less than a first threshold; and the step of storing the data load of the third write request in the persistent storage device includes: storing the data load of the third write request in the second storage medium.

[0009] In some embodiments: the first storage medium includes a three-level cell; and the second storage medium includes a single-level cell.

[0010] In some embodiments, the method further includes: receiving a fourth write request, the fourth write request including a data payload and a cache hint, the cache hint instructing the persistent storage device to abandon caching; and storing the data payload of the fourth write request in the persistent storage device, wherein: the data payload of the fourth write request is greater than a first threshold; and the step of storing the data payload of the fourth write request in the persistent storage device includes: storing the data payload of the fourth write request in a first storage medium.

[0011] In some embodiments, the method further includes: receiving a fifth write request, the fifth write request including a cache hint and a data load larger than a first threshold, the cache hint instructing the persistent storage device to perform caching; determining that a first portion of the cache is full; evicting data from the first portion of the cache; and storing the data load of the fifth write request in the first portion of the cache.

[0012] In some embodiments, the method further includes: receiving a fifth write request, the fifth write request including a cache hint and a data load smaller than a first threshold, the cache hint instructing the persistent storage device to perform caching; determining that a second portion of the cache is full and that space is available in a first portion of the cache; reducing the size of the first portion of the cache; increasing the size of the second portion of the cache; and storing the data load of the fifth write request in the second portion of the cache.

[0013] In some embodiments, the method further includes: receiving a sixth write request, the sixth write request including a cache hint and a data load smaller than a first threshold, the cache hint instructing the persistent storage device to perform caching; determining that a first portion of the cache is full and a second portion of the cache is full; evicting data from the first portion of the cache; reducing the size of the first portion of the cache; increasing the size of the second portion of the cache; and storing the data load of the sixth write request in the second portion of the cache.

[0014] In some embodiments, the method further includes: receiving a sixth write request, the sixth write request including a cache hint and a data load smaller than a first threshold, the cache hint instructing the persistent storage device to perform caching; determining that a first portion of the cache has a size of zero and a second portion of the cache is full; evicting data from the second portion of the cache; and storing the data load of the sixth write request in the second portion of the cache.

[0015] In some embodiments, the first write request is a Non-Volatile Memory Fast (NVMe) write request, and the second write request is a Compute Fast Link (CXL) write request.

[0016] According to embodiments of the present disclosure, a method is provided, the method comprising: receiving a first write request according to a first protocol via a persistent storage device; storing the data payload of the first write request in a first portion of a cache; receiving a second write request according to a second protocol; and storing the data payload of the second write request in a second portion of a cache.

[0017] In some embodiments, the first write request includes a caching hint instructing the persistent storage device to perform caching.

[0018] In some embodiments: a first protocol addresses data units at a first granularity; a second protocol addresses data units at a second granularity different from the first granularity; and the method further includes: receiving a third write request, the third write request including a data payload and a cache hint, the cache hint instructing a persistent storage device to abandon caching; and storing the data payload of the third write request in a persistent storage device of the persistent storage device.

[0019] In some embodiments: the persistent storage device includes a first storage medium and a second storage medium, the first storage medium having a higher read latency than the second storage medium; the data load of the third write request is less than a first threshold; and the step of storing the data load of the third write request in the persistent storage device includes: storing the data load of the third write request in the second storage medium.

[0020] In some embodiments: the first storage medium includes a three-level cell; and the second storage medium includes a single-level cell.

[0021] In some embodiments, the method further includes: receiving a fourth write request, the fourth write request including a data payload and a cache hint, the cache hint instructing a persistent storage device to abandon caching; and storing the data payload of the fourth write request in the persistent storage device, wherein: the data payload of the fourth write request is greater than a first threshold; and the step of storing the data payload of the fourth write request in the persistent storage device includes: storing the data payload of the fourth write request in a first storage medium.

[0022] In some embodiments, the method further includes: receiving a fifth write request, the fifth write request including a cache hint and a data load larger than a first threshold, the cache hint instructing persistent storage to perform caching; determining that a first portion of the cache is full; evicting data from the first portion of the cache; and storing the data load of the fifth write request in the first portion of the cache.

[0023] In some embodiments, the method further includes: receiving a fifth write request, the fifth write request including a cache hint and a data load smaller than a first threshold, the cache hint indicating that persistent storage should perform caching; determining that a second portion of the cache is full and that space is available in a first portion of the cache; reducing the size of the first portion of the cache; increasing the size of the second portion of the cache; and storing the data load of the fifth write request in the second portion of the cache.

[0024] According to embodiments of this disclosure, a persistent storage device is provided, the persistent storage device comprising: means for processing; a cache; and a persistent storage device, wherein the means for processing is configured to perform a method, the method comprising: receiving a first write request comprising a data load greater than the first threshold; storing the data load of the first write request in a first portion of the cache, the first portion being for data units having a size greater than the first threshold; receiving a second write request comprising a data load less than the first threshold; and storing the data load of the second write request in a second portion of the cache, the second portion being for data units having a size less than the first threshold. Attached Figure Description

[0025] These and other features and advantages of this disclosure will be appreciated and understood by referring to the specification, claims and drawings, wherein:

[0026] Figure 1A This is a block diagram of a portion of a computing system according to embodiments of the present disclosure;

[0027] Figure 1B This is a bit allocation diagram according to an embodiment of the present disclosure;

[0028] Figure 1C These are hybrid block diagrams and flowcharts of persistent storage devices according to embodiments of the present disclosure;

[0029] Figure 2A This is a cache data layout diagram according to an embodiment of the present disclosure;

[0030] Figure 2B This is a data layout diagram according to an embodiment of the present disclosure;

[0031] Figure 2C This is a data layout diagram according to an embodiment of the present disclosure;

[0032] Figure 2D This is a data layout diagram according to an embodiment of the present disclosure;

[0033] Figure 2E yes Figures 2A to 2D Legend;

[0034] Figure 2F It is a table of addresses according to embodiments of this disclosure;

[0035] Figure 3A This is a flowchart of a first method for reading data according to an embodiment of the present disclosure;

[0036] Figure 3B This is a flowchart of a first method for writing data according to an embodiment of the present disclosure;

[0037] Figure 3C This is a flowchart of a second method for reading data according to an embodiment of the present disclosure;

[0038] Figure 3D This is a flowchart of a second method for writing data according to an embodiment of the present disclosure;

[0039] Figure 4 It is a decision tree according to embodiments of this disclosure;

[0040] Figure 5A This is a hybrid block diagram and flowchart illustrating a first process performed by a persistent storage device according to an embodiment of the present disclosure;

[0041] Figure 5B This is a hybrid block diagram and flowchart illustrating a second process performed by a persistent storage device according to an embodiment of the present disclosure;

[0042] Figure 5C This is a hybrid block diagram and flowchart illustrating a third process performed by a persistent storage device according to an embodiment of the present disclosure;

[0043] Figure 5D This is a hybrid block diagram and flowchart illustrating a fourth process performed by a persistent storage device according to an embodiment of the present disclosure;

[0044] Figure 5E This is a hybrid block diagram and flowchart illustrating a fifth process performed by a persistent storage device according to an embodiment of the present disclosure;

[0045] Figure 5F This is a hybrid block diagram and flowchart illustrating a sixth process performed by a persistent storage device according to an embodiment of the present disclosure;

[0046] Figure 6 This is a flowchart of a method according to an embodiment of the present disclosure. Detailed Implementation

[0047] The detailed description set forth below with reference to the accompanying drawings is intended as a description of exemplary embodiments of systems and methods for persistent storage devices having dual interfaces provided in this disclosure, and is not intended to represent the only form in which this disclosure may be constructed or utilized. The description, in conjunction with the illustrated embodiments, illustrates the features of this disclosure. However, it should be understood that the same or equivalent functions and structures may be implemented by different embodiments that are also intended to be included within the scope of the disclosure. As shown elsewhere herein, the same element numbers are intended to indicate the same elements or features.

[0048] In some embodiments, the persistent storage device provides two (or more) interfaces to a host computer, the host interfaces having different characteristics, and the persistent storage device is configured to provide data storage and retrieval functions tailored to the respective interfaces to provide improved performance. For example, the persistent storage device may have a Non-Volatile Memory Fast (NVMe) interface and a Compute Fast Link (CXL) interface; for the NVMe interface, the data payload size may be 4 kilobytes (kB) (or multiples of 4 kB), and for the CXL interface, the data payload size may be a cache line (e.g., 64 bytes).

[0049] Persistent storage devices can treat two different protocols with different addressing granularities differently. For example, persistent storage devices can treat NVMe operations and CXL operations differently to provide lower latency, for example, at the CXL interface, partly due to the smaller load size. For example, persistent storage devices can include a cache partitioned into two regions (a region allocated to CXL data and a region allocated to NVMe data). Data accessed via the CXL interface can have a priority for using the cache (e.g., data accessed via the NVMe interface can be evicted to make room for data accessed via the CXL interface). Persistent storage devices can also have two persistent storage media with different performance characteristics (e.g., single-level cell storage media and triple-level cell storage media), and the type with lower latency, for example, can be reserved for storing data accessed via the CXL interface.

[0050] Reference Figure 1A In some embodiments, persistent storage device 105 (e.g., a solid-state drive (SSD)) is connected to host 110. Persistent storage device 105 includes host interface 115, data cache 120, flash translation layer (FTL) 125, flash interface 130, and persistent storage medium (or persistent storage device) 135 (which may include multiple persistent storage chips (e.g., NAND chips such as multiple single-cell (SLC) NAND flash chips and multiple triple-cell (TLC) NAND flash chips)). Data cache 120 may include cache manager 122 and memory (e.g., dynamic random access memory (DRAM)), which may be referred to as cache 140.

[0051] Host interface 115 can support multiple protocols (e.g., Non-Volatile Memory Fast (NVMe) and Compute Fast Link (CXL)) via a single port or multiple ports. Thus, persistent storage device 105 can be a block device capable of executing cached line-addressable input / output requests. Each input / output (I / O) request (which may be a read request or a write request) may carry an optional cache hint, which may take a value selected from a set {cacheable, non-cacheable} that respectively instructs persistent storage device to either cache or forgo caching. An NVMe request with a size of n times 4kB (e.g., a request to read or write data in a block with a size of n times 4kB, where n is an integer greater than 1) can be divided into multiple 4kB sub-requests for further processing.

[0052] When a CXL I / O request is received by persistent storage device 105, cache manager 122 can extract the logical page address (LPA) from the CXL I / O request and process cache hints. Persistent storage device 105 can employ a CXL-prioritized cache design for both reads and writes. Cache 140 can be partitioned into two regions: a first region for CXL data and a second region for NVMe data. The partitions can be dynamically adjusted (based on replacement policies and eviction) such that, for example, the proportion of total memory in cache 140 allocated to CXL data can be increased and the proportion allocated to NVMe data can be decreased, or vice versa. Any data segment that has been accessed using a CXL read request or a CXL write request can be classified as "CXL Data," and any data segment that has not yet been accessed using a CXL read request or a CXL write request (as well as any data segment that has only been accessed using one or more NVMe read or write requests) can be classified as "NVMe Data." Data in the region of cache 140 allocated to CXL Data can be stored in blocks the size of a cache line (e.g., 64 bytes), which can result in a higher hit rate for CXL I / O requests (compared to the case where the data is stored in larger blocks, e.g., 4 kilobytes (kB)).

[0053] The single-level cell portion of persistent storage medium 135 (which may have lower read latency than the triple-level cell portion of persistent storage medium 135) can be dedicated to storing CXL data. Single-level cell flash memory can be faster (e.g., single-level cell flash memory may have lower read latency than the triple-level cell portion of persistent storage medium 135), can use smaller physical pages (e.g., 4kB) than the physical pages (e.g., 16kB) used in the triple-level cell portion of persistent storage medium 135, and can have better endurance; therefore, single-level cell flash memory is well-suited for the intensive small I / O requests of CXL. The triple-level cell portion of persistent storage medium 135 can be dedicated to storing NVMe data. In one example, persistent storage medium 135 can be connected to flash interface 130 via a channel.

[0054] like Figure 1BAs shown, the CXL.MEM (CXL Memory Protocol) request can carry a host physical address (HPA) with 46 or 47 bits. Logical page address (LPA) and cache line offset (CLO) can be used to locate a 64-byte cache line, which can be fetched from the host physical address using bitwise operations. For example, if the smallest addressable data unit in persistent storage 105 is 64 bytes, the byte offset may not be used in persistent storage 105. As used herein, the host physical address is an address defined in the CXL specification that is used by the host to represent a physical address in the memory of host 110.

[0055] A cache hint can be included in every input / output request received from host 110. The cache hint can correspond to one of the options in the set {cacheable, non-cacheable}. When the hint is cacheable and a cache miss occurs, persistent storage 105 can put data into cache 140. When the hint is non-cacheable and a cache miss occurs, persistent storage 105 may not put data into cache 140. The default behavior can be the behavior corresponding to "cache hint is cacheable". The host can send different cache hints for input / output requests targeting different protocols.

[0056] Figure 1C A cache bypass mechanism for write requests is illustrated in some embodiments. As shown, when the cache indicates that the data accompanying the write request can be written to cache 140; otherwise, the data accompanying the write request can be written to persistent storage medium 135. Cacheable data can also be moved to persistent storage medium 135 upon cache eviction.

[0057] Figures 2A to 2E The cache line access priority replacement strategy is shown in some embodiments. Figure 2A and Figure 2B This illustrates the replacement strategies that can be employed when a CXL write request is received and there is no remaining space in the area of ​​cache 140 allocated to CXL data. For example... Figure 2A As shown, when any region of cache 140 is allocated to NVMe data (i.e., the size of the region is non-zero), the existing 4kB blocks of NVMe data in the cache (existing NVMe data) can subsequently be evicted (or sacrificed), so the freed 4kB region can become part of the region of cache 140 allocated to CXL data, and CXL data received as part of a CXL write request (arriving CXL data) can be written to this newly available 4kB region. Figure 2BAs shown, when a region of cache 140 is not allocated to NVMe data (i.e., the size of the region of cache 140 allocated to NVMe data is zero), the existing 64-byte (B) block of CXL data (existing CXL data) of the cache can be subsequently evicted, and the CXL data received as part of a CXL write request can be written to the new free 64-byte region.

[0058] Figure 2C and Figure 2D This illustrates the replacement strategies that can be employed when an NVMe write request is received and there is no remaining space in the area of ​​cache 140 allocated to NVMe data. For example... Figure 2C As shown, when any area of ​​cache 140 is allocated to NVMe data (i.e., the size of the area is non-zero), existing 4kB blocks of NVMe data in the cache can subsequently be evicted, and NVMe data received as part of an NVMe write request (arriving NVMe data) can be written to the new free 4kB area. Figure 2D As shown, when a region of cache 140 is not allocated to NVMe data (i.e., the size of the region of cache 140 allocated to NVMe data is zero), the data in cache 140 can remain in place (e.g., no 64B blocks of data can be evicted), and the NVMe data received as part of an NVMe write request can be directly written to persistent storage medium 135 (i.e., the caching of this data can be omitted). Figure 2E yes Figures 2A to 2D Legend of the diagram.

[0059] In some embodiments, a replacement strategy (discussed below) considering the architecture of persistent storage medium 135, which may include single-level cell media and triple-level cell media as described above, may be employed. The replacement strategy may specify the following: When 4kB of data is evicted (from the area of ​​cache 140 allocated to NVMe data), if the LPA has only been accessed by NVMe, the 4kB block of data may be stored in triple-level cell media. When 4kB of data is evicted (from the area of ​​cache 140 allocated to NVMe data), if the logical page address has also been accessed by CXL, the evicted data may be stored in single-level cell media, and a 64-byte block as CXL data (i.e., accessed via CXL) may be stored in the area of ​​cache 140 allocated to CXL data.

[0060] When a 64-byte block of data is evicted (from the area of ​​cache 140 allocated to CXL data), the evicted data can be written to the single-level cell medium. This can be achieved by (i) using a read-modify-write operation (e.g., from the single-level cell medium) to read a 4kB page containing the 64-byte data block and store it in the single-level cell medium, or (ii) storing the operation in a log-structured format. In some embodiments, the buffer accumulates the evicted 64B data block until the complete 4kB page is obtained. The latter method (storing the operation in a log-structured format) (which can result in relatively high overhead) may involve directly writing the open block to the single-level cell medium and updating the mapping table (e.g., ...). Figure 2F (As shown in the diagram). Subsequently, when any 4kB block is read, the system can examine the log structured data to determine whether any 64-byte block needs to be updated based on the write operations recorded in log structured form. Figure 2F In this context, PPA_old is the old physical page address, CLO_old is the old cache line offset, PPA_new is the new physical page address, and CLO_new is the new cache line offset.

[0061] In some embodiments, cache lines (i.e., 64-byte blocks of data) are periodically evicted from the region of cache 140 allocated to CXL data, and when this results in 4kB of free space in that region, the partition between the region of cache 140 allocated to CXL data and the region of cache 140 allocated to NVMe data can be moved, making the additional 4kB blocks available in the region of cache 140 allocated to NVMe data. This allows cache 140 to be used for NVMe data when CXL I / O requests are infrequent. Parameters controlling such eviction can be user-configurable. For example, a lifetime can be set (e.g., specified by the user), and a 64-byte block can be evicted when it has not been accessed for a time interval exceeding its lifetime.

[0062] In some embodiments, when garbage collection is performed on a single-cell medium, data can be migrated from the single-cell medium to a three-cell medium. When data is migrated in this manner, since it is stored on the three-cell medium, the data can be considered NVMe data, and any records of it that have been accessed via CXL can be erased. All data stored on persistent storage medium 135 can be accessed at any time via CXL or NVMe.

[0063] In some embodiments, cache coherence is not an issue because each (64-byte or 4kB) block is stored in only one location in cache 140 (either in the area of ​​cache 140 allocated to CXL data or in the area of ​​cache 140 allocated to NVMe data).

[0064] Figure 3A and Figure 3B The caching indicator indicates that caching is possible and that cache 140 is full, and that there is both NVMe data and CXL data. The flowchart below shows an example of an NVMe read-modify-write operation. Figure 3A It is a flowchart of the read operation and Figure 3B (This is a flowchart of the write operation). Figure 3A At 302, persistent storage device 105 determines whether the data to be read is in the region of cache 140 allocated to NVMe data. If the data to be read is in the region of cache 140 allocated to NVMe data, then at 304, the data is read from the region of cache 140 allocated to NVMe data, and at 306, a 4kB page is returned. If the data to be read is not in the region of cache 140 allocated to NVMe data, then at 308, the data is read from persistent storage medium 135, and at 310, persistent storage device 105 (e.g., by searching a list of addresses associated with the region of cache 140 allocated to CXL data) determines whether the logical page address to be read is in the set of addresses associated with the corresponding 64-byte block in the region of cache 140 allocated to CXL data. If the logical page address being read is in the set of addresses associated with the corresponding 64-byte block in the region of cache 140 allocated to CXL data, then at 312, the data from the region of cache 140 allocated to CXL data and the data from the region of cache 140 allocated to NVMe data are combined or merged (e.g., any 64-byte block existing in the region of cache 140 allocated to CXL data is overwritten on the corresponding 64-byte block in the data read from the region of cache 140 allocated to NVMe data), and the process proceeds to step 306. Otherwise, at 314, data is written to the region of cache 140 allocated to NVMe data, and the process proceeds to step 306. Thus, when data is read from persistent storage, it is cached only if it does not overlap with any data in the region of cache 140 allocated to CXL data. In cases other than those described above (e.g.) Figure 3A and Figure 3BThe approach can differ depending on the context; for example, if the cache is full of CXL data, the write to the NVMe cache can be skipped at 314.

[0065] exist Figure 3B In order to perform a write operation, at 315, data is evicted from the region of cache 140 allocated to NVMe data; at 316, new data is written to the region of cache 140 allocated to NVMe data; at 318, persistent storage device 105 determines, for example, by searching a list of addresses associated with the region of cache 140 allocated to CXL data, whether the logical page address to be written is in the set of addresses associated with a 64-byte block in the region of cache 140 allocated to CXL data. If the logical page address to be written is in the set of addresses associated with a 64-byte block in the region of cache 140 allocated to CXL data, then at 320, the region of cache 140 allocated to CXL data is updated (for example, the affected CXL data (e.g., one or more 64-byte blocks of data) is invalidated to avoid storing data in both the region of cache 140 allocated to CXL data and the region of cache 140 allocated to NVMe data). Otherwise, this step is skipped (step 320). Then, at 322, a response is sent (e.g., NVMe write command completed). In cases different from the above (e.g.) Figure 3A and Figure 3B The approach can differ depending on the context; for example, if the cache is not full, eviction can be skipped at 315. If the cache is full of CXL data, only NVMe data can be written to persistent storage medium 135 (and not cached).

[0066] Figure 3C and Figure 3D The caching hint indicates that it is cacheable and that the cache is full (140 bytes). The example includes a flowchart of a CXL read-modify-write operation with both NVMe and CXL data. Figure 3C It is a flowchart of the read operation and Figure 3D (This is a flowchart of the write operation). Figure 3CAt 324, persistent storage device 105 (e.g., by searching a list of addresses associated with the region of cache 140 allocated to CXL data) determines whether the data to be read is in the region of cache 140 allocated to CXL data. If the data to be read is in the region of cache 140 allocated to CXL data, then at 326, the data is read from the region of cache 140 allocated to CXL data. If the data to be read is not in the area of ​​cache 140 allocated to CXL data, at 328, persistent storage device 105 determines whether the data is in the area of ​​cache 140 allocated to NVMe data (e.g., by searching a list of addresses associated with the area of ​​cache 140 allocated to NVMe data). If the data is in the area of ​​cache 140 allocated to NVMe data, at 330, the data is read from the area of ​​cache 140 allocated to NVMe data; and if the data is not in the area of ​​cache 140 allocated to NVMe data, at 332, the data is loaded from persistent storage medium 135 and stored in the area of ​​cache 140 allocated to CXL data. At 334, the data (e.g., 64-byte blocks of data) is returned.

[0067] exist Figure 3D At 336, persistent storage device 105 (e.g., by searching a list of addresses associated with regions of cache 140 allocated to CXL data) determines whether the data to be written (e.g., the address of the data) is in the region of cache 140 allocated to CXL data. If the data to be written is in the region of cache 140 allocated to CXL data, then at 338, the data is written to (or updated to) the region of cache 140 allocated to CXL data. If the data to be written is not in the region of cache 140 allocated to CXL data, then at 340, persistent storage device 105 (e.g., by searching a list of addresses associated with regions of cache 140 allocated to NVMe data) determines whether the data to be written (e.g., the address of the data) is in the region of cache 140 allocated to NVMe data. If the data to be written is in the area of ​​cache 140 allocated to NVMe data, then at 342, the data is updated in the area of ​​cache 140 allocated to NVMe data; if the data to be written is not in the area of ​​cache 140 allocated to NVMe data, then at 344, a 64-byte block of data is evicted from the area of ​​cache 140 allocated to CXL data, and execution continues to step 338. Afterwards, at 346, a response is sent (e.g., a CXL write command completion message).

[0068] Figure 4 This illustrates a decision tree used to select whether to execute a CXL read or write request (as part of a read-modify-write instruction) based on whether the request is a read or write request, whether a cache hit or miss occurs, and whether the cache hint indicates cacheability or non-cacheability. Figure 4 In this context, "N / A" indicates that the procedure selection is not affected by cache hints. The column marked "Procedure" identifies the procedure to be followed, with A referring to... Figure 5A B (refer to) Figure 5B C reference Figure 5C D reference Figure 5D E reference Figure 5E And F reference Figure 5F .

[0069] Figure 5A This is an example of a CXL read request in the event of a cache hit. At 511, persistent storage 105 receives the host physical address (HPA) and cache hint, and determines that a cache hit has occurred. Persistent storage 105 calculates the address by concatenating the LPA and CLO, sends the address to the area of ​​cache 140 allocated to CXL data at 512, receives the data (e.g., a cache line (64 bytes)) at 513, and sends the result (cache line) to the host at 514. Figure 5B This is an example of a CXL read request in the case of a cache hint set to be cacheable and a cache miss. At 521, persistent storage 105 receives the host physical address (HPA) and a cache hint; at 522, persistent storage 105 determines that a cache miss has occurred; at 523, persistent storage 105 sends a read request to flash translation layer 125; at 524, persistent storage 105 determines that the data is in the three-level cell medium and moves the data to the single-level cell medium. At 525, the data is cached in the area of ​​cache 140 allocated to CXL data, and at 526, the data is returned to the host. Figure 5C This is an example of a CXL read request in the case of a cache hint set to non-cacheable and a cache miss. At 531, persistent storage 105 receives the host physical address (HPA) and a cache hint; at 532, persistent storage 105 determines that a cache miss has occurred; at 533, persistent storage 105 sends a read request to flash translation layer 125. At 534, the result is read from the Level 3 cell medium (a 4kB block of data can be read, and data in the block can be discarded except for the 64-byte block of data requested by the host), and at 535 the result is returned to the host.

[0070] Figure 5D This is an example of a CXL write request in the event of a cache hit. At 541, persistent storage 105 receives the host physical address (HPA), a cache hint, and a cache line (e.g., the 64-byte block of data to be written), and determines that a cache hit has occurred. At 542, persistent storage 105 sends the address to the area of ​​cache 140 allocated to the CXL data, confirms the cache hit, writes the data at 543, and sends a response to the host at 544. Figure 5E This is an example of a CXL write request in the case of a cache hint and a cache miss, where the device is configured to be cacheable. At 551, persistent storage 105 receives the host physical address (HPA), a cache hint, and a cache line (e.g., a 64-byte block of data to be written); at 552, persistent storage 105 determines that a cache miss has occurred; at 553, persistent storage 105 sends a write request to flash translation layer 125; at 554, persistent storage 105 determines that the data is in a level 3 cell medium and saves the updated data in a single-cell medium (invalidating the old data in the level 3 cell and combining the cache line with the page read from the level 3 cell medium). At 555, the data is cached in the area of ​​cache 140 allocated to CXL data, and at 556, a response is sent to the host. Figure 5F This is an example of a CXL write request in the case of a cache hint set to non-cacheable and a cache miss. At 561, persistent storage 105 receives the host physical address (HPA), a cache hint, and a cache line (e.g., the 64-byte block of data to be written); at 562, persistent storage 105 determines that a cache miss has occurred; at 563, persistent storage 105 sends a write request to flash translation layer 125; at 564, persistent storage 105 determines that the data is in the L3 cell medium and saves the updated data in the L1 cell medium (invalidating the old data in the L3 cell). At 565, a response is sent to cache manager 122; and at 566, the response is forwarded to the host.

[0071] Figures 5A to 5D The process is unaffected by whether a log structured schema is adopted. Figure 5E and Figure 5F In this case, if a structured log mode is used, step four (e.g., 514) is not performed, and 64-byte blocks of data are written directly to the single-level cell medium. Figures 5A to 5F In each of these, the NVMe data paths used for similar operations can be similar.

[0072] In some embodiments, instead of processing two data payload sizes that are exactly different (e.g., 4kB and 64 bytes), persistent storage device 105 may process requests with payload sizes larger than the first threshold differently than requests with payload sizes smaller than the first threshold.

[0073] Figure 6 This is a flowchart of a method in some embodiments. The method includes the following steps: at 605, receiving a first write request (e.g., an NVMe write request) including a data load larger than a first threshold; at 610, storing the data load of the first write request in a first portion of a cache, the first portion being used for data units having a size larger than the first threshold; at 615, receiving a second write request (e.g., a CXL write request) including a data load smaller than the first threshold; and at 620, storing the data load of the second write request in a second portion of a cache, the second portion being used for data units having a size smaller than the first threshold.

[0074] As used herein, “part” means “at least some” of the thing, which can mean less than or all of the thing. Thus, as a special case, “part” of the thing includes the whole thing (i.e., the whole thing is an example of a part of the thing). As used herein, the term “or” should be interpreted as “and / or”, such that, for example, “A or B” means either “A” or “B” and “A and B”.

[0075] The background art provided in the Background section of this disclosure is included only to illustrate the context, and the content of this section is not intended to be considered prior art. Any component or combination of components described herein (e.g., in any system diagram included herein) may be used to perform one or more operations in any flowchart included herein. Furthermore, (i) the operations are example operations and may involve various additional steps not explicitly covered, and (ii) the temporal order of the operations may be changed.

[0076] Each of the terms “processing circuit” and “means for processing” is used herein to refer to any combination of hardware, firmware, and software for processing data or digital signals. Processing circuit hardware may include, for example, application-specific integrated circuits (ASICs), general-purpose or special-purpose central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), and programmable logic devices (such as field-programmable gate arrays (FPGAs)). In processing circuitry, as used herein, each function is performed by hardware configured (i.e., hardwired) to perform that function, or by more general-purpose hardware (such as a CPU) configured to execute instructions stored in a non-transitory storage medium. Processing circuitry may be fabricated on a single printed circuit board (PCB) or distributed across several interconnected PCBs. Processing circuitry may include other processing circuitry; for example, processing circuitry may include two processing circuits (FPGA and CPU) interconnected on a PCB.

[0077] As used herein, when a method (e.g., adjustment) or a first quantity (e.g., a first variable) is referred to as “based on” a second quantity (e.g., a second variable), this means that the second quantity is an input to the method or affects the first quantity (e.g., the second quantity may be an input to a function that computes the first quantity (e.g., a unique input or one of several inputs), or the first quantity may be equal to the second quantity, or the first quantity may be the same as the second quantity (e.g., at one or more locations in memory where the second quantity is stored).

[0078] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the spirit and scope of the inventive concept, the first element, first component, first region, first layer, or first portion discussed herein may be referred to as a second element, second component, second region, second layer, or second portion.

[0079] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. As used herein, the terms “substantially,” “about,” and similar terms are used as approximate terms rather than terms of degree, and are intended to take into account the inherent biases of measurements or calculations that will be recognized by those skilled in the art.

[0080] As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. It will also be understood that the terms “comprising” and / or “including” as used in this specification indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” modify the entire list of elements when following a list, without modifying any individual element in the list. Furthermore, the use of “may” in describing embodiments of the inventive concept means “one or more embodiments of this disclosure.” Additionally, the term “exemplary” is intended to indicate an example or illustration. As used herein, the term “use” and variations thereof may be considered synonymous with the term “utilize” and variations thereof.

[0081] It will be understood that when a component or layer is referred to as being "on" another component or layer, "connected to", "bonded to", or "adjacent to" another component or layer, it may be directly on, directly connected to, directly bonded to, or immediately adjacent to the other component or layer, or one or more intermediate components or layers may exist. Conversely, when a component or layer is referred to as being "directly on" another component or layer, "directly connected to", "directly bonded to", or "immediately adjacent to" another component or layer, no intermediate components or layers exist.

[0082] Any numerical range listed herein is intended to include all subranges of the same numerical precision that fall within the listed range. For example, the range “1.0 to 10.0” or “between 1.0 and 10.0” is intended to include all subranges between the listed minimum value 1.0 and the listed maximum value 10.0 (and includes both the listed minimum value 1.0 and the listed maximum value 10.0) (i.e., a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0 (e.g., 2.4 to 7.6)). Similarly, the range described as "within 35%" is intended to include all subranges between the listed minimum value of 6.5 (i.e., (1-35 / 100) multiplied by 10) and the listed maximum value of 13.5 (i.e., (1+35 / 100) multiplied by 10) (and includes both the listed minimum value of 6.5 and the listed maximum value of 13.5) (i.e., a minimum value equal to or greater than 6.5 and a maximum value equal to or less than 13.5 (e.g., 7.4 to 10.6)). Any maximum numerical limit listed herein is intended to include all lower numerical limits thereunder, and any minimum numerical limit listed in this specification is intended to include all higher numerical limits thereunder.

[0083] Some embodiments may include the features listed below.

[0084] 1. A persistent storage device, comprising:

[0085] Processing circuitry;

[0086] Cache; and

[0087] Persistent storage devices,

[0088] The processing circuit is configured to execute a method, the method comprising:

[0089] Receive the first write request according to the first protocol;

[0090] The data payload of the first write request is stored in the first part of the cache;

[0091] Receive a second write request according to the second protocol; and

[0092] The data payload of the second write request is stored in the second part of the cache.

[0093] 2. The persistent storage device according to statement 1, wherein the first write request includes an instruction to the persistent storage device to use a cache hint for caching.

[0094] 3. The persistent storage device according to statement 1 or statement 2, wherein:

[0095] The first protocol addresses data units at a first granularity;

[0096] The second protocol addresses data units at a different granularity than the first protocol; and

[0097] The method further includes:

[0098] Receive a third write request, the third write request including a data payload and a cache hint, the cache hint instructing the persistent storage device to abandon caching; and

[0099] The data payload of the third write request is stored in persistent storage.

[0100] 4. The persistent storage device according to statement 3, wherein:

[0101] The persistent storage device includes a first storage medium and a second storage medium, wherein the first storage medium has a higher read latency than the second storage medium;

[0102] The data load of the third write request is less than the first threshold; and

[0103] The step of storing the data payload of the third write request in persistent storage includes: storing the data payload of the third write request in a second storage medium.

[0104] 5. The persistent storage device according to statement 4, wherein:

[0105] The first storage medium comprises three levels of cells; and

[0106] The second storage medium comprises a single-level cell.

[0107] 6. The persistent storage device according to statement 4, wherein the method further comprises:

[0108] Receive a fourth write request, which includes a data payload and a cache hint, the cache hint instructing the search for persistent storage to abandon caching; and

[0109] The data payload of the fourth write request is stored in persistent storage.

[0110] in:

[0111] The data load of the fourth write request is greater than the first threshold; and

[0112] The steps of storing the data payload of the fourth write request in persistent storage include: storing the data payload of the fourth write request in a first storage medium.

[0113] 7. The persistent storage device according to statement 6, wherein the method further comprises:

[0114] A fifth write request is received, which includes a cache hint and a data load larger than a first threshold. The cache hint indicates that the persistent storage device should perform caching.

[0115] It was determined that the first part of the cache was full;

[0116] Eject data from the first part of the cache; and

[0117] The data payload of the fifth write request is stored in the first part of the cache.

[0118] 8. The persistent storage device according to statement 6, wherein the method further comprises:

[0119] A fifth write request is received, the fifth write request including a cache hint and a data load smaller than a first threshold, the cache hint instructing the persistent storage device to perform caching;

[0120] Determine that the second part of the cache is full and that there is space available in the first part of the cache;

[0121] Reduce the size of the first part of the cache;

[0122] Increase the size of the second part of the cache; and

[0123] The data payload of the fifth write request is stored in the second part of the cache.

[0124] 9. The persistent storage device according to statement 8, wherein the method further comprises:

[0125] A sixth write request is received, the sixth write request including a cache hint and a data load smaller than a first threshold, the cache hint instructing the persistent storage device to perform caching;

[0126] Determine that the first part of the cache is full and the second part of the cache is full;

[0127] Eject data from the first part of the cache;

[0128] Reduce the size of the first part of the cache;

[0129] Increase the size of the second part of the cache; and

[0130] The data payload of the sixth write request is stored in the second part of the cache.

[0131] 10. The persistent storage device according to statement 8, wherein the method further comprises:

[0132] A sixth write request is received, the sixth write request including a cache hint and a data load smaller than a first threshold, the cache hint instructing the persistent storage device to perform caching;

[0133] It is determined that the first part of the cache has a size of zero and the second part of the cache is full;

[0134] Eject data from the second part of the cache; and

[0135] The data payload of the sixth write request is stored in the second part of the cache.

[0136] 11. The persistent storage device according to any of the foregoing statements, wherein the first write request is a Non-Volatile Memory Fast (NVMe) write request and the second write request is a Compute Fast Link (CXL) write request.

[0137] 12. A method comprising:

[0138] Receive a first write request according to the first protocol through a persistent storage device;

[0139] The data payload of the first write request is stored in the first part of the cache;

[0140] Receive a second write request according to the second protocol; and

[0141] The data payload of the second write request is stored in the second part of the cache.

[0142] 13. The method according to statement 12, wherein the first write request includes instructing the persistent storage device to use a cache hint for caching.

[0143] 14. The method according to statement 12, wherein:

[0144] The first protocol addresses data units at a first granularity;

[0145] The second protocol addresses data units at a different granularity than the first protocol; and

[0146] The method further includes:

[0147] Receive a third write request, which includes a data payload and a cache hint, the cache hint instructing persistent storage to abandon caching; and

[0148] The data payload of the third write request is stored in the persistent storage device of the persistent storage device.

[0149] 15. The method according to statement 14, wherein:

[0150] The persistent storage device includes a first storage medium and a second storage medium, wherein the first storage medium has a higher read latency than the second storage medium;

[0151] The data load of the third write request is less than the first threshold; and

[0152] The step of storing the data payload of the third write request in persistent storage includes: storing the data payload of the third write request in a second storage medium.

[0153] 16. The method according to statement 15, wherein:

[0154] The first storage medium comprises three levels of cells; and

[0155] The second storage medium comprises a single-level cell.

[0156] 17. The method according to statement 15 or statement 16 further includes:

[0157] Receive a fourth write request, which includes a data payload and a cache hint, the cache hint instructing persistent storage to abandon caching; and

[0158] The data payload of the fourth write request is stored in persistent storage, where,

[0159] The data load of the fourth write request is greater than the first threshold; and

[0160] The steps of storing the data payload of the fourth write request in persistent storage include: storing the data payload of the fourth write request in a first storage medium.

[0161] 18. The method according to statement 17 further includes:

[0162] A fifth write request is received, which includes a cache hint and a data payload larger than the first threshold. The cache hint indicates that the persistent storage device should perform caching.

[0163] It was determined that the first part of the cache was full;

[0164] Eject data from the first part of the cache; and

[0165] The data payload of the fifth write request is stored in the first part of the cache.

[0166] 19. The method according to statement 17 further includes:

[0167] A fifth write request is received, which includes a cache hint and a data payload smaller than the first threshold. The cache hint indicates that the persistent storage device should perform caching.

[0168] Determine that the second part of the cache is full and that there is space available in the first part of the cache;

[0169] Reduce the size of the first part of the cache;

[0170] Increase the size of the second part of the cache; and

[0171] The data payload of the fifth write request is stored in the second part of the cache.

[0172] 20. A persistent storage device, comprising:

[0173] Device for processing;

[0174] Cache; and

[0175] Persistent storage devices,

[0176] The apparatus for processing is configured to perform a method, the method comprising:

[0177] Receive a first write request that includes a data load larger than the first threshold;

[0178] The data payload of the first write request is stored in the first part of the cache, the first part being used for data units of a size larger than a first threshold;

[0179] Receive a second write request including a data load smaller than the first threshold; and

[0180] The data payload of the second write request is stored in a second part of the cache, which is used for data units with a size smaller than the first threshold.

[0181] Although exemplary embodiments of systems and methods for persistent storage devices have been specifically described and shown herein, many modifications and variations will be apparent to those skilled in the art. Therefore, it should be understood that systems and methods for persistent storage devices constructed in accordance with the principles of this disclosure may be embodied in ways different from those specifically described herein. The invention is also defined in the appended claims and their equivalents.

Claims

1. A persistent storage device, comprising: Processing circuitry; Cache; as well as Persistent storage devices, The processing circuit is configured to execute a method, the method comprising: Receive a first write request according to a first protocol, wherein the first write request includes a cache hint corresponding to the first protocol; Based on the cache hints included in the first write request, the data payload of the first write request is stored in the first part of the cache corresponding to the first protocol; Receive a second write request according to the second protocol; and The data payload of the second write request is stored in the second part of the cache corresponding to the second protocol. The cache is partitioned into a first part corresponding to the first protocol and a second part corresponding to the second protocol, and the partitions can be dynamically adjusted. The first protocol addresses data units at a first granularity, while the second protocol addresses data units at a second granularity different from the first granularity.

2. The persistent storage device according to claim 1, wherein, The cache hint included in the first write request is configured to instruct the persistent storage device to perform caching.

3. The persistent storage device according to claim 1, wherein: The method further includes: Receive a third write request, the third write request including a data payload and a cache hint, the cache hint included in the third write request instructing the persistent storage device to abandon caching; and The data payload of the third write request is stored in persistent storage.

4. The persistent storage device according to claim 3, wherein: The persistent storage device includes a first storage medium and a second storage medium, wherein the first storage medium has a higher read latency than the second storage medium; The data load of the third write request is less than the first threshold; and The step of storing the data payload of the third write request in persistent storage includes: storing the data payload of the third write request in a second storage medium.

5. The persistent storage device according to claim 4, wherein: The first storage medium comprises three levels of cells; and The second storage medium comprises a single-level cell.

6. The persistent storage device according to claim 4, wherein, The method further includes: Receive a fourth write request, the fourth write request including a data payload and a cache hint, the cache hint included in the fourth write request instructing the persistent storage device to abandon caching; and The data payload of the fourth write request is stored in persistent storage. in: The data load of the fourth write request is greater than the first threshold; and The steps of storing the data payload of the fourth write request in persistent storage include: storing the data payload of the fourth write request in a first storage medium.

7. The persistent storage device according to claim 6, wherein, The method further includes: A fifth write request is received, the fifth write request including a cache hint and a data load larger than a first threshold, the cache hint included in the fifth write request instructing the persistent storage device to perform caching; It has been determined that the first part of the cache is full. Eject data from the first part of the cache; and The data payload of the fifth write request is stored in the first part of the cache.

8. The persistent storage device according to claim 6, wherein, The method further includes: A fifth write request is received, the fifth write request including a cache hint and a data load smaller than a first threshold, the cache hint included in the fifth write request instructing the persistent storage device to perform caching; Determine that the second part of the cache is full and that space is available in the first part of the cache. Reduce the size of the first part of the cache; Increase the size of the second part of the cache; and The data payload of the fifth write request is stored in the second part of the cache.

9. The persistent storage device according to claim 8, wherein, The method further includes: A sixth write request is received, the sixth write request including a cache hint and a data load smaller than a first threshold, the cache hint included in the sixth write request instructing the persistent storage device to perform caching; Determine that the first part of the cache is full and the second part of the cache is full; Eject data from the first part of the cache; Reduce the size of the first part of the cache; Increase the size of the second part of the cache; and The data payload of the sixth write request is stored in the second part of the cache.

10. The persistent storage device according to claim 8, wherein, The method further includes: A sixth write request is received, the sixth write request including a cache hint and a data load smaller than a first threshold, the cache hint included in the sixth write request instructing the persistent storage device to perform caching; It is determined that the first part of the cache has a size of zero and the second part of the cache is full; Eject data from the second part of the cache; and The data payload of the sixth write request is stored in the second part of the cache.

11. The persistent storage device according to claim 1, wherein, The first write request is a non-volatile memory fast write request, and the second write request is a compute fast link write request.

12. A method comprising: A first write request is received via persistent storage device according to a first protocol, wherein the first write request includes a cache hint corresponding to the first protocol; Based on the cache hints included in the first write request, the data payload of the first write request is stored in the first part of the cache corresponding to the first protocol; Receive a second write request according to the second protocol; and The data payload of the second write request is stored in the second part of the cache corresponding to the second protocol. The cache is partitioned into a first part corresponding to the first protocol and a second part corresponding to the second protocol, and the partitions can be dynamically adjusted. The first protocol addresses data units at a first granularity, while the second protocol addresses data units at a second granularity different from the first granularity.

13. The method according to claim 12, wherein, The cache hint included in the first write request is configured to instruct persistent storage to perform caching.

14. The method according to claim 12, wherein: The method further includes: Receive a third write request, which includes a data payload and a cache hint. The cache hint included in the third write request instructs persistent storage to abandon caching. The data payload of the third write request is stored in the persistent storage device of the persistent storage device.

15. The method of claim 14, wherein: The persistent storage device includes a first storage medium and a second storage medium, wherein the first storage medium has a higher read latency than the second storage medium; The data load of the third write request is less than the first threshold; and The step of storing the data payload of the third write request in persistent storage includes: storing the data payload of the third write request in a second storage medium.

16. The method of claim 15, wherein: The first storage medium comprises three levels of cells; and The second storage medium comprises a single-level cell.

17. The method of claim 15, further comprising: Receive a fourth write request, which includes a data payload and a cache hint, the cache hint included in the fourth write request instructing persistent storage to abandon caching; as well as The data payload of the fourth write request is stored in persistent storage. in: The data load of the fourth write request is greater than the first threshold; and The steps of storing the data payload of the fourth write request in persistent storage include: storing the data payload of the fourth write request in a first storage medium.

18. The method of claim 17, further comprising: A fifth write request is received, which includes a cache hint and a data payload larger than the first threshold. The cache hint included in the fifth write request indicates that the persistent storage device should perform caching. It has been determined that the first part of the cache is full. Eject data from the first part of the cache; as well as The data payload of the fifth write request is stored in the first part of the cache.

19. The method of claim 17, further comprising: A fifth write request is received, which includes a cache hint and a data payload smaller than the first threshold. The cache hint included in the fifth write request indicates that the persistent storage device should perform caching. Determine that the second part of the cache is full and that space is available in the first part of the cache. Reduce the size of the first part of the cache; Increase the size of the second part of the cache; as well as The data payload of the fifth write request is stored in the second part of the cache.

20. A persistent storage device, comprising: processor; Cache; as well as Persistent storage devices, The processor is configured to execute a method, the method comprising: Receive a first write request according to a first protocol, which includes a data load greater than a first threshold, wherein the first write request includes a cache hint corresponding to the first protocol; Based on the cache hints included in the first write request, the data payload of the first write request is stored in the first part of the cache corresponding to the first protocol, and the first part is used for data units with a size larger than the first threshold. Receive a second write request according to the second protocol, comprising a data payload smaller than the first threshold; and The data payload of the second write request is stored in the second part of the cache corresponding to the second protocol. The second part is used for data units with a size smaller than the first threshold. The cache is partitioned into a first part corresponding to the first protocol and a second part corresponding to the second protocol, and the partitions can be dynamically adjusted. The first protocol addresses data units at a first granularity, while the second protocol addresses data units at a second granularity different from the first granularity.

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