Display substrate, display device

Abstract

A display substrate and a display device are disclosed. The display substrate includes a display area and a bonding area connected to the display area. The display area includes multiple data signal lines and K rows and L columns of sub-pixels, where K and L are both positive integers greater than 1. Multiple first spaces are included between the K sub-pixel rows, and multiple second spaces are included between the L sub-pixel columns. The first spaces are located between two adjacent sub-pixel rows, and the second spaces are located between two adjacent sub-pixel columns. At least one first space is provided with a first data connection line, and at least one second space is provided with at least one second data connection line. One end of the first data connection line is electrically connected to one of the data signal lines, and the other end is electrically connected to one of the second data connection lines. One end of the second data connection line is electrically connected to the first data line, and the other end is electrically connected to the bonding area.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] In a first aspect, embodiments of this disclosure provide a display substrate, including a display area and a bonding area connected to the display area. The display area includes multiple data signal lines and K rows and L columns of sub-pixels, where K and L are both positive integers greater than 1. Multiple first spaces are included between the K sub-pixel rows, and multiple second spaces are included between the L sub-pixel columns. The first spaces are located between two adjacent sub-pixel rows, and the second spaces are located between two adjacent sub-pixel columns. At least one first space is provided with a first data connection line, and at least one second space is provided with at least one second data connection line. On a plane parallel to the display substrate, the first data connection line extends along a first direction, and the second data connection line extends along a second direction, where the first direction intersects the second direction.

[0005] One end of the first data connection line is electrically connected to one of the data signal lines, and the other end is electrically connected to one of the second data connection lines; one end of the second data connection line is electrically connected to the first data connection line, and the other end is electrically connected to the bonding area.

[0006] In an exemplary embodiment, the first space is further provided with a fourth data connection line, and the second space is further provided with a third data connection line;

[0007] The same second space is provided with at least one second data connection line and at least one third data connection line;

[0008] The fourth data connection line extends along the first direction, with one end electrically connected to the data signal line and the other end connected to the third data connection line; the third data connection line extends along the second direction, with one end connected to the fourth data connection line and the other end electrically connected to the bonding area.

[0009] The first data connection line and the second data connection line are connected by a via, and the third data connection line and the fourth data connection line are integrally formed.

[0010] In an exemplary embodiment, the first data connection line and the fourth data connection line are located in different first spaces.

[0011] In an exemplary embodiment, in the same second space, there is one third data connection line and two second data connection lines. In the plane where the display substrate is located, in the first direction, the two second data connection lines are located on both sides of the third data connection line. The two second data connection lines in the same second space are connected to different first data connection lines.

[0012] Alternatively, in the same second space, there are two third data connection lines and one second data connection line. In the plane where the display substrate is located, in the first direction, the two third data connection lines are located on both sides of the second data connection line, and the two third data connection lines in the same second space are connected to different fourth data connection lines.

[0013] In an exemplary embodiment, there are three second data connection lines in the same second space, and the three second data connection lines are respectively connected to three different first data connection lines.

[0014] In an exemplary embodiment, at least one sub-pixel includes a pixel driving circuit. In a plane perpendicular to the display substrate, the display substrate includes a substrate and a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially stacked on the substrate.

[0015] The first semiconductor layer includes: an active layer of a plurality of low-temperature polysilicon transistors located in the pixel driving circuit; the first conductive layer includes: a control electrode of a plurality of polysilicon transistors located in the pixel driving circuit and a first electrode of a storage capacitor; the second conductive layer includes: a second electrode of a storage capacitor located in the pixel driving circuit; the second semiconductor layer includes: an active layer of a plurality of oxide transistors located in the pixel driving circuit; the third conductive layer includes: a control electrode of a plurality of oxide transistors located in the pixel driving circuit; the fourth conductive layer includes: the first data connection line and the first and second electrodes of a plurality of low-temperature polysilicon transistors and a plurality of oxide transistors located in the pixel driving circuit; the fifth conductive layer includes: a data signal line, a first power line, and the second data connection line.

[0016] In an exemplary embodiment, the display substrate further includes a light-emitting element, and the plurality of low-temperature polysilicon transistors include a seventh transistor for anode reset of the light-emitting element. The third conductive layer further includes a transition connection electrode, and the fourth conductive layer further includes a plurality of second initial signal lines. In the plane of the fourth conductive layer, the main body of the second initial signal line is a zigzag shape extending along a first direction. The plurality of second initial signal lines are arranged in an array along the first direction and the second direction. The second initial signal lines are connected to the active layer of the seventh transistor in the first semiconductor layer through vias and are multiplexed as the first electrode of the seventh transistor. In the same sub-pixel row, two adjacent second initial signal lines are connected to the same transition connection electrode through transition vias.

[0017] In an exemplary embodiment, the adapter electrode extends along a first direction, and the orthographic projection of the adapter electrode on the substrate overlaps with the orthographic projection of one of the second spaces on the substrate.

[0018] In an exemplary embodiment, the fourth conductive layer further includes a fourth data connection line and a third data connection line, wherein the orthographic projection of the fourth data connection line on the substrate at least partially overlaps with the orthographic projection of one of the first spaces on the substrate, and the orthographic projection of the fourth data connection line on the substrate does not overlap with the orthographic projection of the first data connection line on the substrate; the orthographic projection of the third data connection line on the substrate at least partially overlaps with the orthographic projection of one of the second spaces on the substrate.

[0019] The third data connection line extends along the second direction, with one end connected to the fourth data connection line and the other end electrically connected to the bonding area; the fourth data connection line extends along the first direction, with one end connected to the third data connection line and the other end electrically connected to one of the data signal lines in the fifth conductive layer through a via. In an exemplary embodiment, in the same second space, the orthographic projection of the second data connection line on the substrate and the orthographic projection of the third data connection line on the substrate do not overlap.

[0020] In an exemplary embodiment, in the same second space, there is one third data connection line and two second data connection lines, and the orthographic projection of the third data connection line on the substrate is located between the orthographic projections of the two second data connection lines on the substrate.

[0021] Alternatively, in the same second space, there are two third data connection lines and one second data connection line, with the orthographic projection of the second data connection line on the substrate located between the orthographic projections of the two third data connection lines on the substrate.

[0022] In an exemplary embodiment, the orthographic projections of the second data connection line and the third data connection line on the substrate overlap with the orthographic projection of the adapter electrode on the substrate, but the orthographic projections of the second data connection line and the third data connection line on the substrate do not overlap with the orthographic projection of the second initial signal line on the substrate.

[0023] In an exemplary embodiment, the pixel driving circuit further includes: a first transistor to a sixth transistor, and a storage capacitor;

[0024] On a plane parallel to the display substrate, in the same pixel driving circuit, in a first direction, the sixth transistor is located on one side of the storage capacitor, and the fifth and fourth transistors are located on the other side of the storage capacitor; in a second direction, the fifth, sixth, and seventh transistors are located on the same side of the storage capacitor, and the fourth, first, and second transistors are located on the other side of the storage capacitor. Furthermore, the seventh transistor is located on the side of the sixth transistor away from the storage capacitor, and the first transistor is located on the side of the second transistor away from the storage capacitor. The orthographic projection of the storage capacitor onto the substrate overlaps with the orthographic projection of the third transistor onto the substrate. The seventh transistor in the i-th row of sub-pixels is located in the (i-1)-th row of sub-pixels, where i = 2, 3, ..., K.

[0025] In the second direction, in two sub-pixel rows adjacent to the first data connection line, the first transistor of the previous sub-pixel row and the fifth and sixth transistors of the next sub-pixel row are located on both sides of the first data connection line, and the seventh transistor of the next sub-pixel row is located on the same side of the first data connection line as the first transistor of the previous sub-pixel row; in two sub-pixel rows adjacent to the fourth data connection line, the first transistor of the previous sub-pixel row and the fifth and sixth transistors of the next sub-pixel row are located on both sides of the fourth data connection line, and the seventh transistor of the next sub-pixel row is located on the same side of the fourth data connection line as the first transistor of the previous sub-pixel row; in the first direction, the total number of second and third data connection lines is three, and the three data connection lines are arranged along the first direction line. The two data connection lines on both sides are symmetrical with respect to the data connection line in the middle position. In the same sub-pixel row, the first to seventh transistors and the storage capacitor in the two sub-pixel columns adjacent to the second and third data connection lines in the same second space are symmetrically arranged with respect to the data connection line in the middle position.

[0026] In an exemplary embodiment, in the fourth conductive layer, the fourth data connection line and the first electrode of the fourth transistor in one of the pixel driving circuits are integrally formed. The first electrode of the fourth transistor, which is integrally formed with the fourth data connection line, is a strip-shaped structure or a zigzag structure and extends along the second direction. One end is connected to the fourth data connection line, and the other end is electrically connected to the data signal line in the fifth conductive layer through a via. One end of the fourth data connection line is connected to the first electrode of the fourth transistor, and the other end is connected to the third data connection line.

[0027] The first data connection line is integrally formed with the first electrode of one of the fourth transistors. The first electrode of the fourth transistor, which is integrally formed with the first data connection line, is a strip-shaped or zigzag-shaped structure and extends along the second direction. One end of the strip-shaped structure is connected to the first data connection line, and the other end is electrically connected to the data signal line in the fifth conductive layer through a via. One end of the first data connection line is connected to the first electrode of the fourth transistor, and the other end is electrically connected to the second data connection line in the fifth conductive layer through a via.

[0028] In an exemplary embodiment, there are three second data connection lines in the same second space, and the orthographic projections of the three second data connection lines on the substrate do not overlap. The three second data connection lines are electrically connected to the first data connection lines in three different first spaces in the fourth conductive layer through three different vias.

[0029] In an exemplary embodiment, the display substrate further includes a light-emitting element, and the plurality of low-temperature polysilicon transistors include a seventh transistor for resetting the light-emitting element. The fourth conductive layer further includes an initial signal connection line and a plurality of second initial signal lines. The second initial signal lines are connected to the active layer of the seventh transistor in the first semiconductor layer through vias and are multiplexed as the first electrode of the seventh transistor. In the plane of the fourth conductive layer, the main body of the second initial signal line is a zigzag line extending along a first direction, and the plurality of second initial signal lines are arranged along a second direction. The initial signal connection line extends along the second direction and is integrally formed with the plurality of second initial signal lines.

[0030] In an exemplary embodiment, among the three second data connection lines, the orthographic projection of the second data connection line located in the middle position on the substrate overlaps with the orthographic projection of the initial signal connection line on the substrate, and the orthographic projections of the second data connection lines located on both sides on the substrate overlap with the orthographic projections of the second initial signal line on the substrate.

[0031] In an exemplary embodiment, the pixel driving circuit further includes: a first transistor to a sixth transistor, and a storage capacitor;

[0032] On a plane parallel to the display substrate, in the same pixel driving circuit, in a first direction, the sixth transistor is located on one side of the storage capacitor, and the fifth and fourth transistors are located on the other side of the storage capacitor; in a second direction, the fifth, sixth, and seventh transistors are located on the same side of the storage capacitor, and the fourth, first, and second transistors are located on the other side of the storage capacitor. Furthermore, the seventh transistor is located on the side of the sixth transistor away from the storage capacitor, and the first transistor is located on the side of the second transistor away from the storage capacitor. The orthographic projection of the storage capacitor onto the substrate overlaps with the orthographic projection of the third transistor onto the substrate. The seventh transistor in the i-th row of sub-pixels is located in the (i-1)-th row of sub-pixels, where i = 2, 3, ..., K.

[0033] In the second direction, in the two sub-pixel rows adjacent to the first data connection line, the first transistor of the previous sub-pixel row and the fifth and sixth transistors of the next sub-pixel row are located on both sides of the first data connection line, and the seventh transistor of the next sub-pixel row is located on the same side of the first data connection line as the first transistor of the previous sub-pixel row; in the first direction, the three second data connection lines are arranged sequentially, with the second data connection lines on both sides being symmetrical with respect to the second data connection line in the middle position. In the same sub-pixel row, the first to seventh transistors and the storage capacitor in the two sub-pixel columns adjacent to the three second data connection lines are symmetrically arranged with respect to the second data connection line in the middle position.

[0034] In an exemplary embodiment, in the fourth conductive layer, the first data connection line and the first electrode of one of the fourth transistors are integrally formed. The first electrode of the fourth transistor, which is integrally formed with the first data connection line, is a strip-shaped or zigzag-shaped structure and extends along a second direction. One end of the strip-shaped structure is connected to the first data connection line, and the other end is electrically connected to the data signal line in the fifth conductive layer through a via. One end of the first data connection line is connected to the first electrode of the fourth transistor, and the other end is electrically connected to the second data connection line in the fifth conductive layer through a via.

[0035] In an exemplary embodiment, one end of the first data connection line has an overlapping region with the orthographic projection of one of the second data connection lines on the substrate, and is electrically connected to the second data connection line in the overlapping region through a via. The other end of the first data connection line has an overlapping region with the orthographic projection of one of the data signal lines on the substrate, and is electrically connected to the data signal line in the overlapping region through a via.

[0036] Secondly, embodiments of this disclosure also provide a display device, including the display substrate described in any of the above embodiments.

[0037] Thirdly, this disclosure also provides a method for fabricating a display substrate. The display substrate includes a display area and a bonding area connected to the display area. The display area includes multiple data signal lines and K rows and L columns of sub-pixels, where K and L are both positive integers greater than 1. Multiple first spaces are included between the K sub-pixel rows, and multiple second spaces are included between the L sub-pixel columns. The first spaces are located between two adjacent sub-pixel rows, and the second spaces are located between two adjacent sub-pixel columns. At least one first space is provided with a first data connection line, and at least one second space is provided with at least one second data connection line. On a plane parallel to the display substrate, the first data connection line extends along a first direction, and the second data connection line extends along a second direction, where the first direction intersects the second direction. The fabrication method includes:

[0038] One end of the first data connection line is electrically connected to one of the data signal lines, and the other end is electrically connected to one of the second data connection lines; one end of the second data connection line is electrically connected to the first data line, and the other end is electrically connected to the bonding area.

[0039] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0040] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of each component in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0041] Figure 1 This is a schematic diagram of the structure of a display device;

[0042] Figure 2 This is a schematic diagram of the structure of a display substrate;

[0043] Figure 3 This is a schematic diagram of the planar structure of a display area in a display substrate;

[0044] Figure 4 This is a schematic cross-sectional view of a display area in a display substrate.

[0045] Figure 5 This is a schematic diagram of an equivalent circuit for a pixel driving circuit.

[0046] Figure 6 This is a timing diagram of a pixel driving circuit.

[0047] Figure 7a The diagram shown is a schematic representation of the structure of a display substrate provided in an exemplary embodiment of this disclosure.

[0048] Figure 7b The diagram shown is a schematic representation of the structure of a display substrate provided in an exemplary embodiment of this disclosure.

[0049] Figure 8a The diagram shown is a schematic representation of the structure of a display substrate provided in an exemplary embodiment of this disclosure.

[0050] Figure 8b The diagram shown is a schematic representation of the structure of a display substrate provided in an exemplary embodiment of this disclosure.

[0051] Figure 8c The diagram shown is a schematic representation of the structure of a display substrate provided in an exemplary embodiment of this disclosure.

[0052] Figure 9 The diagram shown is a schematic diagram of a display substrate after a shielding layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0053] Figure 10a The diagram shown is a schematic diagram of a display substrate after a first semiconductor layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0054] Figure 10b The diagram shown is a schematic diagram of the first semiconductor layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0055] Figure 11a The diagram shown is a schematic diagram of a display substrate after the formation of the first conductive layer pattern according to an exemplary embodiment of the present disclosure.

[0056] Figure 11b The diagram shown is a schematic diagram of the first conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0057] Figure 12a The diagram shown is a schematic diagram of a display substrate after the second conductive layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0058] Figure 12b The diagram shown is a schematic diagram of the second conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0059] Figure 13a The diagram shown is a schematic diagram of a display substrate after a second semiconductor layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0060] Figure 13b The diagram shown is a schematic diagram of the second semiconductor layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0061] Figure 14a The diagram shown is a schematic diagram of a display substrate after the formation of the third conductive layer pattern according to an exemplary embodiment of the present disclosure.

[0062] Figure 14b The diagram shown is a schematic diagram of the third conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0063] Figure 15 The diagram shown is a schematic diagram of a display substrate after the formation of the sixth insulating layer pattern according to an exemplary embodiment of the present disclosure;

[0064] Figure 16a The diagram shown is a schematic diagram of a display substrate after the fourth conductive layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0065] Figure 16bThe diagram shown is a schematic diagram of the fourth conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0066] Figure 16c The diagram shown is a schematic diagram of a display substrate after the fourth conductive layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0067] Figure 16d The diagram shown is a schematic diagram of the fourth conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0068] Figure 17a The diagram shown is a schematic diagram of the formation of a first planarization layer pattern according to an exemplary embodiment of the present disclosure;

[0069] Figure 17b The diagram shown is a schematic diagram of the formation of a first planarization layer pattern according to an exemplary embodiment of the present disclosure;

[0070] Figure 18a The diagram shown is a schematic diagram of a display substrate after the fifth conductive layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0071] Figure 18b The diagram shown is a schematic diagram of the fifth conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0072] Figure 18c The diagram shown is a schematic diagram of a display substrate after the fifth conductive layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0073] Figure 19a The diagram shown is a schematic diagram of a display substrate after a first semiconductor layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0074] Figure 19b The diagram shown is a schematic diagram of the first semiconductor layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0075] Figure 20a The diagram shown is a schematic diagram of a display substrate after the formation of the first conductive layer pattern according to an exemplary embodiment of the present disclosure.

[0076] Figure 20b The diagram shown is a schematic diagram of the first conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0077] Figure 21 The diagram shown is a schematic diagram of a display substrate after the second conductive layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0078] Figure 22 The diagram shown is a schematic diagram of a display substrate after a second semiconductor layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0079] Figure 23a The diagram shown is a schematic diagram of a display substrate after the formation of the third conductive layer pattern according to an exemplary embodiment of the present disclosure.

[0080] Figure 23b The diagram shown is a schematic diagram of the third conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0081] Figure 24 The diagram shown is a schematic diagram of a display substrate after the formation of the sixth insulating layer pattern according to an exemplary embodiment of the present disclosure;

[0082] Figure 25a The diagram shown is a schematic diagram of a display substrate after the fourth conductive layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0083] Figure 25b The diagram shown is a schematic diagram of the fourth conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0084] Figure 25c The diagram shown is a schematic diagram of a display substrate after the fourth conductive layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0085] Figure 25d The diagram shown is a schematic diagram of the fourth conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0086] Figure 26a The diagram shown is a schematic diagram of a display substrate after a first planarization layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0087] Figure 26b The diagram shown is a schematic diagram of a display substrate after a first planarization layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0088] Figure 27a The diagram shown is a schematic diagram of a display substrate after the fifth conductive layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0089] Figure 27b The diagram shown is a schematic diagram of the fifth conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0090] Figure 27c The diagram shown is a schematic diagram of a display substrate after the fifth conductive layer pattern has been formed, according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0091] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as being limited only to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0092] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the thickness and spacing of each film layer, and the width and spacing of each signal line, can be adjusted according to actual conditions. The drawings described in this disclosure are merely structural schematic diagrams, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0093] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0094] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0095] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0096] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0097] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged. In embodiments of this disclosure, the gate electrode can be referred to as the control electrode.

[0098] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0099] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0100] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0101] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfered corners, curved edges, and other variations.

[0102] In the embodiments of this disclosure, "about" means a value that is not strictly limited and is within the range of process and measurement errors.

[0103] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include at least one scan signal line, at least one data signal line, at least one light-emitting signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, emission stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, an LED driver can sequentially provide transmit signals with cutoff level pulses to LED signal lines E1 to Eo. For example, the LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0104] Figure 2 This is a schematic diagram of the structure of a display substrate. Figure 2As shown, the display substrate may include a display area 100, a bonding area 200 located on one side of the display area 100, and a border area 300 located on other sides of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of sub-pixels Pxij constituting a pixel array, the plurality of sub-pixels Pxij being configured to display moving images or still images, and the display area 100 may be referred to as the effective area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as being rolled, bent, folded, or rolled up. In an exemplary embodiment, the display substrate may further include a display area boundary BD, which may be the edge of the display area 100 near the bonding area 200.

[0105] In an exemplary embodiment, the bonding area 200 may include a fan-out area, a bending area, a driver chip area, and a bonding pin area arranged sequentially along a direction away from the display area. The fan-out area is connected to the display area and includes multiple data fan-out lines configured to connect to the data signal lines of the display area in a fan-out routing manner. The fan-out area occupies a large space, resulting in a larger bottom bezel width. The bending area is connected to the fan-out area and may include a composite insulating layer with grooves, configured to bend the bonding area to the back of the display area. The driver chip area may include an integrated circuit (IC) configured to connect to the multiple data fan-out lines. The bonding pin area may include bonding pads configured to bond to an external flexible printed circuit (FPC).

[0106] In an exemplary embodiment, the bezel region 300 may include a circuit region, a power line region, a crack dam region, and a cutting region arranged sequentially along a direction away from the display region. The circuit region is connected to the display region and may include at least a gate driving circuit connected to a first scan signal line, a second scan signal line, a third scan signal line, and a light emission control line of a pixel driving circuit in the display region. The power line region is connected to the circuit region and may include at least power leads extending parallel to the edge of the display region and connected to a cathode in the display region. The crack dam region is connected to the power line region and may include at least a plurality of cracks formed on a composite insulating layer. The cutting region is connected to the crack dam region and may include at least a cutting groove formed on the composite insulating layer, configured such that after all film layers of the display substrate are prepared, a cutting device cuts along the cutting grooves respectively.

[0107] In an exemplary embodiment, the fan-out area in the binding area 200 and the power line area in the border area 300 may be provided with a first isolation dam and a second isolation dam. The first isolation dam and the second isolation dam may extend along a direction parallel to the edge of the display area to form a ring structure surrounding the display area. The edge of the display area is the edge of the binding area or the border area of ​​the display area.

[0108] Figure 3 This is a schematic diagram of a planar structure of a display area in a display substrate. For example... Figure 3 As shown, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 and a fourth sub-pixel P4 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting device. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting device in each sub-pixel is connected to the pixel driving circuit of its respective sub-pixel, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of its respective sub-pixel.

[0109] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 can be green sub-pixels (G) emitting green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the four sub-pixels can be arranged in a diamond shape to form an RGBG pixel arrangement. In other exemplary embodiments, the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square, etc., and this disclosure does not limit the arrangement.

[0110] In an exemplary embodiment, a pixel unit may include three sub-pixels, which may be arranged in a horizontal, vertical, or triangular manner, etc., and this disclosure does not limit the arrangement.

[0111] Figure 4 This is a schematic cross-sectional view of a display area in a display substrate, illustrating the structure of four sub-pixels within the display area. Figure 4As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0112] In an exemplary embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel can include a pixel driving circuit composed of multiple transistors and storage capacitors. The light-emitting structure layer 103 of each sub-pixel can include a light-emitting device composed of multiple film layers. The multiple film layers can include at least an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of the corresponding color under the driving of the anode and the cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0113] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML) and one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be common layers connected together, and the emissive layers of adjacent sub-pixels may have a small amount of overlap or may be isolated from each other.

[0114] Figure 5 This is a schematic diagram of an equivalent circuit for a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Figure 5As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C. The pixel driving circuit is connected to 10 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, light emission signal line E, first initial signal line INIT1, second initial signal line INIT2, first power supply line VDD and second power supply line VSS).

[0115] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the second terminal of the fifth transistor T5, respectively. The second node N2 is connected to the second terminal of the first transistor T1, the control terminal of the third transistor T3, and the second terminal of the storage capacitor C, respectively. The third node N3 is connected to the second terminal of the second transistor T2, the second terminal of the third transistor T3, and the first terminal of the sixth transistor T6, respectively.

[0116] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0117] In an exemplary embodiment, the control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected to the second node N2. When a conducting scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the first initialization voltage to the second terminal of the storage capacitor C, thereby initializing the storage capacitor C.

[0118] In an exemplary embodiment, the control electrode of the second transistor T2 is connected to the fourth scan signal line S4, the first electrode of the second transistor T2 is connected to the second electrode of the first transistor T1, and the second electrode of the second transistor T2 is connected to the third node N3. When a conducting scan signal is applied to the fourth scan signal line S4, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode of the third transistor T3.

[0119] In an exemplary embodiment, the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as the driving transistor. The third transistor T3 determines the magnitude of the driving current flowing between the first power line VDD and the light-emitting device based on the potential difference between its control electrode and its first electrode.

[0120] In an exemplary embodiment, the control electrode of the fourth transistor T4 is connected to the third scan signal line S3, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. When a conducting scan signal is applied to the third scan signal line S3, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the first node N1.

[0121] In an exemplary embodiment, the control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. When a conducting light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power supply line VDD and the light-emitting device, causing the light-emitting device to emit light.

[0122] In an exemplary embodiment, the control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When a conducting scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits a second initial voltage to the first electrode of the light-emitting device to initialize or release the accumulated charge in the first electrode of the light-emitting device.

[0123] In an exemplary embodiment, the light-emitting device may be an OLED, which includes a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it may be a QLED, which includes a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0124] In an exemplary embodiment, the second electrode of the light-emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal.

[0125] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit simplifies the process flow, reduces the manufacturing difficulty of the display panel, and improves product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0126] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be low-temperature polycrystalline silicon (LTPS) transistors, or oxide transistors, or a combination of LTPS and metal-oxide transistors. The active layer of the LTPS transistor is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the metal-oxide transistor is made of metal-oxide semiconductor (Oxide). LTPS transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating LTPS transistors and metal-oxide transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate allows for the utilization of the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0127] Figure 6 This is a timing diagram of a pixel driving circuit. The following is a breakdown of the circuit's operation. Figure 5 The operation of the example pixel driving circuit illustrates an exemplary embodiment of this disclosure. Figure 5 The pixel driving circuit includes seven transistors (transistor T1 to transistor T7) and one storage capacitor C. Transistor T1 and transistor T2 are N-type oxide transistors, and transistors T3 to T7 are P-type low-temperature polysilicon transistors. In an exemplary embodiment, the operation of the pixel driving circuit may include:

[0128] In the first stage A1, also known as the reset stage, the signal on the second scan signal line S2 is a high-level signal, while the signals on the first scan signal line S1, the third scan signal line S3, the fourth scan signal line S4, and the light-emitting signal line E are low-level signals. The high-level signal on the second scan signal line S2 turns on the first transistor T1, and the signal on the first initial signal line INIT1 is provided to the second node N2 through the first transistor T1 to initialize (reset) the storage capacitor C, clearing the original charge from the storage capacitor. The low-level signals on the first scan signal line S1, the third scan signal line S3, the fourth scan signal line S4, and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this stage, the OLED does not emit light.

[0129] The second stage, A2, is called the data writing stage or threshold compensation stage. The signals of the first scan signal line S1, the third scan signal line S3, and the fourth scan signal line S4 are on, while the signals of the second scan signal line S2 and the light emission signal line E are off. The data signal line D outputs a data voltage. During this stage, because the second terminal of the storage capacitor C is at a low level, the third transistor T3 is turned on. The on signals of the first scan signal line S1, the third scan signal line S3, and the fourth scan signal line S4 turn on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The on-state of the second transistor T2 and the fourth transistor T4 allows the data voltage output from the data signal line D to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second terminal of the storage capacitor C (second node N2) is Vd - |Vth|, where Vd is the data voltage output from the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, providing the signal of the second initial signal line INIT2 to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED, clearing its internal pre-stored voltage, completing the initialization, and ensuring that the OLED does not emit light. The disconnect signal of the second scan signal line S2 turns off the first transistor T1, and the disconnect signal of the light emission signal line E turns off the fifth transistor T5 and the sixth transistor T6.

[0130] The third stage, A3, is called the light-emitting stage. The signal on the light-emitting signal line E is the on signal, while the signals on the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, and the fourth scan signal line S4 are the off signals. The on signal on the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0131] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage at the second node N2 is Vdata - |Vth|, the driving current of the third transistor T3 is:

[0132] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0133] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0134] With the development of OLED display technology, consumers have increasingly higher requirements for the display effect of display products. Ultra-narrow bezels have become a new trend in the development of display products. Therefore, the narrowing of bezels or even bezel-less designs are receiving more and more attention in the design of OLED display products. At present, it is more difficult to narrow the bottom bezel (the bezel on the side of the bonding area) of the display device. In order to reduce the width of the bottom bezel, some display substrates mainly adopt the solution of reducing the length of the fan-out area or the bending area. However, under the current process capabilities, the bottom bezel is still much larger than the left and right bezels.

[0135] An exemplary embodiment of this disclosure provides a display substrate, such as Figures 7a to 8c As shown, it may include: a display area and a binding area connected to the display area. The display area may include multiple data signal lines 71 and K rows and L columns of sub-pixels P, where K and L are both positive integers greater than 1. There are multiple first spaces R1 between the K sub-pixel rows and multiple second spaces R2 between the L sub-pixel columns. The first spaces are located between two adjacent sub-pixel rows, and the second spaces R2 are located between two adjacent sub-pixel columns. At least one first space R1 is provided with a first data connection line 68, and at least one second space R2 is provided with at least one second data connection line 74. On a plane parallel to the display substrate, the first data connection line 68 extends along a first direction X, and the second data connection line 74 extends along a second direction Y. The first direction X and the second direction Y intersect.

[0136] One end of the first data connection line 68 is electrically connected to one of the data signal lines 71, and the other end is electrically connected to one of the second data connection lines; one end of the second data connection line 74 is electrically connected to the first data connection line 68, and the other end is electrically connected to the bonding area.

[0137] The display substrate provided in this embodiment includes a display area comprising multiple data signal lines and K rows and L columns of sub-pixels, where K and L are both positive integers greater than 1. The K rows of sub-pixels are separated by multiple first spaces R1, and the L columns of sub-pixels are separated by multiple second spaces. The first spaces are located between adjacent sub-pixel rows, and the second spaces are located between adjacent sub-pixel columns. At least one first space is provided with a first data connection line, and at least one second space is provided with at least one second data connection line. One end of the first data connection line is electrically connected to one of the data signal lines, and the other end is electrically connected to one of the second data connection lines. One end of the second data connection line is electrically connected to the first data connection line, and the other end is electrically connected to a bonding area. Introducing the first and second data connection lines into the display area significantly reduces the bezel of the display substrate, which is beneficial for achieving narrow bezels in display products.

[0138] In this embodiment, a fanout in AA (FIAA) structure is adopted, where data fanout lines (i.e., the first data connection line 68 and the second data connection line 74) are located in the display area. One end of the multiple data fanout lines is located in the display area of ​​the display substrate and is connected to multiple data signal lines in the display area. The other end of the multiple data fanout lines extends to the bonding area and is connected to the integrated circuit. Since the bonding area does not need to be provided with fan-shaped diagonal lines, the width of the fanout area is reduced, effectively reducing the width of the bottom bezel of the display substrate.

[0139] In an exemplary embodiment, one end of the first data connection line 68 can be electrically connected to one of the data signal lines 71 through a via, and the other end can be electrically connected to one of the second data connection lines through a via; or, one end of the first data connection line 68 and one of the data signal lines 71 can be an integrally formed structure disposed on the same layer, and the other end and one of the second data connection lines can be an integrally formed structure disposed on the same layer.

[0140] In an exemplary embodiment, the second data connection line 74 and the first data connection line 68 can be connected by a via, or the second data connection line 74 and the first data connection line 68 can be a molded structure arranged in the same layer.

[0141] In an exemplary implementation, such as Figures 8a to 8c As shown, the first space R1 is also provided with a fourth data connection line 611, and the second space R2 is also provided with a third data connection line 610.

[0142] The same second space R2 is provided with at least one third data connection line 610 and at least one second data connection line 74;

[0143] The fourth data connection line 611 extends along the first direction X, with one end electrically connected to the data signal line and the other end connected to the third data connection line 610; the third data connection line 610 extends along the second direction Y, with one end connected to the fourth data connection line 611 and the other end electrically connected to the bonding area.

[0144] In an exemplary implementation, such as Figures 8a to 8c , Figures 25d to 27c As shown, the first data connection line 68 and the second data connection line 74 can be connected through vias, and the third data connection line 610 and the fourth data connection line 611 can be an integrally formed structure.

[0145] In an exemplary implementation, such as Figure 8c , Figure 27c As shown, the first data connection line 68 and the fourth data connection line 611 can be located in different first spaces R1, or the first data connection line 68 and the fourth data connection line 611 can be located in the same first space R1, and the orthographic projections of the first data connection line 68 and the fourth data connection line 611 on the substrate do not overlap, and the orthographic projections of the first data connection line 68 and the third data connection line 610 on the substrate do not overlap.

[0146] In an exemplary implementation, such as Figures 8a to 8c As shown, in the same second space R2, there is one third data connection line 610 and two second data connection lines 74. In the plane where the display substrate is located, in the first direction X, the two second data connection lines 74 are located on both sides of the third data connection line 610. The two second data connection lines 74 in the same second space R2 are connected to different first data connection lines 68; or in the same second space R2, there are two third data connection lines 610 and one second data connection line 74. In the plane where the display substrate is located, in the first direction X, the two third data connection lines 610 are located on both sides of the second data connection line 74. The two third data connection lines 610 in the same second space R2 are connected to different fourth data connection lines 611.

[0147] In an exemplary implementation, such as Figure 7a and Figure 7b As shown, in the same second space R2, there are three second data connection lines 74, and the three second data connection lines 74 are respectively connected to three different first data connection lines 68.

[0148] In an exemplary embodiment, at least one sub-pixel P includes a pixel driving circuit. In a plane perpendicular to the display substrate, the display substrate includes a substrate and a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially stacked on the substrate.

[0149] The first semiconductor layer includes: an active layer of multiple low-temperature polysilicon transistors located in the pixel driving circuit; the first conductive layer includes: a control electrode of multiple polysilicon transistors located in the pixel driving circuit and a first electrode of a storage capacitor; the second conductive layer includes: a second electrode of a storage capacitor located in the pixel driving circuit; the second semiconductor layer includes: an active layer of multiple oxide transistors located in the pixel driving circuit; the third conductive layer includes: a control electrode of multiple oxide transistors located in the pixel driving circuit; the fourth conductive layer includes: a first data connection line 68 and the first and second electrodes of multiple low-temperature polysilicon transistors and multiple oxide transistors located in the pixel driving circuit; the fifth conductive layer includes: a data signal line, a first power line, and a second data connection line 74.

[0150] The display substrate provided in this embodiment uses center compression for the pixels, meaning that the pitch of adjacent sub-pixels can remain unchanged. This allows the fanout traces to enter the display area and be placed in the gaps created by the pixel driving circuit (i.e., the first and second spaces mentioned above). The fanout traces (including data fanout lines) use SD metal layers (i.e., the fourth and / or fifth conductive layers mentioned above) in both the horizontal direction (including the first data connection line mentioned above and the fourth data connection line mentioned below) and the vertical direction (including the second data connection line mentioned above and the third data connection line mentioned below). Without increasing the number of BPMasks, FIAA (Fanout In AA, fanout traces are fabricated in the AA area) is used to achieve a narrow bezel, and the LTPO PPI can be increased to 430.

[0151] In an exemplary embodiment, the pitch can be the distance between the midpoints of two adjacent sub-pixels P. For example... Figure 8a and Figure 8b As shown, L1 can be the pitch of two adjacent columns of sub-pixels along the first direction X, and L2 can be the pitch of two adjacent rows of sub-pixels along the second direction Y.

[0152] In an exemplary embodiment, pixel center compression can be understood as compressing the distance or component size between the components in the pixel driving circuit to form the first space R1 and the second space R2 to place the data fan-out line, reduce the bottom bezel of the display substrate, and at the same time keep the pitch of adjacent sub-pixels unchanged so that the resolution of the display substrate does not decrease.

[0153] In an exemplary embodiment, the display substrate further includes a light-emitting element, and among the plurality of low-temperature polysilicon transistors is a seventh transistor for resetting the anode voltage of the light-emitting element, such as... Figure 23b As shown, the third conductive layer also includes a transition connection electrode 53, such as... Figure 25b As shown, the fourth conductive layer also includes a plurality of second initial signal lines 67. In the plane of the fourth conductive layer, the main body of the second initial signal line 67 is a zigzag line extending along the first direction X. The plurality of second initial signal lines 67 are arranged in an array along the first direction X and the second direction Y. The second initial signal lines 67 are connected to the active layer of the seventh transistor in the first semiconductor layer through vias and are multiplexed as the first electrode of the seventh transistor. In the same sub-pixel row, two adjacent second initial signal lines 67 are connected to the same adapter electrode 53 through adapter vias.

[0154] In an exemplary implementation, such as Figures 8b to 8c , Figure 23b As shown, the adapter electrode 53 extends along the first direction X, and the orthographic projection of the adapter electrode 53 on the substrate overlaps with the orthographic projection of one of the second spaces R2 on the substrate.

[0155] In an exemplary implementation, such as Figures 8a to 8c As shown, the fourth conductive layer further includes a fourth data connection line 611 and a third data connection line 610. The orthographic projection of the fourth data connection line 611 on the substrate at least partially overlaps with the orthographic projection of one of the first spaces R1 on the substrate, while the orthographic projection of the fourth data connection line 611 on the substrate does not overlap with the orthographic projection of the first data connection line 68 on the substrate. The orthographic projection of the third data connection line 610 on the substrate at least partially overlaps with the orthographic projection of one of the second spaces R2 on the substrate. In an exemplary embodiment, the third data connection line 610 extends along the second direction Y, with one end connected to the fourth data connection line 611 and the other end electrically connected to the bonding area. The fourth data connection line 611 extends along the first direction X, with one end connected to the third data connection line 610 and the other end electrically connected to one of the data signal lines in the fifth conductive layer through a via. In an exemplary embodiment, in the same second space R2, the orthographic projection of the second data connection line 74 on the substrate does not overlap with the orthographic projection of the third data connection line 610 on the substrate.

[0156] In an exemplary implementation, such as Figure 8cAs shown, within the same second space R2, there is one third data connection line 610 and two second data connection lines 74. The orthographic projection of the third data connection line 610 onto the substrate lies between the orthographic projections of the two second data connection lines 74 onto the substrate. Alternatively, within the same second space R2, there are two third data connection lines 610 and one second data connection line 74. The orthographic projection of the second data connection line 74 onto the substrate lies between the orthographic projections of the two third data connection lines 610 onto the substrate.

[0157] In an exemplary implementation, such as Figure 8b and Figure 8c As shown, the orthographic projections of the second data connection line 74 and the third data connection line 610 on the substrate overlap with the orthographic projection of the adapter connection electrode 53 on the substrate, but the orthographic projections of the second data connection line 74 and the third data connection line 610 on the substrate do not overlap with the orthographic projection of the second initial signal line 67 on the substrate.

[0158] In an exemplary implementation, such as Figure 8b and Figure 8c As shown, the pixel driving circuit also includes: the first transistor T1 to the sixth transistor T6, and a storage capacitor;

[0159] On a plane parallel to the display substrate, in the same pixel driving circuit, in the first direction X, the sixth transistor T6 is located on one side of the storage capacitor, and the fifth transistor T5 and the fourth transistor T4 are located on the other side of the storage capacitor; in the second direction Y, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are located on the same side of the storage capacitor, and the fourth transistor T4, the first transistor T1, and the second transistor T2 are located on the other side of the storage capacitor. Furthermore, the seventh transistor T7 is located on the side of the sixth transistor T6 away from the storage capacitor, and the first transistor T1 is located on the side of the second transistor T2 away from the storage capacitor. The orthographic projection of the storage capacitor on the substrate overlaps with the orthographic projection of the third transistor T3 on the substrate. The seventh transistor T7 in the i-th row of sub-pixels is located in the (i-1)-th row of sub-pixels, where i = 2, 3, ..., K.

[0160] In the second direction Y, in the two sub-pixel rows adjacent to the first data connection line 68, the first transistor T1 of the previous sub-pixel row and the fifth transistor T5 and sixth transistor T6 of the next sub-pixel row are located on both sides of the first data connection line 68, and the seventh transistor T7 of the next sub-pixel row is located on the same side of the first data connection line 68 as the first transistor T1 of the previous sub-pixel row; in the two sub-pixel rows adjacent to the fourth data connection line 611, the first transistor of the previous sub-pixel row and the fifth transistor T5 and sixth transistor T6 of the next sub-pixel row are located on both sides of the fourth data connection line 611, and the seventh transistor T7 of the next sub-pixel row is located on the same side of the first data connection line 68 as the first transistor T1 of the previous sub-pixel row; The seventh transistor of the pixel row is located on the same side of the fourth data connection line 611 as the first transistor of the previous sub-pixel row. In the first direction X, the total number of the second and third data connection lines 610 is three. The three data connection lines are arranged along the first direction line X. The two data connection lines on both sides are symmetrical with respect to the data connection line in the middle position. In the same sub-pixel row, the first transistor T1 to the seventh transistor T7 and the storage capacitor in the two sub-pixel columns adjacent to the second data connection line 74 and the third data connection line 610 in the same second space are symmetrically arranged with respect to the data connection line in the middle position.

[0161] In an exemplary implementation, such as Figure 8b , Figure 8c , 27a to Figure 27c As shown, in the fourth conductive layer, the fourth data connection line 611 and the first electrode of the fourth transistor T4 in one of the pixel driving circuits are integrally formed. The first electrode 64 of the fourth transistor (hereinafter referred to as the fourth connection electrode 64), which is integrally formed with the fourth data connection line 611, is a strip-shaped structure or a zigzag structure and extends along the second direction Y. One end is connected to the fourth data connection line 611, and the other end is electrically connected to the data signal line in the fifth conductive layer through a via. One end of the fourth data connection line 611 is connected to the first electrode 64 of the fourth transistor, and the other end is connected to the third data connection line 610.

[0162] The first data connection line 68 and the first electrode 64 of one of the fourth transistors are integrally formed. The first electrode 64 of the fourth transistor, which is integrally formed with the first data connection line 68, is a strip-shaped structure or a zigzag structure and extends along the second direction Y. One end is connected to the first data connection line 68, and the other end is electrically connected to the data signal line in the fifth conductive layer through a via. One end of the first data connection line 68 is connected to the first electrode 64 of the fourth transistor, and the other end is electrically connected to the second data connection line 74 in the fifth conductive layer through a via.

[0163] In an exemplary implementation, such as Figure 7bAs shown, in the same second space R2, there are three second data connection lines 74, and the orthographic projections of the three second data connection lines 74 on the substrate do not overlap. The three second data connection lines 74 are electrically connected to the first data connection lines 68 in three different first spaces R1 in the fourth conductive layer through three different vias.

[0164] In an exemplary implementation, such as Figure 7b and Figure 16b As shown, the display substrate also includes a light-emitting element, and among the multiple low-temperature polysilicon transistors is a seventh transistor T7 that resets the anode voltage of the light-emitting element. The fourth conductive layer also includes an initial signal connection line 69 and multiple second initial signal lines 67. The second initial signal lines 67 are connected to the active layer of the seventh transistor T7 in the first semiconductor layer through vias and are multiplexed as the first electrode of the seventh transistor T7. In the plane of the fourth conductive layer, the main body of the second initial signal line 67 is a zigzag line extending along the first direction X, and the multiple second initial signal lines 67 are arranged along the second direction Y. The initial signal connection line 69 extends along the second direction Y and is integrally formed with the multiple second initial signal lines 67.

[0165] In an exemplary implementation, such as Figure 7b , Figures 18a-18b As shown, among the three second data connection lines 74, the orthographic projection of the second data connection line 74 located in the middle position on the substrate overlaps with the orthographic projection of the initial signal connection line 69 on the substrate, and the orthographic projections of the second data connection lines 74 located on both sides on the substrate overlap with the orthographic projections of the second initial signal line 67 on the substrate.

[0166] In an exemplary embodiment, the pixel driving circuit further includes: a first transistor T1 to a sixth transistor T6, and a storage capacitor;

[0167] On a plane parallel to the display substrate, in the same pixel driving circuit, in the first direction X, the sixth transistor T6 is located on one side of the storage capacitor, and the fifth transistor T5 and the fourth transistor T4 are located on the other side of the storage capacitor; in the second direction Y, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are located on the same side of the storage capacitor, and the fourth transistor T4, the first transistor T1, and the second transistor T2 are located on the other side of the storage capacitor. Furthermore, the seventh transistor T7 is located on the side of the sixth transistor T6 away from the storage capacitor, and the first transistor T1 is located on the side of the second transistor T2 away from the storage capacitor. The orthographic projection of the storage capacitor on the substrate overlaps with the orthographic projection of the third transistor T3 on the substrate. The seventh transistor T7 in the i-th row of sub-pixels is located in the (i-1)-th row of sub-pixels, where i = 2, 3, ..., K.

[0168] In the second direction Y, in the two sub-pixel rows adjacent to the first data connection line 68, the first transistor T1 of the previous sub-pixel row and the fifth transistor T5 and the sixth transistor T6 of the next sub-pixel row are located on both sides of the first data connection line 68, and the seventh transistor T7 of the next sub-pixel row is located on the same side of the first data connection line 68 as the first transistor T1 of the previous sub-pixel row; in the first direction X, three second data connection lines 74 are arranged sequentially, and the second data connection lines 74 on both sides are symmetrical with respect to the second data connection line 74 in the middle position. In the same sub-pixel row, the first transistors T1 to the seventh transistor T7 and the storage capacitor in the two sub-pixel columns adjacent to the three second data connection lines 74 are symmetrically arranged with respect to the second data connection line 74 in the middle position.

[0169] In an exemplary implementation, such as Figure 7b , Figures 16a to 16d As shown, in the fourth conductive layer, the first data connection line 68 and the first electrode 64 of one of the fourth transistors (hereinafter referred to as the fourth connection electrode 64) are integrally formed. The first electrode 64 of the fourth transistor, which is integrally formed with the first data connection line 68, is a strip-shaped structure or a zigzag structure and extends along the second direction Y. One end is connected to the first data connection line 68, and the other end is electrically connected to the data signal line in the fifth conductive layer through a via. One end of the first data connection line 68 is connected to the first electrode 64 of the fourth transistor, and the other end is electrically connected to the second data connection line 74 in the fifth conductive layer through a via.

[0170] In an exemplary implementation, such as Figures 7a to 8c As shown, the orthographic projection of one end of the first data connection line 68 on the substrate overlaps with the orthographic projection of one of the second data connection lines 74 on the substrate, and is electrically connected to the second data connection line 74 in the overlapping projection area through a via. The orthographic projection of the other end of the first data connection line 68 on the substrate overlaps with the orthographic projection of one of the data signal lines 71 on the substrate, and is electrically connected to the data signal line 71 through a via.

[0171] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate (or substrate plate) using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0172] In an exemplary embodiment, taking eight sub-pixels (two sub-pixel rows and four sub-pixel columns) in the display area (AA) as an example, the fabrication process of one display substrate may include the following operations.

[0173] (101) A substrate is prepared on a glass substrate. In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may include, but is not limited to, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, an adhesive layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer soft films, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also called barrier layers, and the material of the adhesive layer may be amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: firstly, coating a layer of polyimide on a glass substrate, curing it into a film to form a first flexible material (PI1) layer; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible material layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating another layer of polyimide on the amorphous silicon layer, curing it into a film to form a second flexible material (PI2) layer; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thus completing the substrate preparation.

[0174] (102) Forming a masking layer pattern. In an exemplary embodiment, forming a masking layer pattern may include: depositing a conductive thin film of the masking layer on a substrate, patterning the conductive thin film of the masking layer using a patterning process, and forming a masking layer pattern on the substrate, such as... Figure 9 As shown, Figure 9 This is a planar structural diagram of the occlusion layer pattern in eight sub-pixels.

[0175] In an exemplary embodiment, the occlusion layer pattern of each sub-pixel may include a first occlusion structure 11, a second occlusion structure 12, a third occlusion structure 13, and an occlusion block 14. The occlusion block 14 may be rectangular in shape, with chamfered corners. The first occlusion structure 11 may be a strip extending along a first direction X, disposed on one side of the occlusion block 14 in the first direction X, and connected to the occlusion block 14. The second occlusion structure 12 may be a strip extending along a second direction Y, disposed on the opposite side of the occlusion block 14 in the second direction Y, and connected to the occlusion block 14. The third occlusion structure 13 may be a broken line extending along the second direction Y, disposed on one side of the occlusion block 14 in the second direction Y, and connected to the occlusion block 14.

[0176] In an exemplary embodiment, the first occlusion structure 11 of each sub-pixel is connected to the occlusion block 14 of the adjacent sub-pixel in the first direction X, so that the occlusion layers in a row of sub-pixels are connected into one unit to form an interconnected integral structure.

[0177] In an exemplary embodiment, the second occlusion structure 12 of each sub-pixel is connected to the third occlusion structure 13 of the adjacent sub-pixel in the second direction Y, so that the occlusion layers in a sub-pixel column are connected into one, forming an interconnected integral structure.

[0178] In an exemplary embodiment, the shielding layers in the sub-pixel rows and sub-pixel columns are connected as one unit, which can ensure that the shielding layers in the display substrate have the same potential, which is beneficial to improve the uniformity of the panel, avoid display defects in the display substrate, and ensure the display effect of the display substrate.

[0179] In an exemplary embodiment, the occlusion layers of the Nth column and the N+1th column can be mirror-symmetrical with respect to the first center line, the occlusion layers of the N+1th column and the N+2th column can be mirror-symmetrical with respect to the second center line, and the occlusion layers of the N+2th column and the N+3th column can be mirror-symmetrical with respect to the third center line. The first center line, the second center line, and the third center line can be straight lines extending along the second direction Y between adjacent sub-pixel columns.

[0180] In an exemplary embodiment, the shape of the occlusion layer can be the same in multiple sub-pixel rows.

[0181] (103) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate on which the aforementioned pattern is formed; patterning the first semiconductor film using a patterning process to form a first insulating layer covering the masking layer pattern; and a first semiconductor layer pattern disposed on the first insulating layer, such as... Figure 10a and Figure 10b As shown, Figure 10a This is a planar structure diagram of eight sub-pixels. Figure 10b for Figure 10a A planar schematic diagram of the first semiconductor layer.

[0182] In an exemplary embodiment, the first semiconductor layer pattern of each sub-pixel may include the active layer 23 of the third transistor T3 to the active layer 27 of the seventh transistor T7, and the active layer 23 of the third transistor T3 to the active layer 27 of the seventh transistor T7 are an integral structure interconnected.

[0183] In an exemplary embodiment, in the first direction X, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on the same side of the active layer 23 of the third transistor T3, and the active layer 26 of the sixth transistor T6 is located on the other side of the active layer 23 of the third transistor T3; in the second direction Y, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on both sides of the active layer 23 of the third transistor T3, and the active layer 25 of the fifth transistor T5, the active layer 26 of the sixth transistor T6 and the active layer 27 of the seventh transistor T7 are located on the same side of the active layer 23 of the third transistor T3, and the active layer 27 of the seventh transistor T7 is located on the side of the active layer 26 of the sixth transistor T6 away from the active layer 23 of the third transistor T3.

[0184] In an exemplary embodiment, taking the sub-pixel in the Mth row and Nth column as an example: In the first direction X, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on the side of the active layer 23 of the third transistor T3 away from the (N+1)th column sub-pixel, and the active layer 26 of the sixth transistor T6 is located on the side of the active layer 23 of the third transistor T3 away from the (N-1)th column sub-pixel; In the second direction Y, the active layer 24 of the fourth transistor T4 is located on the side of the active layer 23 of the third transistor T3 away from the (M-1)th row sub-pixel, the active layers 25 of the fifth transistor T5, the active layers 26 of the sixth transistor T6, and the active layer 27 of the seventh transistor T7 are located on the side of the active layer 23 of the third transistor T3 away from the (M+1)th row sub-pixel, and the active layer 27 of the seventh transistor T7 is located on the side of the active layer 26 of the sixth transistor T6 away from the active layer 23 of the third transistor T3.

[0185] In an exemplary embodiment, the active layer 23 of the third transistor T3 can be shaped like an "Ω", the active layer 24 of the fourth transistor T4 and the active layer 27 of the seventh transistor T7 can be shaped like an "I", and the active layer 25 of the fifth transistor T5 and the active layer 26 of the sixth transistor T6 can be shaped like an "L".

[0186] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region 23-1 of the active layer 23 of the third transistor T3 may serve as the second region 24-2 of the active layer 24 of the fourth transistor T4 and the second region 25-2 of the active layer 25 of the fifth transistor T5. The second region 23-2 of the active layer 23 of the third transistor T3 may serve as the first region 26-1 of the active layer 26 of the sixth transistor T6. The second region 26-2 of the active layer 26 of the sixth transistor T6 may serve as the second region 27-2 of the active layer 27 of the seventh transistor T7. The first region 24-1 of the active layer 24 of the fourth transistor T4, the first region 25-1 of the active layer 25 of the fifth transistor T5, and the first region 27-1 of the active layer 27 of the seventh transistor T7 may be configured individually.

[0187] In an exemplary embodiment, the orthographic projection of the active layer 23 of the third transistor T3 onto the substrate at least partially overlaps with the orthographic projection of the blocking block 14 onto the substrate. In an exemplary embodiment, the orthographic projection of the channel region of the active layer 23 of the third transistor T3 onto the substrate lies within the range of the orthographic projection of the blocking block 14 onto the substrate.

[0188] In an exemplary embodiment, the first region 25-1 of the active layer 25 of the fifth transistor T5 in the Nth column and the first region 25-1 of the active layer 25 of the fifth transistor T5 in the (N-1)th column are interconnected, and the first region 25-1 of the active layer 25 of the fifth transistor T5 in the N+1th column and the first region 25-1 of the active layer 25 of the fifth transistor T5 in the N+2th column are interconnected. In this exemplary embodiment, since the first region of the active layer of the fifth transistor T5 in each sub-pixel is connected to the subsequently formed first power line, by forming an interconnected integrated structure of the first regions of the active layers of the fifth transistor T5 in adjacent sub-pixels, it can be ensured that the first electrodes of the fifth transistor T5 in adjacent sub-pixels have the same potential. This is beneficial for improving the uniformity of the panel display, avoiding display defects in the display substrate, and ensuring the display effect of the display substrate.

[0189] In an exemplary embodiment, the first semiconductor layer in column N and the first semiconductor layer in column N+1 may be mirror-symmetric with respect to the first center line, the first semiconductor layer in column N+1 and the first semiconductor layer in column N+2 may be mirror-symmetric with respect to the second center line, and the first semiconductor layer in column N+2 and the first semiconductor layer in column N+3 may be mirror-symmetric with respect to the third center line.

[0190] In an exemplary embodiment, the first region 27-1 of the active layer 27 of the seventh transistor T7 in the i-th row of sub-pixels can be set in the (i-1)-th row of sub-pixels, i = 2, 3, ..., M+1.

[0191] In an exemplary embodiment, the first semiconductor layer may be polycrystalline silicon (p-Si), meaning that the third transistor T3 to the seventh transistor T7 may be LTPS thin-film transistors. In another exemplary embodiment, patterning the first semiconductor thin film using a patterning process may include: first forming an amorphous silicon (a-Si) thin film on a first insulating film; then performing a hydrogen removal treatment on the amorphous silicon thin film; and finally performing a crystallization treatment on the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form the pattern of the first semiconductor layer.

[0192] (104) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a second insulating layer covering the first semiconductor layer pattern; and a first conductive layer pattern disposed on the second insulating layer, such as... Figure 11a and Figure 11b As shown, Figure 11b for Figure 11a A planar schematic diagram of the first conductive layer. In an exemplary embodiment, the first conductive layer may be referred to as the first gate metal (GATE1) layer.

[0193] In an exemplary embodiment, the first conductive layer pattern may include at least: a first scan signal line 31, a light emission control line 32, and a first electrode 33 of a storage capacitor. The main body of the first scan signal line 31 and the light emission control line 32 may extend along a first direction X. In the same sub-pixel, the light emission control line 32, the first electrode 33 of the storage capacitor, and the first scan signal line 31 are arranged along a second direction Y.

[0194] In an exemplary embodiment, in the second direction Y, the first scan signal line 31 and the light emission control line 32 are located on both sides of the first electrode 33 of the storage capacitor. For example, in the second direction, the light emission control line 32, the first electrode 33, and the first scan signal line 31 are arranged sequentially.

[0195] Taking the Mth row and Nth column sub-pixel as an example: In the second direction Y, the light emission control line 32 can be located on the side of the first plate 33 of the storage capacitor in this sub-pixel near the M-1th row sub-pixel; the first scan signal line 31 can be located on the side of the first plate 33 of the storage capacitor in this sub-pixel near the M+1th row sub-pixel.

[0196] In an exemplary embodiment, the first electrode 33 can be located between the light-emitting control line 32 and the first scan signal line 31. The first electrode 33 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the first electrode 33 on the substrate overlaps with the orthographic projection of the active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode 33 can simultaneously serve as one electrode of the storage capacitor and the control electrode of the third transistor T3.

[0197] In an exemplary embodiment, the region where the light-emitting control line 32 overlaps with the active layer of the fifth transistor T5 serves as the control electrode of the fifth transistor T5, the region where the light-emitting control line 32 overlaps with the active layer of the sixth transistor T6 serves as the control electrode of the sixth transistor T6, the region where the first scan signal line 31 overlaps with the active layer of the fourth transistor T4 serves as the control electrode of the fourth transistor T4, and the region where the first scan signal line 31 overlaps with the active layer of the seventh transistor T7 serves as the control electrode of the seventh transistor T7.

[0198] In an exemplary embodiment, the first scanning signal line 31 and the light emission control line 32 can be designed with equal width or with non-equal width, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines.

[0199] In an exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the region shielded by the first conductive layer forms the channel region of the third transistor T3 to the seventh transistor T7. The semiconductor layer in the region not shielded by the first conductive layer is conducted, that is, the first region and the second region of the active layer 23 of the third transistor T3 to the active layer 27 of the seventh transistor T7 are both conducted.

[0200] (105) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the third insulating layer, such as... Figures 12a to 12b As shown, Figure 12a This is a planar structure diagram of eight sub-pixels. Figure 12b for Figure 12a A schematic planar view of the second conductive layer. In an exemplary embodiment, the second conductive layer may be referred to as the second gate metal (GATE2) layer.

[0201] In an exemplary embodiment, the second conductive layer pattern includes at least: a first blocking line 41, a second blocking line 42, a second electrode 43 of a storage capacitor, and a first initial signal line 45. The main body portions of the first blocking line 41, the second blocking line 42, and the first initial signal line 45 can extend along a first direction X. The second electrode 43 of the storage capacitor serves as the other electrode of the storage capacitor. In the second direction Y, the second blocking line 42 is located between the first blocking line 41 and the second electrode 43, and the first blocking line 41 is located between the second blocking line 42 and the first initial signal line 45. For example, in the same sub-pixel, the second electrode 43, the second blocking line 42, the first blocking line 41, and the first initial signal line 45 of the storage capacitor are arranged sequentially along the second direction Y.

[0202] In an exemplary embodiment, the first shielding line 41 is configured as a shielding layer for the first transistor T1, shielding the channel of the first transistor T1, and the second shielding line 42 is configured as a shielding layer for the second transistor T2, shielding the channel of the second transistor T2, thereby ensuring the electrical performance of the oxide first transistor T1 and the oxide second transistor T2. In an exemplary embodiment, the signal of the first shielding line 41 and the signal of the subsequent second scan signal line 51 can be the same, that is, the first shielding line 41 and the subsequent second scan signal line 51 are connected in parallel and connected to the same signal source, so that the first shielding line 41 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the first transistor T1, forming a double-gate structure first transistor T1; the signal of the second shielding line 42 and the signal of the subsequent third scan signal line 52 can be the same, that is, the second shielding line 42 and the subsequent third scan signal line 52 are connected in parallel and connected to the same signal source, so that the second shielding line 42 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the second transistor T2, forming a double-gate structure second transistor T2.

[0203] In an exemplary embodiment, the outline of the second electrode plate 43 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 43 on the substrate overlaps with the orthographic projection of the first electrode plate 33 on the substrate. The first electrode plate 33 and the second electrode plate 43 constitute the storage capacitor of the pixel driving circuit. An opening 44 is provided on the second electrode plate 43, and the opening 44 can be located in the middle of the second electrode plate 43. The opening 44 can be rectangular, so that the second electrode plate 43 forms a ring structure. The opening 44 exposes the third insulating layer covering the first electrode plate 33, and the orthographic projection of the first electrode plate 33 on the substrate includes the orthographic projection of the opening 44 on the substrate. In an exemplary embodiment, the opening 44 is configured to accommodate a subsequently formed ninth via, which is located within the opening 44 and exposes the first electrode plate 33, so that the second electrode of the subsequently formed first transistor T1 is connected to the first electrode plate 33.

[0204] (106) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a second semiconductor film on a substrate on which the aforementioned pattern is formed; patterning the second semiconductor film using a patterning process to form a fourth insulating layer covering the substrate; and a second semiconductor layer pattern disposed on the fourth insulating layer, such as... Figures 13a to 13b As shown, Figure 13a This is a planar structure diagram of eight sub-pixels. Figure 13b for Figure 13a A planar schematic diagram of the second semiconductor layer.

[0205] In an exemplary embodiment, the second semiconductor layer pattern in each sub-pixel includes at least: an active layer 21 of the first transistor T1 and an active layer 22 of the second transistor T2, and the active layer 21 of the first transistor T1 and the active layer 22 of the second transistor T2 are an integral structure interconnected with each other.

[0206] In an exemplary embodiment, the active layer 21 of the first transistor T1 and the active layer 22 of the second transistor T2 can be in the shape of an "I" shape. The second region 21-2 of the active layer 21 of the first transistor T1 can be used as the first region 22-1 of the active layer 22 of the second transistor T2. The first region 21-1 of the active layer 21 of the first transistor T1 and the second region 22-2 of the second active layer 22 can be set separately.

[0207] In an exemplary embodiment, the second semiconductor layer in column N and the second semiconductor layer in column N+1 may be mirror-symmetric with respect to the first center line, the second semiconductor layer in column N+1 and the second semiconductor layer in column N+2 may be mirror-symmetric with respect to the second center line, and the second semiconductor layer in column N+2 and the second semiconductor layer in column N+3 may be mirror-symmetric with respect to the third center line.

[0208] In an exemplary embodiment, the shape of the second semiconductor layer in multiple sub-pixel rows can be the same.

[0209] In an exemplary embodiment, in the plane where the display substrate is located, in the first direction X, the active layer 21 of the first transistor T1 and the active layer 22 of the second transistor T2 are located on the side of the active layer 23 of the third transistor T3 away from the active layer 24 of the fourth transistor T4; in the second direction Y, the active layer 21 of the first transistor T1 and the active layer 22 of the second transistor T2 are located on the side of the active layer 23 of the third transistor T3 away from the active layer 25 of the fifth transistor T5, and the active layer 21 of the first transistor T1 is located on the side of the active layer 22 of the second transistor T2 away from the active layer 23 of the third transistor T3.

[0210] In an exemplary embodiment, the second semiconductor layer may be an oxide, meaning that the first transistor T1 and the second transistor T2 are oxide thin-film transistors. In an exemplary embodiment, the oxide may be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc nitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper sulfide oxide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the second semiconductor thin film may be indium gallium zinc oxide (IGZO), which has a higher electron mobility than amorphous silicon. Since the leakage current of IGZO TFT is relatively small, both the first transistor T1 and the second transistor T2 are N-type transistors, which can avoid leakage of the second node N2 during the light-emitting stage.

[0211] (107) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: sequentially depositing a fifth insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer; and a third conductive layer pattern disposed on the fifth insulating layer, such as... Figures 14a to 14b As shown, Figure 14a This is a planar structure diagram of eight sub-pixels. Figure 14b for Figure 14a A schematic planar view of the third conductive layer. In an exemplary embodiment, the third conductive layer may be referred to as the third gate metal (GATE3) layer.

[0212] In an exemplary embodiment, the third conductive layer pattern includes at least: a second scan signal line 51 and a third scan signal line 52. The main body portions of the second scan signal line 51 and the third scan signal line 52 may extend along the first direction X, and the third scan signal line 52 and the second scan signal line 51 are arranged sequentially along the second direction Y.

[0213] In an exemplary embodiment, the region where the second scan signal line 51 overlaps with the active layer 21 of the first transistor T1 serves as the control electrode of the first transistor T1, and the region where the third scan signal line 52 overlaps with the active layer 22 of the second transistor T2 serves as the control electrode of the second transistor T2.

[0214] In an exemplary embodiment, the signals of the first blocking line 41 and the second scanning signal line 51 can be the same, that is, they are connected in parallel and connected to the same signal source, so that the first blocking line 41 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the first transistor T1, forming a dual-gate structure of the first transistor T1.

[0215] In an exemplary embodiment, the signals of the second blocking line 42 and the third scanning signal line 52 can be the same, that is, they are connected in parallel and connected to the same signal source, so that the second blocking line 42 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the second transistor T2, forming a dual-gate structure of the second transistor T2.

[0216] (108) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming a sixth insulating layer pattern may include: depositing a sixth insulating film on a substrate on which the aforementioned pattern is formed, patterning the sixth insulating film using a patterning process to form a sixth insulating layer covering a third conductive layer, wherein a plurality of vias are provided on the sixth insulating layer, such as... Figure 15 As shown, Figure 15 This is a planar structure diagram of eight sub-pixels.

[0217] In an exemplary embodiment, the plurality of vias in each sub-pixel include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, and an eleventh via V11.

[0218] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate lies within the orthographic projection of the active layer 21 of the first transistor T1 onto the substrate. The sixth and fifth insulating layers within the first via V1 are etched away, exposing the surface of the first region 21-1 of the active layer 21 of the first transistor T1. The first via V1 is configured to allow the first electrode of the subsequently formed first transistor T1 to be connected to the active layer 21 of the first transistor T1 through the via.

[0219] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate lies within the orthographic projection of the active layer 22 of the second transistor T2 onto the substrate. The sixth and fifth insulating layers within the second via V2 are etched away, exposing the surface of the second region 22-2 of the active layer 22 of the second transistor T2. The second via V2 is configured to allow the second electrode of the subsequently formed second transistor T2 to be connected to the active layer 22 of the second transistor T2 through the via.

[0220] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate lies within the orthographic projection of the active layer 22 of the second transistor T2 onto the substrate. The sixth and fifth insulating layers within the third via V3 are etched away, exposing the surface of the first region 22-1 of the active layer 22 of the second transistor T2 (which is also the second region 21-2 of the active layer 21 of the first transistor T1). The third via V3 is configured to connect the second electrode of the subsequently formed first transistor T1 to the active layer 21 of the first transistor T1 through the via, and to connect the first electrode of the subsequently formed second transistor T2 to the active layer 22 of the second transistor T2 through the via.

[0221] In an exemplary embodiment, the orthogonal projection of the fourth via V4 onto the substrate lies within the orthogonal projection of the active layer 24 of the fourth transistor T4 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the fourth via V4 are etched away, exposing the first region 24-1 of the active layer 24 of the fourth transistor T4. The fourth via V4 is configured to allow the first electrode of the subsequently formed fourth transistor T4 to be connected to the active layer 24 of the fourth transistor T4 through the via.

[0222] In an exemplary embodiment, the orthogonal projection of the fifth via V5 onto the substrate lies within the orthogonal projection of the active layer 25 of the fifth transistor T5 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the fifth via V5 are etched away, exposing the surface of the first region 25-1 of the active layer 25 of the fifth transistor T5. The fifth via V5 is configured to allow the first electrode of the subsequently formed fifth transistor T5 to be connected to the active layer 25 of the fifth transistor T5 through this via.

[0223] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate lies within the orthographic projection of the active layer 26 of the sixth transistor T6 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the sixth via V6 are etched away, exposing the surface of the first region 26-1 of the active layer 26 of the sixth transistor T6 (which is also the second region of the active layer 23 of the third transistor T3). The sixth via V6 is configured to connect the first electrode of the subsequently formed sixth transistor T6 to the active layer 26 of the sixth transistor T6 through the via, and to connect the second electrode of the subsequently formed third transistor T3 to the active layer 23 of the third transistor T3 through the via.

[0224] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate lies within the orthographic projection of the active layer 26 of the sixth transistor T6 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the seventh via V7 are etched away, exposing the surface of the second region 26-2 of the active layer 26 of the sixth transistor T6 (which is also the second region 27-2 of the active layer 27 of the seventh transistor T7). The seventh via V7 is configured to connect the second electrode of the subsequently formed sixth transistor T6 to the active layer 26 of the sixth transistor T6 through the via, and to connect the second electrode of the subsequently formed seventh transistor T7 to the active layer 27 of the seventh transistor T7 through the via.

[0225] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate lies within the orthographic projection of the active layer 27 of the seventh transistor T7 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the eighth via V8 are etched away, exposing the surface of the first region 27-1 of the active layer 27 of the seventh transistor T7. The eighth via V8 is configured to allow the first electrode of the subsequently formed seventh transistor T7 to be connected to the active layer 27 of the seventh transistor T7 through this via.

[0226] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate lies within the range of the orthographic projection of the opening 44 onto the substrate. The sixth, fifth, fourth, and third insulating layers within the ninth via V9 are etched away, exposing the surface of the first electrode plate 33. The ninth via V9 is configured to allow the second electrode of the subsequently formed first transistor T1 to be connected to the first electrode plate 33 through the via.

[0227] In an exemplary embodiment, the tenth via V10 is located within the orthographic projection of the second electrode plate 43 onto the substrate. The sixth, fifth, and fourth insulating layers within the tenth via V10 are etched away, exposing the surface of the second electrode plate 43. The tenth via V10 is configured to allow a subsequently formed sixth connection electrode to connect to the second electrode plate 43 through this via. In an exemplary embodiment, multiple tenth vias V10, serving as power vias, may be included. These multiple tenth vias V10 may be arranged sequentially along the second direction Y or the first direction X to increase the reliability of the connection between the first power line and the second electrode plate 43.

[0228] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate lies within the range of the orthographic projection of the first initial signal line 45 onto the substrate. The sixth, fifth, and fourth insulating layers within the eleventh via V11 are etched away, exposing the surface of the first initial signal line 45. The eleventh via V11 is configured to allow the first electrode of the subsequently formed first transistor T1 to be connected to the first initial signal line 45 through the via.

[0229] (109) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on a sixth insulating layer, such as... Figures 16a to 16d As shown, Figure 16a This is a planar structure diagram of eight sub-pixels. Figure 16b for Figure 16a A planar schematic diagram of the fourth conductive layer. Figure 16c This is a planar structure diagram with sixteen sub-pixels. Figure 16d for Figure 16c A schematic planar view of the fourth conductive layer. In an exemplary embodiment, the fourth conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0230] In an exemplary embodiment, the fourth conductive layer includes at least: a first connecting electrode 61, a second connecting electrode 62, a third connecting electrode 63, a fourth connecting electrode 64, a fifth connecting electrode 65, a sixth connecting electrode 66, a second initial signal line 67, a first data connecting line 68, and an initial signal connecting line 69.

[0231] In an exemplary embodiment, the first connection electrode 61 is a zigzag shape with its main body extending along the second direction Y. Its first end is connected to the second region 21-2 of the active layer 21 of the first transistor T1 (which is also the first region 22-1 of the active layer 22 of the second transistor T2) through a third via V3, and its second end is connected to the first electrode plate 33 through a ninth via V9, so that the first electrode plate 33, the second electrode of the first transistor T1, and the first electrode of the second transistor T2 have the same potential. In an exemplary embodiment, the first connection electrode 61 can serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2.

[0232] In an exemplary embodiment, the second connection electrode 62 can be a strip shape extending along the first direction X of the main body portion. The second connection electrode 62 is connected to the first region 21-1 of the active layer 21 of the first transistor T1 through a first via V1, and connected to the first initial signal line 45 in the sub-pixel of a sub-pixel row through an eleventh via V11 in that row. In an exemplary embodiment, the second connection electrode 62 can serve as the first electrode of the first transistor T1, and the second connection electrode 62 is configured to be connected to the first initial signal line 45 and the active layer 21 of the first transistor T1.

[0233] In an exemplary embodiment, the Nth column and the (N+1)th column share the same second connection electrode 62, and the (N+2)th column and the (N+3)th column share the same second connection electrode 62. In this exemplary embodiment, since the second connection electrode 62 in each sub-pixel is connected to the first initial signal line 45, by forming an interconnected integrated structure through adjacent sub-pixels sharing the same second connection electrode 62, it can be ensured that the second connection electrodes 62 of adjacent sub-pixels have the same potential. This is beneficial for improving the uniformity of the panel, avoiding display defects in the display substrate, and ensuring the display effect of the display substrate.

[0234] In an exemplary embodiment, one end of the third connection electrode 63 is connected to the second region 22-2 of the active layer 22 of the second transistor T2 through the second via V2, and the other end of the third connection electrode 63 is connected to the second region 23-2 of the active layer 23 of the third transistor T3 (which is also the first region 26-1 of the active layer 26 of the sixth transistor T6) through the sixth via V6. In an exemplary embodiment, the third connection electrode 63 can simultaneously serve as the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, so that the second electrodes of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 have the same potential.

[0235] In an exemplary embodiment, the fourth connection electrode 64 is connected to the first region 24-1 of the active layer 24 of the fourth transistor T4 via the fourth via V4. In an exemplary embodiment, the fourth connection electrode 64 can serve as the first electrode of the fourth transistor T4, configured to connect to a subsequently formed data signal line.

[0236] In an exemplary embodiment, the sixth connection electrode 66 is connected to the first region 25-1 of the active layer 25 of the fifth transistor T5 through the fifth via V5, and the sixth connection electrode 66 is connected to the second electrode plate 43 through the tenth via V10. In an exemplary embodiment, the sixth connection electrode 66 can serve as the first electrode of the fifth transistor T5 and is configured to be connected to a subsequently formed first power line.

[0237] In an exemplary embodiment, the fifth connection electrode 65 is connected to the second region 26-2 of the active layer 26 of the sixth transistor T6 (which is also the second region 27-2 of the active layer 27 of the seventh transistor T7) via the seventh via V7. In an exemplary embodiment, the fifth connection electrode 65 can serve as the second electrode of both the sixth transistor T6 and the seventh transistor T7, and is configured to connect to the anode connection electrode of a subsequently formed light-emitting element.

[0238] In an exemplary embodiment, the second initial signal line 67 can be a zigzag line extending along the first direction X of the main body. The second initial signal line 67 is connected to the first region 27-1 of the active layer 27 of the plurality of seventh transistors T7 through a plurality of eighth vias V8 in a sub-pixel row, thus writing the initial voltage into the plurality of seventh transistors T7 in the sub-pixel row. In an exemplary embodiment, since the second initial signal line 67 is connected to the first region 27-1 of the active layer 27 of all the seventh transistors T7 in a sub-pixel row, it can be ensured that the first electrode of all the seventh transistors T7 in a sub-pixel row has the same potential, which is beneficial to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate. In an exemplary embodiment, the second initial signal line 67 can serve as the first electrode of the seventh transistor T7.

[0239] In an exemplary embodiment, the first data connection line 68 may be a zigzag line extending along the first direction X of the main body. In an exemplary embodiment, the first data connection line 68 is disposed between adjacent row sub-pixels. In an exemplary embodiment, one end of the first data connection line 68 is configured to connect to a subsequently formed second data connection line via a via, and the other end is configured to connect to a subsequently formed data signal line via a via. In an exemplary embodiment, as... Figure 16d As shown, one end of the first data connection line 68 is configured to connect to a subsequently formed second data connection line via a via, and the other end is integrally formed with the fourth connection electrode 64 and configured to connect to a subsequently formed data signal line via a via. In an exemplary embodiment, the fourth connection electrode 64 connected to the first data connection line 68 can be a strip-shaped structure or a zigzag structure extending along the second direction Y, such as... Figure 16c and Figure 16d As shown, one end of the fourth connection electrode 64, which is connected to the first data connection line 68, is electrically connected to the subsequently formed data signal line through a via, and the other end is integrally formed with the first data connection line 68.

[0240] In an exemplary embodiment, in the first direction X, the first data connection line 68 may be located between two adjacent initial signal connection lines 69.

[0241] In an exemplary embodiment, the initial signal connection line 69 can be a strip-shaped structure extending along the second direction Y of the main body, and the initial signal connection line 69 is configured to be integrally formed with the second initial signal line 67. In an exemplary embodiment, one or more columns of sub-pixels can be provided between two adjacent initial signal connection lines 69, for example, two sub-pixels can be provided between two adjacent initial signal connection lines 69. In an exemplary embodiment, the initial signal connection line 69 connects a plurality of second initial signal lines 67 arranged along the second direction Y into an integral structure, so that the plurality of second initial signal lines 67 have the same potential, which is beneficial to improving the uniformity of the panel, avoiding display defects of the display substrate, improving low grayscale image quality, and ensuring the display effect of the display substrate.

[0242] (110) Forming a pattern for the seventh insulating layer and the first planarization layer. In an exemplary embodiment, forming the pattern for the seventh insulating layer and the first planarization layer may include: depositing a seventh insulating film on a substrate on which the aforementioned pattern is formed, then coating a first planarization film, and patterning the first planarization film and the seventh insulating film using a patterning process to form a seventh insulating layer covering the pattern of the fourth conductive layer and a first planarization layer disposed on the seventh insulating layer, wherein a plurality of vias are provided on the seventh insulating layer and the first planarization layer, such as... Figure 17a and Figure 17b As shown, Figure 17a This is a planar structure diagram of eight sub-pixels. Figure 17b This is a planar structure diagram with sixteen sub-pixels.

[0243] In an exemplary embodiment, the plurality of vias in each sub-pixel includes at least: a twelfth via V12, a thirteenth via V13, a fourteenth via V14, and a fifteenth via V15.

[0244] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate lies within the orthographic projection of the fourth connection electrode 64 onto the substrate. The first planarization layer and the seventh insulating layer within the twelfth via V12 are etched away, exposing the surface of the fourth connection electrode 64. The twelfth via V12 is configured to allow subsequently formed data signal lines to be connected to the fourth connection electrode 64 through the via.

[0245] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the substrate lies within the range of the orthographic projection of the fifth connecting electrode 65 onto the substrate. The first planarization layer and the seventh insulating layer within the thirteenth via V13 are etched away, exposing the surface of the fifth connecting electrode 65. The thirteenth via V13 is configured to allow the anode connecting electrode of a subsequently formed light-emitting element to be connected to the fifth connecting electrode 65 through this via.

[0246] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 onto the substrate lies within the range of the orthographic projection of the sixth connection electrode 66 onto the substrate. The first planarization layer and the seventh insulating layer within the fourteenth via V14 are etched away, exposing the surface of the sixth connection electrode 66. The fourteenth via V14 is configured to allow a subsequently formed first power line to be connected to the sixth connection electrode 66 through the via.

[0247] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 onto the substrate lies within the range of the orthographic projection of the first data connection line 68 onto the substrate. The first planarization layer and the seventh insulating layer within the fifteenth via V15 are etched away, exposing the surface of the first data connection line 68. The fifteenth via V15 is configured to allow a subsequently formed second data connection line to be connected to the first data connection line 68 through this via.

[0248] In an exemplary implementation, such as Figure 17b As shown, the orthographic projection of the twelfth via V12, disposed on the fourth connection electrode 64 connected to the first data connection line 68, onto the substrate lies within the orthographic projection range of the first data connection line 68 (i.e., the fourth connection electrode 64) onto the substrate. The first planarization layer and the seventh insulating layer within the twelfth via V12 are etched away, exposing the surface of the first data connection line 68 (i.e., the fourth connection electrode 64). The twelfth via V12 is configured to allow subsequently formed data signal lines to connect to the first data connection line 68 (i.e., the fourth connection electrode 64) through this via. The first data connection line 68 and the fourth connection electrode 64 share a single via for connection to subsequently formed data signal lines, saving space in the pixel driving circuitry. Figure 17b and Figure 18c As shown, one end of the first data connection line 68 is integrally formed with the fourth connection electrode 64 and is electrically connected to the data signal line 71 through the twelfth via V12, while the other end is electrically connected to the second data connection line 74 through the fifteenth via V15.

[0249] (111) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive thin film on a substrate on which the aforementioned pattern is formed, patterning the fifth conductive thin film using a patterning process, and forming a fifth conductive layer disposed on the first planarization layer, such as... Figures 18a to 18c As shown, Figure 18a This is a planar structure diagram of eight sub-pixels. Figure 18c This is a planar structure diagram with sixteen sub-pixels. Figure 18b for Figure 18a A planar schematic diagram of the fifth conductive layer. In an exemplary embodiment, the fifth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0250] In an exemplary embodiment, the fifth conductive layer includes at least: a data signal line 71, a first power supply line 72, an anode connection electrode 73, and a second data connection line 74. In an exemplary embodiment, the anode connection electrode 73 is the anode connection electrode of the light-emitting element.

[0251] In an exemplary embodiment, the data signal line 71 is a zigzag shape with its main body extending along the second direction Y. The data signal line 71 is connected to the fourth connection electrode 64 through the twelfth via V12. Since the fourth connection electrode 64 is connected to the first region 24-1 of the active layer 24 of the fourth transistor T4 through the via, the connection between the data signal line 71 and the first electrode of the fourth transistor T4 is realized, and the data signal is written to the fourth transistor T4.

[0252] In an exemplary embodiment, the first power line 72 is a zigzag shape with its main body extending along the second direction Y. The first power line 72 is connected to the sixth connection electrode 66 through the fourteenth via V14. Since the sixth connection electrode 66 is connected to the second electrode plate 43 through the via, the connection between the first power line 72 and the second electrode plate 43 is realized, and the power signal is written to the second electrode plate 43. Since the sixth connection electrode 66 is connected to the first region 25-1 of the active layer 25 of the fifth transistor T5 through the via, the connection between the first power line 72 and the first electrode of the fifth transistor T5 is realized, and the power signal is written to the fifth transistor T5.

[0253] In an exemplary embodiment, the anode connection electrode 73 is connected to the fifth connection electrode 65 via the thirteenth via V13. Since the fifth connection electrode 65 is connected to the second region 26-2 of the active layer 26 of the sixth transistor T6 (which is also the second region 27-2 of the active layer 27 of the seventh transistor T7) via the via, the connection between the anode connection electrode 73 and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 is realized.

[0254] In an exemplary embodiment, the main body of the second data connection line 74 extends along the second direction Y, and the second data connection line 74 is connected to the first data connection line 68 through a fifteenth via V15. In an exemplary embodiment, the second data connection line 74 is disposed between two adjacent columns of sub-pixels. In an exemplary embodiment, three second data connection lines 74 may be disposed between two adjacent columns of sub-pixels, and three adjacent second data connection lines 74 are respectively connected to the first data connection line 68 in different sub-pixel rows through vias.

[0255] In an exemplary embodiment, any one of the second data connection lines 74 is connected to the first data connection line 68 in the display area through the fifteenth via V15, and is connected to the integrated circuit (IC) in the driver chip area in the bonding area.

[0256] In an exemplary embodiment, taking eight sub-pixels (two sub-pixel rows and four sub-pixel columns) in the display area (AA) as an example, the fabrication process of another display substrate may include the following operations.

[0257] (201) Prepare a substrate on a glass substrate. The preparation method is the same as that described in (101) above, and will not be repeated here.

[0258] (202) Forming a masking layer pattern. The preparation method is the same as (102) above, and will not be repeated here. The formed masking layer pattern is as follows: Figure 9 As shown.

[0259] (203) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate on which the aforementioned pattern is formed; patterning the first semiconductor film using a patterning process to form a first insulating layer covering the masking layer pattern; and a first semiconductor layer pattern disposed on the first insulating layer, such as... Figure 19a and Figure 19b As shown, Figure 19a This is a planar structure diagram of eight sub-pixels. Figure 19b for Figure 19a A planar schematic diagram of the first semiconductor layer.

[0260] In an exemplary embodiment, the first semiconductor layer pattern of each sub-pixel may include the active layer 23 of the third transistor T3 to the active layer 27 of the seventh transistor T7, and the active layer 23 of the third transistor T3 to the active layer 27 of the seventh transistor T7 are an integral structure interconnected.

[0261] In an exemplary embodiment, in the first direction X, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on the same side of the active layer 23 of the third transistor T3, and the active layer 26 of the sixth transistor T6 is located on the other side of the active layer 23 of the third transistor T3; in the second direction Y, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on both sides of the active layer 23 of the third transistor T3, and the active layer 25 of the fifth transistor T5, the active layer 26 of the sixth transistor T6 and the active layer 27 of the seventh transistor T7 are located on the same side of the active layer 23 of the third transistor T3, and the active layer 27 of the seventh transistor T7 is located on the side of the active layer 26 of the sixth transistor T6 away from the active layer 23 of the third transistor T3.

[0262] In an exemplary embodiment, taking the sub-pixel in the Mth row and Nth column as an example: In the first direction X, the active layer 24 of the fourth transistor T4 and the active layer 25 of the fifth transistor T5 are located on the side of the active layer 23 of the third transistor T3 away from the (N+1)th column sub-pixel, and the active layer 26 of the sixth transistor T6 is located on the side of the active layer 23 of the third transistor T3 away from the (N-1)th column sub-pixel; In the second direction Y, the active layer 24 of the fourth transistor T4 is located on the side of the active layer 23 of the third transistor T3 away from the (M-1)th row sub-pixel, the active layers 25 of the fifth transistor T5, the active layers 26 of the sixth transistor T6, and the active layer 27 of the seventh transistor T7 are located on the side of the active layer 23 of the third transistor T3 away from the (M+1)th row sub-pixel, and the active layer 27 of the seventh transistor T7 is located on the side of the active layer 26 of the sixth transistor T6 away from the active layer 23 of the third transistor T3.

[0263] In an exemplary embodiment, the active layer 23 of the third transistor T3 can be Ω-shaped, the active layer 24 of the fourth transistor T4 is a zigzag shape extending along the second direction Y, with the middle of the zigzag bending away from the active layer 31 of the third transistor T3 and the end of the zigzag bending towards the active layer 31 of the third transistor T3, the active layer 27 of the seventh transistor T7 can be I-shaped, and the active layers 25 of the fifth transistor T5 and the active layers 26 of the sixth transistor T6 can be L-shaped.

[0264] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region 23-1 of the active layer 23 of the third transistor T3 may serve as the second region 24-2 of the active layer 24 of the fourth transistor T4 and the second region 25-2 of the active layer 25 of the fifth transistor T5. The second region 23-2 of the active layer 23 of the third transistor T3 may serve as the first region 26-1 of the active layer 26 of the sixth transistor T6. The second region 26-2 of the active layer 26 of the sixth transistor T6 may serve as the second region 27-2 of the active layer 27 of the seventh transistor T7. The first region 24-1 of the active layer 24 of the fourth transistor T4, the first region 25-1 of the active layer 25 of the fifth transistor T5, and the first region 27-1 of the active layer 27 of the seventh transistor T7 may be configured individually.

[0265] In an exemplary embodiment, the orthographic projection of the active layer 23 of the third transistor T3 onto the substrate at least partially overlaps with the orthographic projection of the blocking block 14 onto the substrate. In an exemplary embodiment, the orthographic projection of the channel region of the active layer 23 of the third transistor T3 onto the substrate lies within the range of the orthographic projection of the blocking block 14 onto the substrate.

[0266] In an exemplary embodiment, the first region 25-1 of the active layer 25 of the fifth transistor T5 in the Nth column and the first region 25-1 of the active layer 25 of the fifth transistor T5 in the (N-1)th column are interconnected, and the first region 25-1 of the active layer 25 of the fifth transistor T5 in the N+1th column and the first region 25-1 of the active layer 25 of the fifth transistor T5 in the N+2th column are interconnected. In this exemplary embodiment, since the first region of the active layer of the fifth transistor T5 in each sub-pixel is connected to the subsequently formed first power line, by forming an interconnected integrated structure of the first regions of the active layers of the fifth transistor T5 in adjacent sub-pixels, it can be ensured that the first electrodes of the fifth transistor T5 in adjacent sub-pixels have the same potential. This is beneficial for improving the uniformity of the panel, avoiding display defects in the display substrate, and ensuring the display effect of the display substrate.

[0267] In an exemplary embodiment, the first semiconductor layer in column N and the first semiconductor layer in column N+1 may be mirror-symmetric with respect to the first center line, the first semiconductor layer in column N+1 and the first semiconductor layer in column N+2 may be mirror-symmetric with respect to the second center line, and the first semiconductor layer in column N+2 and the first semiconductor layer in column N+3 may be mirror-symmetric with respect to the third center line.

[0268] In an exemplary embodiment, the first region 27-1 of the active layer 27 of the seventh transistor T7 in the i-th row of sub-pixels can be set in the (i-1)-th row of sub-pixels, i = 2, 3, ..., M+1.

[0269] In an exemplary embodiment, the first semiconductor layer may be polycrystalline silicon (p-Si), meaning that the third transistor T3 to the seventh transistor T7 may be LTPS thin-film transistors. In another exemplary embodiment, patterning the first semiconductor thin film using a patterning process may include: first forming an amorphous silicon (a-Si) thin film on a first insulating film; then performing a hydrogen removal treatment on the amorphous silicon thin film; and finally performing a crystallization treatment on the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form the pattern of the first semiconductor layer.

[0270] (204) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a second insulating layer covering the first semiconductor layer pattern; and a first conductive layer pattern disposed on the second insulating layer, such as... Figure 20a and Figure 20b As shown, Figure 20b for Figure 20a A planar schematic diagram of the first conductive layer. In an exemplary embodiment, the first conductive layer may be referred to as the first gate metal (GATE1) layer.

[0271] In an exemplary embodiment, the first conductive layer pattern may include at least: a first scan signal line 31, a light emission control line 32, and a first electrode 33 of a storage capacitor. The main body of the first scan signal line 31 and the light emission control line 32 may extend along a first direction X. In the same sub-pixel, the light emission control line 32, the first electrode 33 of the storage capacitor, and the first scan signal line 31 are arranged along a second direction Y.

[0272] In an exemplary embodiment, in the second direction Y, the first scan signal line 31 and the light emission control line 32 are located on both sides of the first electrode 33 of the storage capacitor. For example, in the second direction, the light emission control line 32, the first electrode 33, and the first scan signal line 31 are arranged sequentially.

[0273] Taking the Mth row and Nth column sub-pixel as an example: In the second direction Y, the light emission control line 32 can be located on the side of the first plate 33 of the storage capacitor in this sub-pixel near the M-1th row sub-pixel; the first scan signal line 31 can be located on the side of the first plate 33 of the storage capacitor in this sub-pixel near the M+1th row sub-pixel.

[0274] In an exemplary embodiment, the first electrode 33 can be located between the light-emitting control line 32 and the first scan signal line 31. The first electrode 33 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the first electrode 33 on the substrate overlaps with the orthographic projection of the active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode 33 can simultaneously serve as one electrode of the storage capacitor and the control electrode of the third transistor T3.

[0275] In an exemplary embodiment, the region where the light-emitting control line 32 overlaps with the active layer of the fifth transistor T5 serves as the control electrode of the fifth transistor T5, the region where the light-emitting control line 32 overlaps with the active layer of the sixth transistor T6 serves as the control electrode of the sixth transistor T6, the region where the first scan signal line 31 overlaps with the active layer of the fourth transistor T4 serves as the control electrode of the fourth transistor T4, and the region where the first scan signal line 31 overlaps with the active layer of the seventh transistor T7 serves as the control electrode of the seventh transistor T7.

[0276] In an exemplary embodiment, the first scanning signal line 31 and the light emission control line 32 can be designed with equal width or with non-equal width, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines.

[0277] In an exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the region shielded by the first conductive layer forms the channel region of the third transistor T3 to the seventh transistor T7. The semiconductor layer in the region not shielded by the first conductive layer is conducted, that is, the first region and the second region of the active layer 23 of the third transistor T3 to the active layer 27 of the seventh transistor T8 are both conducted.

[0278] (205) Forming the second conductive layer pattern. The preparation method is the same as that described in (105) above, and will not be repeated here. The formed second conductive layer pattern is as follows. Figure 12b As shown, Figure 21 The diagram shown is a planar structure diagram of eight sub-pixels.

[0279] (206) Forming a second semiconductor layer pattern. The fabrication method is the same as described in (106) above, and will not be repeated here. The formed second conductive layer pattern is as follows. Figure 13b As shown, Figure 22 The diagram shown is a planar structure diagram of eight sub-pixels.

[0280] (207) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: sequentially depositing a fifth insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer; and a third conductive layer pattern disposed on the fifth insulating layer, such as... Figures 23a to 23b As shown, Figure 23a This is a planar structure diagram of eight sub-pixels. Figure 23b for Figure 23a A schematic planar view of the third conductive layer. In an exemplary embodiment, the third conductive layer may be referred to as the third gate metal (GATE3) layer.

[0281] In an exemplary embodiment, the third conductive layer pattern includes at least: a second scan signal line 51 and a third scan signal line 52. The main body of the second scan signal line 51, the third scan signal line 52, and the adapter electrode 53 can extend along the first direction X. The third scan signal line 52, the adapter electrode 53, and the second scan signal line 51 are arranged sequentially along the second direction Y.

[0282] In an exemplary embodiment, the region where the second scan signal line 51 overlaps with the active layer 21 of the first transistor T1 serves as the control electrode of the first transistor T1, and the region where the third scan signal line 52 overlaps with the active layer 22 of the second transistor T2 serves as the control electrode of the second transistor T2.

[0283] In an exemplary embodiment, the adapter electrode 53 is connected to the subsequently formed second initial signal line 67 through a via, so that the potential of multiple second initial signal lines 67 of the same row of sub-pixels is the same, thereby improving the display effect.

[0284] In an exemplary embodiment, the signals of the first blocking line 41 and the second scanning signal line 51 can be the same, that is, they are connected in parallel and connected to the same signal source, so that the first blocking line 41 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the first transistor T1, forming a dual-gate structure of the first transistor T1.

[0285] In an exemplary embodiment, the signals of the second blocking line 42 and the third scanning signal line 52 can be the same, that is, they are connected in parallel and connected to the same signal source, so that the second blocking line 42 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the second transistor T2, forming a dual-gate structure of the second transistor T2.

[0286] (208) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming a sixth insulating layer pattern may include: depositing a sixth insulating film on a substrate on which the aforementioned pattern is formed, patterning the sixth insulating film using a patterning process to form a sixth insulating layer covering a third conductive layer, wherein a plurality of vias are provided on the sixth insulating layer, such as... Figure 24 As shown, Figure 24 This is a planar structure diagram of eight sub-pixels.

[0287] In an exemplary embodiment, the plurality of vias in each sub-pixel include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, and a transition via Vm.

[0288] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate lies within the orthographic projection of the active layer 21 of the first transistor T1 onto the substrate. The sixth and fifth insulating layers within the first via V1 are etched away, exposing the surface of the first region 21-1 of the active layer 21 of the first transistor T1. The first via V1 is configured to allow the first electrode of the subsequently formed first transistor T1 to be connected to the active layer 21 of the first transistor T1 through the via.

[0289] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate lies within the orthographic projection of the active layer 22 of the second transistor T2 onto the substrate. The sixth and fifth insulating layers within the second via V2 are etched away, exposing the surface of the second region 22-2 of the active layer 22 of the second transistor T2. The second via V2 is configured to allow the second electrode of the subsequently formed second transistor T2 to be connected to the active layer 22 of the second transistor T2 through the via.

[0290] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate lies within the orthographic projection of the active layer 22 of the second transistor T2 onto the substrate. The sixth and fifth insulating layers within the third via V3 are etched away, exposing the surface of the first region 22-1 of the active layer 22 of the second transistor T2 (which is also the second region 21-2 of the active layer 21 of the first transistor T1). The third via V3 is configured to connect the second electrode of the subsequently formed first transistor T1 to the active layer 21 of the first transistor T1 through the via, and to connect the first electrode of the subsequently formed second transistor T2 to the active layer 22 of the second transistor T2 through the via.

[0291] In an exemplary embodiment, the orthogonal projection of the fourth via V4 onto the substrate lies within the orthogonal projection of the active layer 24 of the fourth transistor T4 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the fourth via V4 are etched away, exposing the first region 24-1 of the active layer 24 of the fourth transistor T4. The fourth via V4 is configured to allow the first electrode of the subsequently formed fourth transistor T4 to be connected to the active layer 24 of the fourth transistor T4 through the via.

[0292] In an exemplary embodiment, the orthogonal projection of the fifth via V5 onto the substrate lies within the orthogonal projection of the active layer 25 of the fifth transistor T5 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the fifth via V5 are etched away, exposing the surface of the first region 25-1 of the active layer 25 of the fifth transistor T5. The fifth via V5 is configured to allow the first electrode of the subsequently formed fifth transistor T5 to be connected to the active layer 25 of the fifth transistor T5 through this via.

[0293] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate lies within the orthographic projection of the active layer 26 of the sixth transistor T6 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the sixth via V6 are etched away, exposing the surface of the first region 26 of the active layer 26 of the sixth transistor T6 (which is also the second region of the active layer 23 of the third transistor T3). The sixth via V6 is configured to connect the first electrode of the subsequently formed sixth transistor T6 to the active layer 26 of the sixth transistor T6 through the via, and to connect the second electrode of the subsequently formed third transistor T3 to the active layer 23 of the third transistor T3 through the via.

[0294] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate lies within the orthographic projection of the active layer 26 of the sixth transistor T6 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the seventh via V7 are etched away, exposing the surface of the second region 26-2 of the active layer 26 of the sixth transistor T6 (which is also the second region 27-2 of the active layer 27 of the seventh transistor T7). The seventh via V7 is configured to connect the second electrode of the subsequently formed sixth transistor T6 to the active layer 26 of the sixth transistor T6 through the via, and to connect the second electrode of the subsequently formed seventh transistor T7 to the active layer 27 of the seventh transistor T7 through the via.

[0295] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate lies within the orthographic projection of the active layer 27 of the seventh transistor T7 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the eighth via V8 are etched away, exposing the surface of the first region 27-1 of the active layer 27 of the seventh transistor T7. The eighth via V8 is configured to allow the first electrode of the subsequently formed seventh transistor T7 to be connected to the active layer 27 of the seventh transistor T7 through this via.

[0296] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate lies within the range of the orthographic projection of the opening 44 onto the substrate. The sixth, fifth, fourth, and third insulating layers within the ninth via V9 are etched away, exposing the surface of the first electrode plate 33. The ninth via V9 is configured to allow the second electrode of the subsequently formed first transistor T1 to be connected to the first electrode plate 33 through the via.

[0297] In an exemplary embodiment, the tenth via V10 is located within the orthographic projection of the second electrode plate 43 onto the substrate. The sixth, fifth, and fourth insulating layers within the tenth via V10 are etched away, exposing the surface of the second electrode plate 43. The tenth via V10 is configured to allow a subsequently formed sixth connection electrode to connect to the second electrode plate 43 through this via. In an exemplary embodiment, multiple tenth vias V10, serving as power vias, may be included. These multiple tenth vias V10 may be arranged sequentially along the second direction Y or the first direction X to increase the reliability of the connection between the first power line and the second electrode plate 43.

[0298] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate lies within the range of the orthographic projection of the first initial signal line 45 onto the substrate. The sixth, fifth, and fourth insulating layers within the eleventh via V11 are etched away, exposing the surface of the first initial signal line 45. The eleventh via V11 is configured to allow the first electrode of the subsequently formed first transistor T1 to be connected to the first initial signal line 45 through the via.

[0299] In an exemplary embodiment, the orthographic projection of the transition via Vm onto the substrate lies within the range of the orthographic projection of the transition connection electrode 53 onto the substrate. The sixth, fifth, and fourth insulating layers within the transition via Vm are etched away, exposing the surface of the transition connection electrode 53. The transition via Vm is configured to allow two adjacent second initial signal lines in the same row to be connected through this via.

[0300] (209) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on a sixth insulating layer, such as... Figures 25a to 25d As shown, Figure 25a This is a planar structure diagram of eight sub-pixels. Figure 25b for Figure 25a A planar schematic diagram of the fourth conductive layer. Figure 25c This is a planar structure diagram with thirty-two sub-pixels. Figure 25d for Figure 25c A schematic planar view of the fourth conductive layer. In an exemplary embodiment, the fourth conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0301] In an exemplary embodiment, the fourth conductive layer includes at least: a first connecting electrode 61, a second connecting electrode 62, a third connecting electrode 63, a fourth connecting electrode 64, a fifth connecting electrode 65, a sixth connecting electrode 66, a second initial signal line 67, a first data connecting line 68, a third data connecting line 610, and a fourth data connecting line 611.

[0302] In an exemplary embodiment, the first connection electrode 61 is a zigzag shape with its main body extending along the second direction Y. Its first end is connected to the second region 21-2 of the active layer 21 of the first transistor T1 (which is also the first region 22-1 of the active layer 22 of the second transistor T2) through a third via V3, and its second end is connected to the first electrode plate 33 through a ninth via V9, so that the first electrode plate 33, the second electrode of the first transistor T1, and the first electrode of the second transistor T2 have the same potential. In an exemplary embodiment, the first connection electrode 61 can serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2.

[0303] In an exemplary embodiment, the second connection electrode 62 can be a strip shape extending along the first direction X of the main body portion. The second connection electrode 62 is connected to the first region 21-1 of the active layer 21 of the first transistor T1 through a first via V1, and connected to the first initial signal line 45 in the sub-pixel of a sub-pixel row through an eleventh via V11 in that row. In an exemplary embodiment, the second connection electrode 62 can serve as the first electrode of the first transistor T1, and the second connection electrode 62 is configured to be connected to the first initial signal line 45 and the active layer 21 of the first transistor T1.

[0304] In an exemplary embodiment, the Nth column and the (N+1)th column share the same second connection electrode 62, and the (N+2)th column and the (N+3)th column share the same second connection electrode 62. In this exemplary embodiment, since the second connection electrode 62 in each sub-pixel is connected to the first initial signal line 45, by forming an interconnected integrated structure through adjacent sub-pixels sharing the same second connection electrode 62, it can be ensured that the second connection electrodes 62 of adjacent sub-pixels have the same potential. This is beneficial for improving the uniformity of the panel, avoiding display defects in the display substrate, and ensuring the display effect of the display substrate.

[0305] In an exemplary embodiment, one end of the third connection electrode 63 is connected to the second region 22-2 of the active layer 22 of the second transistor T2 through the second via V2, and the other end of the third connection electrode 63 is connected to the second region 23-2 of the active layer 23 of the third transistor T3 (which is also the first region 26-1 of the active layer 26 of the sixth transistor T6) through the sixth via V6. In an exemplary embodiment, the third connection electrode 63 can simultaneously serve as the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, so that the second electrodes of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 have the same potential.

[0306] In an exemplary embodiment, the fourth connection electrode 64 is connected to the first region 24-1 of the active layer 24 of the fourth transistor T4 via the fourth via V4. In an exemplary embodiment, the fourth connection electrode 64 can serve as the first electrode of the fourth transistor T4, configured to connect to a subsequently formed data signal line.

[0307] In an exemplary embodiment, the sixth connection electrode 66 is connected to the first region 25-1 of the active layer 25 of the fifth transistor T5 through the fifth via V5, and the sixth connection electrode 66 is connected to the second electrode plate 43 through the tenth via V10. In an exemplary embodiment, the sixth connection electrode 66 can serve as the first electrode of the fifth transistor T5 and is configured to be connected to a subsequently formed first power line.

[0308] In an exemplary embodiment, the fifth connection electrode 65 is connected to the second region 26-2 of the active layer 26 of the sixth transistor T6 (which is also the second region 27-2 of the active layer 27 of the seventh transistor T7) via the seventh via V7. In an exemplary embodiment, the fifth connection electrode 65 can serve as the second electrode of both the sixth transistor T6 and the seventh transistor T7, and is configured to connect to the anode connection electrode of a subsequently formed light-emitting element.

[0309] In an exemplary embodiment, the second initial signal line 67 can be a zigzag line extending along the first direction X of the main body. The second initial signal line 67 is connected to the first region 27-1 of the active layer 27 of the adjacent two columns of the seventh transistor T7 through the eighth via V8 in a sub-pixel row, writing the initial voltage into the adjacent two columns of the seventh transistor T7 in a sub-pixel row. The second initial signal line 67 is connected to the adapter electrode 53 through the adapter via Vm. The adapter electrode 53 electrically connects multiple second initial signal lines 67 in the same row to each other, so that multiple second initial signal lines 67 in the same sub-pixel row have the same potential, which is beneficial to improve the uniformity of the panel and avoid display defects of the display substrate. In the exemplary embodiment, the second initial signal line 67 can be used as the first electrode of the seventh transistor T7.

[0310] In an exemplary embodiment, the first data connection line 68 can be a zigzag or strip shape extending along the first direction X of the main body. In an exemplary embodiment, the first data connection line 68 is disposed between adjacent row sub-pixels. In an exemplary embodiment, one end of the first data connection line 68 is configured to be connected to a subsequently formed second data connection line through a via, and the other end is configured to be connected to a subsequently formed data signal line through a via. In an exemplary embodiment, as... Figure 25d As shown, one end of the first data connection line 68 can be integrally formed with one of the fourth data connection electrodes 64, and the other end is electrically connected to the subsequently formed second data connection line through a via. In an exemplary embodiment, as... Figure 25d As shown, the fourth connection electrode 64 connected to the first data connection line 68 can be a strip-shaped structure or a zigzag structure extending along the second direction Y. One end is integrally formed with the first data connection line 68, and the other end is electrically connected to the subsequently formed data signal line through the twelfth via V12.

[0311] In an exemplary embodiment, the fourth data connection line 611 can be a zigzag or strip shape extending along the first direction X of the main body. In an exemplary embodiment, the fourth data connection line 611 is disposed between adjacent row sub-pixels. In an exemplary embodiment, one end of the fourth data connection line 611 is connected to the third data connection line 610, and the other end is integrally formed with one of the fourth connection electrodes and configured to connect to a subsequently formed data signal line through a via. In an exemplary embodiment, as... Figure 25d As shown, the fourth connection electrode 64 connected to the fourth data connection line 611 can be a strip-shaped structure or a zigzag structure extending along the second direction Y. One end is integrally formed with the fourth data connection line 611, and the other end is electrically connected to the data signal line formed subsequently through the twelfth via V12.

[0312] The main body of the third data connection line 610 extends along the second direction Y. One end of the third data connection line 610 is connected to the fourth data connection line 611, and the other end is connected to the driver chip in the bonding area. In an exemplary embodiment, the third data connection line 610 is disposed between two adjacent columns of sub-pixels. In an exemplary embodiment, two third data connection lines 610 can be disposed between two adjacent columns of sub-pixels, and two adjacent third data connection lines 610 are respectively connected to the fourth data connection lines 611 in different sub-pixel rows.

[0313] In an exemplary embodiment, any one of the third data connection lines 610 is connected to the fourth data connection line 611 in the display area and to the integrated circuit (IC) in the driver chip area in the bonding area.

[0314] (210) Forming a pattern for the seventh insulating layer and the first planarization layer. In an exemplary embodiment, forming the pattern for the seventh insulating layer and the first planarization layer may include: depositing a seventh insulating film on a substrate on which the aforementioned pattern is formed, then coating a first planarization film, and patterning the first planarization film and the seventh insulating film using a patterning process to form a seventh insulating layer covering the pattern of the fourth conductive layer and a first planarization layer disposed on the seventh insulating layer, wherein a plurality of vias are provided on the seventh insulating layer and the first planarization layer, such as... Figure 26a and Figure 26b As shown, 26a is a planar structure diagram of eight sub-pixels. Figure 26b This is a planar structure diagram with thirty-two sub-pixels.

[0315] In an exemplary embodiment, the plurality of vias in each sub-pixel includes at least: a twelfth via V12, a thirteenth via V13, a fourteenth via V14, and a fifteenth via V15.

[0316] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate lies within the orthographic projection of the fourth connection electrode 64 onto the substrate. The first planarization layer and the seventh insulating layer within the twelfth via V12 are etched away, exposing the surface of the fourth connection electrode 64. The twelfth via V12 is configured to allow subsequently formed data signal lines to connect to the fourth connection electrode 64 through this via. The first data connection line 68 and the fourth connection electrode 64 share a single via (V12) for connection to subsequently formed data signal lines, saving space in the pixel driving circuitry.

[0317] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the substrate lies within the range of the orthographic projection of the fifth connecting electrode 65 onto the substrate. The first planarization layer and the seventh insulating layer within the thirteenth via V13 are etched away, exposing the surface of the fifth connecting electrode 65. The thirteenth via V13 is configured to allow the anode connecting electrode of a subsequently formed light-emitting element to be connected to the fifth connecting electrode 65 through this via.

[0318] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 onto the substrate lies within the range of the orthographic projection of the sixth connection electrode 66 onto the substrate. The first planarization layer and the seventh insulating layer within the fourteenth via V14 are etched away, exposing the surface of the sixth connection electrode 66. The fourteenth via V14 is configured to allow a subsequently formed first power line to be connected to the sixth connection electrode 66 through the via.

[0319] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 onto the substrate lies within the range of the orthographic projection of the first data connection line 68 onto the substrate. The first planarization layer and the seventh insulating layer within the fifteenth via V15 are etched away, exposing the surface of the first data connection line 68. The fifteenth via V15 is configured to allow a subsequently formed second data connection line to be connected to the first data connection line 68 through this via.

[0320] (211) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive thin film on a substrate on which the aforementioned pattern is formed, patterning the fifth conductive thin film using a patterning process, and forming a fifth conductive layer disposed on the first planarization layer, such as... Figures 27a to 27c As shown, Figure 27a This is a planar structure diagram of eight sub-pixels. Figure 27b for Figure 27a A planar schematic diagram of the fifth conductive layer. Figure 27c This is a planar structure diagram of thirty-two sub-pixels. In an exemplary embodiment, the fifth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0321] In an exemplary embodiment, the fifth conductive layer includes at least: a data signal line 71, a first power supply line 72, an anode connection electrode 73, and a second data connection line 74. In an exemplary embodiment, the anode connection electrode 73 is the anode connection electrode of the light-emitting element.

[0322] In an exemplary embodiment, the main body of the data signal line 71 extends along the second direction Y, and the data signal line 71 is connected to the fourth connection electrode 64 through the twelfth via V12. Since the fourth connection electrode 64 is connected to the first region 24-1 of the active layer 24 of the fourth transistor T4 through the via, the connection between the data signal line 71 and the first electrode of the fourth transistor T4 is realized, and the data signal is written to the fourth transistor T4.

[0323] In an exemplary embodiment, the first power line 72 is a zigzag shape with its main body extending along the second direction Y. The first power line 72 is connected to the sixth connection electrode 66 through the fourteenth via V14. Since the sixth connection electrode 66 is connected to the second electrode plate 43 through the via, the connection between the first power line 72 and the second electrode plate 43 is realized, and the power signal is written to the second electrode plate 43. Since the sixth connection electrode 66 is connected to the first region 25-1 of the active layer 25 of the fifth transistor T5 through the via, the connection between the first power line 72 and the first electrode of the fifth transistor T5 is realized, and the power signal is written to the fifth transistor T5.

[0324] In an exemplary embodiment, the anode connection electrode 73 is connected to the fifth connection electrode 65 via the thirteenth via V13. Since the fifth connection electrode 65 is connected to the second region 26-2 of the active layer 26 of the sixth transistor T6 (which is also the second region 27-2 of the active layer 27 of the seventh transistor T7) via the via, the connection between the anode connection electrode 73 and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 is realized.

[0325] In an exemplary embodiment, the main body of the second data connection line 74 extends along the second direction Y, and the second data connection line 74 is connected to the first data connection line 68 through the fifteenth via V15. In an exemplary embodiment, the second data connection line 74 is disposed between two adjacent columns of sub-pixels. In an exemplary embodiment, one second data connection line 74 may be disposed between two adjacent columns of sub-pixels.

[0326] In an exemplary embodiment, within the plane of the display substrate, two third data connection lines 610 and one second data connection line 74 are provided between two adjacent columns of sub-pixels. In the first direction X, the second data connection line 74 is disposed between the two third data connection lines 610. The two third data connection lines 610 between two adjacent columns of sub-pixels are connected to two fourth data connection lines 611 respectively located in two first spaces R1. One second data connection line 74 is connected to a first data connection line 68 in the first space R1 through a via.

[0327] like Figure 8c and Figure 27c As shown, the 16 sub-pixels (2 sub-pixel rows, 8 sub-pixel columns) in the display area (AA) prepared by (201) to (211) above are... Figure 8c In the structure shown, in the second space R2 between the N+3rd and N+4th columns of pixels, and in the second space R2 between the N+5th and N+6th columns of pixels, there is one third data connection line 610 and two second data connection lines 74 within the same second space R2. In the plane of the display substrate, in the first direction X, the two second data connection lines 74 are located on either side of the third data connection line 610. The two second data connection lines 74 in the same second space R2 are connected to different first data connection lines 68. In the second space R2 between the N+1th and N+2th columns of pixels, there are two third data connection lines 610 and one second data connection line 74 within the same second space R2. In the plane of the display substrate, in the first direction X, the two third data connection lines 610 are located on either side of the second data connection line 74. The two third data connection lines 610 in the same second space R2 are connected to different fourth data connection lines 611.

[0328] like Figure 27c As shown, the thirty-two sub-pixels (4 sub-pixel rows, 8 sub-pixel columns) in the display area (AA) prepared by (201) to (211) above are... Figure 27cIn the structure shown, in the second space R2 between the N+1th and N+2th columns of pixels and the second space R2 between the N-3th and N-2th columns of pixels, there are two third data connection lines 610 and one second data connection line 74 in the same second space R2. In the plane of the display substrate, in the first direction X, the two third data connection lines 610 are located on both sides of the second data connection line 74. The two third data connection lines 610 in the same second space R2 are connected to different fourth data connection lines 611. In the second space R2 between the N-1th and Nth columns of pixels, there are two second data connection lines 74 and one third data connection line 610 in the same second space R2. In the plane of the display substrate, in the first direction X, the two second data connection lines 74 are located on both sides of the third data connection line 610. The two second data connection lines 74 in the same second space R2 are connected to different first data connection lines 68.

[0329] Thus, the driving circuit layer is fabricated on the substrate. In an exemplary embodiment, in a plane perpendicular to the display substrate, the driving circuit layer may include a shielding layer, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed on the substrate.

[0330] In an exemplary embodiment, the driving circuit layer may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, a seventh insulating layer, and a first planarization layer. The first insulating layer is disposed between the shielding layer and the first semiconductor layer, the second insulating layer is disposed between the first semiconductor layer and the first conductive layer, the third insulating layer is disposed between the first conductive layer and the second conductive layer, the fourth insulating layer is disposed between the second conductive layer and the second semiconductor layer, the fifth insulating layer is disposed between the second semiconductor layer and the third conductive layer, the sixth insulating layer is disposed between the third conductive layer and the fourth conductive layer, and the seventh insulating layer and the first planarization layer are disposed between the fourth conductive layer and the fifth conductive layer.

[0331] In an exemplary embodiment, after the driving circuit layer is fabricated, a light-emitting structure layer is fabricated on the driving circuit layer. The fabrication process of the light-emitting structure layer may include the following operations: forming a second planarization layer pattern, wherein at least an anode via is provided on the second planarization layer; forming an anode pattern, wherein the anode is connected to an anode connecting electrode through the anode via; forming an anode pixel definition layer, wherein pixel openings are provided on the pixel definition layer, and the pixel openings expose the anode; forming an organic light-emitting layer using a vapor deposition or inkjet printing process, wherein a cathode is formed on the organic light-emitting layer; and forming an encapsulation layer, wherein the encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked thereon. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0332] In an exemplary embodiment, the shielding layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo, Ti / Al / Ti, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer, and the seventh insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer, multi-layer, or composite layers. The first insulating layer can be called a buffer layer to improve the substrate's resistance to water and oxygen. The second, third, fourth, and fifth insulating layers can be called gate insulating (GI) layers. The sixth insulating layer can be called an interlayer insulating (ILD) layer. The seventh insulating layer can be called a passivation (PVX) layer.

[0333] The structures and fabrication processes described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structures and patterning processes can be modified and added or reduced as needed. The display substrates in this disclosure can be applied to other display devices with pixel driving circuits, such as quantum dot displays, etc. This disclosure does not limit them.

[0334] This disclosure also provides a display device, including the display substrate of any of the foregoing embodiments. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0335] This disclosure also provides a method for fabricating a display substrate. The display substrate includes a display area and a bonding area connected to the display area. The display area includes multiple data signal lines and K rows and L columns of sub-pixels, where K and L are both positive integers greater than 1. Multiple first spaces are included between the K sub-pixel rows, and multiple second spaces are included between the L sub-pixel columns. The first spaces are located between two adjacent sub-pixel rows, and the second spaces are located between two adjacent sub-pixel columns. At least one first space is provided with a first data connection line, and at least one second space is provided with at least one second data connection line. On a plane parallel to the display substrate, the first data connection line extends along a first direction, and the second data connection line extends along a second direction, with the first and second directions intersecting. The fabrication method includes:

[0336] One end of the first data connection line is electrically connected to one of the data signal lines, and the other end is electrically connected to one of the second data connection lines; one end of the second data connection line is electrically connected to the first data line, and the other end is electrically connected to the bonding area.

[0337] The substrate and display device provided in this disclosure include a display area of ​​the display substrate comprising multiple data signal lines and K rows and L columns of sub-pixels, where K and L are both positive integers greater than 1; multiple first spaces are included between the K sub-pixel rows, and multiple second spaces are included between the L sub-pixel columns; the first spaces are located between two adjacent sub-pixel rows, and the second spaces are located between two adjacent sub-pixel columns; at least one first space is provided with a first data connection line, and at least one second space is provided with at least one second data connection line; one end of the first data connection line is electrically connected to one of the data signal lines, and the other end is electrically connected to one of the second data connection lines; one end of the second data connection line is electrically connected to the first data line, and the other end is electrically connected to the bonding area; the introduction of the first data connection line and the second data connection line in the display area greatly reduces the bezel of the display substrate, which is beneficial for achieving narrow bezels in display products.

[0338] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0339] Where there is no conflict, the features of the embodiments disclosed herein can be combined with each other to obtain new embodiments.

[0340] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of these embodiments and is not intended to limit the scope of these embodiments. Any person skilled in the art to which these embodiments pertain may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the patent protection scope of these embodiments shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising a display area and a bonding area connected to the display area, the display area comprising multiple data signal lines and K rows and L columns of sub-pixels, where K and L are both positive integers greater than 1; the K sub-pixel rows are divided into multiple first spaces, and the L sub-pixel columns are divided into multiple second spaces, the first spaces being located between two adjacent sub-pixel rows, the second spaces being located between two adjacent sub-pixel columns, at least one first space being provided with a first data connection line, and at least one second space being provided with at least one second data connection line; on a plane parallel to the display substrate, the first data connection line extends along a first direction, and the second data connection line extends along a second direction, the first direction intersecting the second direction; One end of the first data connection line is electrically connected to one of the data signal lines, and the other end is electrically connected to one of the second data connection lines; one end of the second data connection line is electrically connected to the first data connection line, and the other end is electrically connected to the bonding area. in, At least one sub-pixel includes a pixel driving circuit. In a plane perpendicular to the display substrate, the display substrate includes a substrate and a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially stacked on the substrate. The first semiconductor layer includes: an active layer located in the pixel driving circuit of a plurality of low-temperature polysilicon transistors; The first conductive layer includes: the control electrode of a plurality of low-temperature polysilicon transistors located in the pixel driving circuit and the first electrode of the storage capacitor; The second conductive layer includes: a second plate located in the storage capacitor of the pixel driving circuit; The second semiconductor layer includes: an active layer of a plurality of oxide transistors located in the pixel driving circuit; The third conductive layer includes: control electrodes of a plurality of oxide transistors located in the pixel driving circuit; The fourth conductive layer includes: the first data connection line, the first and second electrodes of a plurality of low-temperature polysilicon transistors located in the pixel driving circuit, and the first and second electrodes of a plurality of oxide transistors located in the pixel driving circuit. The fifth conductive layer includes: a data signal line, a first power line, and a second data connection line.

2. The display substrate according to claim 1, wherein, The first space is also provided with a fourth data connection line, and the second space is also provided with a third data connection line; The same second space is provided with at least one second data connection line and at least one third data connection line; The fourth data connection line extends along the first direction, with one end electrically connected to the data signal line and the other end connected to the third data connection line; the third data connection line extends along the second direction, with one end connected to the fourth data connection line and the other end electrically connected to the bonding area. The first data connection line and the second data connection line are connected by a via, and the third data connection line and the fourth data connection line are integrally formed.

3. The display substrate according to claim 2, wherein, In the same second space, there is one third data connection line and two second data connection lines. In the plane where the display substrate is located, in the first direction, the two second data connection lines are located on both sides of the third data connection line. The two second data connection lines in the same second space are connected to different first data connection lines. Alternatively, in the same second space, there are two third data connection lines and one second data connection line. In the plane where the display substrate is located, in the first direction, the two third data connection lines are located on both sides of the second data connection line, and the two third data connection lines in the same second space are connected to different fourth data connection lines.

4. The display substrate according to claim 1, wherein, In the same second space, there are three second data connection lines, and the three second data connection lines are respectively connected to three different first data connection lines.

5. The display substrate according to claim 2, wherein, The display substrate further includes a light-emitting element, and the plurality of low-temperature polysilicon transistors include a seventh transistor for anode reset of the light-emitting element. The third conductive layer further includes a transition connection electrode, and the fourth conductive layer further includes a plurality of second initial signal lines. In the plane of the fourth conductive layer, the main body of the second initial signal line is a zigzag line extending along a first direction. The plurality of second initial signal lines are arranged in an array along the first direction and the second direction. The second initial signal lines are connected to the active layer of the seventh transistor in the first semiconductor layer through vias and are multiplexed as the first electrode of the seventh transistor. In the same sub-pixel row, two adjacent second initial signal lines are connected to the same transition connection electrode through transition vias.

6. The display substrate according to claim 5, wherein, The adapter electrode extends along a first direction, and the orthographic projection of the adapter electrode on the substrate overlaps with the orthographic projection of one of the second spaces on the substrate.

7. The display substrate according to claim 5, wherein, The fourth conductive layer further includes a fourth data connection line and a third data connection line. The orthographic projection of the fourth data connection line on the substrate at least partially overlaps with the orthographic projection of one of the first spaces on the substrate, and the orthographic projection of the fourth data connection line on the substrate does not overlap with the orthographic projection of the first data connection line on the substrate. The orthographic projection of the third data connection line on the substrate at least partially overlaps with the orthographic projection of one of the second spaces on the substrate; The third data connection line extends along the second direction, with one end connected to the fourth data connection line and the other end electrically connected to the bonding area; the fourth data connection line extends along the first direction, with one end connected to the third data connection line and the other end electrically connected to one of the data signal lines in the fifth conductive layer through a via.

8. The display substrate according to claim 7, wherein, In the same second space, there is one third data connection line and two second data connection lines. The orthographic projection of the third data connection line on the substrate is located between the orthographic projections of the two second data connection lines on the substrate. Alternatively, in the same second space, there are two third data connection lines and one second data connection line, with the orthographic projection of the second data connection line on the substrate located between the orthographic projections of the two third data connection lines on the substrate. The orthographic projections of the second data connection line and the third data connection line on the substrate overlap with the orthographic projection of the adapter electrode on the substrate, but the orthographic projections of the second data connection line and the third data connection line on the substrate do not overlap.

9. The display substrate according to any one of claims 5 to 8, wherein, The pixel driving circuit further includes: a first transistor to a sixth transistor, and a storage capacitor; In a plane parallel to the display substrate, within the same pixel driving circuit, in a first direction, the sixth transistor is located on one side of the storage capacitor, and the fifth and fourth transistors are located on the other side of the storage capacitor; in a second direction, the fifth, sixth, and seventh transistors are located on the same side of the storage capacitor, and the fourth, first, and second transistors are located on the other side of the storage capacitor. Furthermore, the seventh transistor is located on the side of the sixth transistor away from the storage capacitor, and the first transistor is located on the side of the second transistor away from the storage capacitor. The orthographic projection of the storage capacitor onto the substrate overlaps with the orthographic projection of the third transistor onto the substrate. The seventh transistor in the i-th row of sub-pixels is located in the (i-1)-th row of sub-pixels, where i = 2, 3, ..., K. In the second direction, in two sub-pixel rows adjacent to the first data connection line, the first transistor of the previous sub-pixel row and the fifth and sixth transistors of the next sub-pixel row are located on both sides of the first data connection line, and the seventh transistor of the next sub-pixel row is located on the same side of the first data connection line as the first transistor of the previous sub-pixel row; in two sub-pixel rows adjacent to the fourth data connection line, the first transistor of the previous sub-pixel row and the fifth and sixth transistors of the next sub-pixel row are located on both sides of the fourth data connection line, and the seventh transistor of the next sub-pixel row is located on the same side of the fourth data connection line as the first transistor of the previous sub-pixel row; in the first direction, the total number of second and third data connection lines is three, and the three data connection lines are arranged along the first direction line. The two data connection lines on both sides are symmetrical with respect to the data connection line in the middle position. In the same sub-pixel row, the first to seventh transistors and the storage capacitor in the two sub-pixel columns adjacent to the second and third data connection lines in the same second space are symmetrically arranged with respect to the data connection line in the middle position.

10. The display substrate according to claim 9, wherein, In the fourth conductive layer, the fourth data connection line and the first electrode of the fourth transistor in one of the pixel driving circuits are integrally formed. The first electrode of the fourth transistor integrally formed with the fourth data connection line is a strip-shaped structure or a zigzag structure and extends along the second direction. One end is connected to the fourth data connection line, and the other end is electrically connected to the data signal line in the fifth conductive layer through a via. One end of the fourth data connection line is connected to the first electrode of the fourth transistor, and the other end is connected to the third data connection line. The first data connection line is integrally formed with the first electrode of one of the fourth transistors. The first electrode of the fourth transistor, which is integrally formed with the first data connection line, is a strip-shaped or zigzag-shaped structure and extends along the second direction. One end of the strip-shaped structure is connected to the first data connection line, and the other end is electrically connected to the data signal line in the fifth conductive layer through a via. One end of the first data connection line is connected to the first electrode of the fourth transistor, and the other end is electrically connected to the second data connection line in the fifth conductive layer through a via.

11. The display substrate according to claim 1, wherein, In the same second space, there are three second data connection lines, and the orthographic projections of the three second data connection lines on the substrate do not overlap. The three second data connection lines are electrically connected to the first data connection lines in three different first spaces in the fourth conductive layer through three different vias. The display substrate further includes a light-emitting element, and the pixel driving circuit further includes a seventh transistor for anode reset of the light-emitting element; the fourth conductive layer further includes an initial signal connection line and a plurality of second initial signal lines; the second initial signal lines are connected to the active layer of the seventh transistor in the first semiconductor layer through vias and are multiplexed as the first electrode of the seventh transistor; in the plane of the fourth conductive layer, the main body of the second initial signal line is a zigzag line extending along a first direction, and the plurality of second initial signal lines are arranged along a second direction; the initial signal connection line extends along the second direction and is integrally formed with the plurality of second initial signal lines.

12. The display substrate according to claim 11, wherein, Of the three second data connection lines, the orthographic projection of the second data connection line located in the middle position on the substrate overlaps with the orthographic projection of the initial signal connection line on the substrate, and the orthographic projections of the second data connection lines located on both sides on the substrate overlap with the orthographic projections of the second initial signal line on the substrate.

13. The display substrate according to any one of claims 11 to 12, wherein, The pixel driving circuit further includes: a first transistor to a sixth transistor, and a storage capacitor; In a plane parallel to the display substrate, within the same pixel driving circuit, in a first direction, the sixth transistor is located on one side of the storage capacitor, and the fifth and fourth transistors are located on the other side of the storage capacitor; in a second direction, the fifth, sixth, and seventh transistors are located on the same side of the storage capacitor, and the fourth, first, and second transistors are located on the other side of the storage capacitor. Furthermore, the seventh transistor is located on the side of the sixth transistor away from the storage capacitor, and the first transistor is located on the side of the second transistor away from the storage capacitor. The orthographic projection of the storage capacitor onto the substrate overlaps with the orthographic projection of the third transistor onto the substrate. The seventh transistor in the i-th row of sub-pixels is located in the (i-1)-th row of sub-pixels, where i = 2, 3, ..., K. In the second direction, in the two sub-pixel rows adjacent to the first data connection line, the first transistor of the previous sub-pixel row and the fifth and sixth transistors of the next sub-pixel row are located on both sides of the first data connection line, and the seventh transistor of the next sub-pixel row is located on the same side of the first data connection line as the first transistor of the previous sub-pixel row; in the first direction, the three second data connection lines are arranged sequentially, with the second data connection lines on both sides being symmetrical with respect to the second data connection line in the middle position. In the same sub-pixel row, the first to seventh transistors and the storage capacitor in the two sub-pixel columns adjacent to the three second data connection lines are symmetrically arranged with respect to the second data connection line in the middle position.

14. The display substrate according to claim 13, wherein, In the fourth conductive layer, the first data connection line and the first electrode of one of the fourth transistors are integrally formed. The first electrode of the fourth transistor, which is integrally formed with the first data connection line, is a strip-shaped or zigzag-shaped structure and extends along the second direction. One end of the strip-shaped structure is connected to the first data connection line, and the other end is electrically connected to the data signal line in the fifth conductive layer through a via. One end of the first data connection line is connected to the first electrode of the fourth transistor, and the other end is electrically connected to the second data connection line in the fifth conductive layer through a via.

15. The display substrate according to any one of claims 1, 5 to 8, 10 to 11, wherein, One end of the first data connection line has an overlapping region with the orthographic projection of one of the second data connection lines on the substrate, and is electrically connected to the second data connection line in the overlapping region through a via. The other end of the first data connection line has an overlapping region with the orthographic projection of one of the data signal lines on the substrate, and is electrically connected to the data signal line in the overlapping region through a via.

16. A display device comprising a display substrate as described in any one of claims 1 to 15.

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